2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #include "qemu-option.h"
28 #include "qemu-config.h"
30 #include "qapi/qapi-visit-core.h"
31 #include "arch_init.h"
36 #if defined(CONFIG_KVM)
37 #include <linux/kvm_para.h>
40 /* feature flags taken from "Intel Processor Identification and the CPUID
41 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
42 * between feature naming conventions, aliases may be added.
44 static const char *feature_name
[] = {
45 "fpu", "vme", "de", "pse",
46 "tsc", "msr", "pae", "mce",
47 "cx8", "apic", NULL
, "sep",
48 "mtrr", "pge", "mca", "cmov",
49 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
50 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
51 "fxsr", "sse", "sse2", "ss",
52 "ht" /* Intel htt */, "tm", "ia64", "pbe",
54 static const char *ext_feature_name
[] = {
55 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
56 "ds_cpl", "vmx", "smx", "est",
57 "tm2", "ssse3", "cid", NULL
,
58 "fma", "cx16", "xtpr", "pdcm",
59 NULL
, "pcid", "dca", "sse4.1|sse4_1",
60 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
61 "tsc-deadline", "aes", "xsave", "osxsave",
62 "avx", NULL
, NULL
, "hypervisor",
64 static const char *ext2_feature_name
[] = {
65 "fpu", "vme", "de", "pse",
66 "tsc", "msr", "pae", "mce",
67 "cx8" /* AMD CMPXCHG8B */, "apic", NULL
, "syscall",
68 "mtrr", "pge", "mca", "cmov",
69 "pat", "pse36", NULL
, NULL
/* Linux mp */,
70 "nx|xd", NULL
, "mmxext", "mmx",
71 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
72 NULL
, "lm|i64", "3dnowext", "3dnow",
74 static const char *ext3_feature_name
[] = {
75 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
76 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
77 "3dnowprefetch", "osvw", "ibs", "xop",
78 "skinit", "wdt", NULL
, NULL
,
79 "fma4", NULL
, "cvt16", "nodeid_msr",
80 NULL
, NULL
, NULL
, NULL
,
81 NULL
, NULL
, NULL
, NULL
,
82 NULL
, NULL
, NULL
, NULL
,
85 static const char *kvm_feature_name
[] = {
86 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL
, "kvm_pv_eoi", NULL
,
87 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
88 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
89 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
92 static const char *svm_feature_name
[] = {
93 "npt", "lbrv", "svm_lock", "nrip_save",
94 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
95 NULL
, NULL
, "pause_filter", NULL
,
96 "pfthreshold", NULL
, NULL
, NULL
,
97 NULL
, NULL
, NULL
, NULL
,
98 NULL
, NULL
, NULL
, NULL
,
99 NULL
, NULL
, NULL
, NULL
,
100 NULL
, NULL
, NULL
, NULL
,
103 /* collects per-function cpuid data
105 typedef struct model_features_t
{
106 uint32_t *guest_feat
;
109 const char **flag_names
;
114 int enforce_cpuid
= 0;
116 void host_cpuid(uint32_t function
, uint32_t count
,
117 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
119 #if defined(CONFIG_KVM)
124 : "=a"(vec
[0]), "=b"(vec
[1]),
125 "=c"(vec
[2]), "=d"(vec
[3])
126 : "0"(function
), "c"(count
) : "cc");
128 asm volatile("pusha \n\t"
130 "mov %%eax, 0(%2) \n\t"
131 "mov %%ebx, 4(%2) \n\t"
132 "mov %%ecx, 8(%2) \n\t"
133 "mov %%edx, 12(%2) \n\t"
135 : : "a"(function
), "c"(count
), "S"(vec
)
150 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
152 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
153 * a substring. ex if !NULL points to the first char after a substring,
154 * otherwise the string is assumed to sized by a terminating nul.
155 * Return lexical ordering of *s1:*s2.
157 static int sstrcmp(const char *s1
, const char *e1
, const char *s2
,
161 if (!*s1
|| !*s2
|| *s1
!= *s2
)
164 if (s1
== e1
&& s2
== e2
)
173 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
174 * '|' delimited (possibly empty) strings in which case search for a match
175 * within the alternatives proceeds left to right. Return 0 for success,
176 * non-zero otherwise.
178 static int altcmp(const char *s
, const char *e
, const char *altstr
)
182 for (q
= p
= altstr
; ; ) {
183 while (*p
&& *p
!= '|')
185 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
194 /* search featureset for flag *[s..e), if found set corresponding bit in
195 * *pval and return true, otherwise return false
197 static bool lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
198 const char **featureset
)
204 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
) {
205 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
213 static void add_flagname_to_bitmaps(const char *flagname
, uint32_t *features
,
214 uint32_t *ext_features
,
215 uint32_t *ext2_features
,
216 uint32_t *ext3_features
,
217 uint32_t *kvm_features
,
218 uint32_t *svm_features
)
220 if (!lookup_feature(features
, flagname
, NULL
, feature_name
) &&
221 !lookup_feature(ext_features
, flagname
, NULL
, ext_feature_name
) &&
222 !lookup_feature(ext2_features
, flagname
, NULL
, ext2_feature_name
) &&
223 !lookup_feature(ext3_features
, flagname
, NULL
, ext3_feature_name
) &&
224 !lookup_feature(kvm_features
, flagname
, NULL
, kvm_feature_name
) &&
225 !lookup_feature(svm_features
, flagname
, NULL
, svm_feature_name
))
226 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
229 typedef struct x86_def_t
{
230 struct x86_def_t
*next
;
233 uint32_t vendor1
, vendor2
, vendor3
;
238 uint32_t features
, ext_features
, ext2_features
, ext3_features
;
239 uint32_t kvm_features
, svm_features
;
243 /* Store the results of Centaur's CPUID instructions */
244 uint32_t ext4_features
;
246 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
247 uint32_t cpuid_7_0_ebx_features
;
250 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
251 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
252 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
253 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
254 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
255 CPUID_PSE36 | CPUID_FXSR)
256 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
257 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
258 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
259 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
260 CPUID_PAE | CPUID_SEP | CPUID_APIC)
261 #define EXT2_FEATURE_MASK 0x0183F3FF
263 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
264 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
265 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
266 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
267 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
268 /* partly implemented:
269 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
270 CPUID_PSE36 (needed for Solaris) */
272 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
273 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
274 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
275 CPUID_EXT_HYPERVISOR)
277 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
278 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
279 #define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
280 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
281 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
283 CPUID_EXT2_PDPE1GB */
284 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
285 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
286 #define TCG_SVM_FEATURES 0
288 /* maintains list of cpu model definitions
290 static x86_def_t
*x86_defs
= {NULL
};
292 /* built-in cpu model definitions (deprecated)
294 static x86_def_t builtin_x86_defs
[] = {
298 .vendor1
= CPUID_VENDOR_AMD_1
,
299 .vendor2
= CPUID_VENDOR_AMD_2
,
300 .vendor3
= CPUID_VENDOR_AMD_3
,
304 .features
= PPRO_FEATURES
|
305 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
307 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
| CPUID_EXT_POPCNT
,
308 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) |
309 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
310 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
311 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
312 .xlevel
= 0x8000000A,
317 .vendor1
= CPUID_VENDOR_AMD_1
,
318 .vendor2
= CPUID_VENDOR_AMD_2
,
319 .vendor3
= CPUID_VENDOR_AMD_3
,
323 .features
= PPRO_FEATURES
|
324 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
325 CPUID_PSE36
| CPUID_VME
| CPUID_HT
,
326 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
328 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) |
329 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
330 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
331 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
332 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
334 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
335 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
336 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
337 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
338 .svm_features
= CPUID_SVM_NPT
| CPUID_SVM_LBRV
,
339 .xlevel
= 0x8000001A,
340 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
348 .features
= PPRO_FEATURES
|
349 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
350 CPUID_PSE36
| CPUID_VME
| CPUID_DTS
| CPUID_ACPI
| CPUID_SS
|
351 CPUID_HT
| CPUID_TM
| CPUID_PBE
,
352 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
353 CPUID_EXT_DTES64
| CPUID_EXT_DSCPL
| CPUID_EXT_VMX
| CPUID_EXT_EST
|
354 CPUID_EXT_TM2
| CPUID_EXT_CX16
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
355 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
356 .ext3_features
= CPUID_EXT3_LAHF_LM
,
357 .xlevel
= 0x80000008,
358 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
363 .vendor1
= CPUID_VENDOR_INTEL_1
,
364 .vendor2
= CPUID_VENDOR_INTEL_2
,
365 .vendor3
= CPUID_VENDOR_INTEL_3
,
369 /* Missing: CPUID_VME, CPUID_HT */
370 .features
= PPRO_FEATURES
|
371 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
373 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
374 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
375 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
376 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) |
377 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
378 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
379 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
380 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
381 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
383 .xlevel
= 0x80000008,
384 .model_id
= "Common KVM processor"
392 .features
= PPRO_FEATURES
,
393 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_POPCNT
,
394 .xlevel
= 0x80000004,
402 .features
= PPRO_FEATURES
|
403 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
404 .ext_features
= CPUID_EXT_SSE3
,
405 .ext2_features
= PPRO_FEATURES
& EXT2_FEATURE_MASK
,
407 .xlevel
= 0x80000008,
408 .model_id
= "Common 32-bit KVM processor"
416 .features
= PPRO_FEATURES
| CPUID_VME
|
417 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_DTS
| CPUID_ACPI
|
418 CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
419 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_VMX
|
420 CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
421 .ext2_features
= CPUID_EXT2_NX
,
422 .xlevel
= 0x80000008,
423 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
431 .features
= I486_FEATURES
,
440 .features
= PENTIUM_FEATURES
,
449 .features
= PENTIUM2_FEATURES
,
458 .features
= PENTIUM3_FEATURES
,
464 .vendor1
= CPUID_VENDOR_AMD_1
,
465 .vendor2
= CPUID_VENDOR_AMD_2
,
466 .vendor3
= CPUID_VENDOR_AMD_3
,
470 .features
= PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
| CPUID_MCA
,
471 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) | CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
472 .xlevel
= 0x80000008,
476 /* original is on level 10 */
481 .features
= PPRO_FEATURES
|
482 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
| CPUID_DTS
|
483 CPUID_ACPI
| CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
484 /* Some CPUs got no CPUID_SEP */
485 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
486 CPUID_EXT_DSCPL
| CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
,
487 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) | CPUID_EXT2_NX
,
488 .ext3_features
= CPUID_EXT3_LAHF_LM
,
489 .xlevel
= 0x8000000A,
490 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
495 .vendor1
= CPUID_VENDOR_INTEL_1
,
496 .vendor2
= CPUID_VENDOR_INTEL_2
,
497 .vendor3
= CPUID_VENDOR_INTEL_3
,
501 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
502 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
503 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
504 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
505 CPUID_DE
| CPUID_FP87
,
506 .ext_features
= CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
507 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
508 .ext3_features
= CPUID_EXT3_LAHF_LM
,
509 .xlevel
= 0x8000000A,
510 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
515 .vendor1
= CPUID_VENDOR_INTEL_1
,
516 .vendor2
= CPUID_VENDOR_INTEL_2
,
517 .vendor3
= CPUID_VENDOR_INTEL_3
,
521 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
522 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
523 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
524 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
525 CPUID_DE
| CPUID_FP87
,
526 .ext_features
= CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
528 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
529 .ext3_features
= CPUID_EXT3_LAHF_LM
,
530 .xlevel
= 0x8000000A,
531 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
536 .vendor1
= CPUID_VENDOR_INTEL_1
,
537 .vendor2
= CPUID_VENDOR_INTEL_2
,
538 .vendor3
= CPUID_VENDOR_INTEL_3
,
542 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
543 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
544 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
545 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
546 CPUID_DE
| CPUID_FP87
,
547 .ext_features
= CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
548 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
549 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
550 .ext3_features
= CPUID_EXT3_LAHF_LM
,
551 .xlevel
= 0x8000000A,
552 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
557 .vendor1
= CPUID_VENDOR_INTEL_1
,
558 .vendor2
= CPUID_VENDOR_INTEL_2
,
559 .vendor3
= CPUID_VENDOR_INTEL_3
,
563 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
564 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
565 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
566 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
567 CPUID_DE
| CPUID_FP87
,
568 .ext_features
= CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
569 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
571 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
572 .ext3_features
= CPUID_EXT3_LAHF_LM
,
573 .xlevel
= 0x8000000A,
574 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
577 .name
= "SandyBridge",
579 .vendor1
= CPUID_VENDOR_INTEL_1
,
580 .vendor2
= CPUID_VENDOR_INTEL_2
,
581 .vendor3
= CPUID_VENDOR_INTEL_3
,
585 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
586 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
587 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
588 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
589 CPUID_DE
| CPUID_FP87
,
590 .ext_features
= CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
591 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
592 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
593 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
595 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
597 .ext3_features
= CPUID_EXT3_LAHF_LM
,
598 .xlevel
= 0x8000000A,
599 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
602 .name
= "Opteron_G1",
604 .vendor1
= CPUID_VENDOR_AMD_1
,
605 .vendor2
= CPUID_VENDOR_AMD_2
,
606 .vendor3
= CPUID_VENDOR_AMD_3
,
610 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
611 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
612 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
613 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
614 CPUID_DE
| CPUID_FP87
,
615 .ext_features
= CPUID_EXT_SSE3
,
616 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
617 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
618 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
619 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
620 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
621 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
622 .xlevel
= 0x80000008,
623 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
626 .name
= "Opteron_G2",
628 .vendor1
= CPUID_VENDOR_AMD_1
,
629 .vendor2
= CPUID_VENDOR_AMD_2
,
630 .vendor3
= CPUID_VENDOR_AMD_3
,
634 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
635 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
636 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
637 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
638 CPUID_DE
| CPUID_FP87
,
639 .ext_features
= CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
640 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
641 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
642 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
643 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
644 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
645 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
646 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
647 .ext3_features
= CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
648 .xlevel
= 0x80000008,
649 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
652 .name
= "Opteron_G3",
654 .vendor1
= CPUID_VENDOR_AMD_1
,
655 .vendor2
= CPUID_VENDOR_AMD_2
,
656 .vendor3
= CPUID_VENDOR_AMD_3
,
660 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
661 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
662 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
663 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
664 CPUID_DE
| CPUID_FP87
,
665 .ext_features
= CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
667 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_FXSR
|
668 CPUID_EXT2_MMX
| CPUID_EXT2_NX
| CPUID_EXT2_PSE36
|
669 CPUID_EXT2_PAT
| CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
|
670 CPUID_EXT2_PGE
| CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
|
671 CPUID_EXT2_APIC
| CPUID_EXT2_CX8
| CPUID_EXT2_MCE
|
672 CPUID_EXT2_PAE
| CPUID_EXT2_MSR
| CPUID_EXT2_TSC
| CPUID_EXT2_PSE
|
673 CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
674 .ext3_features
= CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
675 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
676 .xlevel
= 0x80000008,
677 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
680 .name
= "Opteron_G4",
682 .vendor1
= CPUID_VENDOR_AMD_1
,
683 .vendor2
= CPUID_VENDOR_AMD_2
,
684 .vendor3
= CPUID_VENDOR_AMD_3
,
688 .features
= CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
689 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
690 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
691 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
692 CPUID_DE
| CPUID_FP87
,
693 .ext_features
= CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
694 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
695 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
697 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
|
698 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_FXSR
| CPUID_EXT2_MMX
|
699 CPUID_EXT2_NX
| CPUID_EXT2_PSE36
| CPUID_EXT2_PAT
|
700 CPUID_EXT2_CMOV
| CPUID_EXT2_MCA
| CPUID_EXT2_PGE
|
701 CPUID_EXT2_MTRR
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_APIC
|
702 CPUID_EXT2_CX8
| CPUID_EXT2_MCE
| CPUID_EXT2_PAE
| CPUID_EXT2_MSR
|
703 CPUID_EXT2_TSC
| CPUID_EXT2_PSE
| CPUID_EXT2_DE
| CPUID_EXT2_FPU
,
704 .ext3_features
= CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
705 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
706 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
708 .xlevel
= 0x8000001A,
709 .model_id
= "AMD Opteron 62xx class CPU",
713 static int cpu_x86_fill_model_id(char *str
)
715 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
718 for (i
= 0; i
< 3; i
++) {
719 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
720 memcpy(str
+ i
* 16 + 0, &eax
, 4);
721 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
722 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
723 memcpy(str
+ i
* 16 + 12, &edx
, 4);
728 static int cpu_x86_fill_host(x86_def_t
*x86_cpu_def
)
730 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
732 x86_cpu_def
->name
= "host";
733 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
734 x86_cpu_def
->level
= eax
;
735 x86_cpu_def
->vendor1
= ebx
;
736 x86_cpu_def
->vendor2
= edx
;
737 x86_cpu_def
->vendor3
= ecx
;
739 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
740 x86_cpu_def
->family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
741 x86_cpu_def
->model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
742 x86_cpu_def
->stepping
= eax
& 0x0F;
743 x86_cpu_def
->ext_features
= ecx
;
744 x86_cpu_def
->features
= edx
;
746 if (kvm_enabled() && x86_cpu_def
->level
>= 7) {
747 x86_cpu_def
->cpuid_7_0_ebx_features
= kvm_arch_get_supported_cpuid(kvm_state
, 0x7, 0, R_EBX
);
749 x86_cpu_def
->cpuid_7_0_ebx_features
= 0;
752 host_cpuid(0x80000000, 0, &eax
, &ebx
, &ecx
, &edx
);
753 x86_cpu_def
->xlevel
= eax
;
755 host_cpuid(0x80000001, 0, &eax
, &ebx
, &ecx
, &edx
);
756 x86_cpu_def
->ext2_features
= edx
;
757 x86_cpu_def
->ext3_features
= ecx
;
758 cpu_x86_fill_model_id(x86_cpu_def
->model_id
);
759 x86_cpu_def
->vendor_override
= 0;
761 /* Call Centaur's CPUID instruction. */
762 if (x86_cpu_def
->vendor1
== CPUID_VENDOR_VIA_1
&&
763 x86_cpu_def
->vendor2
== CPUID_VENDOR_VIA_2
&&
764 x86_cpu_def
->vendor3
== CPUID_VENDOR_VIA_3
) {
765 host_cpuid(0xC0000000, 0, &eax
, &ebx
, &ecx
, &edx
);
766 if (eax
>= 0xC0000001) {
767 /* Support VIA max extended level */
768 x86_cpu_def
->xlevel2
= eax
;
769 host_cpuid(0xC0000001, 0, &eax
, &ebx
, &ecx
, &edx
);
770 x86_cpu_def
->ext4_features
= edx
;
775 * Every SVM feature requires emulation support in KVM - so we can't just
776 * read the host features here. KVM might even support SVM features not
777 * available on the host hardware. Just set all bits and mask out the
778 * unsupported ones later.
780 x86_cpu_def
->svm_features
= -1;
785 static int unavailable_host_feature(struct model_features_t
*f
, uint32_t mask
)
789 for (i
= 0; i
< 32; ++i
)
791 fprintf(stderr
, "warning: host cpuid %04x_%04x lacks requested"
792 " flag '%s' [0x%08x]\n",
793 f
->cpuid
>> 16, f
->cpuid
& 0xffff,
794 f
->flag_names
[i
] ? f
->flag_names
[i
] : "[reserved]", mask
);
800 /* best effort attempt to inform user requested cpu flags aren't making
801 * their way to the guest. Note: ft[].check_feat ideally should be
802 * specified via a guest_def field to suppress report of extraneous flags.
804 static int check_features_against_host(x86_def_t
*guest_def
)
809 struct model_features_t ft
[] = {
810 {&guest_def
->features
, &host_def
.features
,
811 ~0, feature_name
, 0x00000000},
812 {&guest_def
->ext_features
, &host_def
.ext_features
,
813 ~CPUID_EXT_HYPERVISOR
, ext_feature_name
, 0x00000001},
814 {&guest_def
->ext2_features
, &host_def
.ext2_features
,
815 ~PPRO_FEATURES
, ext2_feature_name
, 0x80000000},
816 {&guest_def
->ext3_features
, &host_def
.ext3_features
,
817 ~CPUID_EXT3_SVM
, ext3_feature_name
, 0x80000001}};
819 cpu_x86_fill_host(&host_def
);
820 for (rv
= 0, i
= 0; i
< ARRAY_SIZE(ft
); ++i
)
821 for (mask
= 1; mask
; mask
<<= 1)
822 if (ft
[i
].check_feat
& mask
&& *ft
[i
].guest_feat
& mask
&&
823 !(*ft
[i
].host_feat
& mask
)) {
824 unavailable_host_feature(&ft
[i
], mask
);
830 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
, void *opaque
,
831 const char *name
, Error
**errp
)
833 X86CPU
*cpu
= X86_CPU(obj
);
834 CPUX86State
*env
= &cpu
->env
;
837 value
= (env
->cpuid_version
>> 8) & 0xf;
839 value
+= (env
->cpuid_version
>> 20) & 0xff;
841 visit_type_int(v
, &value
, name
, errp
);
844 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
, void *opaque
,
845 const char *name
, Error
**errp
)
847 X86CPU
*cpu
= X86_CPU(obj
);
848 CPUX86State
*env
= &cpu
->env
;
849 const int64_t min
= 0;
850 const int64_t max
= 0xff + 0xf;
853 visit_type_int(v
, &value
, name
, errp
);
854 if (error_is_set(errp
)) {
857 if (value
< min
|| value
> max
) {
858 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
859 name
? name
: "null", value
, min
, max
);
863 env
->cpuid_version
&= ~0xff00f00;
865 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
867 env
->cpuid_version
|= value
<< 8;
871 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
, void *opaque
,
872 const char *name
, Error
**errp
)
874 X86CPU
*cpu
= X86_CPU(obj
);
875 CPUX86State
*env
= &cpu
->env
;
878 value
= (env
->cpuid_version
>> 4) & 0xf;
879 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
880 visit_type_int(v
, &value
, name
, errp
);
883 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
, void *opaque
,
884 const char *name
, Error
**errp
)
886 X86CPU
*cpu
= X86_CPU(obj
);
887 CPUX86State
*env
= &cpu
->env
;
888 const int64_t min
= 0;
889 const int64_t max
= 0xff;
892 visit_type_int(v
, &value
, name
, errp
);
893 if (error_is_set(errp
)) {
896 if (value
< min
|| value
> max
) {
897 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
898 name
? name
: "null", value
, min
, max
);
902 env
->cpuid_version
&= ~0xf00f0;
903 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
906 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
907 void *opaque
, const char *name
,
910 X86CPU
*cpu
= X86_CPU(obj
);
911 CPUX86State
*env
= &cpu
->env
;
914 value
= env
->cpuid_version
& 0xf;
915 visit_type_int(v
, &value
, name
, errp
);
918 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
919 void *opaque
, const char *name
,
922 X86CPU
*cpu
= X86_CPU(obj
);
923 CPUX86State
*env
= &cpu
->env
;
924 const int64_t min
= 0;
925 const int64_t max
= 0xf;
928 visit_type_int(v
, &value
, name
, errp
);
929 if (error_is_set(errp
)) {
932 if (value
< min
|| value
> max
) {
933 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
934 name
? name
: "null", value
, min
, max
);
938 env
->cpuid_version
&= ~0xf;
939 env
->cpuid_version
|= value
& 0xf;
942 static void x86_cpuid_get_level(Object
*obj
, Visitor
*v
, void *opaque
,
943 const char *name
, Error
**errp
)
945 X86CPU
*cpu
= X86_CPU(obj
);
947 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
950 static void x86_cpuid_set_level(Object
*obj
, Visitor
*v
, void *opaque
,
951 const char *name
, Error
**errp
)
953 X86CPU
*cpu
= X86_CPU(obj
);
955 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
958 static void x86_cpuid_get_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
959 const char *name
, Error
**errp
)
961 X86CPU
*cpu
= X86_CPU(obj
);
963 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
966 static void x86_cpuid_set_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
967 const char *name
, Error
**errp
)
969 X86CPU
*cpu
= X86_CPU(obj
);
971 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
974 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
976 X86CPU
*cpu
= X86_CPU(obj
);
977 CPUX86State
*env
= &cpu
->env
;
981 value
= (char *)g_malloc(12 + 1);
982 for (i
= 0; i
< 4; i
++) {
983 value
[i
] = env
->cpuid_vendor1
>> (8 * i
);
984 value
[i
+ 4] = env
->cpuid_vendor2
>> (8 * i
);
985 value
[i
+ 8] = env
->cpuid_vendor3
>> (8 * i
);
991 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
994 X86CPU
*cpu
= X86_CPU(obj
);
995 CPUX86State
*env
= &cpu
->env
;
998 if (strlen(value
) != 12) {
999 error_set(errp
, QERR_PROPERTY_VALUE_BAD
, "",
1004 env
->cpuid_vendor1
= 0;
1005 env
->cpuid_vendor2
= 0;
1006 env
->cpuid_vendor3
= 0;
1007 for (i
= 0; i
< 4; i
++) {
1008 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1009 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1010 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1012 env
->cpuid_vendor_override
= 1;
1015 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1017 X86CPU
*cpu
= X86_CPU(obj
);
1018 CPUX86State
*env
= &cpu
->env
;
1022 value
= g_malloc(48 + 1);
1023 for (i
= 0; i
< 48; i
++) {
1024 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1030 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1033 X86CPU
*cpu
= X86_CPU(obj
);
1034 CPUX86State
*env
= &cpu
->env
;
1037 if (model_id
== NULL
) {
1040 len
= strlen(model_id
);
1041 memset(env
->cpuid_model
, 0, 48);
1042 for (i
= 0; i
< 48; i
++) {
1046 c
= (uint8_t)model_id
[i
];
1048 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1052 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1053 const char *name
, Error
**errp
)
1055 X86CPU
*cpu
= X86_CPU(obj
);
1058 value
= cpu
->env
.tsc_khz
* 1000;
1059 visit_type_int(v
, &value
, name
, errp
);
1062 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
1063 const char *name
, Error
**errp
)
1065 X86CPU
*cpu
= X86_CPU(obj
);
1066 const int64_t min
= 0;
1067 const int64_t max
= INT64_MAX
;
1070 visit_type_int(v
, &value
, name
, errp
);
1071 if (error_is_set(errp
)) {
1074 if (value
< min
|| value
> max
) {
1075 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1076 name
? name
: "null", value
, min
, max
);
1080 cpu
->env
.tsc_khz
= value
/ 1000;
1083 static int cpu_x86_find_by_name(x86_def_t
*x86_cpu_def
, const char *cpu_model
)
1088 char *s
= g_strdup(cpu_model
);
1089 char *featurestr
, *name
= strtok(s
, ",");
1090 /* Features to be added*/
1091 uint32_t plus_features
= 0, plus_ext_features
= 0;
1092 uint32_t plus_ext2_features
= 0, plus_ext3_features
= 0;
1093 uint32_t plus_kvm_features
= 0, plus_svm_features
= 0;
1094 /* Features to be removed */
1095 uint32_t minus_features
= 0, minus_ext_features
= 0;
1096 uint32_t minus_ext2_features
= 0, minus_ext3_features
= 0;
1097 uint32_t minus_kvm_features
= 0, minus_svm_features
= 0;
1100 for (def
= x86_defs
; def
; def
= def
->next
)
1101 if (name
&& !strcmp(name
, def
->name
))
1103 if (kvm_enabled() && name
&& strcmp(name
, "host") == 0) {
1104 cpu_x86_fill_host(x86_cpu_def
);
1108 memcpy(x86_cpu_def
, def
, sizeof(*def
));
1111 #if defined(CONFIG_KVM)
1112 plus_kvm_features
= (1 << KVM_FEATURE_CLOCKSOURCE
) |
1113 (1 << KVM_FEATURE_NOP_IO_DELAY
) |
1114 (1 << KVM_FEATURE_MMU_OP
) |
1115 (1 << KVM_FEATURE_CLOCKSOURCE2
) |
1116 (1 << KVM_FEATURE_ASYNC_PF
) |
1117 (1 << KVM_FEATURE_STEAL_TIME
) |
1118 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT
);
1120 plus_kvm_features
= 0;
1123 add_flagname_to_bitmaps("hypervisor", &plus_features
,
1124 &plus_ext_features
, &plus_ext2_features
, &plus_ext3_features
,
1125 &plus_kvm_features
, &plus_svm_features
);
1127 featurestr
= strtok(NULL
, ",");
1129 while (featurestr
) {
1131 if (featurestr
[0] == '+') {
1132 add_flagname_to_bitmaps(featurestr
+ 1, &plus_features
,
1133 &plus_ext_features
, &plus_ext2_features
,
1134 &plus_ext3_features
, &plus_kvm_features
,
1135 &plus_svm_features
);
1136 } else if (featurestr
[0] == '-') {
1137 add_flagname_to_bitmaps(featurestr
+ 1, &minus_features
,
1138 &minus_ext_features
, &minus_ext2_features
,
1139 &minus_ext3_features
, &minus_kvm_features
,
1140 &minus_svm_features
);
1141 } else if ((val
= strchr(featurestr
, '='))) {
1143 if (!strcmp(featurestr
, "family")) {
1145 numvalue
= strtoul(val
, &err
, 0);
1146 if (!*val
|| *err
|| numvalue
> 0xff + 0xf) {
1147 fprintf(stderr
, "bad numerical value %s\n", val
);
1150 x86_cpu_def
->family
= numvalue
;
1151 } else if (!strcmp(featurestr
, "model")) {
1153 numvalue
= strtoul(val
, &err
, 0);
1154 if (!*val
|| *err
|| numvalue
> 0xff) {
1155 fprintf(stderr
, "bad numerical value %s\n", val
);
1158 x86_cpu_def
->model
= numvalue
;
1159 } else if (!strcmp(featurestr
, "stepping")) {
1161 numvalue
= strtoul(val
, &err
, 0);
1162 if (!*val
|| *err
|| numvalue
> 0xf) {
1163 fprintf(stderr
, "bad numerical value %s\n", val
);
1166 x86_cpu_def
->stepping
= numvalue
;
1167 } else if (!strcmp(featurestr
, "level")) {
1169 numvalue
= strtoul(val
, &err
, 0);
1170 if (!*val
|| *err
) {
1171 fprintf(stderr
, "bad numerical value %s\n", val
);
1174 x86_cpu_def
->level
= numvalue
;
1175 } else if (!strcmp(featurestr
, "xlevel")) {
1177 numvalue
= strtoul(val
, &err
, 0);
1178 if (!*val
|| *err
) {
1179 fprintf(stderr
, "bad numerical value %s\n", val
);
1182 if (numvalue
< 0x80000000) {
1183 numvalue
+= 0x80000000;
1185 x86_cpu_def
->xlevel
= numvalue
;
1186 } else if (!strcmp(featurestr
, "vendor")) {
1187 if (strlen(val
) != 12) {
1188 fprintf(stderr
, "vendor string must be 12 chars long\n");
1191 x86_cpu_def
->vendor1
= 0;
1192 x86_cpu_def
->vendor2
= 0;
1193 x86_cpu_def
->vendor3
= 0;
1194 for(i
= 0; i
< 4; i
++) {
1195 x86_cpu_def
->vendor1
|= ((uint8_t)val
[i
]) << (8 * i
);
1196 x86_cpu_def
->vendor2
|= ((uint8_t)val
[i
+ 4]) << (8 * i
);
1197 x86_cpu_def
->vendor3
|= ((uint8_t)val
[i
+ 8]) << (8 * i
);
1199 x86_cpu_def
->vendor_override
= 1;
1200 } else if (!strcmp(featurestr
, "model_id")) {
1201 pstrcpy(x86_cpu_def
->model_id
, sizeof(x86_cpu_def
->model_id
),
1203 } else if (!strcmp(featurestr
, "tsc_freq")) {
1207 tsc_freq
= strtosz_suffix_unit(val
, &err
,
1208 STRTOSZ_DEFSUFFIX_B
, 1000);
1209 if (tsc_freq
< 0 || *err
) {
1210 fprintf(stderr
, "bad numerical value %s\n", val
);
1213 x86_cpu_def
->tsc_khz
= tsc_freq
/ 1000;
1214 } else if (!strcmp(featurestr
, "hv_spinlocks")) {
1216 numvalue
= strtoul(val
, &err
, 0);
1217 if (!*val
|| *err
) {
1218 fprintf(stderr
, "bad numerical value %s\n", val
);
1221 hyperv_set_spinlock_retries(numvalue
);
1223 fprintf(stderr
, "unrecognized feature %s\n", featurestr
);
1226 } else if (!strcmp(featurestr
, "check")) {
1228 } else if (!strcmp(featurestr
, "enforce")) {
1229 check_cpuid
= enforce_cpuid
= 1;
1230 } else if (!strcmp(featurestr
, "hv_relaxed")) {
1231 hyperv_enable_relaxed_timing(true);
1232 } else if (!strcmp(featurestr
, "hv_vapic")) {
1233 hyperv_enable_vapic_recommended(true);
1235 fprintf(stderr
, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr
);
1238 featurestr
= strtok(NULL
, ",");
1240 x86_cpu_def
->features
|= plus_features
;
1241 x86_cpu_def
->ext_features
|= plus_ext_features
;
1242 x86_cpu_def
->ext2_features
|= plus_ext2_features
;
1243 x86_cpu_def
->ext3_features
|= plus_ext3_features
;
1244 x86_cpu_def
->kvm_features
|= plus_kvm_features
;
1245 x86_cpu_def
->svm_features
|= plus_svm_features
;
1246 x86_cpu_def
->features
&= ~minus_features
;
1247 x86_cpu_def
->ext_features
&= ~minus_ext_features
;
1248 x86_cpu_def
->ext2_features
&= ~minus_ext2_features
;
1249 x86_cpu_def
->ext3_features
&= ~minus_ext3_features
;
1250 x86_cpu_def
->kvm_features
&= ~minus_kvm_features
;
1251 x86_cpu_def
->svm_features
&= ~minus_svm_features
;
1253 if (check_features_against_host(x86_cpu_def
) && enforce_cpuid
)
1264 /* generate a composite string into buf of all cpuid names in featureset
1265 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1266 * if flags, suppress names undefined in featureset.
1268 static void listflags(char *buf
, int bufsize
, uint32_t fbits
,
1269 const char **featureset
, uint32_t flags
)
1271 const char **p
= &featureset
[31];
1275 b
= 4 <= bufsize
? buf
+ (bufsize
-= 3) - 1 : NULL
;
1277 for (q
= buf
, bit
= 31; fbits
&& bufsize
; --p
, fbits
&= ~(1 << bit
), --bit
)
1278 if (fbits
& 1 << bit
&& (*p
|| !flags
)) {
1280 nc
= snprintf(q
, bufsize
, "%s%s", q
== buf
? "" : " ", *p
);
1282 nc
= snprintf(q
, bufsize
, "%s[%d]", q
== buf
? "" : " ", bit
);
1283 if (bufsize
<= nc
) {
1285 memcpy(b
, "...", sizeof("..."));
1294 /* generate CPU information. */
1295 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1300 for (def
= x86_defs
; def
; def
= def
->next
) {
1301 snprintf(buf
, sizeof(buf
), "%s", def
->name
);
1302 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
1304 if (kvm_enabled()) {
1305 (*cpu_fprintf
)(f
, "x86 %16s\n", "[host]");
1307 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
1308 listflags(buf
, sizeof(buf
), (uint32_t)~0, feature_name
, 1);
1309 (*cpu_fprintf
)(f
, " f_edx: %s\n", buf
);
1310 listflags(buf
, sizeof(buf
), (uint32_t)~0, ext_feature_name
, 1);
1311 (*cpu_fprintf
)(f
, " f_ecx: %s\n", buf
);
1312 listflags(buf
, sizeof(buf
), (uint32_t)~0, ext2_feature_name
, 1);
1313 (*cpu_fprintf
)(f
, " extf_edx: %s\n", buf
);
1314 listflags(buf
, sizeof(buf
), (uint32_t)~0, ext3_feature_name
, 1);
1315 (*cpu_fprintf
)(f
, " extf_ecx: %s\n", buf
);
1318 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
1320 CpuDefinitionInfoList
*cpu_list
= NULL
;
1323 for (def
= x86_defs
; def
; def
= def
->next
) {
1324 CpuDefinitionInfoList
*entry
;
1325 CpuDefinitionInfo
*info
;
1327 info
= g_malloc0(sizeof(*info
));
1328 info
->name
= g_strdup(def
->name
);
1330 entry
= g_malloc0(sizeof(*entry
));
1331 entry
->value
= info
;
1332 entry
->next
= cpu_list
;
1339 int cpu_x86_register(X86CPU
*cpu
, const char *cpu_model
)
1341 CPUX86State
*env
= &cpu
->env
;
1342 x86_def_t def1
, *def
= &def1
;
1343 Error
*error
= NULL
;
1345 memset(def
, 0, sizeof(*def
));
1347 if (cpu_x86_find_by_name(def
, cpu_model
) < 0)
1350 env
->cpuid_vendor1
= def
->vendor1
;
1351 env
->cpuid_vendor2
= def
->vendor2
;
1352 env
->cpuid_vendor3
= def
->vendor3
;
1354 env
->cpuid_vendor1
= CPUID_VENDOR_INTEL_1
;
1355 env
->cpuid_vendor2
= CPUID_VENDOR_INTEL_2
;
1356 env
->cpuid_vendor3
= CPUID_VENDOR_INTEL_3
;
1358 env
->cpuid_vendor_override
= def
->vendor_override
;
1359 object_property_set_int(OBJECT(cpu
), def
->level
, "level", &error
);
1360 object_property_set_int(OBJECT(cpu
), def
->family
, "family", &error
);
1361 object_property_set_int(OBJECT(cpu
), def
->model
, "model", &error
);
1362 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", &error
);
1363 env
->cpuid_features
= def
->features
;
1364 env
->cpuid_ext_features
= def
->ext_features
;
1365 env
->cpuid_ext2_features
= def
->ext2_features
;
1366 env
->cpuid_ext3_features
= def
->ext3_features
;
1367 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "xlevel", &error
);
1368 env
->cpuid_kvm_features
= def
->kvm_features
;
1369 env
->cpuid_svm_features
= def
->svm_features
;
1370 env
->cpuid_ext4_features
= def
->ext4_features
;
1371 env
->cpuid_7_0_ebx
= def
->cpuid_7_0_ebx_features
;
1372 env
->cpuid_xlevel2
= def
->xlevel2
;
1373 object_property_set_int(OBJECT(cpu
), (int64_t)def
->tsc_khz
* 1000,
1374 "tsc-frequency", &error
);
1375 if (!kvm_enabled()) {
1376 env
->cpuid_features
&= TCG_FEATURES
;
1377 env
->cpuid_ext_features
&= TCG_EXT_FEATURES
;
1378 env
->cpuid_ext2_features
&= (TCG_EXT2_FEATURES
1379 #ifdef TARGET_X86_64
1380 | CPUID_EXT2_SYSCALL
| CPUID_EXT2_LM
1383 env
->cpuid_ext3_features
&= TCG_EXT3_FEATURES
;
1384 env
->cpuid_svm_features
&= TCG_SVM_FEATURES
;
1386 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", &error
);
1387 if (error_is_set(&error
)) {
1394 #if !defined(CONFIG_USER_ONLY)
1396 void cpu_clear_apic_feature(CPUX86State
*env
)
1398 env
->cpuid_features
&= ~CPUID_APIC
;
1401 #endif /* !CONFIG_USER_ONLY */
1403 /* Initialize list of CPU models, filling some non-static fields if necessary
1405 void x86_cpudef_setup(void)
1408 static const char *model_with_versions
[] = { "qemu32", "qemu64", "athlon" };
1410 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
1411 x86_def_t
*def
= &builtin_x86_defs
[i
];
1412 def
->next
= x86_defs
;
1414 /* Look for specific "cpudef" models that */
1415 /* have the QEMU version in .model_id */
1416 for (j
= 0; j
< ARRAY_SIZE(model_with_versions
); j
++) {
1417 if (strcmp(model_with_versions
[j
], def
->name
) == 0) {
1418 pstrcpy(def
->model_id
, sizeof(def
->model_id
),
1419 "QEMU Virtual CPU version ");
1420 pstrcat(def
->model_id
, sizeof(def
->model_id
),
1421 qemu_get_version());
1430 static void get_cpuid_vendor(CPUX86State
*env
, uint32_t *ebx
,
1431 uint32_t *ecx
, uint32_t *edx
)
1433 *ebx
= env
->cpuid_vendor1
;
1434 *edx
= env
->cpuid_vendor2
;
1435 *ecx
= env
->cpuid_vendor3
;
1437 /* sysenter isn't supported on compatibility mode on AMD, syscall
1438 * isn't supported in compatibility mode on Intel.
1439 * Normally we advertise the actual cpu vendor, but you can override
1440 * this if you want to use KVM's sysenter/syscall emulation
1441 * in compatibility mode and when doing cross vendor migration
1443 if (kvm_enabled() && ! env
->cpuid_vendor_override
) {
1444 host_cpuid(0, 0, NULL
, ebx
, ecx
, edx
);
1448 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
1449 uint32_t *eax
, uint32_t *ebx
,
1450 uint32_t *ecx
, uint32_t *edx
)
1452 /* test if maximum index reached */
1453 if (index
& 0x80000000) {
1454 if (index
> env
->cpuid_xlevel
) {
1455 if (env
->cpuid_xlevel2
> 0) {
1456 /* Handle the Centaur's CPUID instruction. */
1457 if (index
> env
->cpuid_xlevel2
) {
1458 index
= env
->cpuid_xlevel2
;
1459 } else if (index
< 0xC0000000) {
1460 index
= env
->cpuid_xlevel
;
1463 index
= env
->cpuid_xlevel
;
1467 if (index
> env
->cpuid_level
)
1468 index
= env
->cpuid_level
;
1473 *eax
= env
->cpuid_level
;
1474 get_cpuid_vendor(env
, ebx
, ecx
, edx
);
1477 *eax
= env
->cpuid_version
;
1478 *ebx
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1479 *ecx
= env
->cpuid_ext_features
;
1480 *edx
= env
->cpuid_features
;
1481 if (env
->nr_cores
* env
->nr_threads
> 1) {
1482 *ebx
|= (env
->nr_cores
* env
->nr_threads
) << 16;
1483 *edx
|= 1 << 28; /* HTT bit */
1487 /* cache info: needed for Pentium Pro compatibility */
1494 /* cache info: needed for Core compatibility */
1495 if (env
->nr_cores
> 1) {
1496 *eax
= (env
->nr_cores
- 1) << 26;
1501 case 0: /* L1 dcache info */
1507 case 1: /* L1 icache info */
1513 case 2: /* L2 cache info */
1515 if (env
->nr_threads
> 1) {
1516 *eax
|= (env
->nr_threads
- 1) << 14;
1522 default: /* end of info */
1531 /* mwait info: needed for Core compatibility */
1532 *eax
= 0; /* Smallest monitor-line size in bytes */
1533 *ebx
= 0; /* Largest monitor-line size in bytes */
1534 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
1538 /* Thermal and Power Leaf */
1545 /* Structured Extended Feature Flags Enumeration Leaf */
1547 *eax
= 0; /* Maximum ECX value for sub-leaves */
1548 *ebx
= env
->cpuid_7_0_ebx
; /* Feature flags */
1549 *ecx
= 0; /* Reserved */
1550 *edx
= 0; /* Reserved */
1559 /* Direct Cache Access Information Leaf */
1560 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
1566 /* Architectural Performance Monitoring Leaf */
1567 if (kvm_enabled()) {
1568 KVMState
*s
= env
->kvm_state
;
1570 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
1571 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
1572 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
1573 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
1582 /* Processor Extended State */
1583 if (!(env
->cpuid_ext_features
& CPUID_EXT_XSAVE
)) {
1590 if (kvm_enabled()) {
1591 KVMState
*s
= env
->kvm_state
;
1593 *eax
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EAX
);
1594 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EBX
);
1595 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_ECX
);
1596 *edx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EDX
);
1605 *eax
= env
->cpuid_xlevel
;
1606 *ebx
= env
->cpuid_vendor1
;
1607 *edx
= env
->cpuid_vendor2
;
1608 *ecx
= env
->cpuid_vendor3
;
1611 *eax
= env
->cpuid_version
;
1613 *ecx
= env
->cpuid_ext3_features
;
1614 *edx
= env
->cpuid_ext2_features
;
1616 /* The Linux kernel checks for the CMPLegacy bit and
1617 * discards multiple thread information if it is set.
1618 * So dont set it here for Intel to make Linux guests happy.
1620 if (env
->nr_cores
* env
->nr_threads
> 1) {
1621 uint32_t tebx
, tecx
, tedx
;
1622 get_cpuid_vendor(env
, &tebx
, &tecx
, &tedx
);
1623 if (tebx
!= CPUID_VENDOR_INTEL_1
||
1624 tedx
!= CPUID_VENDOR_INTEL_2
||
1625 tecx
!= CPUID_VENDOR_INTEL_3
) {
1626 *ecx
|= 1 << 1; /* CmpLegacy bit */
1633 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
1634 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
1635 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
1636 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
1639 /* cache info (L1 cache) */
1646 /* cache info (L2 cache) */
1653 /* virtual & phys address size in low 2 bytes. */
1654 /* XXX: This value must match the one used in the MMU code. */
1655 if (env
->cpuid_ext2_features
& CPUID_EXT2_LM
) {
1656 /* 64 bit processor */
1657 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1658 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
1660 if (env
->cpuid_features
& CPUID_PSE36
)
1661 *eax
= 0x00000024; /* 36 bits physical */
1663 *eax
= 0x00000020; /* 32 bits physical */
1668 if (env
->nr_cores
* env
->nr_threads
> 1) {
1669 *ecx
|= (env
->nr_cores
* env
->nr_threads
) - 1;
1673 if (env
->cpuid_ext3_features
& CPUID_EXT3_SVM
) {
1674 *eax
= 0x00000001; /* SVM Revision */
1675 *ebx
= 0x00000010; /* nr of ASIDs */
1677 *edx
= env
->cpuid_svm_features
; /* optional features */
1686 *eax
= env
->cpuid_xlevel2
;
1692 /* Support for VIA CPU's CPUID instruction */
1693 *eax
= env
->cpuid_version
;
1696 *edx
= env
->cpuid_ext4_features
;
1701 /* Reserved for the future, and now filled with zero */
1708 /* reserved values: zero */
1717 /* CPUClass::reset() */
1718 static void x86_cpu_reset(CPUState
*s
)
1720 X86CPU
*cpu
= X86_CPU(s
);
1721 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
1722 CPUX86State
*env
= &cpu
->env
;
1725 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
1726 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
1727 log_cpu_state(env
, X86_DUMP_FPU
| X86_DUMP_CCOP
);
1730 xcc
->parent_reset(s
);
1733 memset(env
, 0, offsetof(CPUX86State
, breakpoints
));
1737 env
->old_exception
= -1;
1739 /* init to reset state */
1741 #ifdef CONFIG_SOFTMMU
1742 env
->hflags
|= HF_SOFTMMU_MASK
;
1744 env
->hflags2
|= HF2_GIF_MASK
;
1746 cpu_x86_update_cr0(env
, 0x60000010);
1747 env
->a20_mask
= ~0x0;
1748 env
->smbase
= 0x30000;
1750 env
->idt
.limit
= 0xffff;
1751 env
->gdt
.limit
= 0xffff;
1752 env
->ldt
.limit
= 0xffff;
1753 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
1754 env
->tr
.limit
= 0xffff;
1755 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
1757 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
1758 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
1759 DESC_R_MASK
| DESC_A_MASK
);
1760 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
1761 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1763 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
1764 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1766 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
1767 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1769 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
1770 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1772 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
1773 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1777 env
->regs
[R_EDX
] = env
->cpuid_version
;
1782 for (i
= 0; i
< 8; i
++) {
1787 env
->mxcsr
= 0x1f80;
1789 env
->pat
= 0x0007040600070406ULL
;
1790 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
1792 memset(env
->dr
, 0, sizeof(env
->dr
));
1793 env
->dr
[6] = DR6_FIXED_1
;
1794 env
->dr
[7] = DR7_FIXED_1
;
1795 cpu_breakpoint_remove_all(env
, BP_CPU
);
1796 cpu_watchpoint_remove_all(env
, BP_CPU
);
1798 #if !defined(CONFIG_USER_ONLY)
1799 /* We hard-wire the BSP to the first CPU. */
1800 if (env
->cpu_index
== 0) {
1801 apic_designate_bsp(env
->apic_state
);
1804 env
->halted
= !cpu_is_bsp(cpu
);
1808 #ifndef CONFIG_USER_ONLY
1809 bool cpu_is_bsp(X86CPU
*cpu
)
1811 return cpu_get_apic_base(cpu
->env
.apic_state
) & MSR_IA32_APICBASE_BSP
;
1814 /* TODO: remove me, when reset over QOM tree is implemented */
1815 static void x86_cpu_machine_reset_cb(void *opaque
)
1817 X86CPU
*cpu
= opaque
;
1818 cpu_reset(CPU(cpu
));
1822 static void mce_init(X86CPU
*cpu
)
1824 CPUX86State
*cenv
= &cpu
->env
;
1827 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
1828 && (cenv
->cpuid_features
& (CPUID_MCE
| CPUID_MCA
)) ==
1829 (CPUID_MCE
| CPUID_MCA
)) {
1830 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
1831 cenv
->mcg_ctl
= ~(uint64_t)0;
1832 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
1833 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
1838 void x86_cpu_realize(Object
*obj
, Error
**errp
)
1840 X86CPU
*cpu
= X86_CPU(obj
);
1842 #ifndef CONFIG_USER_ONLY
1843 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
1847 qemu_init_vcpu(&cpu
->env
);
1848 cpu_reset(CPU(cpu
));
1851 static void x86_cpu_initfn(Object
*obj
)
1853 X86CPU
*cpu
= X86_CPU(obj
);
1854 CPUX86State
*env
= &cpu
->env
;
1859 object_property_add(obj
, "family", "int",
1860 x86_cpuid_version_get_family
,
1861 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
1862 object_property_add(obj
, "model", "int",
1863 x86_cpuid_version_get_model
,
1864 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
1865 object_property_add(obj
, "stepping", "int",
1866 x86_cpuid_version_get_stepping
,
1867 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
1868 object_property_add(obj
, "level", "int",
1869 x86_cpuid_get_level
,
1870 x86_cpuid_set_level
, NULL
, NULL
, NULL
);
1871 object_property_add(obj
, "xlevel", "int",
1872 x86_cpuid_get_xlevel
,
1873 x86_cpuid_set_xlevel
, NULL
, NULL
, NULL
);
1874 object_property_add_str(obj
, "vendor",
1875 x86_cpuid_get_vendor
,
1876 x86_cpuid_set_vendor
, NULL
);
1877 object_property_add_str(obj
, "model-id",
1878 x86_cpuid_get_model_id
,
1879 x86_cpuid_set_model_id
, NULL
);
1880 object_property_add(obj
, "tsc-frequency", "int",
1881 x86_cpuid_get_tsc_freq
,
1882 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
1884 env
->cpuid_apic_id
= env
->cpu_index
;
1886 /* init various static tables used in TCG mode */
1887 if (tcg_enabled() && !inited
) {
1889 optimize_flags_init();
1890 #ifndef CONFIG_USER_ONLY
1891 cpu_set_debug_excp_handler(breakpoint_handler
);
1896 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
1898 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1899 CPUClass
*cc
= CPU_CLASS(oc
);
1901 xcc
->parent_reset
= cc
->reset
;
1902 cc
->reset
= x86_cpu_reset
;
1905 static const TypeInfo x86_cpu_type_info
= {
1906 .name
= TYPE_X86_CPU
,
1908 .instance_size
= sizeof(X86CPU
),
1909 .instance_init
= x86_cpu_initfn
,
1911 .class_size
= sizeof(X86CPUClass
),
1912 .class_init
= x86_cpu_common_class_init
,
1915 static void x86_cpu_register_types(void)
1917 type_register_static(&x86_cpu_type_info
);
1920 type_init(x86_cpu_register_types
)