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bootindex: add del_boot_device_path function
[qemu/ar7.git] / hw / usb / hcd-uhci.c
blob5b88f3070f4230a956dc1622ebd11157f2716afe
1 /*
2 * USB UHCI controller emulation
3 *
4 * Copyright (c) 2005 Fabrice Bellard
5 *
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * THE SOFTWARE.
27 */
28 #include "hw/hw.h"
29 #include "hw/usb.h"
30 #include "hw/usb/uhci-regs.h"
31 #include "hw/pci/pci.h"
32 #include "qemu/timer.h"
33 #include "qemu/iov.h"
34 #include "sysemu/dma.h"
35 #include "trace.h"
36 #include "qemu/main-loop.h"
37
38 //#define DEBUG
39 //#define DEBUG_DUMP_DATA
40
41 #define FRAME_TIMER_FREQ 1000
42
43 #define FRAME_MAX_LOOPS 256
44
45 /* Must be large enough to handle 10 frame delay for initial isoc requests */
46 #define QH_VALID 32
47
48 #define MAX_FRAMES_PER_TICK (QH_VALID / 2)
49
50 #define NB_PORTS 2
51
52 enum {
53 TD_RESULT_STOP_FRAME = 10,
54 TD_RESULT_COMPLETE,
55 TD_RESULT_NEXT_QH,
56 TD_RESULT_ASYNC_START,
57 TD_RESULT_ASYNC_CONT,
58 };
59
60 typedef struct UHCIState UHCIState;
61 typedef struct UHCIAsync UHCIAsync;
62 typedef struct UHCIQueue UHCIQueue;
63 typedef struct UHCIInfo UHCIInfo;
64 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass;
65
66 struct UHCIInfo {
67 const char *name;
68 uint16_t vendor_id;
69 uint16_t device_id;
70 uint8_t revision;
71 uint8_t irq_pin;
72 int (*initfn)(PCIDevice *dev);
73 bool unplug;
74 };
75
76 struct UHCIPCIDeviceClass {
77 PCIDeviceClass parent_class;
78 UHCIInfo info;
79 };
80
81 /*
82 * Pending async transaction.
83 * 'packet' must be the first field because completion
84 * handler does "(UHCIAsync *) pkt" cast.
85 */
86
87 struct UHCIAsync {
88 USBPacket packet;
89 uint8_t static_buf[64]; /* 64 bytes is enough, except for isoc packets */
90 uint8_t *buf;
91 UHCIQueue *queue;
92 QTAILQ_ENTRY(UHCIAsync) next;
93 uint32_t td_addr;
94 uint8_t done;
95 };
96
97 struct UHCIQueue {
98 uint32_t qh_addr;
99 uint32_t token;
100 UHCIState *uhci;
101 USBEndpoint *ep;
102 QTAILQ_ENTRY(UHCIQueue) next;
103 QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs;
104 int8_t valid;
105 };
106
107 typedef struct UHCIPort {
108 USBPort port;
109 uint16_t ctrl;
110 } UHCIPort;
111
112 struct UHCIState {
113 PCIDevice dev;
114 MemoryRegion io_bar;
115 USBBus bus; /* Note unused when we're a companion controller */
116 uint16_t cmd; /* cmd register */
117 uint16_t status;
118 uint16_t intr; /* interrupt enable register */
119 uint16_t frnum; /* frame number */
120 uint32_t fl_base_addr; /* frame list base address */
121 uint8_t sof_timing;
122 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
123 int64_t expire_time;
124 QEMUTimer *frame_timer;
125 QEMUBH *bh;
126 uint32_t frame_bytes;
127 uint32_t frame_bandwidth;
128 bool completions_only;
129 UHCIPort ports[NB_PORTS];
130
131 /* Interrupts that should be raised at the end of the current frame. */
132 uint32_t pending_int_mask;
133
134 /* Active packets */
135 QTAILQ_HEAD(, UHCIQueue) queues;
136 uint8_t num_ports_vmstate;
137
138 /* Properties */
139 char *masterbus;
140 uint32_t firstport;
141 uint32_t maxframes;
142 };
143
144 typedef struct UHCI_TD {
145 uint32_t link;
146 uint32_t ctrl; /* see TD_CTRL_xxx */
147 uint32_t token;
148 uint32_t buffer;
149 } UHCI_TD;
150
151 typedef struct UHCI_QH {
152 uint32_t link;
153 uint32_t el_link;
154 } UHCI_QH;
155
156 static void uhci_async_cancel(UHCIAsync *async);
157 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td);
158 static void uhci_resume(void *opaque);
159
160 static inline int32_t uhci_queue_token(UHCI_TD *td)
161 {
162 if ((td->token & (0xf << 15)) == 0) {
163 /* ctrl ep, cover ep and dev, not pid! */
164 return td->token & 0x7ff00;
165 } else {
166 /* covers ep, dev, pid -> identifies the endpoint */
167 return td->token & 0x7ffff;
168 }
169 }
170
171 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td,
172 USBEndpoint *ep)
173 {
174 UHCIQueue *queue;
175
176 queue = g_new0(UHCIQueue, 1);
177 queue->uhci = s;
178 queue->qh_addr = qh_addr;
179 queue->token = uhci_queue_token(td);
180 queue->ep = ep;
181 QTAILQ_INIT(&queue->asyncs);
182 QTAILQ_INSERT_HEAD(&s->queues, queue, next);
183 queue->valid = QH_VALID;
184 trace_usb_uhci_queue_add(queue->token);
185 return queue;
186 }
187
188 static void uhci_queue_free(UHCIQueue *queue, const char *reason)
189 {
190 UHCIState *s = queue->uhci;
191 UHCIAsync *async;
192
193 while (!QTAILQ_EMPTY(&queue->asyncs)) {
194 async = QTAILQ_FIRST(&queue->asyncs);
195 uhci_async_cancel(async);
196 }
197 usb_device_ep_stopped(queue->ep->dev, queue->ep);
198
199 trace_usb_uhci_queue_del(queue->token, reason);
200 QTAILQ_REMOVE(&s->queues, queue, next);
201 g_free(queue);
202 }
203
204 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td)
205 {
206 uint32_t token = uhci_queue_token(td);
207 UHCIQueue *queue;
208
209 QTAILQ_FOREACH(queue, &s->queues, next) {
210 if (queue->token == token) {
211 return queue;
212 }
213 }
214 return NULL;
215 }
216
217 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td,
218 uint32_t td_addr, bool queuing)
219 {
220 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs);
221 uint32_t queue_token_addr = (queue->token >> 8) & 0x7f;
222
223 return queue->qh_addr == qh_addr &&
224 queue->token == uhci_queue_token(td) &&
225 queue_token_addr == queue->ep->dev->addr &&
226 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL ||
227 first->td_addr == td_addr);
228 }
229
230 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr)
231 {
232 UHCIAsync *async = g_new0(UHCIAsync, 1);
233
234 async->queue = queue;
235 async->td_addr = td_addr;
236 usb_packet_init(&async->packet);
237 trace_usb_uhci_packet_add(async->queue->token, async->td_addr);
238
239 return async;
240 }
241
242 static void uhci_async_free(UHCIAsync *async)
243 {
244 trace_usb_uhci_packet_del(async->queue->token, async->td_addr);
245 usb_packet_cleanup(&async->packet);
246 if (async->buf != async->static_buf) {
247 g_free(async->buf);
248 }
249 g_free(async);
250 }
251
252 static void uhci_async_link(UHCIAsync *async)
253 {
254 UHCIQueue *queue = async->queue;
255 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
256 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr);
257 }
258
259 static void uhci_async_unlink(UHCIAsync *async)
260 {
261 UHCIQueue *queue = async->queue;
262 QTAILQ_REMOVE(&queue->asyncs, async, next);
263 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr);
264 }
265
266 static void uhci_async_cancel(UHCIAsync *async)
267 {
268 uhci_async_unlink(async);
269 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr,
270 async->done);
271 if (!async->done)
272 usb_cancel_packet(&async->packet);
273 uhci_async_free(async);
274 }
275
276 /*
277 * Mark all outstanding async packets as invalid.
278 * This is used for canceling them when TDs are removed by the HCD.
279 */
280 static void uhci_async_validate_begin(UHCIState *s)
281 {
282 UHCIQueue *queue;
283
284 QTAILQ_FOREACH(queue, &s->queues, next) {
285 queue->valid--;
286 }
287 }
288
289 /*
290 * Cancel async packets that are no longer valid
291 */
292 static void uhci_async_validate_end(UHCIState *s)
293 {
294 UHCIQueue *queue, *n;
295
296 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
297 if (!queue->valid) {
298 uhci_queue_free(queue, "validate-end");
299 }
300 }
301 }
302
303 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
304 {
305 UHCIQueue *queue, *n;
306
307 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
308 if (queue->ep->dev == dev) {
309 uhci_queue_free(queue, "cancel-device");
310 }
311 }
312 }
313
314 static void uhci_async_cancel_all(UHCIState *s)
315 {
316 UHCIQueue *queue, *nq;
317
318 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) {
319 uhci_queue_free(queue, "cancel-all");
320 }
321 }
322
323 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr)
324 {
325 UHCIQueue *queue;
326 UHCIAsync *async;
327
328 QTAILQ_FOREACH(queue, &s->queues, next) {
329 QTAILQ_FOREACH(async, &queue->asyncs, next) {
330 if (async->td_addr == td_addr) {
331 return async;
332 }
333 }
334 }
335 return NULL;
336 }
337
338 static void uhci_update_irq(UHCIState *s)
339 {
340 int level;
341 if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
342 ((s->status2 & 2) && (s->intr & (1 << 3))) ||
343 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
344 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
345 (s->status & UHCI_STS_HSERR) ||
346 (s->status & UHCI_STS_HCPERR)) {
347 level = 1;
348 } else {
349 level = 0;
350 }
351 pci_set_irq(&s->dev, level);
352 }
353
354 static void uhci_reset(void *opaque)
355 {
356 UHCIState *s = opaque;
357 uint8_t *pci_conf;
358 int i;
359 UHCIPort *port;
360
361 trace_usb_uhci_reset();
362
363 pci_conf = s->dev.config;
364
365 pci_conf[0x6a] = 0x01; /* usb clock */
366 pci_conf[0x6b] = 0x00;
367 s->cmd = 0;
368 s->status = 0;
369 s->status2 = 0;
370 s->intr = 0;
371 s->fl_base_addr = 0;
372 s->sof_timing = 64;
373
374 for(i = 0; i < NB_PORTS; i++) {
375 port = &s->ports[i];
376 port->ctrl = 0x0080;
377 if (port->port.dev && port->port.dev->attached) {
378 usb_port_reset(&port->port);
379 }
380 }
381
382 uhci_async_cancel_all(s);
383 qemu_bh_cancel(s->bh);
384 uhci_update_irq(s);
385 }
386
387 static const VMStateDescription vmstate_uhci_port = {
388 .name = "uhci port",
389 .version_id = 1,
390 .minimum_version_id = 1,
391 .fields = (VMStateField[]) {
392 VMSTATE_UINT16(ctrl, UHCIPort),
393 VMSTATE_END_OF_LIST()
394 }
395 };
396
397 static int uhci_post_load(void *opaque, int version_id)
398 {
399 UHCIState *s = opaque;
400
401 if (version_id < 2) {
402 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
403 (get_ticks_per_sec() / FRAME_TIMER_FREQ);
404 }
405 return 0;
406 }
407
408 static const VMStateDescription vmstate_uhci = {
409 .name = "uhci",
410 .version_id = 3,
411 .minimum_version_id = 1,
412 .post_load = uhci_post_load,
413 .fields = (VMStateField[]) {
414 VMSTATE_PCI_DEVICE(dev, UHCIState),
415 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState),
416 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
417 vmstate_uhci_port, UHCIPort),
418 VMSTATE_UINT16(cmd, UHCIState),
419 VMSTATE_UINT16(status, UHCIState),
420 VMSTATE_UINT16(intr, UHCIState),
421 VMSTATE_UINT16(frnum, UHCIState),
422 VMSTATE_UINT32(fl_base_addr, UHCIState),
423 VMSTATE_UINT8(sof_timing, UHCIState),
424 VMSTATE_UINT8(status2, UHCIState),
425 VMSTATE_TIMER(frame_timer, UHCIState),
426 VMSTATE_INT64_V(expire_time, UHCIState, 2),
427 VMSTATE_UINT32_V(pending_int_mask, UHCIState, 3),
428 VMSTATE_END_OF_LIST()
429 }
430 };
431
432 static void uhci_port_write(void *opaque, hwaddr addr,
433 uint64_t val, unsigned size)
434 {
435 UHCIState *s = opaque;
436
437 trace_usb_uhci_mmio_writew(addr, val);
438
439 switch(addr) {
440 case 0x00:
441 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
442 /* start frame processing */
443 trace_usb_uhci_schedule_start();
444 s->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
445 (get_ticks_per_sec() / FRAME_TIMER_FREQ);
446 timer_mod(s->frame_timer, s->expire_time);
447 s->status &= ~UHCI_STS_HCHALTED;
448 } else if (!(val & UHCI_CMD_RS)) {
449 s->status |= UHCI_STS_HCHALTED;
450 }
451 if (val & UHCI_CMD_GRESET) {
452 UHCIPort *port;
453 int i;
454
455 /* send reset on the USB bus */
456 for(i = 0; i < NB_PORTS; i++) {
457 port = &s->ports[i];
458 usb_device_reset(port->port.dev);
459 }
460 uhci_reset(s);
461 return;
462 }
463 if (val & UHCI_CMD_HCRESET) {
464 uhci_reset(s);
465 return;
466 }
467 s->cmd = val;
468 if (val & UHCI_CMD_EGSM) {
469 if ((s->ports[0].ctrl & UHCI_PORT_RD) ||
470 (s->ports[1].ctrl & UHCI_PORT_RD)) {
471 uhci_resume(s);
472 }
473 }
474 break;
475 case 0x02:
476 s->status &= ~val;
477 /* XXX: the chip spec is not coherent, so we add a hidden
478 register to distinguish between IOC and SPD */
479 if (val & UHCI_STS_USBINT)
480 s->status2 = 0;
481 uhci_update_irq(s);
482 break;
483 case 0x04:
484 s->intr = val;
485 uhci_update_irq(s);
486 break;
487 case 0x06:
488 if (s->status & UHCI_STS_HCHALTED)
489 s->frnum = val & 0x7ff;
490 break;
491 case 0x08:
492 s->fl_base_addr &= 0xffff0000;
493 s->fl_base_addr |= val & ~0xfff;
494 break;
495 case 0x0a:
496 s->fl_base_addr &= 0x0000ffff;
497 s->fl_base_addr |= (val << 16);
498 break;
499 case 0x0c:
500 s->sof_timing = val & 0xff;
501 break;
502 case 0x10 ... 0x1f:
503 {
504 UHCIPort *port;
505 USBDevice *dev;
506 int n;
507
508 n = (addr >> 1) & 7;
509 if (n >= NB_PORTS)
510 return;
511 port = &s->ports[n];
512 dev = port->port.dev;
513 if (dev && dev->attached) {
514 /* port reset */
515 if ( (val & UHCI_PORT_RESET) &&
516 !(port->ctrl & UHCI_PORT_RESET) ) {
517 usb_device_reset(dev);
518 }
519 }
520 port->ctrl &= UHCI_PORT_READ_ONLY;
521 /* enabled may only be set if a device is connected */
522 if (!(port->ctrl & UHCI_PORT_CCS)) {
523 val &= ~UHCI_PORT_EN;
524 }
525 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
526 /* some bits are reset when a '1' is written to them */
527 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
528 }
529 break;
530 }
531 }
532
533 static uint64_t uhci_port_read(void *opaque, hwaddr addr, unsigned size)
534 {
535 UHCIState *s = opaque;
536 uint32_t val;
537
538 switch(addr) {
539 case 0x00:
540 val = s->cmd;
541 break;
542 case 0x02:
543 val = s->status;
544 break;
545 case 0x04:
546 val = s->intr;
547 break;
548 case 0x06:
549 val = s->frnum;
550 break;
551 case 0x08:
552 val = s->fl_base_addr & 0xffff;
553 break;
554 case 0x0a:
555 val = (s->fl_base_addr >> 16) & 0xffff;
556 break;
557 case 0x0c:
558 val = s->sof_timing;
559 break;
560 case 0x10 ... 0x1f:
561 {
562 UHCIPort *port;
563 int n;
564 n = (addr >> 1) & 7;
565 if (n >= NB_PORTS)
566 goto read_default;
567 port = &s->ports[n];
568 val = port->ctrl;
569 }
570 break;
571 default:
572 read_default:
573 val = 0xff7f; /* disabled port */
574 break;
575 }
576
577 trace_usb_uhci_mmio_readw(addr, val);
578
579 return val;
580 }
581
582 /* signal resume if controller suspended */
583 static void uhci_resume (void *opaque)
584 {
585 UHCIState *s = (UHCIState *)opaque;
586
587 if (!s)
588 return;
589
590 if (s->cmd & UHCI_CMD_EGSM) {
591 s->cmd |= UHCI_CMD_FGR;
592 s->status |= UHCI_STS_RD;
593 uhci_update_irq(s);
594 }
595 }
596
597 static void uhci_attach(USBPort *port1)
598 {
599 UHCIState *s = port1->opaque;
600 UHCIPort *port = &s->ports[port1->index];
601
602 /* set connect status */
603 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
604
605 /* update speed */
606 if (port->port.dev->speed == USB_SPEED_LOW) {
607 port->ctrl |= UHCI_PORT_LSDA;
608 } else {
609 port->ctrl &= ~UHCI_PORT_LSDA;
610 }
611
612 uhci_resume(s);
613 }
614
615 static void uhci_detach(USBPort *port1)
616 {
617 UHCIState *s = port1->opaque;
618 UHCIPort *port = &s->ports[port1->index];
619
620 uhci_async_cancel_device(s, port1->dev);
621
622 /* set connect status */
623 if (port->ctrl & UHCI_PORT_CCS) {
624 port->ctrl &= ~UHCI_PORT_CCS;
625 port->ctrl |= UHCI_PORT_CSC;
626 }
627 /* disable port */
628 if (port->ctrl & UHCI_PORT_EN) {
629 port->ctrl &= ~UHCI_PORT_EN;
630 port->ctrl |= UHCI_PORT_ENC;
631 }
632
633 uhci_resume(s);
634 }
635
636 static void uhci_child_detach(USBPort *port1, USBDevice *child)
637 {
638 UHCIState *s = port1->opaque;
639
640 uhci_async_cancel_device(s, child);
641 }
642
643 static void uhci_wakeup(USBPort *port1)
644 {
645 UHCIState *s = port1->opaque;
646 UHCIPort *port = &s->ports[port1->index];
647
648 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
649 port->ctrl |= UHCI_PORT_RD;
650 uhci_resume(s);
651 }
652 }
653
654 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
655 {
656 USBDevice *dev;
657 int i;
658
659 for (i = 0; i < NB_PORTS; i++) {
660 UHCIPort *port = &s->ports[i];
661 if (!(port->ctrl & UHCI_PORT_EN)) {
662 continue;
663 }
664 dev = usb_find_device(&port->port, addr);
665 if (dev != NULL) {
666 return dev;
667 }
668 }
669 return NULL;
670 }
671
672 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link)
673 {
674 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td));
675 le32_to_cpus(&td->link);
676 le32_to_cpus(&td->ctrl);
677 le32_to_cpus(&td->token);
678 le32_to_cpus(&td->buffer);
679 }
680
681 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr,
682 int status, uint32_t *int_mask)
683 {
684 uint32_t queue_token = uhci_queue_token(td);
685 int ret;
686
687 switch (status) {
688 case USB_RET_NAK:
689 td->ctrl |= TD_CTRL_NAK;
690 return TD_RESULT_NEXT_QH;
691
692 case USB_RET_STALL:
693 td->ctrl |= TD_CTRL_STALL;
694 trace_usb_uhci_packet_complete_stall(queue_token, td_addr);
695 ret = TD_RESULT_NEXT_QH;
696 break;
697
698 case USB_RET_BABBLE:
699 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
700 /* frame interrupted */
701 trace_usb_uhci_packet_complete_babble(queue_token, td_addr);
702 ret = TD_RESULT_STOP_FRAME;
703 break;
704
705 case USB_RET_IOERROR:
706 case USB_RET_NODEV:
707 default:
708 td->ctrl |= TD_CTRL_TIMEOUT;
709 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT);
710 trace_usb_uhci_packet_complete_error(queue_token, td_addr);
711 ret = TD_RESULT_NEXT_QH;
712 break;
713 }
714
715 td->ctrl &= ~TD_CTRL_ACTIVE;
716 s->status |= UHCI_STS_USBERR;
717 if (td->ctrl & TD_CTRL_IOC) {
718 *int_mask |= 0x01;
719 }
720 uhci_update_irq(s);
721 return ret;
722 }
723
724 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
725 {
726 int len = 0, max_len;
727 uint8_t pid;
728
729 max_len = ((td->token >> 21) + 1) & 0x7ff;
730 pid = td->token & 0xff;
731
732 if (td->ctrl & TD_CTRL_IOS)
733 td->ctrl &= ~TD_CTRL_ACTIVE;
734
735 if (async->packet.status != USB_RET_SUCCESS) {
736 return uhci_handle_td_error(s, td, async->td_addr,
737 async->packet.status, int_mask);
738 }
739
740 len = async->packet.actual_length;
741 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
742
743 /* The NAK bit may have been set by a previous frame, so clear it
744 here. The docs are somewhat unclear, but win2k relies on this
745 behavior. */
746 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
747 if (td->ctrl & TD_CTRL_IOC)
748 *int_mask |= 0x01;
749
750 if (pid == USB_TOKEN_IN) {
751 pci_dma_write(&s->dev, td->buffer, async->buf, len);
752 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
753 *int_mask |= 0x02;
754 /* short packet: do not update QH */
755 trace_usb_uhci_packet_complete_shortxfer(async->queue->token,
756 async->td_addr);
757 return TD_RESULT_NEXT_QH;
758 }
759 }
760
761 /* success */
762 trace_usb_uhci_packet_complete_success(async->queue->token,
763 async->td_addr);
764 return TD_RESULT_COMPLETE;
765 }
766
767 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
768 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask)
769 {
770 int ret, max_len;
771 bool spd;
772 bool queuing = (q != NULL);
773 uint8_t pid = td->token & 0xff;
774 UHCIAsync *async = uhci_async_find_td(s, td_addr);
775
776 if (async) {
777 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) {
778 assert(q == NULL || q == async->queue);
779 q = async->queue;
780 } else {
781 uhci_queue_free(async->queue, "guest re-used pending td");
782 async = NULL;
783 }
784 }
785
786 if (q == NULL) {
787 q = uhci_queue_find(s, td);
788 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) {
789 uhci_queue_free(q, "guest re-used qh");
790 q = NULL;
791 }
792 }
793
794 if (q) {
795 q->valid = QH_VALID;
796 }
797
798 /* Is active ? */
799 if (!(td->ctrl & TD_CTRL_ACTIVE)) {
800 if (async) {
801 /* Guest marked a pending td non-active, cancel the queue */
802 uhci_queue_free(async->queue, "pending td non-active");
803 }
804 /*
805 * ehci11d spec page 22: "Even if the Active bit in the TD is already
806 * cleared when the TD is fetched ... an IOC interrupt is generated"
807 */
808 if (td->ctrl & TD_CTRL_IOC) {
809 *int_mask |= 0x01;
810 }
811 return TD_RESULT_NEXT_QH;
812 }
813
814 if (async) {
815 if (queuing) {
816 /* we are busy filling the queue, we are not prepared
817 to consume completed packages then, just leave them
818 in async state */
819 return TD_RESULT_ASYNC_CONT;
820 }
821 if (!async->done) {
822 UHCI_TD last_td;
823 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head);
824 /*
825 * While we are waiting for the current td to complete, the guest
826 * may have added more tds to the queue. Note we re-read the td
827 * rather then caching it, as we want to see guest made changes!
828 */
829 uhci_read_td(s, &last_td, last->td_addr);
830 uhci_queue_fill(async->queue, &last_td);
831
832 return TD_RESULT_ASYNC_CONT;
833 }
834 uhci_async_unlink(async);
835 goto done;
836 }
837
838 if (s->completions_only) {
839 return TD_RESULT_ASYNC_CONT;
840 }
841
842 /* Allocate new packet */
843 if (q == NULL) {
844 USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
845 USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
846
847 if (ep == NULL) {
848 return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV,
849 int_mask);
850 }
851 q = uhci_queue_new(s, qh_addr, td, ep);
852 }
853 async = uhci_async_alloc(q, td_addr);
854
855 max_len = ((td->token >> 21) + 1) & 0x7ff;
856 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0);
857 usb_packet_setup(&async->packet, pid, q->ep, 0, td_addr, spd,
858 (td->ctrl & TD_CTRL_IOC) != 0);
859 if (max_len <= sizeof(async->static_buf)) {
860 async->buf = async->static_buf;
861 } else {
862 async->buf = g_malloc(max_len);
863 }
864 usb_packet_addbuf(&async->packet, async->buf, max_len);
865
866 switch(pid) {
867 case USB_TOKEN_OUT:
868 case USB_TOKEN_SETUP:
869 pci_dma_read(&s->dev, td->buffer, async->buf, max_len);
870 usb_handle_packet(q->ep->dev, &async->packet);
871 if (async->packet.status == USB_RET_SUCCESS) {
872 async->packet.actual_length = max_len;
873 }
874 break;
875
876 case USB_TOKEN_IN:
877 usb_handle_packet(q->ep->dev, &async->packet);
878 break;
879
880 default:
881 /* invalid pid : frame interrupted */
882 uhci_async_free(async);
883 s->status |= UHCI_STS_HCPERR;
884 uhci_update_irq(s);
885 return TD_RESULT_STOP_FRAME;
886 }
887
888 if (async->packet.status == USB_RET_ASYNC) {
889 uhci_async_link(async);
890 if (!queuing) {
891 uhci_queue_fill(q, td);
892 }
893 return TD_RESULT_ASYNC_START;
894 }
895
896 done:
897 ret = uhci_complete_td(s, td, async, int_mask);
898 uhci_async_free(async);
899 return ret;
900 }
901
902 static void uhci_async_complete(USBPort *port, USBPacket *packet)
903 {
904 UHCIAsync *async = container_of(packet, UHCIAsync, packet);
905 UHCIState *s = async->queue->uhci;
906
907 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
908 uhci_async_cancel(async);
909 return;
910 }
911
912 async->done = 1;
913 /* Force processing of this packet *now*, needed for migration */
914 s->completions_only = true;
915 qemu_bh_schedule(s->bh);
916 }
917
918 static int is_valid(uint32_t link)
919 {
920 return (link & 1) == 0;
921 }
922
923 static int is_qh(uint32_t link)
924 {
925 return (link & 2) != 0;
926 }
927
928 static int depth_first(uint32_t link)
929 {
930 return (link & 4) != 0;
931 }
932
933 /* QH DB used for detecting QH loops */
934 #define UHCI_MAX_QUEUES 128
935 typedef struct {
936 uint32_t addr[UHCI_MAX_QUEUES];
937 int count;
938 } QhDb;
939
940 static void qhdb_reset(QhDb *db)
941 {
942 db->count = 0;
943 }
944
945 /* Add QH to DB. Returns 1 if already present or DB is full. */
946 static int qhdb_insert(QhDb *db, uint32_t addr)
947 {
948 int i;
949 for (i = 0; i < db->count; i++)
950 if (db->addr[i] == addr)
951 return 1;
952
953 if (db->count >= UHCI_MAX_QUEUES)
954 return 1;
955
956 db->addr[db->count++] = addr;
957 return 0;
958 }
959
960 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td)
961 {
962 uint32_t int_mask = 0;
963 uint32_t plink = td->link;
964 UHCI_TD ptd;
965 int ret;
966
967 while (is_valid(plink)) {
968 uhci_read_td(q->uhci, &ptd, plink);
969 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
970 break;
971 }
972 if (uhci_queue_token(&ptd) != q->token) {
973 break;
974 }
975 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
976 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask);
977 if (ret == TD_RESULT_ASYNC_CONT) {
978 break;
979 }
980 assert(ret == TD_RESULT_ASYNC_START);
981 assert(int_mask == 0);
982 plink = ptd.link;
983 }
984 usb_device_flush_ep_queue(q->ep->dev, q->ep);
985 }
986
987 static void uhci_process_frame(UHCIState *s)
988 {
989 uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
990 uint32_t curr_qh, td_count = 0;
991 int cnt, ret;
992 UHCI_TD td;
993 UHCI_QH qh;
994 QhDb qhdb;
995
996 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
997
998 pci_dma_read(&s->dev, frame_addr, &link, 4);
999 le32_to_cpus(&link);
1000
1001 int_mask = 0;
1002 curr_qh = 0;
1003
1004 qhdb_reset(&qhdb);
1005
1006 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
1007 if (!s->completions_only && s->frame_bytes >= s->frame_bandwidth) {
1008 /* We've reached the usb 1.1 bandwidth, which is
1009 1280 bytes/frame, stop processing */
1010 trace_usb_uhci_frame_stop_bandwidth();
1011 break;
1012 }
1013 if (is_qh(link)) {
1014 /* QH */
1015 trace_usb_uhci_qh_load(link & ~0xf);
1016
1017 if (qhdb_insert(&qhdb, link)) {
1018 /*
1019 * We're going in circles. Which is not a bug because
1020 * HCD is allowed to do that as part of the BW management.
1021 *
1022 * Stop processing here if no transaction has been done
1023 * since we've been here last time.
1024 */
1025 if (td_count == 0) {
1026 trace_usb_uhci_frame_loop_stop_idle();
1027 break;
1028 } else {
1029 trace_usb_uhci_frame_loop_continue();
1030 td_count = 0;
1031 qhdb_reset(&qhdb);
1032 qhdb_insert(&qhdb, link);
1033 }
1034 }
1035
1036 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
1037 le32_to_cpus(&qh.link);
1038 le32_to_cpus(&qh.el_link);
1039
1040 if (!is_valid(qh.el_link)) {
1041 /* QH w/o elements */
1042 curr_qh = 0;
1043 link = qh.link;
1044 } else {
1045 /* QH with elements */
1046 curr_qh = link;
1047 link = qh.el_link;
1048 }
1049 continue;
1050 }
1051
1052 /* TD */
1053 uhci_read_td(s, &td, link);
1054 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token);
1055
1056 old_td_ctrl = td.ctrl;
1057 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask);
1058 if (old_td_ctrl != td.ctrl) {
1059 /* update the status bits of the TD */
1060 val = cpu_to_le32(td.ctrl);
1061 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
1062 }
1063
1064 switch (ret) {
1065 case TD_RESULT_STOP_FRAME: /* interrupted frame */
1066 goto out;
1067
1068 case TD_RESULT_NEXT_QH:
1069 case TD_RESULT_ASYNC_CONT:
1070 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf);
1071 link = curr_qh ? qh.link : td.link;
1072 continue;
1073
1074 case TD_RESULT_ASYNC_START:
1075 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf);
1076 link = curr_qh ? qh.link : td.link;
1077 continue;
1078
1079 case TD_RESULT_COMPLETE:
1080 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf);
1081 link = td.link;
1082 td_count++;
1083 s->frame_bytes += (td.ctrl & 0x7ff) + 1;
1084
1085 if (curr_qh) {
1086 /* update QH element link */
1087 qh.el_link = link;
1088 val = cpu_to_le32(qh.el_link);
1089 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
1090
1091 if (!depth_first(link)) {
1092 /* done with this QH */
1093 curr_qh = 0;
1094 link = qh.link;
1095 }
1096 }
1097 break;
1098
1099 default:
1100 assert(!"unknown return code");
1101 }
1102
1103 /* go to the next entry */
1104 }
1105
1106 out:
1107 s->pending_int_mask |= int_mask;
1108 }
1109
1110 static void uhci_bh(void *opaque)
1111 {
1112 UHCIState *s = opaque;
1113 uhci_process_frame(s);
1114 }
1115
1116 static void uhci_frame_timer(void *opaque)
1117 {
1118 UHCIState *s = opaque;
1119 uint64_t t_now, t_last_run;
1120 int i, frames;
1121 const uint64_t frame_t = get_ticks_per_sec() / FRAME_TIMER_FREQ;
1122
1123 s->completions_only = false;
1124 qemu_bh_cancel(s->bh);
1125
1126 if (!(s->cmd & UHCI_CMD_RS)) {
1127 /* Full stop */
1128 trace_usb_uhci_schedule_stop();
1129 timer_del(s->frame_timer);
1130 uhci_async_cancel_all(s);
1131 /* set hchalted bit in status - UHCI11D 2.1.2 */
1132 s->status |= UHCI_STS_HCHALTED;
1133 return;
1134 }
1135
1136 /* We still store expire_time in our state, for migration */
1137 t_last_run = s->expire_time - frame_t;
1138 t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1139
1140 /* Process up to MAX_FRAMES_PER_TICK frames */
1141 frames = (t_now - t_last_run) / frame_t;
1142 if (frames > s->maxframes) {
1143 int skipped = frames - s->maxframes;
1144 s->expire_time += skipped * frame_t;
1145 s->frnum = (s->frnum + skipped) & 0x7ff;
1146 frames -= skipped;
1147 }
1148 if (frames > MAX_FRAMES_PER_TICK) {
1149 frames = MAX_FRAMES_PER_TICK;
1150 }
1151
1152 for (i = 0; i < frames; i++) {
1153 s->frame_bytes = 0;
1154 trace_usb_uhci_frame_start(s->frnum);
1155 uhci_async_validate_begin(s);
1156 uhci_process_frame(s);
1157 uhci_async_validate_end(s);
1158 /* The spec says frnum is the frame currently being processed, and
1159 * the guest must look at frnum - 1 on interrupt, so inc frnum now */
1160 s->frnum = (s->frnum + 1) & 0x7ff;
1161 s->expire_time += frame_t;
1162 }
1163
1164 /* Complete the previous frame(s) */
1165 if (s->pending_int_mask) {
1166 s->status2 |= s->pending_int_mask;
1167 s->status |= UHCI_STS_USBINT;
1168 uhci_update_irq(s);
1169 }
1170 s->pending_int_mask = 0;
1171
1172 timer_mod(s->frame_timer, t_now + frame_t);
1173 }
1174
1175 static const MemoryRegionOps uhci_ioport_ops = {
1176 .read = uhci_port_read,
1177 .write = uhci_port_write,
1178 .valid.min_access_size = 1,
1179 .valid.max_access_size = 4,
1180 .impl.min_access_size = 2,
1181 .impl.max_access_size = 2,
1182 .endianness = DEVICE_LITTLE_ENDIAN,
1183 };
1184
1185 static USBPortOps uhci_port_ops = {
1186 .attach = uhci_attach,
1187 .detach = uhci_detach,
1188 .child_detach = uhci_child_detach,
1189 .wakeup = uhci_wakeup,
1190 .complete = uhci_async_complete,
1191 };
1192
1193 static USBBusOps uhci_bus_ops = {
1194 };
1195
1196 static int usb_uhci_common_initfn(PCIDevice *dev)
1197 {
1198 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1199 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class);
1200 UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1201 uint8_t *pci_conf = s->dev.config;
1202 int i;
1203
1204 pci_conf[PCI_CLASS_PROG] = 0x00;
1205 /* TODO: reset value should be 0. */
1206 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
1207
1208 pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1);
1209
1210 if (s->masterbus) {
1211 USBPort *ports[NB_PORTS];
1212 for(i = 0; i < NB_PORTS; i++) {
1213 ports[i] = &s->ports[i].port;
1214 }
1215 if (usb_register_companion(s->masterbus, ports, NB_PORTS,
1216 s->firstport, s, &uhci_port_ops,
1217 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1218 return -1;
1219 }
1220 } else {
1221 usb_bus_new(&s->bus, sizeof(s->bus), &uhci_bus_ops, DEVICE(dev));
1222 for (i = 0; i < NB_PORTS; i++) {
1223 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1224 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1225 }
1226 }
1227 s->bh = qemu_bh_new(uhci_bh, s);
1228 s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, uhci_frame_timer, s);
1229 s->num_ports_vmstate = NB_PORTS;
1230 QTAILQ_INIT(&s->queues);
1231
1232 qemu_register_reset(uhci_reset, s);
1233
1234 memory_region_init_io(&s->io_bar, OBJECT(s), &uhci_ioport_ops, s,
1235 "uhci", 0x20);
1236
1237 /* Use region 4 for consistency with real hardware. BSD guests seem
1238 to rely on this. */
1239 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1240
1241 return 0;
1242 }
1243
1244 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
1245 {
1246 UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1247 uint8_t *pci_conf = s->dev.config;
1248
1249 /* USB misc control 1/2 */
1250 pci_set_long(pci_conf + 0x40,0x00001000);
1251 /* PM capability */
1252 pci_set_long(pci_conf + 0x80,0x00020001);
1253 /* USB legacy support */
1254 pci_set_long(pci_conf + 0xc0,0x00002000);
1255
1256 return usb_uhci_common_initfn(dev);
1257 }
1258
1259 static void usb_uhci_exit(PCIDevice *dev)
1260 {
1261 UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1262
1263 trace_usb_uhci_exit();
1264
1265 if (s->frame_timer) {
1266 timer_del(s->frame_timer);
1267 timer_free(s->frame_timer);
1268 s->frame_timer = NULL;
1269 }
1270
1271 if (s->bh) {
1272 qemu_bh_delete(s->bh);
1273 }
1274
1275 uhci_async_cancel_all(s);
1276
1277 if (!s->masterbus) {
1278 usb_bus_release(&s->bus);
1279 }
1280 }
1281
1282 static Property uhci_properties_companion[] = {
1283 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1284 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
1285 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1286 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128),
1287 DEFINE_PROP_END_OF_LIST(),
1288 };
1289 static Property uhci_properties_standalone[] = {
1290 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1291 DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128),
1292 DEFINE_PROP_END_OF_LIST(),
1293 };
1294
1295 static void uhci_class_init(ObjectClass *klass, void *data)
1296 {
1297 DeviceClass *dc = DEVICE_CLASS(klass);
1298 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1299 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class);
1300 UHCIInfo *info = data;
1301
1302 k->init = info->initfn ? info->initfn : usb_uhci_common_initfn;
1303 k->exit = info->unplug ? usb_uhci_exit : NULL;
1304 k->vendor_id = info->vendor_id;
1305 k->device_id = info->device_id;
1306 k->revision = info->revision;
1307 k->class_id = PCI_CLASS_SERIAL_USB;
1308 dc->vmsd = &vmstate_uhci;
1309 if (!info->unplug) {
1310 /* uhci controllers in companion setups can't be hotplugged */
1311 dc->hotpluggable = false;
1312 dc->props = uhci_properties_companion;
1313 } else {
1314 dc->props = uhci_properties_standalone;
1315 }
1316 set_bit(DEVICE_CATEGORY_USB, dc->categories);
1317 u->info = *info;
1318 }
1319
1320 static UHCIInfo uhci_info[] = {
1321 {
1322 .name = "piix3-usb-uhci",
1323 .vendor_id = PCI_VENDOR_ID_INTEL,
1324 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2,
1325 .revision = 0x01,
1326 .irq_pin = 3,
1327 .unplug = true,
1328 },{
1329 .name = "piix4-usb-uhci",
1330 .vendor_id = PCI_VENDOR_ID_INTEL,
1331 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2,
1332 .revision = 0x01,
1333 .irq_pin = 3,
1334 .unplug = true,
1335 },{
1336 .name = "vt82c686b-usb-uhci",
1337 .vendor_id = PCI_VENDOR_ID_VIA,
1338 .device_id = PCI_DEVICE_ID_VIA_UHCI,
1339 .revision = 0x01,
1340 .irq_pin = 3,
1341 .initfn = usb_uhci_vt82c686b_initfn,
1342 .unplug = true,
1343 },{
1344 .name = "ich9-usb-uhci1", /* 00:1d.0 */
1345 .vendor_id = PCI_VENDOR_ID_INTEL,
1346 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1,
1347 .revision = 0x03,
1348 .irq_pin = 0,
1349 .unplug = false,
1350 },{
1351 .name = "ich9-usb-uhci2", /* 00:1d.1 */
1352 .vendor_id = PCI_VENDOR_ID_INTEL,
1353 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2,
1354 .revision = 0x03,
1355 .irq_pin = 1,
1356 .unplug = false,
1357 },{
1358 .name = "ich9-usb-uhci3", /* 00:1d.2 */
1359 .vendor_id = PCI_VENDOR_ID_INTEL,
1360 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3,
1361 .revision = 0x03,
1362 .irq_pin = 2,
1363 .unplug = false,
1364 },{
1365 .name = "ich9-usb-uhci4", /* 00:1a.0 */
1366 .vendor_id = PCI_VENDOR_ID_INTEL,
1367 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4,
1368 .revision = 0x03,
1369 .irq_pin = 0,
1370 .unplug = false,
1371 },{
1372 .name = "ich9-usb-uhci5", /* 00:1a.1 */
1373 .vendor_id = PCI_VENDOR_ID_INTEL,
1374 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5,
1375 .revision = 0x03,
1376 .irq_pin = 1,
1377 .unplug = false,
1378 },{
1379 .name = "ich9-usb-uhci6", /* 00:1a.2 */
1380 .vendor_id = PCI_VENDOR_ID_INTEL,
1381 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6,
1382 .revision = 0x03,
1383 .irq_pin = 2,
1384 .unplug = false,
1385 }
1386 };
1387
1388 static void uhci_register_types(void)
1389 {
1390 TypeInfo uhci_type_info = {
1391 .parent = TYPE_PCI_DEVICE,
1392 .instance_size = sizeof(UHCIState),
1393 .class_size = sizeof(UHCIPCIDeviceClass),
1394 .class_init = uhci_class_init,
1395 };
1396 int i;
1397
1398 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) {
1399 uhci_type_info.name = uhci_info[i].name;
1400 uhci_type_info.class_data = uhci_info + i;
1401 type_register(&uhci_type_info);
1402 }
1403 }
1404
1405 type_init(uhci_register_types)
AR7 emulation for QEMU