hw/ide/pci.c

   1 /*
   2  * QEMU IDE Emulation: PCI Bus support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/i386/pc.h>
  27 #include <hw/pci/pci.h>
  28 #include <hw/isa/isa.h>
  29 #include "sysemu/block-backend.h"
  30 #include "sysemu/dma.h"
  31 #include "qemu/error-report.h"
  32 #include <hw/ide/pci.h>
  33
  34 #define BMDMA_PAGE_SIZE 4096
  35
  36 #define BM_MIGRATION_COMPAT_STATUS_BITS \
  37         (IDE_RETRY_DMA | IDE_RETRY_PIO | \
  38         IDE_RETRY_READ | IDE_RETRY_FLUSH)
  39
  40 static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
  41                             BlockCompletionFunc *dma_cb)
  42 {
  43     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  44
  45     bm->dma_cb = dma_cb;
  46     bm->cur_prd_last = 0;
  47     bm->cur_prd_addr = 0;
  48     bm->cur_prd_len = 0;
  49
  50     if (bm->status & BM_STATUS_DMAING) {
  51         bm->dma_cb(bmdma_active_if(bm), 0);
  52     }
  53 }
  54
  55 /**
  56  * Prepare an sglist based on available PRDs.
  57  * @limit: How many bytes to prepare total.
  58  *
  59  * Returns the number of bytes prepared, -1 on error.
  60  * IDEState.io_buffer_size will contain the number of bytes described
  61  * by the PRDs, whether or not we added them to the sglist.
  62  */
  63 static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit)
  64 {
  65     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  66     IDEState *s = bmdma_active_if(bm);
  67     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
  68     struct {
  69         uint32_t addr;
  70         uint32_t size;
  71     } prd;
  72     int l, len;
  73
  74     pci_dma_sglist_init(&s->sg, pci_dev,
  75                         s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
  76     s->io_buffer_size = 0;
  77     for(;;) {
  78         if (bm->cur_prd_len == 0) {
  79             /* end of table (with a fail safe of one page) */
  80             if (bm->cur_prd_last ||
  81                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE) {
  82                 return s->sg.size;
  83             }
  84             pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
  85             bm->cur_addr += 8;
  86             prd.addr = le32_to_cpu(prd.addr);
  87             prd.size = le32_to_cpu(prd.size);
  88             len = prd.size & 0xfffe;
  89             if (len == 0)
  90                 len = 0x10000;
  91             bm->cur_prd_len = len;
  92             bm->cur_prd_addr = prd.addr;
  93             bm->cur_prd_last = (prd.size & 0x80000000);
  94         }
  95         l = bm->cur_prd_len;
  96         if (l > 0) {
  97             uint64_t sg_len;
  98
  99             /* Don't add extra bytes to the SGList; consume any remaining
 100              * PRDs from the guest, but ignore them. */
 101             sg_len = MIN(limit - s->sg.size, bm->cur_prd_len);
 102             if (sg_len) {
 103                 qemu_sglist_add(&s->sg, bm->cur_prd_addr, sg_len);
 104             }
 105
 106             /* Note: We limit the max transfer to be 2GiB.
 107              * This should accommodate the largest ATA transaction
 108              * for LBA48 (65,536 sectors) and 32K sector sizes. */
 109             if (s->sg.size > INT32_MAX) {
 110                 error_report("IDE: sglist describes more than 2GiB.");
 111                 break;
 112             }
 113             bm->cur_prd_addr += l;
 114             bm->cur_prd_len -= l;
 115             s->io_buffer_size += l;
 116         }
 117     }
 118
 119     qemu_sglist_destroy(&s->sg);
 120     s->io_buffer_size = 0;
 121     return -1;
 122 }
 123
 124 /* return 0 if buffer completed */
 125 static int bmdma_rw_buf(IDEDMA *dma, int is_write)
 126 {
 127     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 128     IDEState *s = bmdma_active_if(bm);
 129     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 130     struct {
 131         uint32_t addr;
 132         uint32_t size;
 133     } prd;
 134     int l, len;
 135
 136     for(;;) {
 137         l = s->io_buffer_size - s->io_buffer_index;
 138         if (l <= 0)
 139             break;
 140         if (bm->cur_prd_len == 0) {
 141             /* end of table (with a fail safe of one page) */
 142             if (bm->cur_prd_last ||
 143                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
 144                 return 0;
 145             pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
 146             bm->cur_addr += 8;
 147             prd.addr = le32_to_cpu(prd.addr);
 148             prd.size = le32_to_cpu(prd.size);
 149             len = prd.size & 0xfffe;
 150             if (len == 0)
 151                 len = 0x10000;
 152             bm->cur_prd_len = len;
 153             bm->cur_prd_addr = prd.addr;
 154             bm->cur_prd_last = (prd.size & 0x80000000);
 155         }
 156         if (l > bm->cur_prd_len)
 157             l = bm->cur_prd_len;
 158         if (l > 0) {
 159             if (is_write) {
 160                 pci_dma_write(pci_dev, bm->cur_prd_addr,
 161                               s->io_buffer + s->io_buffer_index, l);
 162             } else {
 163                 pci_dma_read(pci_dev, bm->cur_prd_addr,
 164                              s->io_buffer + s->io_buffer_index, l);
 165             }
 166             bm->cur_prd_addr += l;
 167             bm->cur_prd_len -= l;
 168             s->io_buffer_index += l;
 169         }
 170     }
 171     return 1;
 172 }
 173
 174 static void bmdma_set_inactive(IDEDMA *dma, bool more)
 175 {
 176     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 177
 178     bm->dma_cb = NULL;
 179     if (more) {
 180         bm->status |= BM_STATUS_DMAING;
 181     } else {
 182         bm->status &= ~BM_STATUS_DMAING;
 183     }
 184 }
 185
 186 static void bmdma_restart_dma(IDEDMA *dma)
 187 {
 188     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 189
 190     bm->cur_addr = bm->addr;
 191 }
 192
 193 static void bmdma_cancel(BMDMAState *bm)
 194 {
 195     if (bm->status & BM_STATUS_DMAING) {
 196         /* cancel DMA request */
 197         bmdma_set_inactive(&bm->dma, false);
 198     }
 199 }
 200
 201 static void bmdma_reset(IDEDMA *dma)
 202 {
 203     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 204
 205 #ifdef DEBUG_IDE
 206     printf("ide: dma_reset\n");
 207 #endif
 208     bmdma_cancel(bm);
 209     bm->cmd = 0;
 210     bm->status = 0;
 211     bm->addr = 0;
 212     bm->cur_addr = 0;
 213     bm->cur_prd_last = 0;
 214     bm->cur_prd_addr = 0;
 215     bm->cur_prd_len = 0;
 216 }
 217
 218 static void bmdma_irq(void *opaque, int n, int level)
 219 {
 220     BMDMAState *bm = opaque;
 221
 222     if (!level) {
 223         /* pass through lower */
 224         qemu_set_irq(bm->irq, level);
 225         return;
 226     }
 227
 228     bm->status |= BM_STATUS_INT;
 229
 230     /* trigger the real irq */
 231     qemu_set_irq(bm->irq, level);
 232 }
 233
 234 void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
 235 {
 236 #ifdef DEBUG_IDE
 237     printf("%s: 0x%08x\n", __func__, val);
 238 #endif
 239
 240     /* Ignore writes to SSBM if it keeps the old value */
 241     if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
 242         if (!(val & BM_CMD_START)) {
 243             /*
 244              * We can't cancel Scatter Gather DMA in the middle of the
 245              * operation or a partial (not full) DMA transfer would reach
 246              * the storage so we wait for completion instead (we beahve
 247              * like if the DMA was completed by the time the guest trying
 248              * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
 249              * set).
 250              *
 251              * In the future we'll be able to safely cancel the I/O if the
 252              * whole DMA operation will be submitted to disk with a single
 253              * aio operation with preadv/pwritev.
 254              */
 255             if (bm->bus->dma->aiocb) {
 256                 blk_drain_all();
 257                 assert(bm->bus->dma->aiocb == NULL);
 258             }
 259             bm->status &= ~BM_STATUS_DMAING;
 260         } else {
 261             bm->cur_addr = bm->addr;
 262             if (!(bm->status & BM_STATUS_DMAING)) {
 263                 bm->status |= BM_STATUS_DMAING;
 264                 /* start dma transfer if possible */
 265                 if (bm->dma_cb)
 266                     bm->dma_cb(bmdma_active_if(bm), 0);
 267             }
 268         }
 269     }
 270
 271     bm->cmd = val & 0x09;
 272 }
 273
 274 static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
 275                                 unsigned width)
 276 {
 277     BMDMAState *bm = opaque;
 278     uint32_t mask = (1ULL << (width * 8)) - 1;
 279     uint64_t data;
 280
 281     data = (bm->addr >> (addr * 8)) & mask;
 282 #ifdef DEBUG_IDE
 283     printf("%s: 0x%08x\n", __func__, (unsigned)data);
 284 #endif
 285     return data;
 286 }
 287
 288 static void bmdma_addr_write(void *opaque, hwaddr addr,
 289                              uint64_t data, unsigned width)
 290 {
 291     BMDMAState *bm = opaque;
 292     int shift = addr * 8;
 293     uint32_t mask = (1ULL << (width * 8)) - 1;
 294
 295 #ifdef DEBUG_IDE
 296     printf("%s: 0x%08x\n", __func__, (unsigned)data);
 297 #endif
 298     bm->addr &= ~(mask << shift);
 299     bm->addr |= ((data & mask) << shift) & ~3;
 300 }
 301
 302 MemoryRegionOps bmdma_addr_ioport_ops = {
 303     .read = bmdma_addr_read,
 304     .write = bmdma_addr_write,
 305     .endianness = DEVICE_LITTLE_ENDIAN,
 306 };
 307
 308 static bool ide_bmdma_current_needed(void *opaque)
 309 {
 310     BMDMAState *bm = opaque;
 311
 312     return (bm->cur_prd_len != 0);
 313 }
 314
 315 static bool ide_bmdma_status_needed(void *opaque)
 316 {
 317     BMDMAState *bm = opaque;
 318
 319     /* Older versions abused some bits in the status register for internal
 320      * error state. If any of these bits are set, we must add a subsection to
 321      * transfer the real status register */
 322     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 323
 324     return ((bm->status & abused_bits) != 0);
 325 }
 326
 327 static void ide_bmdma_pre_save(void *opaque)
 328 {
 329     BMDMAState *bm = opaque;
 330     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 331
 332     bm->migration_retry_unit = bm->bus->retry_unit;
 333     bm->migration_retry_sector_num = bm->bus->retry_sector_num;
 334     bm->migration_retry_nsector = bm->bus->retry_nsector;
 335     bm->migration_compat_status =
 336         (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
 337 }
 338
 339 /* This function accesses bm->bus->error_status which is loaded only after
 340  * BMDMA itself. This is why the function is called from ide_pci_post_load
 341  * instead of being registered with VMState where it would run too early. */
 342 static int ide_bmdma_post_load(void *opaque, int version_id)
 343 {
 344     BMDMAState *bm = opaque;
 345     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 346
 347     if (bm->status == 0) {
 348         bm->status = bm->migration_compat_status & ~abused_bits;
 349         bm->bus->error_status |= bm->migration_compat_status & abused_bits;
 350     }
 351     if (bm->bus->error_status) {
 352         bm->bus->retry_sector_num = bm->migration_retry_sector_num;
 353         bm->bus->retry_nsector = bm->migration_retry_nsector;
 354         bm->bus->retry_unit = bm->migration_retry_unit;
 355     }
 356
 357     return 0;
 358 }
 359
 360 static const VMStateDescription vmstate_bmdma_current = {
 361     .name = "ide bmdma_current",
 362     .version_id = 1,
 363     .minimum_version_id = 1,
 364     .needed = ide_bmdma_current_needed,
 365     .fields = (VMStateField[]) {
 366         VMSTATE_UINT32(cur_addr, BMDMAState),
 367         VMSTATE_UINT32(cur_prd_last, BMDMAState),
 368         VMSTATE_UINT32(cur_prd_addr, BMDMAState),
 369         VMSTATE_UINT32(cur_prd_len, BMDMAState),
 370         VMSTATE_END_OF_LIST()
 371     }
 372 };
 373
 374 static const VMStateDescription vmstate_bmdma_status = {
 375     .name ="ide bmdma/status",
 376     .version_id = 1,
 377     .minimum_version_id = 1,
 378     .needed = ide_bmdma_status_needed,
 379     .fields = (VMStateField[]) {
 380         VMSTATE_UINT8(status, BMDMAState),
 381         VMSTATE_END_OF_LIST()
 382     }
 383 };
 384
 385 static const VMStateDescription vmstate_bmdma = {
 386     .name = "ide bmdma",
 387     .version_id = 3,
 388     .minimum_version_id = 0,
 389     .pre_save  = ide_bmdma_pre_save,
 390     .fields = (VMStateField[]) {
 391         VMSTATE_UINT8(cmd, BMDMAState),
 392         VMSTATE_UINT8(migration_compat_status, BMDMAState),
 393         VMSTATE_UINT32(addr, BMDMAState),
 394         VMSTATE_INT64(migration_retry_sector_num, BMDMAState),
 395         VMSTATE_UINT32(migration_retry_nsector, BMDMAState),
 396         VMSTATE_UINT8(migration_retry_unit, BMDMAState),
 397         VMSTATE_END_OF_LIST()
 398     },
 399     .subsections = (const VMStateDescription*[]) {
 400         &vmstate_bmdma_current,
 401         &vmstate_bmdma_status,
 402         NULL
 403     }
 404 };
 405
 406 static int ide_pci_post_load(void *opaque, int version_id)
 407 {
 408     PCIIDEState *d = opaque;
 409     int i;
 410
 411     for(i = 0; i < 2; i++) {
 412         /* current versions always store 0/1, but older version
 413            stored bigger values. We only need last bit */
 414         d->bmdma[i].migration_retry_unit &= 1;
 415         ide_bmdma_post_load(&d->bmdma[i], -1);
 416     }
 417
 418     return 0;
 419 }
 420
 421 const VMStateDescription vmstate_ide_pci = {
 422     .name = "ide",
 423     .version_id = 3,
 424     .minimum_version_id = 0,
 425     .post_load = ide_pci_post_load,
 426     .fields = (VMStateField[]) {
 427         VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
 428         VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
 429                              vmstate_bmdma, BMDMAState),
 430         VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
 431         VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
 432         VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
 433         VMSTATE_END_OF_LIST()
 434     }
 435 };
 436
 437 void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
 438 {
 439     PCIIDEState *d = PCI_IDE(dev);
 440     static const int bus[4]  = { 0, 0, 1, 1 };
 441     static const int unit[4] = { 0, 1, 0, 1 };
 442     int i;
 443
 444     for (i = 0; i < 4; i++) {
 445         if (hd_table[i] == NULL)
 446             continue;
 447         ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
 448     }
 449 }
 450
 451 static const struct IDEDMAOps bmdma_ops = {
 452     .start_dma = bmdma_start_dma,
 453     .prepare_buf = bmdma_prepare_buf,
 454     .rw_buf = bmdma_rw_buf,
 455     .restart_dma = bmdma_restart_dma,
 456     .set_inactive = bmdma_set_inactive,
 457     .reset = bmdma_reset,
 458 };
 459
 460 void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
 461 {
 462     if (bus->dma == &bm->dma) {
 463         return;
 464     }
 465
 466     bm->dma.ops = &bmdma_ops;
 467     bus->dma = &bm->dma;
 468     bm->irq = bus->irq;
 469     bus->irq = qemu_allocate_irq(bmdma_irq, bm, 0);
 470     bm->pci_dev = d;
 471 }
 472
 473 static const TypeInfo pci_ide_type_info = {
 474     .name = TYPE_PCI_IDE,
 475     .parent = TYPE_PCI_DEVICE,
 476     .instance_size = sizeof(PCIIDEState),
 477     .abstract = true,
 478 };
 479
 480 static void pci_ide_register_types(void)
 481 {
 482     type_register_static(&pci_ide_type_info);
 483 }
 484
 485 type_init(pci_ide_register_types)