hw/char/exynos4210_uart.c

   1 /*
   2  *  Exynos4210 UART Emulation
   3  *
   4  *  Copyright (C) 2011 Samsung Electronics Co Ltd.
   5  *    Maksim Kozlov, <m.kozlov@samsung.com>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License as published by the
   9  *  Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  *  for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  */
  21
  22 #include "hw/sysbus.h"
  23 #include "sysemu/sysemu.h"
  24 #include "sysemu/char.h"
  25
  26 #include "hw/arm/exynos4210.h"
  27
  28 #undef DEBUG_UART
  29 #undef DEBUG_UART_EXTEND
  30 #undef DEBUG_IRQ
  31 #undef DEBUG_Rx_DATA
  32 #undef DEBUG_Tx_DATA
  33
  34 #define DEBUG_UART            0
  35 #define DEBUG_UART_EXTEND     0
  36 #define DEBUG_IRQ             0
  37 #define DEBUG_Rx_DATA         0
  38 #define DEBUG_Tx_DATA         0
  39
  40 #if DEBUG_UART
  41 #define  PRINT_DEBUG(fmt, args...)  \
  42         do { \
  43             fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
  44         } while (0)
  45
  46 #if DEBUG_UART_EXTEND
  47 #define  PRINT_DEBUG_EXTEND(fmt, args...) \
  48         do { \
  49             fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
  50         } while (0)
  51 #else
  52 #define  PRINT_DEBUG_EXTEND(fmt, args...) \
  53         do {} while (0)
  54 #endif /* EXTEND */
  55
  56 #else
  57 #define  PRINT_DEBUG(fmt, args...)  \
  58         do {} while (0)
  59 #define  PRINT_DEBUG_EXTEND(fmt, args...) \
  60         do {} while (0)
  61 #endif
  62
  63 #define  PRINT_ERROR(fmt, args...) \
  64         do { \
  65             fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
  66         } while (0)
  67
  68 /*
  69  *  Offsets for UART registers relative to SFR base address
  70  *  for UARTn
  71  *
  72  */
  73 #define ULCON      0x0000 /* Line Control             */
  74 #define UCON       0x0004 /* Control                  */
  75 #define UFCON      0x0008 /* FIFO Control             */
  76 #define UMCON      0x000C /* Modem Control            */
  77 #define UTRSTAT    0x0010 /* Tx/Rx Status             */
  78 #define UERSTAT    0x0014 /* UART Error Status        */
  79 #define UFSTAT     0x0018 /* FIFO Status              */
  80 #define UMSTAT     0x001C /* Modem Status             */
  81 #define UTXH       0x0020 /* Transmit Buffer          */
  82 #define URXH       0x0024 /* Receive Buffer           */
  83 #define UBRDIV     0x0028 /* Baud Rate Divisor        */
  84 #define UFRACVAL   0x002C /* Divisor Fractional Value */
  85 #define UINTP      0x0030 /* Interrupt Pending        */
  86 #define UINTSP     0x0034 /* Interrupt Source Pending */
  87 #define UINTM      0x0038 /* Interrupt Mask           */
  88
  89 /*
  90  * for indexing register in the uint32_t array
  91  *
  92  * 'reg' - register offset (see offsets definitions above)
  93  *
  94  */
  95 #define I_(reg) (reg / sizeof(uint32_t))
  96
  97 typedef struct Exynos4210UartReg {
  98     const char         *name; /* the only reason is the debug output */
  99     hwaddr  offset;
 100     uint32_t            reset_value;
 101 } Exynos4210UartReg;
 102
 103 static Exynos4210UartReg exynos4210_uart_regs[] = {
 104     {"ULCON",    ULCON,    0x00000000},
 105     {"UCON",     UCON,     0x00003000},
 106     {"UFCON",    UFCON,    0x00000000},
 107     {"UMCON",    UMCON,    0x00000000},
 108     {"UTRSTAT",  UTRSTAT,  0x00000006}, /* RO */
 109     {"UERSTAT",  UERSTAT,  0x00000000}, /* RO */
 110     {"UFSTAT",   UFSTAT,   0x00000000}, /* RO */
 111     {"UMSTAT",   UMSTAT,   0x00000000}, /* RO */
 112     {"UTXH",     UTXH,     0x5c5c5c5c}, /* WO, undefined reset value*/
 113     {"URXH",     URXH,     0x00000000}, /* RO */
 114     {"UBRDIV",   UBRDIV,   0x00000000},
 115     {"UFRACVAL", UFRACVAL, 0x00000000},
 116     {"UINTP",    UINTP,    0x00000000},
 117     {"UINTSP",   UINTSP,   0x00000000},
 118     {"UINTM",    UINTM,    0x00000000},
 119 };
 120
 121 #define EXYNOS4210_UART_REGS_MEM_SIZE    0x3C
 122
 123 /* UART FIFO Control */
 124 #define UFCON_FIFO_ENABLE                    0x1
 125 #define UFCON_Rx_FIFO_RESET                  0x2
 126 #define UFCON_Tx_FIFO_RESET                  0x4
 127 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT    8
 128 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
 129 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT    4
 130 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
 131
 132 /* Uart FIFO Status */
 133 #define UFSTAT_Rx_FIFO_COUNT        0xff
 134 #define UFSTAT_Rx_FIFO_FULL         0x100
 135 #define UFSTAT_Rx_FIFO_ERROR        0x200
 136 #define UFSTAT_Tx_FIFO_COUNT_SHIFT  16
 137 #define UFSTAT_Tx_FIFO_COUNT        (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
 138 #define UFSTAT_Tx_FIFO_FULL_SHIFT   24
 139 #define UFSTAT_Tx_FIFO_FULL         (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
 140
 141 /* UART Interrupt Source Pending */
 142 #define UINTSP_RXD      0x1 /* Receive interrupt  */
 143 #define UINTSP_ERROR    0x2 /* Error interrupt    */
 144 #define UINTSP_TXD      0x4 /* Transmit interrupt */
 145 #define UINTSP_MODEM    0x8 /* Modem interrupt    */
 146
 147 /* UART Line Control */
 148 #define ULCON_IR_MODE_SHIFT   6
 149 #define ULCON_PARITY_SHIFT    3
 150 #define ULCON_STOP_BIT_SHIFT  1
 151
 152 /* UART Tx/Rx Status */
 153 #define UTRSTAT_TRANSMITTER_EMPTY       0x4
 154 #define UTRSTAT_Tx_BUFFER_EMPTY         0x2
 155 #define UTRSTAT_Rx_BUFFER_DATA_READY    0x1
 156
 157 /* UART Error Status */
 158 #define UERSTAT_OVERRUN  0x1
 159 #define UERSTAT_PARITY   0x2
 160 #define UERSTAT_FRAME    0x4
 161 #define UERSTAT_BREAK    0x8
 162
 163 typedef struct {
 164     uint8_t    *data;
 165     uint32_t    sp, rp; /* store and retrieve pointers */
 166     uint32_t    size;
 167 } Exynos4210UartFIFO;
 168
 169 #define TYPE_EXYNOS4210_UART "exynos4210.uart"
 170 #define EXYNOS4210_UART(obj) \
 171     OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART)
 172
 173 typedef struct Exynos4210UartState {
 174     SysBusDevice parent_obj;
 175
 176     MemoryRegion iomem;
 177
 178     uint32_t             reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
 179     Exynos4210UartFIFO   rx;
 180     Exynos4210UartFIFO   tx;
 181
 182     CharDriverState  *chr;
 183     qemu_irq          irq;
 184
 185     uint32_t channel;
 186
 187 } Exynos4210UartState;
 188
 189
 190 #if DEBUG_UART
 191 /* Used only for debugging inside PRINT_DEBUG_... macros */
 192 static const char *exynos4210_uart_regname(hwaddr  offset)
 193 {
 194
 195     int i;
 196
 197     for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
 198         if (offset == exynos4210_uart_regs[i].offset) {
 199             return exynos4210_uart_regs[i].name;
 200         }
 201     }
 202
 203     return NULL;
 204 }
 205 #endif
 206
 207
 208 static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch)
 209 {
 210     q->data[q->sp] = ch;
 211     q->sp = (q->sp + 1) % q->size;
 212 }
 213
 214 static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
 215 {
 216     uint8_t ret = q->data[q->rp];
 217     q->rp = (q->rp + 1) % q->size;
 218     return  ret;
 219 }
 220
 221 static int fifo_elements_number(Exynos4210UartFIFO *q)
 222 {
 223     if (q->sp < q->rp) {
 224         return q->size - q->rp + q->sp;
 225     }
 226
 227     return q->sp - q->rp;
 228 }
 229
 230 static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
 231 {
 232     return q->size - fifo_elements_number(q);
 233 }
 234
 235 static void fifo_reset(Exynos4210UartFIFO *q)
 236 {
 237     g_free(q->data);
 238     q->data = NULL;
 239
 240     q->data = (uint8_t *)g_malloc0(q->size);
 241
 242     q->sp = 0;
 243     q->rp = 0;
 244 }
 245
 246 static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
 247 {
 248     uint32_t level = 0;
 249     uint32_t reg;
 250
 251     reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >>
 252             UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;
 253
 254     switch (s->channel) {
 255     case 0:
 256         level = reg * 32;
 257         break;
 258     case 1:
 259     case 4:
 260         level = reg * 8;
 261         break;
 262     case 2:
 263     case 3:
 264         level = reg * 2;
 265         break;
 266     default:
 267         level = 0;
 268         PRINT_ERROR("Wrong UART channel number: %d\n", s->channel);
 269     }
 270
 271     return level;
 272 }
 273
 274 static void exynos4210_uart_update_irq(Exynos4210UartState *s)
 275 {
 276     /*
 277      * The Tx interrupt is always requested if the number of data in the
 278      * transmit FIFO is smaller than the trigger level.
 279      */
 280     if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
 281
 282         uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >>
 283                 UFSTAT_Tx_FIFO_COUNT_SHIFT;
 284
 285         if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
 286             s->reg[I_(UINTSP)] |= UINTSP_TXD;
 287         }
 288     }
 289
 290     s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)];
 291
 292     if (s->reg[I_(UINTP)]) {
 293         qemu_irq_raise(s->irq);
 294
 295 #if DEBUG_IRQ
 296         fprintf(stderr, "UART%d: IRQ has been raised: %08x\n",
 297                 s->channel, s->reg[I_(UINTP)]);
 298 #endif
 299
 300     } else {
 301         qemu_irq_lower(s->irq);
 302     }
 303 }
 304
 305 static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
 306 {
 307     int speed, parity, data_bits, stop_bits, frame_size;
 308     QEMUSerialSetParams ssp;
 309     uint64_t uclk_rate;
 310
 311     if (s->reg[I_(UBRDIV)] == 0) {
 312         return;
 313     }
 314
 315     frame_size = 1; /* start bit */
 316     if (s->reg[I_(ULCON)] & 0x20) {
 317         frame_size++; /* parity bit */
 318         if (s->reg[I_(ULCON)] & 0x28) {
 319             parity = 'E';
 320         } else {
 321             parity = 'O';
 322         }
 323     } else {
 324         parity = 'N';
 325     }
 326
 327     if (s->reg[I_(ULCON)] & 0x4) {
 328         stop_bits = 2;
 329     } else {
 330         stop_bits = 1;
 331     }
 332
 333     data_bits = (s->reg[I_(ULCON)] & 0x3) + 5;
 334
 335     frame_size += data_bits + stop_bits;
 336
 337     uclk_rate = 24000000;
 338
 339     speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) +
 340             (s->reg[I_(UFRACVAL)] & 0x7) + 16);
 341
 342     ssp.speed     = speed;
 343     ssp.parity    = parity;
 344     ssp.data_bits = data_bits;
 345     ssp.stop_bits = stop_bits;
 346
 347     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 348
 349     PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",
 350                 s->channel, speed, parity, data_bits, stop_bits);
 351 }
 352
 353 static void exynos4210_uart_write(void *opaque, hwaddr offset,
 354                                uint64_t val, unsigned size)
 355 {
 356     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 357     uint8_t ch;
 358
 359     PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel,
 360         offset, exynos4210_uart_regname(offset), (long long unsigned int)val);
 361
 362     switch (offset) {
 363     case ULCON:
 364     case UBRDIV:
 365     case UFRACVAL:
 366         s->reg[I_(offset)] = val;
 367         exynos4210_uart_update_parameters(s);
 368         break;
 369     case UFCON:
 370         s->reg[I_(UFCON)] = val;
 371         if (val & UFCON_Rx_FIFO_RESET) {
 372             fifo_reset(&s->rx);
 373             s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET;
 374             PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel);
 375         }
 376         if (val & UFCON_Tx_FIFO_RESET) {
 377             fifo_reset(&s->tx);
 378             s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET;
 379             PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel);
 380         }
 381         break;
 382
 383     case UTXH:
 384         if (s->chr) {
 385             s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
 386                     UTRSTAT_Tx_BUFFER_EMPTY);
 387             ch = (uint8_t)val;
 388             qemu_chr_fe_write(s->chr, &ch, 1);
 389 #if DEBUG_Tx_DATA
 390             fprintf(stderr, "%c", ch);
 391 #endif
 392             s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY |
 393                     UTRSTAT_Tx_BUFFER_EMPTY;
 394             s->reg[I_(UINTSP)]  |= UINTSP_TXD;
 395             exynos4210_uart_update_irq(s);
 396         }
 397         break;
 398
 399     case UINTP:
 400         s->reg[I_(UINTP)] &= ~val;
 401         s->reg[I_(UINTSP)] &= ~val;
 402         PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n",
 403                     s->channel, offset, s->reg[I_(UINTP)]);
 404         exynos4210_uart_update_irq(s);
 405         break;
 406     case UTRSTAT:
 407     case UERSTAT:
 408     case UFSTAT:
 409     case UMSTAT:
 410     case URXH:
 411         PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n",
 412                     s->channel, exynos4210_uart_regname(offset), offset);
 413         break;
 414     case UINTSP:
 415         s->reg[I_(UINTSP)]  &= ~val;
 416         break;
 417     case UINTM:
 418         s->reg[I_(UINTM)] = val;
 419         exynos4210_uart_update_irq(s);
 420         break;
 421     case UCON:
 422     case UMCON:
 423     default:
 424         s->reg[I_(offset)] = val;
 425         break;
 426     }
 427 }
 428 static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
 429                                   unsigned size)
 430 {
 431     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 432     uint32_t res;
 433
 434     switch (offset) {
 435     case UERSTAT: /* Read Only */
 436         res = s->reg[I_(UERSTAT)];
 437         s->reg[I_(UERSTAT)] = 0;
 438         return res;
 439     case UFSTAT: /* Read Only */
 440         s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff;
 441         if (fifo_empty_elements_number(&s->rx) == 0) {
 442             s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL;
 443             s->reg[I_(UFSTAT)] &= ~0xff;
 444         }
 445         return s->reg[I_(UFSTAT)];
 446     case URXH:
 447         if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
 448             if (fifo_elements_number(&s->rx)) {
 449                 res = fifo_retrieve(&s->rx);
 450 #if DEBUG_Rx_DATA
 451                 fprintf(stderr, "%c", res);
 452 #endif
 453                 if (!fifo_elements_number(&s->rx)) {
 454                     s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
 455                 } else {
 456                     s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
 457                 }
 458             } else {
 459                 s->reg[I_(UINTSP)] |= UINTSP_ERROR;
 460                 exynos4210_uart_update_irq(s);
 461                 res = 0;
 462             }
 463         } else {
 464             s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
 465             res = s->reg[I_(URXH)];
 466         }
 467         return res;
 468     case UTXH:
 469         PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n",
 470                     s->channel, exynos4210_uart_regname(offset), offset);
 471         break;
 472     default:
 473         return s->reg[I_(offset)];
 474     }
 475
 476     return 0;
 477 }
 478
 479 static const MemoryRegionOps exynos4210_uart_ops = {
 480     .read = exynos4210_uart_read,
 481     .write = exynos4210_uart_write,
 482     .endianness = DEVICE_NATIVE_ENDIAN,
 483     .valid = {
 484         .max_access_size = 4,
 485         .unaligned = false
 486     },
 487 };
 488
 489 static int exynos4210_uart_can_receive(void *opaque)
 490 {
 491     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 492
 493     return fifo_empty_elements_number(&s->rx);
 494 }
 495
 496
 497 static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
 498 {
 499     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 500     int i;
 501
 502     if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
 503         if (fifo_empty_elements_number(&s->rx) < size) {
 504             for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) {
 505                 fifo_store(&s->rx, buf[i]);
 506             }
 507             s->reg[I_(UINTSP)] |= UINTSP_ERROR;
 508             s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
 509         } else {
 510             for (i = 0; i < size; i++) {
 511                 fifo_store(&s->rx, buf[i]);
 512             }
 513             s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
 514         }
 515         /* XXX: Around here we maybe should check Rx trigger level */
 516         s->reg[I_(UINTSP)] |= UINTSP_RXD;
 517     } else {
 518         s->reg[I_(URXH)] = buf[0];
 519         s->reg[I_(UINTSP)] |= UINTSP_RXD;
 520         s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
 521     }
 522
 523     exynos4210_uart_update_irq(s);
 524 }
 525
 526
 527 static void exynos4210_uart_event(void *opaque, int event)
 528 {
 529     Exynos4210UartState *s = (Exynos4210UartState *)opaque;
 530
 531     if (event == CHR_EVENT_BREAK) {
 532         /* When the RxDn is held in logic 0, then a null byte is pushed into the
 533          * fifo */
 534         fifo_store(&s->rx, '\0');
 535         s->reg[I_(UERSTAT)] |= UERSTAT_BREAK;
 536         exynos4210_uart_update_irq(s);
 537     }
 538 }
 539
 540
 541 static void exynos4210_uart_reset(DeviceState *dev)
 542 {
 543     Exynos4210UartState *s = EXYNOS4210_UART(dev);
 544     int i;
 545
 546     for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
 547         s->reg[I_(exynos4210_uart_regs[i].offset)] =
 548                 exynos4210_uart_regs[i].reset_value;
 549     }
 550
 551     fifo_reset(&s->rx);
 552     fifo_reset(&s->tx);
 553
 554     PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size);
 555 }
 556
 557 static const VMStateDescription vmstate_exynos4210_uart_fifo = {
 558     .name = "exynos4210.uart.fifo",
 559     .version_id = 1,
 560     .minimum_version_id = 1,
 561     .fields = (VMStateField[]) {
 562         VMSTATE_UINT32(sp, Exynos4210UartFIFO),
 563         VMSTATE_UINT32(rp, Exynos4210UartFIFO),
 564         VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, 0, size),
 565         VMSTATE_END_OF_LIST()
 566     }
 567 };
 568
 569 static const VMStateDescription vmstate_exynos4210_uart = {
 570     .name = "exynos4210.uart",
 571     .version_id = 1,
 572     .minimum_version_id = 1,
 573     .fields = (VMStateField[]) {
 574         VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
 575                        vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
 576         VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,
 577                              EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
 578         VMSTATE_END_OF_LIST()
 579     }
 580 };
 581
 582 DeviceState *exynos4210_uart_create(hwaddr addr,
 583                                     int fifo_size,
 584                                     int channel,
 585                                     CharDriverState *chr,
 586                                     qemu_irq irq)
 587 {
 588     DeviceState  *dev;
 589     SysBusDevice *bus;
 590
 591     const char chr_name[] = "serial";
 592     char label[ARRAY_SIZE(chr_name) + 1];
 593
 594     dev = qdev_create(NULL, TYPE_EXYNOS4210_UART);
 595
 596     if (!chr) {
 597         if (channel >= MAX_SERIAL_PORTS) {
 598             hw_error("Only %d serial ports are supported by QEMU.\n",
 599                      MAX_SERIAL_PORTS);
 600         }
 601         chr = serial_hds[channel];
 602         if (!chr) {
 603             snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel);
 604             chr = qemu_chr_new(label, "null", NULL);
 605             if (!(chr)) {
 606                 hw_error("Can't assign serial port to UART%d.\n", channel);
 607             }
 608         }
 609     }
 610
 611     qdev_prop_set_chr(dev, "chardev", chr);
 612     qdev_prop_set_uint32(dev, "channel", channel);
 613     qdev_prop_set_uint32(dev, "rx-size", fifo_size);
 614     qdev_prop_set_uint32(dev, "tx-size", fifo_size);
 615
 616     bus = SYS_BUS_DEVICE(dev);
 617     qdev_init_nofail(dev);
 618     if (addr != (hwaddr)-1) {
 619         sysbus_mmio_map(bus, 0, addr);
 620     }
 621     sysbus_connect_irq(bus, 0, irq);
 622
 623     return dev;
 624 }
 625
 626 static int exynos4210_uart_init(SysBusDevice *dev)
 627 {
 628     Exynos4210UartState *s = EXYNOS4210_UART(dev);
 629
 630     /* memory mapping */
 631     memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_uart_ops, s,
 632                           "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);
 633     sysbus_init_mmio(dev, &s->iomem);
 634
 635     sysbus_init_irq(dev, &s->irq);
 636
 637     qemu_chr_add_handlers(s->chr, exynos4210_uart_can_receive,
 638                           exynos4210_uart_receive, exynos4210_uart_event, s);
 639
 640     return 0;
 641 }
 642
 643 static Property exynos4210_uart_properties[] = {
 644     DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr),
 645     DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0),
 646     DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16),
 647     DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16),
 648     DEFINE_PROP_END_OF_LIST(),
 649 };
 650
 651 static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
 652 {
 653     DeviceClass *dc = DEVICE_CLASS(klass);
 654     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 655
 656     k->init = exynos4210_uart_init;
 657     dc->reset = exynos4210_uart_reset;
 658     dc->props = exynos4210_uart_properties;
 659     dc->vmsd = &vmstate_exynos4210_uart;
 660 }
 661
 662 static const TypeInfo exynos4210_uart_info = {
 663     .name          = TYPE_EXYNOS4210_UART,
 664     .parent        = TYPE_SYS_BUS_DEVICE,
 665     .instance_size = sizeof(Exynos4210UartState),
 666     .class_init    = exynos4210_uart_class_init,
 667 };
 668
 669 static void exynos4210_uart_register(void)
 670 {
 671     type_register_static(&exynos4210_uart_info);
 672 }
 673
 674 type_init(exynos4210_uart_register)