target-arm/op_helper.c

   1 /*
   2  *  ARM helper routines
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery, LLC
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "helper.h"
  21
  22 #define SIGNBIT (uint32_t)0x80000000
  23 #define SIGNBIT64 ((uint64_t)1 << 63)
  24
  25 static void raise_exception(CPUARMState *env, int tt)
  26 {
  27     env->exception_index = tt;
  28     cpu_loop_exit(env);
  29 }
  30
  31 uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
  32                           uint32_t rn, uint32_t maxindex)
  33 {
  34     uint32_t val;
  35     uint32_t tmp;
  36     int index;
  37     int shift;
  38     uint64_t *table;
  39     table = (uint64_t *)&env->vfp.regs[rn];
  40     val = 0;
  41     for (shift = 0; shift < 32; shift += 8) {
  42         index = (ireg >> shift) & 0xff;
  43         if (index < maxindex) {
  44             tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
  45             val |= tmp << shift;
  46         } else {
  47             val |= def & (0xff << shift);
  48         }
  49     }
  50     return val;
  51 }
  52
  53 #if !defined(CONFIG_USER_ONLY)
  54
  55 #include "exec/softmmu_exec.h"
  56
  57 #define MMUSUFFIX _mmu
  58
  59 #define SHIFT 0
  60 #include "exec/softmmu_template.h"
  61
  62 #define SHIFT 1
  63 #include "exec/softmmu_template.h"
  64
  65 #define SHIFT 2
  66 #include "exec/softmmu_template.h"
  67
  68 #define SHIFT 3
  69 #include "exec/softmmu_template.h"
  70
  71 /* try to fill the TLB and return an exception if error. If retaddr is
  72    NULL, it means that the function was called in C code (i.e. not
  73    from generated code or from helper.c) */
  74 void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
  75               uintptr_t retaddr)
  76 {
  77     int ret;
  78
  79     ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
  80     if (unlikely(ret)) {
  81         if (retaddr) {
  82             /* now we have a real cpu fault */
  83             cpu_restore_state(env, retaddr);
  84         }
  85         raise_exception(env, env->exception_index);
  86     }
  87 }
  88 #endif
  89
  90 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
  91 {
  92     uint32_t res = a + b;
  93     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
  94         env->QF = 1;
  95     return res;
  96 }
  97
  98 uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
  99 {
 100     uint32_t res = a + b;
 101     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
 102         env->QF = 1;
 103         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
 104     }
 105     return res;
 106 }
 107
 108 uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 109 {
 110     uint32_t res = a - b;
 111     if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
 112         env->QF = 1;
 113         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
 114     }
 115     return res;
 116 }
 117
 118 uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
 119 {
 120     uint32_t res;
 121     if (val >= 0x40000000) {
 122         res = ~SIGNBIT;
 123         env->QF = 1;
 124     } else if (val <= (int32_t)0xc0000000) {
 125         res = SIGNBIT;
 126         env->QF = 1;
 127     } else {
 128         res = val << 1;
 129     }
 130     return res;
 131 }
 132
 133 uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 134 {
 135     uint32_t res = a + b;
 136     if (res < a) {
 137         env->QF = 1;
 138         res = ~0;
 139     }
 140     return res;
 141 }
 142
 143 uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 144 {
 145     uint32_t res = a - b;
 146     if (res > a) {
 147         env->QF = 1;
 148         res = 0;
 149     }
 150     return res;
 151 }
 152
 153 /* Signed saturation.  */
 154 static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
 155 {
 156     int32_t top;
 157     uint32_t mask;
 158
 159     top = val >> shift;
 160     mask = (1u << shift) - 1;
 161     if (top > 0) {
 162         env->QF = 1;
 163         return mask;
 164     } else if (top < -1) {
 165         env->QF = 1;
 166         return ~mask;
 167     }
 168     return val;
 169 }
 170
 171 /* Unsigned saturation.  */
 172 static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
 173 {
 174     uint32_t max;
 175
 176     max = (1u << shift) - 1;
 177     if (val < 0) {
 178         env->QF = 1;
 179         return 0;
 180     } else if (val > max) {
 181         env->QF = 1;
 182         return max;
 183     }
 184     return val;
 185 }
 186
 187 /* Signed saturate.  */
 188 uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
 189 {
 190     return do_ssat(env, x, shift);
 191 }
 192
 193 /* Dual halfword signed saturate.  */
 194 uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 195 {
 196     uint32_t res;
 197
 198     res = (uint16_t)do_ssat(env, (int16_t)x, shift);
 199     res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
 200     return res;
 201 }
 202
 203 /* Unsigned saturate.  */
 204 uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
 205 {
 206     return do_usat(env, x, shift);
 207 }
 208
 209 /* Dual halfword unsigned saturate.  */
 210 uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 211 {
 212     uint32_t res;
 213
 214     res = (uint16_t)do_usat(env, (int16_t)x, shift);
 215     res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
 216     return res;
 217 }
 218
 219 void HELPER(wfi)(CPUARMState *env)
 220 {
 221     CPUState *cs = CPU(arm_env_get_cpu(env));
 222
 223     env->exception_index = EXCP_HLT;
 224     cs->halted = 1;
 225     cpu_loop_exit(env);
 226 }
 227
 228 void HELPER(exception)(CPUARMState *env, uint32_t excp)
 229 {
 230     env->exception_index = excp;
 231     cpu_loop_exit(env);
 232 }
 233
 234 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 235 {
 236     return cpsr_read(env) & ~CPSR_EXEC;
 237 }
 238
 239 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
 240 {
 241     cpsr_write(env, val, mask);
 242 }
 243
 244 /* Access to user mode registers from privileged modes.  */
 245 uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
 246 {
 247     uint32_t val;
 248
 249     if (regno == 13) {
 250         val = env->banked_r13[0];
 251     } else if (regno == 14) {
 252         val = env->banked_r14[0];
 253     } else if (regno >= 8
 254                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 255         val = env->usr_regs[regno - 8];
 256     } else {
 257         val = env->regs[regno];
 258     }
 259     return val;
 260 }
 261
 262 void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
 263 {
 264     if (regno == 13) {
 265         env->banked_r13[0] = val;
 266     } else if (regno == 14) {
 267         env->banked_r14[0] = val;
 268     } else if (regno >= 8
 269                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 270         env->usr_regs[regno - 8] = val;
 271     } else {
 272         env->regs[regno] = val;
 273     }
 274 }
 275
 276 void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip)
 277 {
 278     const ARMCPRegInfo *ri = rip;
 279     switch (ri->accessfn(env, ri)) {
 280     case CP_ACCESS_OK:
 281         return;
 282     case CP_ACCESS_TRAP:
 283     case CP_ACCESS_TRAP_UNCATEGORIZED:
 284         /* These cases will eventually need to generate different
 285          * syndrome information.
 286          */
 287         break;
 288     default:
 289         g_assert_not_reached();
 290     }
 291     raise_exception(env, EXCP_UDEF);
 292 }
 293
 294 void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
 295 {
 296     const ARMCPRegInfo *ri = rip;
 297
 298     ri->writefn(env, ri, value);
 299 }
 300
 301 uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
 302 {
 303     const ARMCPRegInfo *ri = rip;
 304
 305     return ri->readfn(env, ri);
 306 }
 307
 308 void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
 309 {
 310     const ARMCPRegInfo *ri = rip;
 311
 312     ri->writefn(env, ri, value);
 313 }
 314
 315 uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
 316 {
 317     const ARMCPRegInfo *ri = rip;
 318
 319     return ri->readfn(env, ri);
 320 }
 321
 322 void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
 323 {
 324     /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
 325      * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
 326      * to catch that case at translate time.
 327      */
 328     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
 329         raise_exception(env, EXCP_UDEF);
 330     }
 331
 332     switch (op) {
 333     case 0x05: /* SPSel */
 334         env->pstate = deposit32(env->pstate, 0, 1, imm);
 335         break;
 336     case 0x1e: /* DAIFSet */
 337         env->daif |= (imm << 6) & PSTATE_DAIF;
 338         break;
 339     case 0x1f: /* DAIFClear */
 340         env->daif &= ~((imm << 6) & PSTATE_DAIF);
 341         break;
 342     default:
 343         g_assert_not_reached();
 344     }
 345 }
 346
 347 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
 348    The only way to do that in TCG is a conditional branch, which clobbers
 349    all our temporaries.  For now implement these as helper functions.  */
 350
 351 /* Similarly for variable shift instructions.  */
 352
 353 uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 354 {
 355     int shift = i & 0xff;
 356     if (shift >= 32) {
 357         if (shift == 32)
 358             env->CF = x & 1;
 359         else
 360             env->CF = 0;
 361         return 0;
 362     } else if (shift != 0) {
 363         env->CF = (x >> (32 - shift)) & 1;
 364         return x << shift;
 365     }
 366     return x;
 367 }
 368
 369 uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 370 {
 371     int shift = i & 0xff;
 372     if (shift >= 32) {
 373         if (shift == 32)
 374             env->CF = (x >> 31) & 1;
 375         else
 376             env->CF = 0;
 377         return 0;
 378     } else if (shift != 0) {
 379         env->CF = (x >> (shift - 1)) & 1;
 380         return x >> shift;
 381     }
 382     return x;
 383 }
 384
 385 uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 386 {
 387     int shift = i & 0xff;
 388     if (shift >= 32) {
 389         env->CF = (x >> 31) & 1;
 390         return (int32_t)x >> 31;
 391     } else if (shift != 0) {
 392         env->CF = (x >> (shift - 1)) & 1;
 393         return (int32_t)x >> shift;
 394     }
 395     return x;
 396 }
 397
 398 uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
 399 {
 400     int shift1, shift;
 401     shift1 = i & 0xff;
 402     shift = shift1 & 0x1f;
 403     if (shift == 0) {
 404         if (shift1 != 0)
 405             env->CF = (x >> 31) & 1;
 406         return x;
 407     } else {
 408         env->CF = (x >> (shift - 1)) & 1;
 409         return ((uint32_t)x >> shift) | (x << (32 - shift));
 410     }
 411 }