target-ppc/translate_init.c

   1 /*
   2  *  PowerPC CPU initialization for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /* A lot of PowerPC definition have been included here.
  21  * Most of them are not usable for now but have been kept
  22  * inside "#if defined(TODO) ... #endif" statements to make tests easier.
  23  */
  24
  25 #include "dis-asm.h"
  26 #include "gdbstub.h"
  27
  28 //#define PPC_DUMP_CPU
  29 //#define PPC_DEBUG_SPR
  30 //#define PPC_DUMP_SPR_ACCESSES
  31 #if defined(CONFIG_USER_ONLY)
  32 #define TODO_USER_ONLY 1
  33 #endif
  34
  35 struct ppc_def_t {
  36     const char *name;
  37     uint32_t pvr;
  38     uint32_t svr;
  39     uint64_t insns_flags;
  40     uint64_t msr_mask;
  41     powerpc_mmu_t   mmu_model;
  42     powerpc_excp_t  excp_model;
  43     powerpc_input_t bus_model;
  44     uint32_t flags;
  45     int bfd_mach;
  46     void (*init_proc)(CPUPPCState *env);
  47     int  (*check_pow)(CPUPPCState *env);
  48 };
  49
  50 /* For user-mode emulation, we don't emulate any IRQ controller */
  51 #if defined(CONFIG_USER_ONLY)
  52 #define PPC_IRQ_INIT_FN(name)                                                 \
  53 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
  54 {                                                                             \
  55 }
  56 #else
  57 #define PPC_IRQ_INIT_FN(name)                                                 \
  58 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
  59 #endif
  60
  61 PPC_IRQ_INIT_FN(40x);
  62 PPC_IRQ_INIT_FN(6xx);
  63 PPC_IRQ_INIT_FN(970);
  64 PPC_IRQ_INIT_FN(POWER7);
  65 PPC_IRQ_INIT_FN(e500);
  66
  67 /* Generic callbacks:
  68  * do nothing but store/retrieve spr value
  69  */
  70 static void spr_read_generic (void *opaque, int gprn, int sprn)
  71 {
  72     gen_load_spr(cpu_gpr[gprn], sprn);
  73 #ifdef PPC_DUMP_SPR_ACCESSES
  74     {
  75         TCGv t0 = tcg_const_i32(sprn);
  76         gen_helper_load_dump_spr(t0);
  77         tcg_temp_free_i32(t0);
  78     }
  79 #endif
  80 }
  81
  82 static void spr_write_generic (void *opaque, int sprn, int gprn)
  83 {
  84     gen_store_spr(sprn, cpu_gpr[gprn]);
  85 #ifdef PPC_DUMP_SPR_ACCESSES
  86     {
  87         TCGv t0 = tcg_const_i32(sprn);
  88         gen_helper_store_dump_spr(t0);
  89         tcg_temp_free_i32(t0);
  90     }
  91 #endif
  92 }
  93
  94 #if !defined(CONFIG_USER_ONLY)
  95 static void spr_write_clear (void *opaque, int sprn, int gprn)
  96 {
  97     TCGv t0 = tcg_temp_new();
  98     TCGv t1 = tcg_temp_new();
  99     gen_load_spr(t0, sprn);
 100     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
 101     tcg_gen_and_tl(t0, t0, t1);
 102     gen_store_spr(sprn, t0);
 103     tcg_temp_free(t0);
 104     tcg_temp_free(t1);
 105 }
 106 #endif
 107
 108 /* SPR common to all PowerPC */
 109 /* XER */
 110 static void spr_read_xer (void *opaque, int gprn, int sprn)
 111 {
 112     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
 113 }
 114
 115 static void spr_write_xer (void *opaque, int sprn, int gprn)
 116 {
 117     tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
 118 }
 119
 120 /* LR */
 121 static void spr_read_lr (void *opaque, int gprn, int sprn)
 122 {
 123     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
 124 }
 125
 126 static void spr_write_lr (void *opaque, int sprn, int gprn)
 127 {
 128     tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
 129 }
 130
 131 /* CTR */
 132 static void spr_read_ctr (void *opaque, int gprn, int sprn)
 133 {
 134     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
 135 }
 136
 137 static void spr_write_ctr (void *opaque, int sprn, int gprn)
 138 {
 139     tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
 140 }
 141
 142 /* User read access to SPR */
 143 /* USPRx */
 144 /* UMMCRx */
 145 /* UPMCx */
 146 /* USIA */
 147 /* UDECR */
 148 static void spr_read_ureg (void *opaque, int gprn, int sprn)
 149 {
 150     gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
 151 }
 152
 153 /* SPR common to all non-embedded PowerPC */
 154 /* DECR */
 155 #if !defined(CONFIG_USER_ONLY)
 156 static void spr_read_decr (void *opaque, int gprn, int sprn)
 157 {
 158     if (use_icount) {
 159         gen_io_start();
 160     }
 161     gen_helper_load_decr(cpu_gpr[gprn]);
 162     if (use_icount) {
 163         gen_io_end();
 164         gen_stop_exception(opaque);
 165     }
 166 }
 167
 168 static void spr_write_decr (void *opaque, int sprn, int gprn)
 169 {
 170     if (use_icount) {
 171         gen_io_start();
 172     }
 173     gen_helper_store_decr(cpu_gpr[gprn]);
 174     if (use_icount) {
 175         gen_io_end();
 176         gen_stop_exception(opaque);
 177     }
 178 }
 179 #endif
 180
 181 /* SPR common to all non-embedded PowerPC, except 601 */
 182 /* Time base */
 183 static void spr_read_tbl (void *opaque, int gprn, int sprn)
 184 {
 185     if (use_icount) {
 186         gen_io_start();
 187     }
 188     gen_helper_load_tbl(cpu_gpr[gprn]);
 189     if (use_icount) {
 190         gen_io_end();
 191         gen_stop_exception(opaque);
 192     }
 193 }
 194
 195 static void spr_read_tbu (void *opaque, int gprn, int sprn)
 196 {
 197     if (use_icount) {
 198         gen_io_start();
 199     }
 200     gen_helper_load_tbu(cpu_gpr[gprn]);
 201     if (use_icount) {
 202         gen_io_end();
 203         gen_stop_exception(opaque);
 204     }
 205 }
 206
 207 __attribute__ (( unused ))
 208 static void spr_read_atbl (void *opaque, int gprn, int sprn)
 209 {
 210     gen_helper_load_atbl(cpu_gpr[gprn]);
 211 }
 212
 213 __attribute__ (( unused ))
 214 static void spr_read_atbu (void *opaque, int gprn, int sprn)
 215 {
 216     gen_helper_load_atbu(cpu_gpr[gprn]);
 217 }
 218
 219 #if !defined(CONFIG_USER_ONLY)
 220 static void spr_write_tbl (void *opaque, int sprn, int gprn)
 221 {
 222     if (use_icount) {
 223         gen_io_start();
 224     }
 225     gen_helper_store_tbl(cpu_gpr[gprn]);
 226     if (use_icount) {
 227         gen_io_end();
 228         gen_stop_exception(opaque);
 229     }
 230 }
 231
 232 static void spr_write_tbu (void *opaque, int sprn, int gprn)
 233 {
 234     if (use_icount) {
 235         gen_io_start();
 236     }
 237     gen_helper_store_tbu(cpu_gpr[gprn]);
 238     if (use_icount) {
 239         gen_io_end();
 240         gen_stop_exception(opaque);
 241     }
 242 }
 243
 244 __attribute__ (( unused ))
 245 static void spr_write_atbl (void *opaque, int sprn, int gprn)
 246 {
 247     gen_helper_store_atbl(cpu_gpr[gprn]);
 248 }
 249
 250 __attribute__ (( unused ))
 251 static void spr_write_atbu (void *opaque, int sprn, int gprn)
 252 {
 253     gen_helper_store_atbu(cpu_gpr[gprn]);
 254 }
 255
 256 #if defined(TARGET_PPC64)
 257 __attribute__ (( unused ))
 258 static void spr_read_purr (void *opaque, int gprn, int sprn)
 259 {
 260     gen_helper_load_purr(cpu_gpr[gprn]);
 261 }
 262 #endif
 263 #endif
 264
 265 #if !defined(CONFIG_USER_ONLY)
 266 /* IBAT0U...IBAT0U */
 267 /* IBAT0L...IBAT7L */
 268 static void spr_read_ibat (void *opaque, int gprn, int sprn)
 269 {
 270     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 271 }
 272
 273 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
 274 {
 275     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
 276 }
 277
 278 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
 279 {
 280     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 281     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
 282     tcg_temp_free_i32(t0);
 283 }
 284
 285 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
 286 {
 287     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
 288     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
 289     tcg_temp_free_i32(t0);
 290 }
 291
 292 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
 293 {
 294     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
 295     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
 296     tcg_temp_free_i32(t0);
 297 }
 298
 299 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
 300 {
 301     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
 302     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
 303     tcg_temp_free_i32(t0);
 304 }
 305
 306 /* DBAT0U...DBAT7U */
 307 /* DBAT0L...DBAT7L */
 308 static void spr_read_dbat (void *opaque, int gprn, int sprn)
 309 {
 310     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
 311 }
 312
 313 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
 314 {
 315     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
 316 }
 317
 318 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
 319 {
 320     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
 321     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
 322     tcg_temp_free_i32(t0);
 323 }
 324
 325 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
 326 {
 327     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
 328     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
 329     tcg_temp_free_i32(t0);
 330 }
 331
 332 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
 333 {
 334     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
 335     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
 336     tcg_temp_free_i32(t0);
 337 }
 338
 339 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
 340 {
 341     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
 342     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
 343     tcg_temp_free_i32(t0);
 344 }
 345
 346 /* SDR1 */
 347 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
 348 {
 349     gen_helper_store_sdr1(cpu_gpr[gprn]);
 350 }
 351
 352 /* 64 bits PowerPC specific SPRs */
 353 /* ASR */
 354 #if defined(TARGET_PPC64)
 355 static void spr_read_hior (void *opaque, int gprn, int sprn)
 356 {
 357     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
 358 }
 359
 360 static void spr_write_hior (void *opaque, int sprn, int gprn)
 361 {
 362     TCGv t0 = tcg_temp_new();
 363     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
 364     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
 365     tcg_temp_free(t0);
 366 }
 367
 368 static void spr_read_asr (void *opaque, int gprn, int sprn)
 369 {
 370     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
 371 }
 372
 373 static void spr_write_asr (void *opaque, int sprn, int gprn)
 374 {
 375     gen_helper_store_asr(cpu_gpr[gprn]);
 376 }
 377 #endif
 378 #endif
 379
 380 /* PowerPC 601 specific registers */
 381 /* RTC */
 382 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
 383 {
 384     gen_helper_load_601_rtcl(cpu_gpr[gprn]);
 385 }
 386
 387 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
 388 {
 389     gen_helper_load_601_rtcu(cpu_gpr[gprn]);
 390 }
 391
 392 #if !defined(CONFIG_USER_ONLY)
 393 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
 394 {
 395     gen_helper_store_601_rtcu(cpu_gpr[gprn]);
 396 }
 397
 398 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
 399 {
 400     gen_helper_store_601_rtcl(cpu_gpr[gprn]);
 401 }
 402
 403 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
 404 {
 405     DisasContext *ctx = opaque;
 406
 407     gen_helper_store_hid0_601(cpu_gpr[gprn]);
 408     /* Must stop the translation as endianness may have changed */
 409     gen_stop_exception(ctx);
 410 }
 411 #endif
 412
 413 /* Unified bats */
 414 #if !defined(CONFIG_USER_ONLY)
 415 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
 416 {
 417     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 418 }
 419
 420 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
 421 {
 422     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 423     gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
 424     tcg_temp_free_i32(t0);
 425 }
 426
 427 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
 428 {
 429     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 430     gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
 431     tcg_temp_free_i32(t0);
 432 }
 433 #endif
 434
 435 /* PowerPC 40x specific registers */
 436 #if !defined(CONFIG_USER_ONLY)
 437 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
 438 {
 439     gen_helper_load_40x_pit(cpu_gpr[gprn]);
 440 }
 441
 442 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
 443 {
 444     gen_helper_store_40x_pit(cpu_gpr[gprn]);
 445 }
 446
 447 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
 448 {
 449     DisasContext *ctx = opaque;
 450
 451     gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
 452     /* We must stop translation as we may have rebooted */
 453     gen_stop_exception(ctx);
 454 }
 455
 456 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
 457 {
 458     gen_helper_store_40x_sler(cpu_gpr[gprn]);
 459 }
 460
 461 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
 462 {
 463     gen_helper_store_booke_tcr(cpu_gpr[gprn]);
 464 }
 465
 466 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
 467 {
 468     gen_helper_store_booke_tsr(cpu_gpr[gprn]);
 469 }
 470 #endif
 471
 472 /* PowerPC 403 specific registers */
 473 /* PBL1 / PBU1 / PBL2 / PBU2 */
 474 #if !defined(CONFIG_USER_ONLY)
 475 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
 476 {
 477     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
 478 }
 479
 480 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
 481 {
 482     TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
 483     gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
 484     tcg_temp_free_i32(t0);
 485 }
 486
 487 static void spr_write_pir (void *opaque, int sprn, int gprn)
 488 {
 489     TCGv t0 = tcg_temp_new();
 490     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
 491     gen_store_spr(SPR_PIR, t0);
 492     tcg_temp_free(t0);
 493 }
 494 #endif
 495
 496 /* SPE specific registers */
 497 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
 498 {
 499     TCGv_i32 t0 = tcg_temp_new_i32();
 500     tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
 501     tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
 502     tcg_temp_free_i32(t0);
 503 }
 504
 505 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
 506 {
 507     TCGv_i32 t0 = tcg_temp_new_i32();
 508     tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
 509     tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
 510     tcg_temp_free_i32(t0);
 511 }
 512
 513 #if !defined(CONFIG_USER_ONLY)
 514 /* Callback used to write the exception vector base */
 515 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
 516 {
 517     TCGv t0 = tcg_temp_new();
 518     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
 519     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 520     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
 521     gen_store_spr(sprn, t0);
 522     tcg_temp_free(t0);
 523 }
 524
 525 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
 526 {
 527     DisasContext *ctx = opaque;
 528
 529     if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
 530         TCGv t0 = tcg_temp_new();
 531         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
 532         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 533         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
 534         gen_store_spr(sprn, t0);
 535         tcg_temp_free(t0);
 536     } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
 537         TCGv t0 = tcg_temp_new();
 538         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
 539         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 540         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
 541         gen_store_spr(sprn, t0);
 542         tcg_temp_free(t0);
 543     } else {
 544         printf("Trying to write an unknown exception vector %d %03x\n",
 545                sprn, sprn);
 546         gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
 547     }
 548 }
 549 #endif
 550
 551 static inline void vscr_init (CPUPPCState *env, uint32_t val)
 552 {
 553     env->vscr = val;
 554     /* Altivec always uses round-to-nearest */
 555     set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
 556     set_flush_to_zero(vscr_nj, &env->vec_status);
 557 }
 558
 559 #if defined(CONFIG_USER_ONLY)
 560 #define spr_register(env, num, name, uea_read, uea_write,                     \
 561                      oea_read, oea_write, initial_value)                      \
 562 do {                                                                          \
 563      _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
 564 } while (0)
 565 static inline void _spr_register (CPUPPCState *env, int num,
 566                                   const char *name,
 567                                   void (*uea_read)(void *opaque, int gprn, int sprn),
 568                                   void (*uea_write)(void *opaque, int sprn, int gprn),
 569                                   target_ulong initial_value)
 570 #else
 571 static inline void spr_register (CPUPPCState *env, int num,
 572                                  const char *name,
 573                                  void (*uea_read)(void *opaque, int gprn, int sprn),
 574                                  void (*uea_write)(void *opaque, int sprn, int gprn),
 575                                  void (*oea_read)(void *opaque, int gprn, int sprn),
 576                                  void (*oea_write)(void *opaque, int sprn, int gprn),
 577                                  target_ulong initial_value)
 578 #endif
 579 {
 580     ppc_spr_t *spr;
 581
 582     spr = &env->spr_cb[num];
 583     if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
 584 #if !defined(CONFIG_USER_ONLY)
 585         spr->oea_read != NULL || spr->oea_write != NULL ||
 586 #endif
 587         spr->uea_read != NULL || spr->uea_write != NULL) {
 588         printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
 589         exit(1);
 590     }
 591 #if defined(PPC_DEBUG_SPR)
 592     printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
 593            name, initial_value);
 594 #endif
 595     spr->name = name;
 596     spr->uea_read = uea_read;
 597     spr->uea_write = uea_write;
 598 #if !defined(CONFIG_USER_ONLY)
 599     spr->oea_read = oea_read;
 600     spr->oea_write = oea_write;
 601 #endif
 602     env->spr[num] = initial_value;
 603 }
 604
 605 /* Generic PowerPC SPRs */
 606 static void gen_spr_generic (CPUPPCState *env)
 607 {
 608     /* Integer processing */
 609     spr_register(env, SPR_XER, "XER",
 610                  &spr_read_xer, &spr_write_xer,
 611                  &spr_read_xer, &spr_write_xer,
 612                  0x00000000);
 613     /* Branch contol */
 614     spr_register(env, SPR_LR, "LR",
 615                  &spr_read_lr, &spr_write_lr,
 616                  &spr_read_lr, &spr_write_lr,
 617                  0x00000000);
 618     spr_register(env, SPR_CTR, "CTR",
 619                  &spr_read_ctr, &spr_write_ctr,
 620                  &spr_read_ctr, &spr_write_ctr,
 621                  0x00000000);
 622     /* Interrupt processing */
 623     spr_register(env, SPR_SRR0, "SRR0",
 624                  SPR_NOACCESS, SPR_NOACCESS,
 625                  &spr_read_generic, &spr_write_generic,
 626                  0x00000000);
 627     spr_register(env, SPR_SRR1, "SRR1",
 628                  SPR_NOACCESS, SPR_NOACCESS,
 629                  &spr_read_generic, &spr_write_generic,
 630                  0x00000000);
 631     /* Processor control */
 632     spr_register(env, SPR_SPRG0, "SPRG0",
 633                  SPR_NOACCESS, SPR_NOACCESS,
 634                  &spr_read_generic, &spr_write_generic,
 635                  0x00000000);
 636     spr_register(env, SPR_SPRG1, "SPRG1",
 637                  SPR_NOACCESS, SPR_NOACCESS,
 638                  &spr_read_generic, &spr_write_generic,
 639                  0x00000000);
 640     spr_register(env, SPR_SPRG2, "SPRG2",
 641                  SPR_NOACCESS, SPR_NOACCESS,
 642                  &spr_read_generic, &spr_write_generic,
 643                  0x00000000);
 644     spr_register(env, SPR_SPRG3, "SPRG3",
 645                  SPR_NOACCESS, SPR_NOACCESS,
 646                  &spr_read_generic, &spr_write_generic,
 647                  0x00000000);
 648 }
 649
 650 /* SPR common to all non-embedded PowerPC, including 601 */
 651 static void gen_spr_ne_601 (CPUPPCState *env)
 652 {
 653     /* Exception processing */
 654     spr_register(env, SPR_DSISR, "DSISR",
 655                  SPR_NOACCESS, SPR_NOACCESS,
 656                  &spr_read_generic, &spr_write_generic,
 657                  0x00000000);
 658     spr_register(env, SPR_DAR, "DAR",
 659                  SPR_NOACCESS, SPR_NOACCESS,
 660                  &spr_read_generic, &spr_write_generic,
 661                  0x00000000);
 662     /* Timer */
 663     spr_register(env, SPR_DECR, "DECR",
 664                  SPR_NOACCESS, SPR_NOACCESS,
 665                  &spr_read_decr, &spr_write_decr,
 666                  0x00000000);
 667     /* Memory management */
 668     spr_register(env, SPR_SDR1, "SDR1",
 669                  SPR_NOACCESS, SPR_NOACCESS,
 670                  &spr_read_generic, &spr_write_sdr1,
 671                  0x00000000);
 672 }
 673
 674 /* BATs 0-3 */
 675 static void gen_low_BATs (CPUPPCState *env)
 676 {
 677 #if !defined(CONFIG_USER_ONLY)
 678     spr_register(env, SPR_IBAT0U, "IBAT0U",
 679                  SPR_NOACCESS, SPR_NOACCESS,
 680                  &spr_read_ibat, &spr_write_ibatu,
 681                  0x00000000);
 682     spr_register(env, SPR_IBAT0L, "IBAT0L",
 683                  SPR_NOACCESS, SPR_NOACCESS,
 684                  &spr_read_ibat, &spr_write_ibatl,
 685                  0x00000000);
 686     spr_register(env, SPR_IBAT1U, "IBAT1U",
 687                  SPR_NOACCESS, SPR_NOACCESS,
 688                  &spr_read_ibat, &spr_write_ibatu,
 689                  0x00000000);
 690     spr_register(env, SPR_IBAT1L, "IBAT1L",
 691                  SPR_NOACCESS, SPR_NOACCESS,
 692                  &spr_read_ibat, &spr_write_ibatl,
 693                  0x00000000);
 694     spr_register(env, SPR_IBAT2U, "IBAT2U",
 695                  SPR_NOACCESS, SPR_NOACCESS,
 696                  &spr_read_ibat, &spr_write_ibatu,
 697                  0x00000000);
 698     spr_register(env, SPR_IBAT2L, "IBAT2L",
 699                  SPR_NOACCESS, SPR_NOACCESS,
 700                  &spr_read_ibat, &spr_write_ibatl,
 701                  0x00000000);
 702     spr_register(env, SPR_IBAT3U, "IBAT3U",
 703                  SPR_NOACCESS, SPR_NOACCESS,
 704                  &spr_read_ibat, &spr_write_ibatu,
 705                  0x00000000);
 706     spr_register(env, SPR_IBAT3L, "IBAT3L",
 707                  SPR_NOACCESS, SPR_NOACCESS,
 708                  &spr_read_ibat, &spr_write_ibatl,
 709                  0x00000000);
 710     spr_register(env, SPR_DBAT0U, "DBAT0U",
 711                  SPR_NOACCESS, SPR_NOACCESS,
 712                  &spr_read_dbat, &spr_write_dbatu,
 713                  0x00000000);
 714     spr_register(env, SPR_DBAT0L, "DBAT0L",
 715                  SPR_NOACCESS, SPR_NOACCESS,
 716                  &spr_read_dbat, &spr_write_dbatl,
 717                  0x00000000);
 718     spr_register(env, SPR_DBAT1U, "DBAT1U",
 719                  SPR_NOACCESS, SPR_NOACCESS,
 720                  &spr_read_dbat, &spr_write_dbatu,
 721                  0x00000000);
 722     spr_register(env, SPR_DBAT1L, "DBAT1L",
 723                  SPR_NOACCESS, SPR_NOACCESS,
 724                  &spr_read_dbat, &spr_write_dbatl,
 725                  0x00000000);
 726     spr_register(env, SPR_DBAT2U, "DBAT2U",
 727                  SPR_NOACCESS, SPR_NOACCESS,
 728                  &spr_read_dbat, &spr_write_dbatu,
 729                  0x00000000);
 730     spr_register(env, SPR_DBAT2L, "DBAT2L",
 731                  SPR_NOACCESS, SPR_NOACCESS,
 732                  &spr_read_dbat, &spr_write_dbatl,
 733                  0x00000000);
 734     spr_register(env, SPR_DBAT3U, "DBAT3U",
 735                  SPR_NOACCESS, SPR_NOACCESS,
 736                  &spr_read_dbat, &spr_write_dbatu,
 737                  0x00000000);
 738     spr_register(env, SPR_DBAT3L, "DBAT3L",
 739                  SPR_NOACCESS, SPR_NOACCESS,
 740                  &spr_read_dbat, &spr_write_dbatl,
 741                  0x00000000);
 742     env->nb_BATs += 4;
 743 #endif
 744 }
 745
 746 /* BATs 4-7 */
 747 static void gen_high_BATs (CPUPPCState *env)
 748 {
 749 #if !defined(CONFIG_USER_ONLY)
 750     spr_register(env, SPR_IBAT4U, "IBAT4U",
 751                  SPR_NOACCESS, SPR_NOACCESS,
 752                  &spr_read_ibat_h, &spr_write_ibatu_h,
 753                  0x00000000);
 754     spr_register(env, SPR_IBAT4L, "IBAT4L",
 755                  SPR_NOACCESS, SPR_NOACCESS,
 756                  &spr_read_ibat_h, &spr_write_ibatl_h,
 757                  0x00000000);
 758     spr_register(env, SPR_IBAT5U, "IBAT5U",
 759                  SPR_NOACCESS, SPR_NOACCESS,
 760                  &spr_read_ibat_h, &spr_write_ibatu_h,
 761                  0x00000000);
 762     spr_register(env, SPR_IBAT5L, "IBAT5L",
 763                  SPR_NOACCESS, SPR_NOACCESS,
 764                  &spr_read_ibat_h, &spr_write_ibatl_h,
 765                  0x00000000);
 766     spr_register(env, SPR_IBAT6U, "IBAT6U",
 767                  SPR_NOACCESS, SPR_NOACCESS,
 768                  &spr_read_ibat_h, &spr_write_ibatu_h,
 769                  0x00000000);
 770     spr_register(env, SPR_IBAT6L, "IBAT6L",
 771                  SPR_NOACCESS, SPR_NOACCESS,
 772                  &spr_read_ibat_h, &spr_write_ibatl_h,
 773                  0x00000000);
 774     spr_register(env, SPR_IBAT7U, "IBAT7U",
 775                  SPR_NOACCESS, SPR_NOACCESS,
 776                  &spr_read_ibat_h, &spr_write_ibatu_h,
 777                  0x00000000);
 778     spr_register(env, SPR_IBAT7L, "IBAT7L",
 779                  SPR_NOACCESS, SPR_NOACCESS,
 780                  &spr_read_ibat_h, &spr_write_ibatl_h,
 781                  0x00000000);
 782     spr_register(env, SPR_DBAT4U, "DBAT4U",
 783                  SPR_NOACCESS, SPR_NOACCESS,
 784                  &spr_read_dbat_h, &spr_write_dbatu_h,
 785                  0x00000000);
 786     spr_register(env, SPR_DBAT4L, "DBAT4L",
 787                  SPR_NOACCESS, SPR_NOACCESS,
 788                  &spr_read_dbat_h, &spr_write_dbatl_h,
 789                  0x00000000);
 790     spr_register(env, SPR_DBAT5U, "DBAT5U",
 791                  SPR_NOACCESS, SPR_NOACCESS,
 792                  &spr_read_dbat_h, &spr_write_dbatu_h,
 793                  0x00000000);
 794     spr_register(env, SPR_DBAT5L, "DBAT5L",
 795                  SPR_NOACCESS, SPR_NOACCESS,
 796                  &spr_read_dbat_h, &spr_write_dbatl_h,
 797                  0x00000000);
 798     spr_register(env, SPR_DBAT6U, "DBAT6U",
 799                  SPR_NOACCESS, SPR_NOACCESS,
 800                  &spr_read_dbat_h, &spr_write_dbatu_h,
 801                  0x00000000);
 802     spr_register(env, SPR_DBAT6L, "DBAT6L",
 803                  SPR_NOACCESS, SPR_NOACCESS,
 804                  &spr_read_dbat_h, &spr_write_dbatl_h,
 805                  0x00000000);
 806     spr_register(env, SPR_DBAT7U, "DBAT7U",
 807                  SPR_NOACCESS, SPR_NOACCESS,
 808                  &spr_read_dbat_h, &spr_write_dbatu_h,
 809                  0x00000000);
 810     spr_register(env, SPR_DBAT7L, "DBAT7L",
 811                  SPR_NOACCESS, SPR_NOACCESS,
 812                  &spr_read_dbat_h, &spr_write_dbatl_h,
 813                  0x00000000);
 814     env->nb_BATs += 4;
 815 #endif
 816 }
 817
 818 /* Generic PowerPC time base */
 819 static void gen_tbl (CPUPPCState *env)
 820 {
 821     spr_register(env, SPR_VTBL,  "TBL",
 822                  &spr_read_tbl, SPR_NOACCESS,
 823                  &spr_read_tbl, SPR_NOACCESS,
 824                  0x00000000);
 825     spr_register(env, SPR_TBL,   "TBL",
 826                  &spr_read_tbl, SPR_NOACCESS,
 827                  &spr_read_tbl, &spr_write_tbl,
 828                  0x00000000);
 829     spr_register(env, SPR_VTBU,  "TBU",
 830                  &spr_read_tbu, SPR_NOACCESS,
 831                  &spr_read_tbu, SPR_NOACCESS,
 832                  0x00000000);
 833     spr_register(env, SPR_TBU,   "TBU",
 834                  &spr_read_tbu, SPR_NOACCESS,
 835                  &spr_read_tbu, &spr_write_tbu,
 836                  0x00000000);
 837 }
 838
 839 /* Softare table search registers */
 840 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
 841 {
 842 #if !defined(CONFIG_USER_ONLY)
 843     env->nb_tlb = nb_tlbs;
 844     env->nb_ways = nb_ways;
 845     env->id_tlbs = 1;
 846     spr_register(env, SPR_DMISS, "DMISS",
 847                  SPR_NOACCESS, SPR_NOACCESS,
 848                  &spr_read_generic, SPR_NOACCESS,
 849                  0x00000000);
 850     spr_register(env, SPR_DCMP, "DCMP",
 851                  SPR_NOACCESS, SPR_NOACCESS,
 852                  &spr_read_generic, SPR_NOACCESS,
 853                  0x00000000);
 854     spr_register(env, SPR_HASH1, "HASH1",
 855                  SPR_NOACCESS, SPR_NOACCESS,
 856                  &spr_read_generic, SPR_NOACCESS,
 857                  0x00000000);
 858     spr_register(env, SPR_HASH2, "HASH2",
 859                  SPR_NOACCESS, SPR_NOACCESS,
 860                  &spr_read_generic, SPR_NOACCESS,
 861                  0x00000000);
 862     spr_register(env, SPR_IMISS, "IMISS",
 863                  SPR_NOACCESS, SPR_NOACCESS,
 864                  &spr_read_generic, SPR_NOACCESS,
 865                  0x00000000);
 866     spr_register(env, SPR_ICMP, "ICMP",
 867                  SPR_NOACCESS, SPR_NOACCESS,
 868                  &spr_read_generic, SPR_NOACCESS,
 869                  0x00000000);
 870     spr_register(env, SPR_RPA, "RPA",
 871                  SPR_NOACCESS, SPR_NOACCESS,
 872                  &spr_read_generic, &spr_write_generic,
 873                  0x00000000);
 874 #endif
 875 }
 876
 877 /* SPR common to MPC755 and G2 */
 878 static void gen_spr_G2_755 (CPUPPCState *env)
 879 {
 880     /* SGPRs */
 881     spr_register(env, SPR_SPRG4, "SPRG4",
 882                  SPR_NOACCESS, SPR_NOACCESS,
 883                  &spr_read_generic, &spr_write_generic,
 884                  0x00000000);
 885     spr_register(env, SPR_SPRG5, "SPRG5",
 886                  SPR_NOACCESS, SPR_NOACCESS,
 887                  &spr_read_generic, &spr_write_generic,
 888                  0x00000000);
 889     spr_register(env, SPR_SPRG6, "SPRG6",
 890                  SPR_NOACCESS, SPR_NOACCESS,
 891                  &spr_read_generic, &spr_write_generic,
 892                  0x00000000);
 893     spr_register(env, SPR_SPRG7, "SPRG7",
 894                  SPR_NOACCESS, SPR_NOACCESS,
 895                  &spr_read_generic, &spr_write_generic,
 896                  0x00000000);
 897 }
 898
 899 /* SPR common to all 7xx PowerPC implementations */
 900 static void gen_spr_7xx (CPUPPCState *env)
 901 {
 902     /* Breakpoints */
 903     /* XXX : not implemented */
 904     spr_register(env, SPR_DABR, "DABR",
 905                  SPR_NOACCESS, SPR_NOACCESS,
 906                  &spr_read_generic, &spr_write_generic,
 907                  0x00000000);
 908     /* XXX : not implemented */
 909     spr_register(env, SPR_IABR, "IABR",
 910                  SPR_NOACCESS, SPR_NOACCESS,
 911                  &spr_read_generic, &spr_write_generic,
 912                  0x00000000);
 913     /* Cache management */
 914     /* XXX : not implemented */
 915     spr_register(env, SPR_ICTC, "ICTC",
 916                  SPR_NOACCESS, SPR_NOACCESS,
 917                  &spr_read_generic, &spr_write_generic,
 918                  0x00000000);
 919     /* Performance monitors */
 920     /* XXX : not implemented */
 921     spr_register(env, SPR_MMCR0, "MMCR0",
 922                  SPR_NOACCESS, SPR_NOACCESS,
 923                  &spr_read_generic, &spr_write_generic,
 924                  0x00000000);
 925     /* XXX : not implemented */
 926     spr_register(env, SPR_MMCR1, "MMCR1",
 927                  SPR_NOACCESS, SPR_NOACCESS,
 928                  &spr_read_generic, &spr_write_generic,
 929                  0x00000000);
 930     /* XXX : not implemented */
 931     spr_register(env, SPR_PMC1, "PMC1",
 932                  SPR_NOACCESS, SPR_NOACCESS,
 933                  &spr_read_generic, &spr_write_generic,
 934                  0x00000000);
 935     /* XXX : not implemented */
 936     spr_register(env, SPR_PMC2, "PMC2",
 937                  SPR_NOACCESS, SPR_NOACCESS,
 938                  &spr_read_generic, &spr_write_generic,
 939                  0x00000000);
 940     /* XXX : not implemented */
 941     spr_register(env, SPR_PMC3, "PMC3",
 942                  SPR_NOACCESS, SPR_NOACCESS,
 943                  &spr_read_generic, &spr_write_generic,
 944                  0x00000000);
 945     /* XXX : not implemented */
 946     spr_register(env, SPR_PMC4, "PMC4",
 947                  SPR_NOACCESS, SPR_NOACCESS,
 948                  &spr_read_generic, &spr_write_generic,
 949                  0x00000000);
 950     /* XXX : not implemented */
 951     spr_register(env, SPR_SIAR, "SIAR",
 952                  SPR_NOACCESS, SPR_NOACCESS,
 953                  &spr_read_generic, SPR_NOACCESS,
 954                  0x00000000);
 955     /* XXX : not implemented */
 956     spr_register(env, SPR_UMMCR0, "UMMCR0",
 957                  &spr_read_ureg, SPR_NOACCESS,
 958                  &spr_read_ureg, SPR_NOACCESS,
 959                  0x00000000);
 960     /* XXX : not implemented */
 961     spr_register(env, SPR_UMMCR1, "UMMCR1",
 962                  &spr_read_ureg, SPR_NOACCESS,
 963                  &spr_read_ureg, SPR_NOACCESS,
 964                  0x00000000);
 965     /* XXX : not implemented */
 966     spr_register(env, SPR_UPMC1, "UPMC1",
 967                  &spr_read_ureg, SPR_NOACCESS,
 968                  &spr_read_ureg, SPR_NOACCESS,
 969                  0x00000000);
 970     /* XXX : not implemented */
 971     spr_register(env, SPR_UPMC2, "UPMC2",
 972                  &spr_read_ureg, SPR_NOACCESS,
 973                  &spr_read_ureg, SPR_NOACCESS,
 974                  0x00000000);
 975     /* XXX : not implemented */
 976     spr_register(env, SPR_UPMC3, "UPMC3",
 977                  &spr_read_ureg, SPR_NOACCESS,
 978                  &spr_read_ureg, SPR_NOACCESS,
 979                  0x00000000);
 980     /* XXX : not implemented */
 981     spr_register(env, SPR_UPMC4, "UPMC4",
 982                  &spr_read_ureg, SPR_NOACCESS,
 983                  &spr_read_ureg, SPR_NOACCESS,
 984                  0x00000000);
 985     /* XXX : not implemented */
 986     spr_register(env, SPR_USIAR, "USIAR",
 987                  &spr_read_ureg, SPR_NOACCESS,
 988                  &spr_read_ureg, SPR_NOACCESS,
 989                  0x00000000);
 990     /* External access control */
 991     /* XXX : not implemented */
 992     spr_register(env, SPR_EAR, "EAR",
 993                  SPR_NOACCESS, SPR_NOACCESS,
 994                  &spr_read_generic, &spr_write_generic,
 995                  0x00000000);
 996 }
 997
 998 static void gen_spr_thrm (CPUPPCState *env)
 999 {
1000     /* Thermal management */
1001     /* XXX : not implemented */
1002     spr_register(env, SPR_THRM1, "THRM1",
1003                  SPR_NOACCESS, SPR_NOACCESS,
1004                  &spr_read_generic, &spr_write_generic,
1005                  0x00000000);
1006     /* XXX : not implemented */
1007     spr_register(env, SPR_THRM2, "THRM2",
1008                  SPR_NOACCESS, SPR_NOACCESS,
1009                  &spr_read_generic, &spr_write_generic,
1010                  0x00000000);
1011     /* XXX : not implemented */
1012     spr_register(env, SPR_THRM3, "THRM3",
1013                  SPR_NOACCESS, SPR_NOACCESS,
1014                  &spr_read_generic, &spr_write_generic,
1015                  0x00000000);
1016 }
1017
1018 /* SPR specific to PowerPC 604 implementation */
1019 static void gen_spr_604 (CPUPPCState *env)
1020 {
1021     /* Processor identification */
1022     spr_register(env, SPR_PIR, "PIR",
1023                  SPR_NOACCESS, SPR_NOACCESS,
1024                  &spr_read_generic, &spr_write_pir,
1025                  0x00000000);
1026     /* Breakpoints */
1027     /* XXX : not implemented */
1028     spr_register(env, SPR_IABR, "IABR",
1029                  SPR_NOACCESS, SPR_NOACCESS,
1030                  &spr_read_generic, &spr_write_generic,
1031                  0x00000000);
1032     /* XXX : not implemented */
1033     spr_register(env, SPR_DABR, "DABR",
1034                  SPR_NOACCESS, SPR_NOACCESS,
1035                  &spr_read_generic, &spr_write_generic,
1036                  0x00000000);
1037     /* Performance counters */
1038     /* XXX : not implemented */
1039     spr_register(env, SPR_MMCR0, "MMCR0",
1040                  SPR_NOACCESS, SPR_NOACCESS,
1041                  &spr_read_generic, &spr_write_generic,
1042                  0x00000000);
1043     /* XXX : not implemented */
1044     spr_register(env, SPR_PMC1, "PMC1",
1045                  SPR_NOACCESS, SPR_NOACCESS,
1046                  &spr_read_generic, &spr_write_generic,
1047                  0x00000000);
1048     /* XXX : not implemented */
1049     spr_register(env, SPR_PMC2, "PMC2",
1050                  SPR_NOACCESS, SPR_NOACCESS,
1051                  &spr_read_generic, &spr_write_generic,
1052                  0x00000000);
1053     /* XXX : not implemented */
1054     spr_register(env, SPR_SIAR, "SIAR",
1055                  SPR_NOACCESS, SPR_NOACCESS,
1056                  &spr_read_generic, SPR_NOACCESS,
1057                  0x00000000);
1058     /* XXX : not implemented */
1059     spr_register(env, SPR_SDA, "SDA",
1060                  SPR_NOACCESS, SPR_NOACCESS,
1061                  &spr_read_generic, SPR_NOACCESS,
1062                  0x00000000);
1063     /* External access control */
1064     /* XXX : not implemented */
1065     spr_register(env, SPR_EAR, "EAR",
1066                  SPR_NOACCESS, SPR_NOACCESS,
1067                  &spr_read_generic, &spr_write_generic,
1068                  0x00000000);
1069 }
1070
1071 /* SPR specific to PowerPC 603 implementation */
1072 static void gen_spr_603 (CPUPPCState *env)
1073 {
1074     /* External access control */
1075     /* XXX : not implemented */
1076     spr_register(env, SPR_EAR, "EAR",
1077                  SPR_NOACCESS, SPR_NOACCESS,
1078                  &spr_read_generic, &spr_write_generic,
1079                  0x00000000);
1080 }
1081
1082 /* SPR specific to PowerPC G2 implementation */
1083 static void gen_spr_G2 (CPUPPCState *env)
1084 {
1085     /* Memory base address */
1086     /* MBAR */
1087     /* XXX : not implemented */
1088     spr_register(env, SPR_MBAR, "MBAR",
1089                  SPR_NOACCESS, SPR_NOACCESS,
1090                  &spr_read_generic, &spr_write_generic,
1091                  0x00000000);
1092     /* Exception processing */
1093     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1094                  SPR_NOACCESS, SPR_NOACCESS,
1095                  &spr_read_generic, &spr_write_generic,
1096                  0x00000000);
1097     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1098                  SPR_NOACCESS, SPR_NOACCESS,
1099                  &spr_read_generic, &spr_write_generic,
1100                  0x00000000);
1101     /* Breakpoints */
1102     /* XXX : not implemented */
1103     spr_register(env, SPR_DABR, "DABR",
1104                  SPR_NOACCESS, SPR_NOACCESS,
1105                  &spr_read_generic, &spr_write_generic,
1106                  0x00000000);
1107     /* XXX : not implemented */
1108     spr_register(env, SPR_DABR2, "DABR2",
1109                  SPR_NOACCESS, SPR_NOACCESS,
1110                  &spr_read_generic, &spr_write_generic,
1111                  0x00000000);
1112     /* XXX : not implemented */
1113     spr_register(env, SPR_IABR, "IABR",
1114                  SPR_NOACCESS, SPR_NOACCESS,
1115                  &spr_read_generic, &spr_write_generic,
1116                  0x00000000);
1117     /* XXX : not implemented */
1118     spr_register(env, SPR_IABR2, "IABR2",
1119                  SPR_NOACCESS, SPR_NOACCESS,
1120                  &spr_read_generic, &spr_write_generic,
1121                  0x00000000);
1122     /* XXX : not implemented */
1123     spr_register(env, SPR_IBCR, "IBCR",
1124                  SPR_NOACCESS, SPR_NOACCESS,
1125                  &spr_read_generic, &spr_write_generic,
1126                  0x00000000);
1127     /* XXX : not implemented */
1128     spr_register(env, SPR_DBCR, "DBCR",
1129                  SPR_NOACCESS, SPR_NOACCESS,
1130                  &spr_read_generic, &spr_write_generic,
1131                  0x00000000);
1132 }
1133
1134 /* SPR specific to PowerPC 602 implementation */
1135 static void gen_spr_602 (CPUPPCState *env)
1136 {
1137     /* ESA registers */
1138     /* XXX : not implemented */
1139     spr_register(env, SPR_SER, "SER",
1140                  SPR_NOACCESS, SPR_NOACCESS,
1141                  &spr_read_generic, &spr_write_generic,
1142                  0x00000000);
1143     /* XXX : not implemented */
1144     spr_register(env, SPR_SEBR, "SEBR",
1145                  SPR_NOACCESS, SPR_NOACCESS,
1146                  &spr_read_generic, &spr_write_generic,
1147                  0x00000000);
1148     /* XXX : not implemented */
1149     spr_register(env, SPR_ESASRR, "ESASRR",
1150                  SPR_NOACCESS, SPR_NOACCESS,
1151                  &spr_read_generic, &spr_write_generic,
1152                  0x00000000);
1153     /* Floating point status */
1154     /* XXX : not implemented */
1155     spr_register(env, SPR_SP, "SP",
1156                  SPR_NOACCESS, SPR_NOACCESS,
1157                  &spr_read_generic, &spr_write_generic,
1158                  0x00000000);
1159     /* XXX : not implemented */
1160     spr_register(env, SPR_LT, "LT",
1161                  SPR_NOACCESS, SPR_NOACCESS,
1162                  &spr_read_generic, &spr_write_generic,
1163                  0x00000000);
1164     /* Watchdog timer */
1165     /* XXX : not implemented */
1166     spr_register(env, SPR_TCR, "TCR",
1167                  SPR_NOACCESS, SPR_NOACCESS,
1168                  &spr_read_generic, &spr_write_generic,
1169                  0x00000000);
1170     /* Interrupt base */
1171     spr_register(env, SPR_IBR, "IBR",
1172                  SPR_NOACCESS, SPR_NOACCESS,
1173                  &spr_read_generic, &spr_write_generic,
1174                  0x00000000);
1175     /* XXX : not implemented */
1176     spr_register(env, SPR_IABR, "IABR",
1177                  SPR_NOACCESS, SPR_NOACCESS,
1178                  &spr_read_generic, &spr_write_generic,
1179                  0x00000000);
1180 }
1181
1182 /* SPR specific to PowerPC 601 implementation */
1183 static void gen_spr_601 (CPUPPCState *env)
1184 {
1185     /* Multiplication/division register */
1186     /* MQ */
1187     spr_register(env, SPR_MQ, "MQ",
1188                  &spr_read_generic, &spr_write_generic,
1189                  &spr_read_generic, &spr_write_generic,
1190                  0x00000000);
1191     /* RTC registers */
1192     spr_register(env, SPR_601_RTCU, "RTCU",
1193                  SPR_NOACCESS, SPR_NOACCESS,
1194                  SPR_NOACCESS, &spr_write_601_rtcu,
1195                  0x00000000);
1196     spr_register(env, SPR_601_VRTCU, "RTCU",
1197                  &spr_read_601_rtcu, SPR_NOACCESS,
1198                  &spr_read_601_rtcu, SPR_NOACCESS,
1199                  0x00000000);
1200     spr_register(env, SPR_601_RTCL, "RTCL",
1201                  SPR_NOACCESS, SPR_NOACCESS,
1202                  SPR_NOACCESS, &spr_write_601_rtcl,
1203                  0x00000000);
1204     spr_register(env, SPR_601_VRTCL, "RTCL",
1205                  &spr_read_601_rtcl, SPR_NOACCESS,
1206                  &spr_read_601_rtcl, SPR_NOACCESS,
1207                  0x00000000);
1208     /* Timer */
1209 #if 0 /* ? */
1210     spr_register(env, SPR_601_UDECR, "UDECR",
1211                  &spr_read_decr, SPR_NOACCESS,
1212                  &spr_read_decr, SPR_NOACCESS,
1213                  0x00000000);
1214 #endif
1215     /* External access control */
1216     /* XXX : not implemented */
1217     spr_register(env, SPR_EAR, "EAR",
1218                  SPR_NOACCESS, SPR_NOACCESS,
1219                  &spr_read_generic, &spr_write_generic,
1220                  0x00000000);
1221     /* Memory management */
1222 #if !defined(CONFIG_USER_ONLY)
1223     spr_register(env, SPR_IBAT0U, "IBAT0U",
1224                  SPR_NOACCESS, SPR_NOACCESS,
1225                  &spr_read_601_ubat, &spr_write_601_ubatu,
1226                  0x00000000);
1227     spr_register(env, SPR_IBAT0L, "IBAT0L",
1228                  SPR_NOACCESS, SPR_NOACCESS,
1229                  &spr_read_601_ubat, &spr_write_601_ubatl,
1230                  0x00000000);
1231     spr_register(env, SPR_IBAT1U, "IBAT1U",
1232                  SPR_NOACCESS, SPR_NOACCESS,
1233                  &spr_read_601_ubat, &spr_write_601_ubatu,
1234                  0x00000000);
1235     spr_register(env, SPR_IBAT1L, "IBAT1L",
1236                  SPR_NOACCESS, SPR_NOACCESS,
1237                  &spr_read_601_ubat, &spr_write_601_ubatl,
1238                  0x00000000);
1239     spr_register(env, SPR_IBAT2U, "IBAT2U",
1240                  SPR_NOACCESS, SPR_NOACCESS,
1241                  &spr_read_601_ubat, &spr_write_601_ubatu,
1242                  0x00000000);
1243     spr_register(env, SPR_IBAT2L, "IBAT2L",
1244                  SPR_NOACCESS, SPR_NOACCESS,
1245                  &spr_read_601_ubat, &spr_write_601_ubatl,
1246                  0x00000000);
1247     spr_register(env, SPR_IBAT3U, "IBAT3U",
1248                  SPR_NOACCESS, SPR_NOACCESS,
1249                  &spr_read_601_ubat, &spr_write_601_ubatu,
1250                  0x00000000);
1251     spr_register(env, SPR_IBAT3L, "IBAT3L",
1252                  SPR_NOACCESS, SPR_NOACCESS,
1253                  &spr_read_601_ubat, &spr_write_601_ubatl,
1254                  0x00000000);
1255     env->nb_BATs = 4;
1256 #endif
1257 }
1258
1259 static void gen_spr_74xx (CPUPPCState *env)
1260 {
1261     /* Processor identification */
1262     spr_register(env, SPR_PIR, "PIR",
1263                  SPR_NOACCESS, SPR_NOACCESS,
1264                  &spr_read_generic, &spr_write_pir,
1265                  0x00000000);
1266     /* XXX : not implemented */
1267     spr_register(env, SPR_MMCR2, "MMCR2",
1268                  SPR_NOACCESS, SPR_NOACCESS,
1269                  &spr_read_generic, &spr_write_generic,
1270                  0x00000000);
1271     /* XXX : not implemented */
1272     spr_register(env, SPR_UMMCR2, "UMMCR2",
1273                  &spr_read_ureg, SPR_NOACCESS,
1274                  &spr_read_ureg, SPR_NOACCESS,
1275                  0x00000000);
1276     /* XXX: not implemented */
1277     spr_register(env, SPR_BAMR, "BAMR",
1278                  SPR_NOACCESS, SPR_NOACCESS,
1279                  &spr_read_generic, &spr_write_generic,
1280                  0x00000000);
1281     /* XXX : not implemented */
1282     spr_register(env, SPR_MSSCR0, "MSSCR0",
1283                  SPR_NOACCESS, SPR_NOACCESS,
1284                  &spr_read_generic, &spr_write_generic,
1285                  0x00000000);
1286     /* Hardware implementation registers */
1287     /* XXX : not implemented */
1288     spr_register(env, SPR_HID0, "HID0",
1289                  SPR_NOACCESS, SPR_NOACCESS,
1290                  &spr_read_generic, &spr_write_generic,
1291                  0x00000000);
1292     /* XXX : not implemented */
1293     spr_register(env, SPR_HID1, "HID1",
1294                  SPR_NOACCESS, SPR_NOACCESS,
1295                  &spr_read_generic, &spr_write_generic,
1296                  0x00000000);
1297     /* Altivec */
1298     spr_register(env, SPR_VRSAVE, "VRSAVE",
1299                  &spr_read_generic, &spr_write_generic,
1300                  &spr_read_generic, &spr_write_generic,
1301                  0x00000000);
1302     /* XXX : not implemented */
1303     spr_register(env, SPR_L2CR, "L2CR",
1304                  SPR_NOACCESS, SPR_NOACCESS,
1305                  &spr_read_generic, &spr_write_generic,
1306                  0x00000000);
1307     /* Not strictly an SPR */
1308     vscr_init(env, 0x00010000);
1309 }
1310
1311 static void gen_l3_ctrl (CPUPPCState *env)
1312 {
1313     /* L3CR */
1314     /* XXX : not implemented */
1315     spr_register(env, SPR_L3CR, "L3CR",
1316                  SPR_NOACCESS, SPR_NOACCESS,
1317                  &spr_read_generic, &spr_write_generic,
1318                  0x00000000);
1319     /* L3ITCR0 */
1320     /* XXX : not implemented */
1321     spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1322                  SPR_NOACCESS, SPR_NOACCESS,
1323                  &spr_read_generic, &spr_write_generic,
1324                  0x00000000);
1325     /* L3PM */
1326     /* XXX : not implemented */
1327     spr_register(env, SPR_L3PM, "L3PM",
1328                  SPR_NOACCESS, SPR_NOACCESS,
1329                  &spr_read_generic, &spr_write_generic,
1330                  0x00000000);
1331 }
1332
1333 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1334 {
1335 #if !defined(CONFIG_USER_ONLY)
1336     env->nb_tlb = nb_tlbs;
1337     env->nb_ways = nb_ways;
1338     env->id_tlbs = 1;
1339     /* XXX : not implemented */
1340     spr_register(env, SPR_PTEHI, "PTEHI",
1341                  SPR_NOACCESS, SPR_NOACCESS,
1342                  &spr_read_generic, &spr_write_generic,
1343                  0x00000000);
1344     /* XXX : not implemented */
1345     spr_register(env, SPR_PTELO, "PTELO",
1346                  SPR_NOACCESS, SPR_NOACCESS,
1347                  &spr_read_generic, &spr_write_generic,
1348                  0x00000000);
1349     /* XXX : not implemented */
1350     spr_register(env, SPR_TLBMISS, "TLBMISS",
1351                  SPR_NOACCESS, SPR_NOACCESS,
1352                  &spr_read_generic, &spr_write_generic,
1353                  0x00000000);
1354 #endif
1355 }
1356
1357 static void gen_spr_usprgh (CPUPPCState *env)
1358 {
1359     spr_register(env, SPR_USPRG4, "USPRG4",
1360                  &spr_read_ureg, SPR_NOACCESS,
1361                  &spr_read_ureg, SPR_NOACCESS,
1362                  0x00000000);
1363     spr_register(env, SPR_USPRG5, "USPRG5",
1364                  &spr_read_ureg, SPR_NOACCESS,
1365                  &spr_read_ureg, SPR_NOACCESS,
1366                  0x00000000);
1367     spr_register(env, SPR_USPRG6, "USPRG6",
1368                  &spr_read_ureg, SPR_NOACCESS,
1369                  &spr_read_ureg, SPR_NOACCESS,
1370                  0x00000000);
1371     spr_register(env, SPR_USPRG7, "USPRG7",
1372                  &spr_read_ureg, SPR_NOACCESS,
1373                  &spr_read_ureg, SPR_NOACCESS,
1374                  0x00000000);
1375 }
1376
1377 /* PowerPC BookE SPR */
1378 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1379 {
1380     const char *ivor_names[64] = {
1381         "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1382         "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1383         "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1384         "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1385         "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1386         "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1387         "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1388         "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1389         "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1390         "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1391         "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1392         "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1393         "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1394         "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1395         "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1396         "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1397     };
1398 #define SPR_BOOKE_IVORxx (-1)
1399     int ivor_sprn[64] = {
1400         SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1401         SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1402         SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1403         SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1404         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1405         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1406         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1407         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1408         SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1409         SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1410         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1411         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1412         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1413         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1414         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1415         SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1416     };
1417     int i;
1418
1419     /* Interrupt processing */
1420     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1421                  SPR_NOACCESS, SPR_NOACCESS,
1422                  &spr_read_generic, &spr_write_generic,
1423                  0x00000000);
1424     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1425                  SPR_NOACCESS, SPR_NOACCESS,
1426                  &spr_read_generic, &spr_write_generic,
1427                  0x00000000);
1428     /* Debug */
1429     /* XXX : not implemented */
1430     spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1431                  SPR_NOACCESS, SPR_NOACCESS,
1432                  &spr_read_generic, &spr_write_generic,
1433                  0x00000000);
1434     /* XXX : not implemented */
1435     spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1436                  SPR_NOACCESS, SPR_NOACCESS,
1437                  &spr_read_generic, &spr_write_generic,
1438                  0x00000000);
1439     /* XXX : not implemented */
1440     spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1441                  SPR_NOACCESS, SPR_NOACCESS,
1442                  &spr_read_generic, &spr_write_generic,
1443                  0x00000000);
1444     /* XXX : not implemented */
1445     spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1446                  SPR_NOACCESS, SPR_NOACCESS,
1447                  &spr_read_generic, &spr_write_generic,
1448                  0x00000000);
1449     /* XXX : not implemented */
1450     spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1451                  SPR_NOACCESS, SPR_NOACCESS,
1452                  &spr_read_generic, &spr_write_generic,
1453                  0x00000000);
1454     /* XXX : not implemented */
1455     spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1456                  SPR_NOACCESS, SPR_NOACCESS,
1457                  &spr_read_generic, &spr_write_generic,
1458                  0x00000000);
1459     /* XXX : not implemented */
1460     spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1461                  SPR_NOACCESS, SPR_NOACCESS,
1462                  &spr_read_generic, &spr_write_generic,
1463                  0x00000000);
1464     /* XXX : not implemented */
1465     spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1466                  SPR_NOACCESS, SPR_NOACCESS,
1467                  &spr_read_generic, &spr_write_clear,
1468                  0x00000000);
1469     spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1470                  SPR_NOACCESS, SPR_NOACCESS,
1471                  &spr_read_generic, &spr_write_generic,
1472                  0x00000000);
1473     spr_register(env, SPR_BOOKE_ESR, "ESR",
1474                  SPR_NOACCESS, SPR_NOACCESS,
1475                  &spr_read_generic, &spr_write_generic,
1476                  0x00000000);
1477     spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1478                  SPR_NOACCESS, SPR_NOACCESS,
1479                  &spr_read_generic, &spr_write_excp_prefix,
1480                  0x00000000);
1481     /* Exception vectors */
1482     for (i = 0; i < 64; i++) {
1483         if (ivor_mask & (1ULL << i)) {
1484             if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1485                 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1486                 exit(1);
1487             }
1488             spr_register(env, ivor_sprn[i], ivor_names[i],
1489                          SPR_NOACCESS, SPR_NOACCESS,
1490                          &spr_read_generic, &spr_write_excp_vector,
1491                          0x00000000);
1492         }
1493     }
1494     spr_register(env, SPR_BOOKE_PID, "PID",
1495                  SPR_NOACCESS, SPR_NOACCESS,
1496                  &spr_read_generic, &spr_write_generic,
1497                  0x00000000);
1498     spr_register(env, SPR_BOOKE_TCR, "TCR",
1499                  SPR_NOACCESS, SPR_NOACCESS,
1500                  &spr_read_generic, &spr_write_booke_tcr,
1501                  0x00000000);
1502     spr_register(env, SPR_BOOKE_TSR, "TSR",
1503                  SPR_NOACCESS, SPR_NOACCESS,
1504                  &spr_read_generic, &spr_write_booke_tsr,
1505                  0x00000000);
1506     /* Timer */
1507     spr_register(env, SPR_DECR, "DECR",
1508                  SPR_NOACCESS, SPR_NOACCESS,
1509                  &spr_read_decr, &spr_write_decr,
1510                  0x00000000);
1511     spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1512                  SPR_NOACCESS, SPR_NOACCESS,
1513                  SPR_NOACCESS, &spr_write_generic,
1514                  0x00000000);
1515     /* SPRGs */
1516     spr_register(env, SPR_USPRG0, "USPRG0",
1517                  &spr_read_generic, &spr_write_generic,
1518                  &spr_read_generic, &spr_write_generic,
1519                  0x00000000);
1520     spr_register(env, SPR_SPRG4, "SPRG4",
1521                  SPR_NOACCESS, SPR_NOACCESS,
1522                  &spr_read_generic, &spr_write_generic,
1523                  0x00000000);
1524     spr_register(env, SPR_SPRG5, "SPRG5",
1525                  SPR_NOACCESS, SPR_NOACCESS,
1526                  &spr_read_generic, &spr_write_generic,
1527                  0x00000000);
1528     spr_register(env, SPR_SPRG6, "SPRG6",
1529                  SPR_NOACCESS, SPR_NOACCESS,
1530                  &spr_read_generic, &spr_write_generic,
1531                  0x00000000);
1532     spr_register(env, SPR_SPRG7, "SPRG7",
1533                  SPR_NOACCESS, SPR_NOACCESS,
1534                  &spr_read_generic, &spr_write_generic,
1535                  0x00000000);
1536 }
1537
1538 /* FSL storage control registers */
1539 static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
1540 {
1541 #if !defined(CONFIG_USER_ONLY)
1542     const char *mas_names[8] = {
1543         "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1544     };
1545     int mas_sprn[8] = {
1546         SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1547         SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1548     };
1549     int i;
1550
1551     /* TLB assist registers */
1552     /* XXX : not implemented */
1553     for (i = 0; i < 8; i++) {
1554         if (mas_mask & (1 << i)) {
1555             spr_register(env, mas_sprn[i], mas_names[i],
1556                          SPR_NOACCESS, SPR_NOACCESS,
1557                          &spr_read_generic, &spr_write_generic,
1558                          0x00000000);
1559         }
1560     }
1561     if (env->nb_pids > 1) {
1562         /* XXX : not implemented */
1563         spr_register(env, SPR_BOOKE_PID1, "PID1",
1564                      SPR_NOACCESS, SPR_NOACCESS,
1565                      &spr_read_generic, &spr_write_generic,
1566                      0x00000000);
1567     }
1568     if (env->nb_pids > 2) {
1569         /* XXX : not implemented */
1570         spr_register(env, SPR_BOOKE_PID2, "PID2",
1571                      SPR_NOACCESS, SPR_NOACCESS,
1572                      &spr_read_generic, &spr_write_generic,
1573                      0x00000000);
1574     }
1575     /* XXX : not implemented */
1576     spr_register(env, SPR_MMUCFG, "MMUCFG",
1577                  SPR_NOACCESS, SPR_NOACCESS,
1578                  &spr_read_generic, SPR_NOACCESS,
1579                  0x00000000); /* TOFIX */
1580     /* XXX : not implemented */
1581     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1582                  SPR_NOACCESS, SPR_NOACCESS,
1583                  &spr_read_generic, &spr_write_generic,
1584                  0x00000000); /* TOFIX */
1585     switch (env->nb_ways) {
1586     case 4:
1587         /* XXX : not implemented */
1588         spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1589                      SPR_NOACCESS, SPR_NOACCESS,
1590                      &spr_read_generic, SPR_NOACCESS,
1591                      0x00000000); /* TOFIX */
1592         /* Fallthru */
1593     case 3:
1594         /* XXX : not implemented */
1595         spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1596                      SPR_NOACCESS, SPR_NOACCESS,
1597                      &spr_read_generic, SPR_NOACCESS,
1598                      0x00000000); /* TOFIX */
1599         /* Fallthru */
1600     case 2:
1601         /* XXX : not implemented */
1602         spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1603                      SPR_NOACCESS, SPR_NOACCESS,
1604                      &spr_read_generic, SPR_NOACCESS,
1605                      0x00000000); /* TOFIX */
1606         /* Fallthru */
1607     case 1:
1608         /* XXX : not implemented */
1609         spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1610                      SPR_NOACCESS, SPR_NOACCESS,
1611                      &spr_read_generic, SPR_NOACCESS,
1612                      0x00000000); /* TOFIX */
1613         /* Fallthru */
1614     case 0:
1615     default:
1616         break;
1617     }
1618 #endif
1619 }
1620
1621 /* SPR specific to PowerPC 440 implementation */
1622 static void gen_spr_440 (CPUPPCState *env)
1623 {
1624     /* Cache control */
1625     /* XXX : not implemented */
1626     spr_register(env, SPR_440_DNV0, "DNV0",
1627                  SPR_NOACCESS, SPR_NOACCESS,
1628                  &spr_read_generic, &spr_write_generic,
1629                  0x00000000);
1630     /* XXX : not implemented */
1631     spr_register(env, SPR_440_DNV1, "DNV1",
1632                  SPR_NOACCESS, SPR_NOACCESS,
1633                  &spr_read_generic, &spr_write_generic,
1634                  0x00000000);
1635     /* XXX : not implemented */
1636     spr_register(env, SPR_440_DNV2, "DNV2",
1637                  SPR_NOACCESS, SPR_NOACCESS,
1638                  &spr_read_generic, &spr_write_generic,
1639                  0x00000000);
1640     /* XXX : not implemented */
1641     spr_register(env, SPR_440_DNV3, "DNV3",
1642                  SPR_NOACCESS, SPR_NOACCESS,
1643                  &spr_read_generic, &spr_write_generic,
1644                  0x00000000);
1645     /* XXX : not implemented */
1646     spr_register(env, SPR_440_DTV0, "DTV0",
1647                  SPR_NOACCESS, SPR_NOACCESS,
1648                  &spr_read_generic, &spr_write_generic,
1649                  0x00000000);
1650     /* XXX : not implemented */
1651     spr_register(env, SPR_440_DTV1, "DTV1",
1652                  SPR_NOACCESS, SPR_NOACCESS,
1653                  &spr_read_generic, &spr_write_generic,
1654                  0x00000000);
1655     /* XXX : not implemented */
1656     spr_register(env, SPR_440_DTV2, "DTV2",
1657                  SPR_NOACCESS, SPR_NOACCESS,
1658                  &spr_read_generic, &spr_write_generic,
1659                  0x00000000);
1660     /* XXX : not implemented */
1661     spr_register(env, SPR_440_DTV3, "DTV3",
1662                  SPR_NOACCESS, SPR_NOACCESS,
1663                  &spr_read_generic, &spr_write_generic,
1664                  0x00000000);
1665     /* XXX : not implemented */
1666     spr_register(env, SPR_440_DVLIM, "DVLIM",
1667                  SPR_NOACCESS, SPR_NOACCESS,
1668                  &spr_read_generic, &spr_write_generic,
1669                  0x00000000);
1670     /* XXX : not implemented */
1671     spr_register(env, SPR_440_INV0, "INV0",
1672                  SPR_NOACCESS, SPR_NOACCESS,
1673                  &spr_read_generic, &spr_write_generic,
1674                  0x00000000);
1675     /* XXX : not implemented */
1676     spr_register(env, SPR_440_INV1, "INV1",
1677                  SPR_NOACCESS, SPR_NOACCESS,
1678                  &spr_read_generic, &spr_write_generic,
1679                  0x00000000);
1680     /* XXX : not implemented */
1681     spr_register(env, SPR_440_INV2, "INV2",
1682                  SPR_NOACCESS, SPR_NOACCESS,
1683                  &spr_read_generic, &spr_write_generic,
1684                  0x00000000);
1685     /* XXX : not implemented */
1686     spr_register(env, SPR_440_INV3, "INV3",
1687                  SPR_NOACCESS, SPR_NOACCESS,
1688                  &spr_read_generic, &spr_write_generic,
1689                  0x00000000);
1690     /* XXX : not implemented */
1691     spr_register(env, SPR_440_ITV0, "ITV0",
1692                  SPR_NOACCESS, SPR_NOACCESS,
1693                  &spr_read_generic, &spr_write_generic,
1694                  0x00000000);
1695     /* XXX : not implemented */
1696     spr_register(env, SPR_440_ITV1, "ITV1",
1697                  SPR_NOACCESS, SPR_NOACCESS,
1698                  &spr_read_generic, &spr_write_generic,
1699                  0x00000000);
1700     /* XXX : not implemented */
1701     spr_register(env, SPR_440_ITV2, "ITV2",
1702                  SPR_NOACCESS, SPR_NOACCESS,
1703                  &spr_read_generic, &spr_write_generic,
1704                  0x00000000);
1705     /* XXX : not implemented */
1706     spr_register(env, SPR_440_ITV3, "ITV3",
1707                  SPR_NOACCESS, SPR_NOACCESS,
1708                  &spr_read_generic, &spr_write_generic,
1709                  0x00000000);
1710     /* XXX : not implemented */
1711     spr_register(env, SPR_440_IVLIM, "IVLIM",
1712                  SPR_NOACCESS, SPR_NOACCESS,
1713                  &spr_read_generic, &spr_write_generic,
1714                  0x00000000);
1715     /* Cache debug */
1716     /* XXX : not implemented */
1717     spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1718                  SPR_NOACCESS, SPR_NOACCESS,
1719                  &spr_read_generic, SPR_NOACCESS,
1720                  0x00000000);
1721     /* XXX : not implemented */
1722     spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1723                  SPR_NOACCESS, SPR_NOACCESS,
1724                  &spr_read_generic, SPR_NOACCESS,
1725                  0x00000000);
1726     /* XXX : not implemented */
1727     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1728                  SPR_NOACCESS, SPR_NOACCESS,
1729                  &spr_read_generic, SPR_NOACCESS,
1730                  0x00000000);
1731     /* XXX : not implemented */
1732     spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1733                  SPR_NOACCESS, SPR_NOACCESS,
1734                  &spr_read_generic, SPR_NOACCESS,
1735                  0x00000000);
1736     /* XXX : not implemented */
1737     spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1738                  SPR_NOACCESS, SPR_NOACCESS,
1739                  &spr_read_generic, SPR_NOACCESS,
1740                  0x00000000);
1741     /* XXX : not implemented */
1742     spr_register(env, SPR_440_DBDR, "DBDR",
1743                  SPR_NOACCESS, SPR_NOACCESS,
1744                  &spr_read_generic, &spr_write_generic,
1745                  0x00000000);
1746     /* Processor control */
1747     spr_register(env, SPR_4xx_CCR0, "CCR0",
1748                  SPR_NOACCESS, SPR_NOACCESS,
1749                  &spr_read_generic, &spr_write_generic,
1750                  0x00000000);
1751     spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1752                  SPR_NOACCESS, SPR_NOACCESS,
1753                  &spr_read_generic, SPR_NOACCESS,
1754                  0x00000000);
1755     /* Storage control */
1756     spr_register(env, SPR_440_MMUCR, "MMUCR",
1757                  SPR_NOACCESS, SPR_NOACCESS,
1758                  &spr_read_generic, &spr_write_generic,
1759                  0x00000000);
1760 }
1761
1762 /* SPR shared between PowerPC 40x implementations */
1763 static void gen_spr_40x (CPUPPCState *env)
1764 {
1765     /* Cache */
1766     /* not emulated, as Qemu do not emulate caches */
1767     spr_register(env, SPR_40x_DCCR, "DCCR",
1768                  SPR_NOACCESS, SPR_NOACCESS,
1769                  &spr_read_generic, &spr_write_generic,
1770                  0x00000000);
1771     /* not emulated, as Qemu do not emulate caches */
1772     spr_register(env, SPR_40x_ICCR, "ICCR",
1773                  SPR_NOACCESS, SPR_NOACCESS,
1774                  &spr_read_generic, &spr_write_generic,
1775                  0x00000000);
1776     /* not emulated, as Qemu do not emulate caches */
1777     spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1778                  SPR_NOACCESS, SPR_NOACCESS,
1779                  &spr_read_generic, SPR_NOACCESS,
1780                  0x00000000);
1781     /* Exception */
1782     spr_register(env, SPR_40x_DEAR, "DEAR",
1783                  SPR_NOACCESS, SPR_NOACCESS,
1784                  &spr_read_generic, &spr_write_generic,
1785                  0x00000000);
1786     spr_register(env, SPR_40x_ESR, "ESR",
1787                  SPR_NOACCESS, SPR_NOACCESS,
1788                  &spr_read_generic, &spr_write_generic,
1789                  0x00000000);
1790     spr_register(env, SPR_40x_EVPR, "EVPR",
1791                  SPR_NOACCESS, SPR_NOACCESS,
1792                  &spr_read_generic, &spr_write_excp_prefix,
1793                  0x00000000);
1794     spr_register(env, SPR_40x_SRR2, "SRR2",
1795                  &spr_read_generic, &spr_write_generic,
1796                  &spr_read_generic, &spr_write_generic,
1797                  0x00000000);
1798     spr_register(env, SPR_40x_SRR3, "SRR3",
1799                  &spr_read_generic, &spr_write_generic,
1800                  &spr_read_generic, &spr_write_generic,
1801                  0x00000000);
1802     /* Timers */
1803     spr_register(env, SPR_40x_PIT, "PIT",
1804                  SPR_NOACCESS, SPR_NOACCESS,
1805                  &spr_read_40x_pit, &spr_write_40x_pit,
1806                  0x00000000);
1807     spr_register(env, SPR_40x_TCR, "TCR",
1808                  SPR_NOACCESS, SPR_NOACCESS,
1809                  &spr_read_generic, &spr_write_booke_tcr,
1810                  0x00000000);
1811     spr_register(env, SPR_40x_TSR, "TSR",
1812                  SPR_NOACCESS, SPR_NOACCESS,
1813                  &spr_read_generic, &spr_write_booke_tsr,
1814                  0x00000000);
1815 }
1816
1817 /* SPR specific to PowerPC 405 implementation */
1818 static void gen_spr_405 (CPUPPCState *env)
1819 {
1820     /* MMU */
1821     spr_register(env, SPR_40x_PID, "PID",
1822                  SPR_NOACCESS, SPR_NOACCESS,
1823                  &spr_read_generic, &spr_write_generic,
1824                  0x00000000);
1825     spr_register(env, SPR_4xx_CCR0, "CCR0",
1826                  SPR_NOACCESS, SPR_NOACCESS,
1827                  &spr_read_generic, &spr_write_generic,
1828                  0x00700000);
1829     /* Debug interface */
1830     /* XXX : not implemented */
1831     spr_register(env, SPR_40x_DBCR0, "DBCR0",
1832                  SPR_NOACCESS, SPR_NOACCESS,
1833                  &spr_read_generic, &spr_write_40x_dbcr0,
1834                  0x00000000);
1835     /* XXX : not implemented */
1836     spr_register(env, SPR_405_DBCR1, "DBCR1",
1837                  SPR_NOACCESS, SPR_NOACCESS,
1838                  &spr_read_generic, &spr_write_generic,
1839                  0x00000000);
1840     /* XXX : not implemented */
1841     spr_register(env, SPR_40x_DBSR, "DBSR",
1842                  SPR_NOACCESS, SPR_NOACCESS,
1843                  &spr_read_generic, &spr_write_clear,
1844                  /* Last reset was system reset */
1845                  0x00000300);
1846     /* XXX : not implemented */
1847     spr_register(env, SPR_40x_DAC1, "DAC1",
1848                  SPR_NOACCESS, SPR_NOACCESS,
1849                  &spr_read_generic, &spr_write_generic,
1850                  0x00000000);
1851     spr_register(env, SPR_40x_DAC2, "DAC2",
1852                  SPR_NOACCESS, SPR_NOACCESS,
1853                  &spr_read_generic, &spr_write_generic,
1854                  0x00000000);
1855     /* XXX : not implemented */
1856     spr_register(env, SPR_405_DVC1, "DVC1",
1857                  SPR_NOACCESS, SPR_NOACCESS,
1858                  &spr_read_generic, &spr_write_generic,
1859                  0x00000000);
1860     /* XXX : not implemented */
1861     spr_register(env, SPR_405_DVC2, "DVC2",
1862                  SPR_NOACCESS, SPR_NOACCESS,
1863                  &spr_read_generic, &spr_write_generic,
1864                  0x00000000);
1865     /* XXX : not implemented */
1866     spr_register(env, SPR_40x_IAC1, "IAC1",
1867                  SPR_NOACCESS, SPR_NOACCESS,
1868                  &spr_read_generic, &spr_write_generic,
1869                  0x00000000);
1870     spr_register(env, SPR_40x_IAC2, "IAC2",
1871                  SPR_NOACCESS, SPR_NOACCESS,
1872                  &spr_read_generic, &spr_write_generic,
1873                  0x00000000);
1874     /* XXX : not implemented */
1875     spr_register(env, SPR_405_IAC3, "IAC3",
1876                  SPR_NOACCESS, SPR_NOACCESS,
1877                  &spr_read_generic, &spr_write_generic,
1878                  0x00000000);
1879     /* XXX : not implemented */
1880     spr_register(env, SPR_405_IAC4, "IAC4",
1881                  SPR_NOACCESS, SPR_NOACCESS,
1882                  &spr_read_generic, &spr_write_generic,
1883                  0x00000000);
1884     /* Storage control */
1885     /* XXX: TODO: not implemented */
1886     spr_register(env, SPR_405_SLER, "SLER",
1887                  SPR_NOACCESS, SPR_NOACCESS,
1888                  &spr_read_generic, &spr_write_40x_sler,
1889                  0x00000000);
1890     spr_register(env, SPR_40x_ZPR, "ZPR",
1891                  SPR_NOACCESS, SPR_NOACCESS,
1892                  &spr_read_generic, &spr_write_generic,
1893                  0x00000000);
1894     /* XXX : not implemented */
1895     spr_register(env, SPR_405_SU0R, "SU0R",
1896                  SPR_NOACCESS, SPR_NOACCESS,
1897                  &spr_read_generic, &spr_write_generic,
1898                  0x00000000);
1899     /* SPRG */
1900     spr_register(env, SPR_USPRG0, "USPRG0",
1901                  &spr_read_ureg, SPR_NOACCESS,
1902                  &spr_read_ureg, SPR_NOACCESS,
1903                  0x00000000);
1904     spr_register(env, SPR_SPRG4, "SPRG4",
1905                  SPR_NOACCESS, SPR_NOACCESS,
1906                  &spr_read_generic, &spr_write_generic,
1907                  0x00000000);
1908     spr_register(env, SPR_SPRG5, "SPRG5",
1909                  SPR_NOACCESS, SPR_NOACCESS,
1910                  spr_read_generic, &spr_write_generic,
1911                  0x00000000);
1912     spr_register(env, SPR_SPRG6, "SPRG6",
1913                  SPR_NOACCESS, SPR_NOACCESS,
1914                  spr_read_generic, &spr_write_generic,
1915                  0x00000000);
1916     spr_register(env, SPR_SPRG7, "SPRG7",
1917                  SPR_NOACCESS, SPR_NOACCESS,
1918                  spr_read_generic, &spr_write_generic,
1919                  0x00000000);
1920     gen_spr_usprgh(env);
1921 }
1922
1923 /* SPR shared between PowerPC 401 & 403 implementations */
1924 static void gen_spr_401_403 (CPUPPCState *env)
1925 {
1926     /* Time base */
1927     spr_register(env, SPR_403_VTBL,  "TBL",
1928                  &spr_read_tbl, SPR_NOACCESS,
1929                  &spr_read_tbl, SPR_NOACCESS,
1930                  0x00000000);
1931     spr_register(env, SPR_403_TBL,   "TBL",
1932                  SPR_NOACCESS, SPR_NOACCESS,
1933                  SPR_NOACCESS, &spr_write_tbl,
1934                  0x00000000);
1935     spr_register(env, SPR_403_VTBU,  "TBU",
1936                  &spr_read_tbu, SPR_NOACCESS,
1937                  &spr_read_tbu, SPR_NOACCESS,
1938                  0x00000000);
1939     spr_register(env, SPR_403_TBU,   "TBU",
1940                  SPR_NOACCESS, SPR_NOACCESS,
1941                  SPR_NOACCESS, &spr_write_tbu,
1942                  0x00000000);
1943     /* Debug */
1944     /* not emulated, as Qemu do not emulate caches */
1945     spr_register(env, SPR_403_CDBCR, "CDBCR",
1946                  SPR_NOACCESS, SPR_NOACCESS,
1947                  &spr_read_generic, &spr_write_generic,
1948                  0x00000000);
1949 }
1950
1951 /* SPR specific to PowerPC 401 implementation */
1952 static void gen_spr_401 (CPUPPCState *env)
1953 {
1954     /* Debug interface */
1955     /* XXX : not implemented */
1956     spr_register(env, SPR_40x_DBCR0, "DBCR",
1957                  SPR_NOACCESS, SPR_NOACCESS,
1958                  &spr_read_generic, &spr_write_40x_dbcr0,
1959                  0x00000000);
1960     /* XXX : not implemented */
1961     spr_register(env, SPR_40x_DBSR, "DBSR",
1962                  SPR_NOACCESS, SPR_NOACCESS,
1963                  &spr_read_generic, &spr_write_clear,
1964                  /* Last reset was system reset */
1965                  0x00000300);
1966     /* XXX : not implemented */
1967     spr_register(env, SPR_40x_DAC1, "DAC",
1968                  SPR_NOACCESS, SPR_NOACCESS,
1969                  &spr_read_generic, &spr_write_generic,
1970                  0x00000000);
1971     /* XXX : not implemented */
1972     spr_register(env, SPR_40x_IAC1, "IAC",
1973                  SPR_NOACCESS, SPR_NOACCESS,
1974                  &spr_read_generic, &spr_write_generic,
1975                  0x00000000);
1976     /* Storage control */
1977     /* XXX: TODO: not implemented */
1978     spr_register(env, SPR_405_SLER, "SLER",
1979                  SPR_NOACCESS, SPR_NOACCESS,
1980                  &spr_read_generic, &spr_write_40x_sler,
1981                  0x00000000);
1982     /* not emulated, as Qemu never does speculative access */
1983     spr_register(env, SPR_40x_SGR, "SGR",
1984                  SPR_NOACCESS, SPR_NOACCESS,
1985                  &spr_read_generic, &spr_write_generic,
1986                  0xFFFFFFFF);
1987     /* not emulated, as Qemu do not emulate caches */
1988     spr_register(env, SPR_40x_DCWR, "DCWR",
1989                  SPR_NOACCESS, SPR_NOACCESS,
1990                  &spr_read_generic, &spr_write_generic,
1991                  0x00000000);
1992 }
1993
1994 static void gen_spr_401x2 (CPUPPCState *env)
1995 {
1996     gen_spr_401(env);
1997     spr_register(env, SPR_40x_PID, "PID",
1998                  SPR_NOACCESS, SPR_NOACCESS,
1999                  &spr_read_generic, &spr_write_generic,
2000                  0x00000000);
2001     spr_register(env, SPR_40x_ZPR, "ZPR",
2002                  SPR_NOACCESS, SPR_NOACCESS,
2003                  &spr_read_generic, &spr_write_generic,
2004                  0x00000000);
2005 }
2006
2007 /* SPR specific to PowerPC 403 implementation */
2008 static void gen_spr_403 (CPUPPCState *env)
2009 {
2010     /* Debug interface */
2011     /* XXX : not implemented */
2012     spr_register(env, SPR_40x_DBCR0, "DBCR0",
2013                  SPR_NOACCESS, SPR_NOACCESS,
2014                  &spr_read_generic, &spr_write_40x_dbcr0,
2015                  0x00000000);
2016     /* XXX : not implemented */
2017     spr_register(env, SPR_40x_DBSR, "DBSR",
2018                  SPR_NOACCESS, SPR_NOACCESS,
2019                  &spr_read_generic, &spr_write_clear,
2020                  /* Last reset was system reset */
2021                  0x00000300);
2022     /* XXX : not implemented */
2023     spr_register(env, SPR_40x_DAC1, "DAC1",
2024                  SPR_NOACCESS, SPR_NOACCESS,
2025                  &spr_read_generic, &spr_write_generic,
2026                  0x00000000);
2027     /* XXX : not implemented */
2028     spr_register(env, SPR_40x_DAC2, "DAC2",
2029                  SPR_NOACCESS, SPR_NOACCESS,
2030                  &spr_read_generic, &spr_write_generic,
2031                  0x00000000);
2032     /* XXX : not implemented */
2033     spr_register(env, SPR_40x_IAC1, "IAC1",
2034                  SPR_NOACCESS, SPR_NOACCESS,
2035                  &spr_read_generic, &spr_write_generic,
2036                  0x00000000);
2037     /* XXX : not implemented */
2038     spr_register(env, SPR_40x_IAC2, "IAC2",
2039                  SPR_NOACCESS, SPR_NOACCESS,
2040                  &spr_read_generic, &spr_write_generic,
2041                  0x00000000);
2042 }
2043
2044 static void gen_spr_403_real (CPUPPCState *env)
2045 {
2046     spr_register(env, SPR_403_PBL1,  "PBL1",
2047                  SPR_NOACCESS, SPR_NOACCESS,
2048                  &spr_read_403_pbr, &spr_write_403_pbr,
2049                  0x00000000);
2050     spr_register(env, SPR_403_PBU1,  "PBU1",
2051                  SPR_NOACCESS, SPR_NOACCESS,
2052                  &spr_read_403_pbr, &spr_write_403_pbr,
2053                  0x00000000);
2054     spr_register(env, SPR_403_PBL2,  "PBL2",
2055                  SPR_NOACCESS, SPR_NOACCESS,
2056                  &spr_read_403_pbr, &spr_write_403_pbr,
2057                  0x00000000);
2058     spr_register(env, SPR_403_PBU2,  "PBU2",
2059                  SPR_NOACCESS, SPR_NOACCESS,
2060                  &spr_read_403_pbr, &spr_write_403_pbr,
2061                  0x00000000);
2062 }
2063
2064 static void gen_spr_403_mmu (CPUPPCState *env)
2065 {
2066     /* MMU */
2067     spr_register(env, SPR_40x_PID, "PID",
2068                  SPR_NOACCESS, SPR_NOACCESS,
2069                  &spr_read_generic, &spr_write_generic,
2070                  0x00000000);
2071     spr_register(env, SPR_40x_ZPR, "ZPR",
2072                  SPR_NOACCESS, SPR_NOACCESS,
2073                  &spr_read_generic, &spr_write_generic,
2074                  0x00000000);
2075 }
2076
2077 /* SPR specific to PowerPC compression coprocessor extension */
2078 static void gen_spr_compress (CPUPPCState *env)
2079 {
2080     /* XXX : not implemented */
2081     spr_register(env, SPR_401_SKR, "SKR",
2082                  SPR_NOACCESS, SPR_NOACCESS,
2083                  &spr_read_generic, &spr_write_generic,
2084                  0x00000000);
2085 }
2086
2087 #if defined (TARGET_PPC64)
2088 /* SPR specific to PowerPC 620 */
2089 static void gen_spr_620 (CPUPPCState *env)
2090 {
2091     /* Processor identification */
2092     spr_register(env, SPR_PIR, "PIR",
2093                  SPR_NOACCESS, SPR_NOACCESS,
2094                  &spr_read_generic, &spr_write_pir,
2095                  0x00000000);
2096     spr_register(env, SPR_ASR, "ASR",
2097                  SPR_NOACCESS, SPR_NOACCESS,
2098                  &spr_read_asr, &spr_write_asr,
2099                  0x00000000);
2100     /* Breakpoints */
2101     /* XXX : not implemented */
2102     spr_register(env, SPR_IABR, "IABR",
2103                  SPR_NOACCESS, SPR_NOACCESS,
2104                  &spr_read_generic, &spr_write_generic,
2105                  0x00000000);
2106     /* XXX : not implemented */
2107     spr_register(env, SPR_DABR, "DABR",
2108                  SPR_NOACCESS, SPR_NOACCESS,
2109                  &spr_read_generic, &spr_write_generic,
2110                  0x00000000);
2111     /* XXX : not implemented */
2112     spr_register(env, SPR_SIAR, "SIAR",
2113                  SPR_NOACCESS, SPR_NOACCESS,
2114                  &spr_read_generic, SPR_NOACCESS,
2115                  0x00000000);
2116     /* XXX : not implemented */
2117     spr_register(env, SPR_SDA, "SDA",
2118                  SPR_NOACCESS, SPR_NOACCESS,
2119                  &spr_read_generic, SPR_NOACCESS,
2120                  0x00000000);
2121     /* XXX : not implemented */
2122     spr_register(env, SPR_620_PMC1R, "PMC1",
2123                  SPR_NOACCESS, SPR_NOACCESS,
2124                  &spr_read_generic, SPR_NOACCESS,
2125                  0x00000000);
2126     spr_register(env, SPR_620_PMC1W, "PMC1",
2127                  SPR_NOACCESS, SPR_NOACCESS,
2128                   SPR_NOACCESS, &spr_write_generic,
2129                  0x00000000);
2130     /* XXX : not implemented */
2131     spr_register(env, SPR_620_PMC2R, "PMC2",
2132                  SPR_NOACCESS, SPR_NOACCESS,
2133                  &spr_read_generic, SPR_NOACCESS,
2134                  0x00000000);
2135     spr_register(env, SPR_620_PMC2W, "PMC2",
2136                  SPR_NOACCESS, SPR_NOACCESS,
2137                   SPR_NOACCESS, &spr_write_generic,
2138                  0x00000000);
2139     /* XXX : not implemented */
2140     spr_register(env, SPR_620_MMCR0R, "MMCR0",
2141                  SPR_NOACCESS, SPR_NOACCESS,
2142                  &spr_read_generic, SPR_NOACCESS,
2143                  0x00000000);
2144     spr_register(env, SPR_620_MMCR0W, "MMCR0",
2145                  SPR_NOACCESS, SPR_NOACCESS,
2146                   SPR_NOACCESS, &spr_write_generic,
2147                  0x00000000);
2148     /* External access control */
2149     /* XXX : not implemented */
2150     spr_register(env, SPR_EAR, "EAR",
2151                  SPR_NOACCESS, SPR_NOACCESS,
2152                  &spr_read_generic, &spr_write_generic,
2153                  0x00000000);
2154 #if 0 // XXX: check this
2155     /* XXX : not implemented */
2156     spr_register(env, SPR_620_PMR0, "PMR0",
2157                  SPR_NOACCESS, SPR_NOACCESS,
2158                  &spr_read_generic, &spr_write_generic,
2159                  0x00000000);
2160     /* XXX : not implemented */
2161     spr_register(env, SPR_620_PMR1, "PMR1",
2162                  SPR_NOACCESS, SPR_NOACCESS,
2163                  &spr_read_generic, &spr_write_generic,
2164                  0x00000000);
2165     /* XXX : not implemented */
2166     spr_register(env, SPR_620_PMR2, "PMR2",
2167                  SPR_NOACCESS, SPR_NOACCESS,
2168                  &spr_read_generic, &spr_write_generic,
2169                  0x00000000);
2170     /* XXX : not implemented */
2171     spr_register(env, SPR_620_PMR3, "PMR3",
2172                  SPR_NOACCESS, SPR_NOACCESS,
2173                  &spr_read_generic, &spr_write_generic,
2174                  0x00000000);
2175     /* XXX : not implemented */
2176     spr_register(env, SPR_620_PMR4, "PMR4",
2177                  SPR_NOACCESS, SPR_NOACCESS,
2178                  &spr_read_generic, &spr_write_generic,
2179                  0x00000000);
2180     /* XXX : not implemented */
2181     spr_register(env, SPR_620_PMR5, "PMR5",
2182                  SPR_NOACCESS, SPR_NOACCESS,
2183                  &spr_read_generic, &spr_write_generic,
2184                  0x00000000);
2185     /* XXX : not implemented */
2186     spr_register(env, SPR_620_PMR6, "PMR6",
2187                  SPR_NOACCESS, SPR_NOACCESS,
2188                  &spr_read_generic, &spr_write_generic,
2189                  0x00000000);
2190     /* XXX : not implemented */
2191     spr_register(env, SPR_620_PMR7, "PMR7",
2192                  SPR_NOACCESS, SPR_NOACCESS,
2193                  &spr_read_generic, &spr_write_generic,
2194                  0x00000000);
2195     /* XXX : not implemented */
2196     spr_register(env, SPR_620_PMR8, "PMR8",
2197                  SPR_NOACCESS, SPR_NOACCESS,
2198                  &spr_read_generic, &spr_write_generic,
2199                  0x00000000);
2200     /* XXX : not implemented */
2201     spr_register(env, SPR_620_PMR9, "PMR9",
2202                  SPR_NOACCESS, SPR_NOACCESS,
2203                  &spr_read_generic, &spr_write_generic,
2204                  0x00000000);
2205     /* XXX : not implemented */
2206     spr_register(env, SPR_620_PMRA, "PMR10",
2207                  SPR_NOACCESS, SPR_NOACCESS,
2208                  &spr_read_generic, &spr_write_generic,
2209                  0x00000000);
2210     /* XXX : not implemented */
2211     spr_register(env, SPR_620_PMRB, "PMR11",
2212                  SPR_NOACCESS, SPR_NOACCESS,
2213                  &spr_read_generic, &spr_write_generic,
2214                  0x00000000);
2215     /* XXX : not implemented */
2216     spr_register(env, SPR_620_PMRC, "PMR12",
2217                  SPR_NOACCESS, SPR_NOACCESS,
2218                  &spr_read_generic, &spr_write_generic,
2219                  0x00000000);
2220     /* XXX : not implemented */
2221     spr_register(env, SPR_620_PMRD, "PMR13",
2222                  SPR_NOACCESS, SPR_NOACCESS,
2223                  &spr_read_generic, &spr_write_generic,
2224                  0x00000000);
2225     /* XXX : not implemented */
2226     spr_register(env, SPR_620_PMRE, "PMR14",
2227                  SPR_NOACCESS, SPR_NOACCESS,
2228                  &spr_read_generic, &spr_write_generic,
2229                  0x00000000);
2230     /* XXX : not implemented */
2231     spr_register(env, SPR_620_PMRF, "PMR15",
2232                  SPR_NOACCESS, SPR_NOACCESS,
2233                  &spr_read_generic, &spr_write_generic,
2234                  0x00000000);
2235 #endif
2236     /* XXX : not implemented */
2237     spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2238                  SPR_NOACCESS, SPR_NOACCESS,
2239                  &spr_read_generic, &spr_write_generic,
2240                  0x00000000);
2241     /* XXX : not implemented */
2242     spr_register(env, SPR_620_L2CR, "L2CR",
2243                  SPR_NOACCESS, SPR_NOACCESS,
2244                  &spr_read_generic, &spr_write_generic,
2245                  0x00000000);
2246     /* XXX : not implemented */
2247     spr_register(env, SPR_620_L2SR, "L2SR",
2248                  SPR_NOACCESS, SPR_NOACCESS,
2249                  &spr_read_generic, &spr_write_generic,
2250                  0x00000000);
2251 }
2252 #endif /* defined (TARGET_PPC64) */
2253
2254 static void gen_spr_5xx_8xx (CPUPPCState *env)
2255 {
2256     /* Exception processing */
2257     spr_register(env, SPR_DSISR, "DSISR",
2258                  SPR_NOACCESS, SPR_NOACCESS,
2259                  &spr_read_generic, &spr_write_generic,
2260                  0x00000000);
2261     spr_register(env, SPR_DAR, "DAR",
2262                  SPR_NOACCESS, SPR_NOACCESS,
2263                  &spr_read_generic, &spr_write_generic,
2264                  0x00000000);
2265     /* Timer */
2266     spr_register(env, SPR_DECR, "DECR",
2267                  SPR_NOACCESS, SPR_NOACCESS,
2268                  &spr_read_decr, &spr_write_decr,
2269                  0x00000000);
2270     /* XXX : not implemented */
2271     spr_register(env, SPR_MPC_EIE, "EIE",
2272                  SPR_NOACCESS, SPR_NOACCESS,
2273                  &spr_read_generic, &spr_write_generic,
2274                  0x00000000);
2275     /* XXX : not implemented */
2276     spr_register(env, SPR_MPC_EID, "EID",
2277                  SPR_NOACCESS, SPR_NOACCESS,
2278                  &spr_read_generic, &spr_write_generic,
2279                  0x00000000);
2280     /* XXX : not implemented */
2281     spr_register(env, SPR_MPC_NRI, "NRI",
2282                  SPR_NOACCESS, SPR_NOACCESS,
2283                  &spr_read_generic, &spr_write_generic,
2284                  0x00000000);
2285     /* XXX : not implemented */
2286     spr_register(env, SPR_MPC_CMPA, "CMPA",
2287                  SPR_NOACCESS, SPR_NOACCESS,
2288                  &spr_read_generic, &spr_write_generic,
2289                  0x00000000);
2290     /* XXX : not implemented */
2291     spr_register(env, SPR_MPC_CMPB, "CMPB",
2292                  SPR_NOACCESS, SPR_NOACCESS,
2293                  &spr_read_generic, &spr_write_generic,
2294                  0x00000000);
2295     /* XXX : not implemented */
2296     spr_register(env, SPR_MPC_CMPC, "CMPC",
2297                  SPR_NOACCESS, SPR_NOACCESS,
2298                  &spr_read_generic, &spr_write_generic,
2299                  0x00000000);
2300     /* XXX : not implemented */
2301     spr_register(env, SPR_MPC_CMPD, "CMPD",
2302                  SPR_NOACCESS, SPR_NOACCESS,
2303                  &spr_read_generic, &spr_write_generic,
2304                  0x00000000);
2305     /* XXX : not implemented */
2306     spr_register(env, SPR_MPC_ECR, "ECR",
2307                  SPR_NOACCESS, SPR_NOACCESS,
2308                  &spr_read_generic, &spr_write_generic,
2309                  0x00000000);
2310     /* XXX : not implemented */
2311     spr_register(env, SPR_MPC_DER, "DER",
2312                  SPR_NOACCESS, SPR_NOACCESS,
2313                  &spr_read_generic, &spr_write_generic,
2314                  0x00000000);
2315     /* XXX : not implemented */
2316     spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2317                  SPR_NOACCESS, SPR_NOACCESS,
2318                  &spr_read_generic, &spr_write_generic,
2319                  0x00000000);
2320     /* XXX : not implemented */
2321     spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2322                  SPR_NOACCESS, SPR_NOACCESS,
2323                  &spr_read_generic, &spr_write_generic,
2324                  0x00000000);
2325     /* XXX : not implemented */
2326     spr_register(env, SPR_MPC_CMPE, "CMPE",
2327                  SPR_NOACCESS, SPR_NOACCESS,
2328                  &spr_read_generic, &spr_write_generic,
2329                  0x00000000);
2330     /* XXX : not implemented */
2331     spr_register(env, SPR_MPC_CMPF, "CMPF",
2332                  SPR_NOACCESS, SPR_NOACCESS,
2333                  &spr_read_generic, &spr_write_generic,
2334                  0x00000000);
2335     /* XXX : not implemented */
2336     spr_register(env, SPR_MPC_CMPG, "CMPG",
2337                  SPR_NOACCESS, SPR_NOACCESS,
2338                  &spr_read_generic, &spr_write_generic,
2339                  0x00000000);
2340     /* XXX : not implemented */
2341     spr_register(env, SPR_MPC_CMPH, "CMPH",
2342                  SPR_NOACCESS, SPR_NOACCESS,
2343                  &spr_read_generic, &spr_write_generic,
2344                  0x00000000);
2345     /* XXX : not implemented */
2346     spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2347                  SPR_NOACCESS, SPR_NOACCESS,
2348                  &spr_read_generic, &spr_write_generic,
2349                  0x00000000);
2350     /* XXX : not implemented */
2351     spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2352                  SPR_NOACCESS, SPR_NOACCESS,
2353                  &spr_read_generic, &spr_write_generic,
2354                  0x00000000);
2355     /* XXX : not implemented */
2356     spr_register(env, SPR_MPC_BAR, "BAR",
2357                  SPR_NOACCESS, SPR_NOACCESS,
2358                  &spr_read_generic, &spr_write_generic,
2359                  0x00000000);
2360     /* XXX : not implemented */
2361     spr_register(env, SPR_MPC_DPDR, "DPDR",
2362                  SPR_NOACCESS, SPR_NOACCESS,
2363                  &spr_read_generic, &spr_write_generic,
2364                  0x00000000);
2365     /* XXX : not implemented */
2366     spr_register(env, SPR_MPC_IMMR, "IMMR",
2367                  SPR_NOACCESS, SPR_NOACCESS,
2368                  &spr_read_generic, &spr_write_generic,
2369                  0x00000000);
2370 }
2371
2372 static void gen_spr_5xx (CPUPPCState *env)
2373 {
2374     /* XXX : not implemented */
2375     spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2376                  SPR_NOACCESS, SPR_NOACCESS,
2377                  &spr_read_generic, &spr_write_generic,
2378                  0x00000000);
2379     /* XXX : not implemented */
2380     spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2381                  SPR_NOACCESS, SPR_NOACCESS,
2382                  &spr_read_generic, &spr_write_generic,
2383                  0x00000000);
2384     /* XXX : not implemented */
2385     spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2386                  SPR_NOACCESS, SPR_NOACCESS,
2387                  &spr_read_generic, &spr_write_generic,
2388                  0x00000000);
2389     /* XXX : not implemented */
2390     spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2391                  SPR_NOACCESS, SPR_NOACCESS,
2392                  &spr_read_generic, &spr_write_generic,
2393                  0x00000000);
2394     /* XXX : not implemented */
2395     spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2396                  SPR_NOACCESS, SPR_NOACCESS,
2397                  &spr_read_generic, &spr_write_generic,
2398                  0x00000000);
2399     /* XXX : not implemented */
2400     spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2401                  SPR_NOACCESS, SPR_NOACCESS,
2402                  &spr_read_generic, &spr_write_generic,
2403                  0x00000000);
2404     /* XXX : not implemented */
2405     spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2406                  SPR_NOACCESS, SPR_NOACCESS,
2407                  &spr_read_generic, &spr_write_generic,
2408                  0x00000000);
2409     /* XXX : not implemented */
2410     spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2411                  SPR_NOACCESS, SPR_NOACCESS,
2412                  &spr_read_generic, &spr_write_generic,
2413                  0x00000000);
2414     /* XXX : not implemented */
2415     spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2416                  SPR_NOACCESS, SPR_NOACCESS,
2417                  &spr_read_generic, &spr_write_generic,
2418                  0x00000000);
2419     /* XXX : not implemented */
2420     spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2421                  SPR_NOACCESS, SPR_NOACCESS,
2422                  &spr_read_generic, &spr_write_generic,
2423                  0x00000000);
2424     /* XXX : not implemented */
2425     spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2426                  SPR_NOACCESS, SPR_NOACCESS,
2427                  &spr_read_generic, &spr_write_generic,
2428                  0x00000000);
2429     /* XXX : not implemented */
2430     spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2431                  SPR_NOACCESS, SPR_NOACCESS,
2432                  &spr_read_generic, &spr_write_generic,
2433                  0x00000000);
2434     /* XXX : not implemented */
2435     spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2436                  SPR_NOACCESS, SPR_NOACCESS,
2437                  &spr_read_generic, &spr_write_generic,
2438                  0x00000000);
2439     /* XXX : not implemented */
2440     spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2441                  SPR_NOACCESS, SPR_NOACCESS,
2442                  &spr_read_generic, &spr_write_generic,
2443                  0x00000000);
2444     /* XXX : not implemented */
2445     spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2446                  SPR_NOACCESS, SPR_NOACCESS,
2447                  &spr_read_generic, &spr_write_generic,
2448                  0x00000000);
2449     /* XXX : not implemented */
2450     spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2451                  SPR_NOACCESS, SPR_NOACCESS,
2452                  &spr_read_generic, &spr_write_generic,
2453                  0x00000000);
2454     /* XXX : not implemented */
2455     spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2456                  SPR_NOACCESS, SPR_NOACCESS,
2457                  &spr_read_generic, &spr_write_generic,
2458                  0x00000000);
2459     /* XXX : not implemented */
2460     spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2461                  SPR_NOACCESS, SPR_NOACCESS,
2462                  &spr_read_generic, &spr_write_generic,
2463                  0x00000000);
2464     /* XXX : not implemented */
2465     spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2466                  SPR_NOACCESS, SPR_NOACCESS,
2467                  &spr_read_generic, &spr_write_generic,
2468                  0x00000000);
2469     /* XXX : not implemented */
2470     spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2471                  SPR_NOACCESS, SPR_NOACCESS,
2472                  &spr_read_generic, &spr_write_generic,
2473                  0x00000000);
2474     /* XXX : not implemented */
2475     spr_register(env, SPR_RCPU_FPECR, "FPECR",
2476                  SPR_NOACCESS, SPR_NOACCESS,
2477                  &spr_read_generic, &spr_write_generic,
2478                  0x00000000);
2479 }
2480
2481 static void gen_spr_8xx (CPUPPCState *env)
2482 {
2483     /* XXX : not implemented */
2484     spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2485                  SPR_NOACCESS, SPR_NOACCESS,
2486                  &spr_read_generic, &spr_write_generic,
2487                  0x00000000);
2488     /* XXX : not implemented */
2489     spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2490                  SPR_NOACCESS, SPR_NOACCESS,
2491                  &spr_read_generic, &spr_write_generic,
2492                  0x00000000);
2493     /* XXX : not implemented */
2494     spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2495                  SPR_NOACCESS, SPR_NOACCESS,
2496                  &spr_read_generic, &spr_write_generic,
2497                  0x00000000);
2498     /* XXX : not implemented */
2499     spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2500                  SPR_NOACCESS, SPR_NOACCESS,
2501                  &spr_read_generic, &spr_write_generic,
2502                  0x00000000);
2503     /* XXX : not implemented */
2504     spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2505                  SPR_NOACCESS, SPR_NOACCESS,
2506                  &spr_read_generic, &spr_write_generic,
2507                  0x00000000);
2508     /* XXX : not implemented */
2509     spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2510                  SPR_NOACCESS, SPR_NOACCESS,
2511                  &spr_read_generic, &spr_write_generic,
2512                  0x00000000);
2513     /* XXX : not implemented */
2514     spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2515                  SPR_NOACCESS, SPR_NOACCESS,
2516                  &spr_read_generic, &spr_write_generic,
2517                  0x00000000);
2518     /* XXX : not implemented */
2519     spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2520                  SPR_NOACCESS, SPR_NOACCESS,
2521                  &spr_read_generic, &spr_write_generic,
2522                  0x00000000);
2523     /* XXX : not implemented */
2524     spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2525                  SPR_NOACCESS, SPR_NOACCESS,
2526                  &spr_read_generic, &spr_write_generic,
2527                  0x00000000);
2528     /* XXX : not implemented */
2529     spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2530                  SPR_NOACCESS, SPR_NOACCESS,
2531                  &spr_read_generic, &spr_write_generic,
2532                  0x00000000);
2533     /* XXX : not implemented */
2534     spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2535                  SPR_NOACCESS, SPR_NOACCESS,
2536                  &spr_read_generic, &spr_write_generic,
2537                  0x00000000);
2538     /* XXX : not implemented */
2539     spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2540                  SPR_NOACCESS, SPR_NOACCESS,
2541                  &spr_read_generic, &spr_write_generic,
2542                  0x00000000);
2543     /* XXX : not implemented */
2544     spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2545                  SPR_NOACCESS, SPR_NOACCESS,
2546                  &spr_read_generic, &spr_write_generic,
2547                  0x00000000);
2548     /* XXX : not implemented */
2549     spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2550                  SPR_NOACCESS, SPR_NOACCESS,
2551                  &spr_read_generic, &spr_write_generic,
2552                  0x00000000);
2553     /* XXX : not implemented */
2554     spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2555                  SPR_NOACCESS, SPR_NOACCESS,
2556                  &spr_read_generic, &spr_write_generic,
2557                  0x00000000);
2558     /* XXX : not implemented */
2559     spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2560                  SPR_NOACCESS, SPR_NOACCESS,
2561                  &spr_read_generic, &spr_write_generic,
2562                  0x00000000);
2563     /* XXX : not implemented */
2564     spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2565                  SPR_NOACCESS, SPR_NOACCESS,
2566                  &spr_read_generic, &spr_write_generic,
2567                  0x00000000);
2568     /* XXX : not implemented */
2569     spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2570                  SPR_NOACCESS, SPR_NOACCESS,
2571                  &spr_read_generic, &spr_write_generic,
2572                  0x00000000);
2573     /* XXX : not implemented */
2574     spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2575                  SPR_NOACCESS, SPR_NOACCESS,
2576                  &spr_read_generic, &spr_write_generic,
2577                  0x00000000);
2578     /* XXX : not implemented */
2579     spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2580                  SPR_NOACCESS, SPR_NOACCESS,
2581                  &spr_read_generic, &spr_write_generic,
2582                  0x00000000);
2583     /* XXX : not implemented */
2584     spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2585                  SPR_NOACCESS, SPR_NOACCESS,
2586                  &spr_read_generic, &spr_write_generic,
2587                  0x00000000);
2588     /* XXX : not implemented */
2589     spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2590                  SPR_NOACCESS, SPR_NOACCESS,
2591                  &spr_read_generic, &spr_write_generic,
2592                  0x00000000);
2593     /* XXX : not implemented */
2594     spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2595                  SPR_NOACCESS, SPR_NOACCESS,
2596                  &spr_read_generic, &spr_write_generic,
2597                  0x00000000);
2598     /* XXX : not implemented */
2599     spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2600                  SPR_NOACCESS, SPR_NOACCESS,
2601                  &spr_read_generic, &spr_write_generic,
2602                  0x00000000);
2603     /* XXX : not implemented */
2604     spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2605                  SPR_NOACCESS, SPR_NOACCESS,
2606                  &spr_read_generic, &spr_write_generic,
2607                  0x00000000);
2608 }
2609
2610 // XXX: TODO
2611 /*
2612  * AMR     => SPR 29 (Power 2.04)
2613  * CTRL    => SPR 136 (Power 2.04)
2614  * CTRL    => SPR 152 (Power 2.04)
2615  * SCOMC   => SPR 276 (64 bits ?)
2616  * SCOMD   => SPR 277 (64 bits ?)
2617  * TBU40   => SPR 286 (Power 2.04 hypv)
2618  * HSPRG0  => SPR 304 (Power 2.04 hypv)
2619  * HSPRG1  => SPR 305 (Power 2.04 hypv)
2620  * HDSISR  => SPR 306 (Power 2.04 hypv)
2621  * HDAR    => SPR 307 (Power 2.04 hypv)
2622  * PURR    => SPR 309 (Power 2.04 hypv)
2623  * HDEC    => SPR 310 (Power 2.04 hypv)
2624  * HIOR    => SPR 311 (hypv)
2625  * RMOR    => SPR 312 (970)
2626  * HRMOR   => SPR 313 (Power 2.04 hypv)
2627  * HSRR0   => SPR 314 (Power 2.04 hypv)
2628  * HSRR1   => SPR 315 (Power 2.04 hypv)
2629  * LPCR    => SPR 316 (970)
2630  * LPIDR   => SPR 317 (970)
2631  * EPR     => SPR 702 (Power 2.04 emb)
2632  * perf    => 768-783 (Power 2.04)
2633  * perf    => 784-799 (Power 2.04)
2634  * PPR     => SPR 896 (Power 2.04)
2635  * EPLC    => SPR 947 (Power 2.04 emb)
2636  * EPSC    => SPR 948 (Power 2.04 emb)
2637  * DABRX   => 1015    (Power 2.04 hypv)
2638  * FPECR   => SPR 1022 (?)
2639  * ... and more (thermal management, performance counters, ...)
2640  */
2641
2642 /*****************************************************************************/
2643 /* Exception vectors models                                                  */
2644 static void init_excp_4xx_real (CPUPPCState *env)
2645 {
2646 #if !defined(CONFIG_USER_ONLY)
2647     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2648     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2649     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2650     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2651     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2652     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2653     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2654     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2655     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2656     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2657     env->hreset_excp_prefix = 0x00000000UL;
2658     env->ivor_mask = 0x0000FFF0UL;
2659     env->ivpr_mask = 0xFFFF0000UL;
2660     /* Hardware reset vector */
2661     env->hreset_vector = 0xFFFFFFFCUL;
2662 #endif
2663 }
2664
2665 static void init_excp_4xx_softmmu (CPUPPCState *env)
2666 {
2667 #if !defined(CONFIG_USER_ONLY)
2668     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2669     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2670     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2671     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2672     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2673     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2674     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2675     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2676     env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2677     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2678     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2679     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2680     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2681     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2682     env->hreset_excp_prefix = 0x00000000UL;
2683     env->ivor_mask = 0x0000FFF0UL;
2684     env->ivpr_mask = 0xFFFF0000UL;
2685     /* Hardware reset vector */
2686     env->hreset_vector = 0xFFFFFFFCUL;
2687 #endif
2688 }
2689
2690 static void init_excp_MPC5xx (CPUPPCState *env)
2691 {
2692 #if !defined(CONFIG_USER_ONLY)
2693     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2694     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2695     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2696     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2697     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2698     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2699     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2700     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2701     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2702     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2703     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2704     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2705     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2706     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2707     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2708     env->hreset_excp_prefix = 0x00000000UL;
2709     env->ivor_mask = 0x0000FFF0UL;
2710     env->ivpr_mask = 0xFFFF0000UL;
2711     /* Hardware reset vector */
2712     env->hreset_vector = 0xFFFFFFFCUL;
2713 #endif
2714 }
2715
2716 static void init_excp_MPC8xx (CPUPPCState *env)
2717 {
2718 #if !defined(CONFIG_USER_ONLY)
2719     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2720     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2721     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2722     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2723     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2724     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2725     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2726     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2727     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2728     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2729     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2730     env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2731     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2732     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2733     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2734     env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2735     env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2736     env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2737     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2738     env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2739     env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2740     env->hreset_excp_prefix = 0x00000000UL;
2741     env->ivor_mask = 0x0000FFF0UL;
2742     env->ivpr_mask = 0xFFFF0000UL;
2743     /* Hardware reset vector */
2744     env->hreset_vector = 0xFFFFFFFCUL;
2745 #endif
2746 }
2747
2748 static void init_excp_G2 (CPUPPCState *env)
2749 {
2750 #if !defined(CONFIG_USER_ONLY)
2751     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2752     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2753     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2754     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2755     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2756     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2757     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2758     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2759     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2760     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2761     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2762     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2763     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2764     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2765     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2766     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2767     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2768     env->hreset_excp_prefix = 0x00000000UL;
2769     /* Hardware reset vector */
2770     env->hreset_vector = 0xFFFFFFFCUL;
2771 #endif
2772 }
2773
2774 static void init_excp_e200 (CPUPPCState *env)
2775 {
2776 #if !defined(CONFIG_USER_ONLY)
2777     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2778     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2779     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2780     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2781     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2782     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2783     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2784     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2785     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2786     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2787     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2788     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2789     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2790     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2791     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2792     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2793     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2794     env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2795     env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2796     env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2797     env->hreset_excp_prefix = 0x00000000UL;
2798     env->ivor_mask = 0x0000FFF7UL;
2799     env->ivpr_mask = 0xFFFF0000UL;
2800     /* Hardware reset vector */
2801     env->hreset_vector = 0xFFFFFFFCUL;
2802 #endif
2803 }
2804
2805 static void init_excp_BookE (CPUPPCState *env)
2806 {
2807 #if !defined(CONFIG_USER_ONLY)
2808     env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2809     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2810     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2811     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2812     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2813     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2814     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2815     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2816     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2817     env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2818     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2819     env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2820     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2821     env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2822     env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2823     env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2824     env->hreset_excp_prefix = 0x00000000UL;
2825     env->ivor_mask = 0x0000FFE0UL;
2826     env->ivpr_mask = 0xFFFF0000UL;
2827     /* Hardware reset vector */
2828     env->hreset_vector = 0xFFFFFFFCUL;
2829 #endif
2830 }
2831
2832 static void init_excp_601 (CPUPPCState *env)
2833 {
2834 #if !defined(CONFIG_USER_ONLY)
2835     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2836     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2837     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2838     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2839     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2840     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2841     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2842     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2843     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2844     env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2845     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2846     env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2847     env->hreset_excp_prefix = 0xFFF00000UL;
2848     /* Hardware reset vector */
2849     env->hreset_vector = 0x00000100UL;
2850 #endif
2851 }
2852
2853 static void init_excp_602 (CPUPPCState *env)
2854 {
2855 #if !defined(CONFIG_USER_ONLY)
2856     /* XXX: exception prefix has a special behavior on 602 */
2857     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2858     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2859     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2860     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2861     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2862     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2863     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2864     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2865     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2866     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2867     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2868     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2869     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2870     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2871     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2872     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2873     env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2874     env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2875     env->hreset_excp_prefix = 0xFFF00000UL;
2876     /* Hardware reset vector */
2877     env->hreset_vector = 0xFFFFFFFCUL;
2878 #endif
2879 }
2880
2881 static void init_excp_603 (CPUPPCState *env)
2882 {
2883 #if !defined(CONFIG_USER_ONLY)
2884     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2885     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2886     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2887     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2888     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2889     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2890     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2891     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2892     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2893     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2894     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2895     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2896     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2897     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2898     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2899     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2900     env->hreset_excp_prefix = 0x00000000UL;
2901     /* Hardware reset vector */
2902     env->hreset_vector = 0xFFFFFFFCUL;
2903 #endif
2904 }
2905
2906 static void init_excp_604 (CPUPPCState *env)
2907 {
2908 #if !defined(CONFIG_USER_ONLY)
2909     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2910     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2911     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2912     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2913     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2914     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2915     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2916     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2917     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2918     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2919     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2920     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2921     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2922     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2923     env->hreset_excp_prefix = 0xFFF00000UL;
2924     /* Hardware reset vector */
2925     env->hreset_vector = 0x00000100UL;
2926 #endif
2927 }
2928
2929 #if defined(TARGET_PPC64)
2930 static void init_excp_620 (CPUPPCState *env)
2931 {
2932 #if !defined(CONFIG_USER_ONLY)
2933     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2934     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2935     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2936     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2937     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2938     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2939     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2940     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2941     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2942     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2943     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2944     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2945     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2946     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2947     env->hreset_excp_prefix = 0xFFF00000UL;
2948     /* Hardware reset vector */
2949     env->hreset_vector = 0x0000000000000100ULL;
2950 #endif
2951 }
2952 #endif /* defined(TARGET_PPC64) */
2953
2954 static void init_excp_7x0 (CPUPPCState *env)
2955 {
2956 #if !defined(CONFIG_USER_ONLY)
2957     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2958     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2959     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2960     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2961     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2962     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2963     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2964     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2965     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2966     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2967     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2968     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2969     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2970     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2971     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2972     env->hreset_excp_prefix = 0x00000000UL;
2973     /* Hardware reset vector */
2974     env->hreset_vector = 0xFFFFFFFCUL;
2975 #endif
2976 }
2977
2978 static void init_excp_750cl (CPUPPCState *env)
2979 {
2980 #if !defined(CONFIG_USER_ONLY)
2981     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2982     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2983     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2984     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2985     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2986     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2987     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2988     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2989     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2990     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2991     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2992     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2993     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2994     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2995     env->hreset_excp_prefix = 0x00000000UL;
2996     /* Hardware reset vector */
2997     env->hreset_vector = 0xFFFFFFFCUL;
2998 #endif
2999 }
3000
3001 static void init_excp_750cx (CPUPPCState *env)
3002 {
3003 #if !defined(CONFIG_USER_ONLY)
3004     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3005     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3006     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3007     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3008     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3009     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3010     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3011     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3012     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3013     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3014     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3015     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3016     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3017     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3018     env->hreset_excp_prefix = 0x00000000UL;
3019     /* Hardware reset vector */
3020     env->hreset_vector = 0xFFFFFFFCUL;
3021 #endif
3022 }
3023
3024 /* XXX: Check if this is correct */
3025 static void init_excp_7x5 (CPUPPCState *env)
3026 {
3027 #if !defined(CONFIG_USER_ONLY)
3028     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3029     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3030     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3031     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3032     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3033     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3034     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3035     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3036     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3037     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3038     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3039     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3040     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3041     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3042     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3043     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3044     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3045     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3046     env->hreset_excp_prefix = 0x00000000UL;
3047     /* Hardware reset vector */
3048     env->hreset_vector = 0xFFFFFFFCUL;
3049 #endif
3050 }
3051
3052 static void init_excp_7400 (CPUPPCState *env)
3053 {
3054 #if !defined(CONFIG_USER_ONLY)
3055     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3056     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3057     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3058     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3059     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3060     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3061     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3062     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3063     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3064     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3065     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3066     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3067     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3068     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3069     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3070     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3071     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3072     env->hreset_excp_prefix = 0x00000000UL;
3073     /* Hardware reset vector */
3074     env->hreset_vector = 0xFFFFFFFCUL;
3075 #endif
3076 }
3077
3078 static void init_excp_7450 (CPUPPCState *env)
3079 {
3080 #if !defined(CONFIG_USER_ONLY)
3081     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3082     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3083     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3084     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3085     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3086     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3087     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3088     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3089     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3090     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3091     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3092     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3093     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3094     env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3095     env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3096     env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3097     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3098     env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3099     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3100     env->hreset_excp_prefix = 0x00000000UL;
3101     /* Hardware reset vector */
3102     env->hreset_vector = 0xFFFFFFFCUL;
3103 #endif
3104 }
3105
3106 #if defined (TARGET_PPC64)
3107 static void init_excp_970 (CPUPPCState *env)
3108 {
3109 #if !defined(CONFIG_USER_ONLY)
3110     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3111     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3112     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3113     env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3114     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3115     env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3116     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3117     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3118     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3119     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3120     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3121     env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3122     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3123     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3124     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3125     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3126     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3127     env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3128     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3129     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3130     env->hreset_excp_prefix = 0x00000000FFF00000ULL;
3131     /* Hardware reset vector */
3132     env->hreset_vector = 0x0000000000000100ULL;
3133 #endif
3134 }
3135
3136 static void init_excp_POWER7 (CPUPPCState *env)
3137 {
3138 #if !defined(CONFIG_USER_ONLY)
3139     env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3140     env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3141     env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3142     env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3143     env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3144     env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3145     env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3146     env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3147     env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3148     env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3149     env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3150     env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3151     env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3152     env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3153     env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3154     env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3155     env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3156     env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3157     env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3158     env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3159     env->hreset_excp_prefix = 0;
3160     /* Hardware reset vector */
3161     env->hreset_vector = 0x0000000000000100ULL;
3162 #endif
3163 }
3164 #endif
3165
3166 /*****************************************************************************/
3167 /* Power management enable checks                                            */
3168 static int check_pow_none (CPUPPCState *env)
3169 {
3170     return 0;
3171 }
3172
3173 static int check_pow_nocheck (CPUPPCState *env)
3174 {
3175     return 1;
3176 }
3177
3178 static int check_pow_hid0 (CPUPPCState *env)
3179 {
3180     if (env->spr[SPR_HID0] & 0x00E00000)
3181         return 1;
3182
3183     return 0;
3184 }
3185
3186 static int check_pow_hid0_74xx (CPUPPCState *env)
3187 {
3188     if (env->spr[SPR_HID0] & 0x00600000)
3189         return 1;
3190
3191     return 0;
3192 }
3193
3194 /*****************************************************************************/
3195 /* PowerPC implementations definitions                                       */
3196
3197 /* PowerPC 401                                                               */
3198 #define POWERPC_INSNS_401    (PPC_INSNS_BASE | PPC_STRING |                   \
3199                               PPC_WRTEE | PPC_DCR |                           \
3200                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3201                               PPC_CACHE_DCBZ |                                \
3202                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3203                               PPC_4xx_COMMON | PPC_40x_EXCP)
3204 #define POWERPC_MSRM_401     (0x00000000000FD201ULL)
3205 #define POWERPC_MMU_401      (POWERPC_MMU_REAL)
3206 #define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
3207 #define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
3208 #define POWERPC_BFDM_401     (bfd_mach_ppc_403)
3209 #define POWERPC_FLAG_401     (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3210                               POWERPC_FLAG_BUS_CLK)
3211 #define check_pow_401        check_pow_nocheck
3212
3213 static void init_proc_401 (CPUPPCState *env)
3214 {
3215     gen_spr_40x(env);
3216     gen_spr_401_403(env);
3217     gen_spr_401(env);
3218     init_excp_4xx_real(env);
3219     env->dcache_line_size = 32;
3220     env->icache_line_size = 32;
3221     /* Allocate hardware IRQ controller */
3222     ppc40x_irq_init(env);
3223 }
3224
3225 /* PowerPC 401x2                                                             */
3226 #define POWERPC_INSNS_401x2  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3227                               PPC_DCR | PPC_WRTEE |                           \
3228                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3229                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3230                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3231                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3232                               PPC_4xx_COMMON | PPC_40x_EXCP)
3233 #define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
3234 #define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
3235 #define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
3236 #define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
3237 #define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
3238 #define POWERPC_FLAG_401x2   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3239                               POWERPC_FLAG_BUS_CLK)
3240 #define check_pow_401x2      check_pow_nocheck
3241
3242 static void init_proc_401x2 (CPUPPCState *env)
3243 {
3244     gen_spr_40x(env);
3245     gen_spr_401_403(env);
3246     gen_spr_401x2(env);
3247     gen_spr_compress(env);
3248     /* Memory management */
3249 #if !defined(CONFIG_USER_ONLY)
3250     env->nb_tlb = 64;
3251     env->nb_ways = 1;
3252     env->id_tlbs = 0;
3253 #endif
3254     init_excp_4xx_softmmu(env);
3255     env->dcache_line_size = 32;
3256     env->icache_line_size = 32;
3257     /* Allocate hardware IRQ controller */
3258     ppc40x_irq_init(env);
3259 }
3260
3261 /* PowerPC 401x3                                                             */
3262 #define POWERPC_INSNS_401x3  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3263                               PPC_DCR | PPC_WRTEE |                           \
3264                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3265                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3266                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3267                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3268                               PPC_4xx_COMMON | PPC_40x_EXCP)
3269 #define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
3270 #define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
3271 #define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
3272 #define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
3273 #define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
3274 #define POWERPC_FLAG_401x3   (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3275                               POWERPC_FLAG_BUS_CLK)
3276 #define check_pow_401x3      check_pow_nocheck
3277
3278 __attribute__ (( unused ))
3279 static void init_proc_401x3 (CPUPPCState *env)
3280 {
3281     gen_spr_40x(env);
3282     gen_spr_401_403(env);
3283     gen_spr_401(env);
3284     gen_spr_401x2(env);
3285     gen_spr_compress(env);
3286     init_excp_4xx_softmmu(env);
3287     env->dcache_line_size = 32;
3288     env->icache_line_size = 32;
3289     /* Allocate hardware IRQ controller */
3290     ppc40x_irq_init(env);
3291 }
3292
3293 /* IOP480                                                                    */
3294 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING |                   \
3295                               PPC_DCR | PPC_WRTEE |                           \
3296                               PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |    \
3297                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3298                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3299                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3300                               PPC_4xx_COMMON | PPC_40x_EXCP)
3301 #define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
3302 #define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
3303 #define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
3304 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3305 #define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
3306 #define POWERPC_FLAG_IOP480  (POWERPC_FLAG_CE | POWERPC_FLAG_DE |             \
3307                               POWERPC_FLAG_BUS_CLK)
3308 #define check_pow_IOP480     check_pow_nocheck
3309
3310 static void init_proc_IOP480 (CPUPPCState *env)
3311 {
3312     gen_spr_40x(env);
3313     gen_spr_401_403(env);
3314     gen_spr_401x2(env);
3315     gen_spr_compress(env);
3316     /* Memory management */
3317 #if !defined(CONFIG_USER_ONLY)
3318     env->nb_tlb = 64;
3319     env->nb_ways = 1;
3320     env->id_tlbs = 0;
3321 #endif
3322     init_excp_4xx_softmmu(env);
3323     env->dcache_line_size = 32;
3324     env->icache_line_size = 32;
3325     /* Allocate hardware IRQ controller */
3326     ppc40x_irq_init(env);
3327 }
3328
3329 /* PowerPC 403                                                               */
3330 #define POWERPC_INSNS_403    (PPC_INSNS_BASE | PPC_STRING |                   \
3331                               PPC_DCR | PPC_WRTEE |                           \
3332                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3333                               PPC_CACHE_DCBZ |                                \
3334                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3335                               PPC_4xx_COMMON | PPC_40x_EXCP)
3336 #define POWERPC_MSRM_403     (0x000000000007D00DULL)
3337 #define POWERPC_MMU_403      (POWERPC_MMU_REAL)
3338 #define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
3339 #define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
3340 #define POWERPC_BFDM_403     (bfd_mach_ppc_403)
3341 #define POWERPC_FLAG_403     (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3342                               POWERPC_FLAG_BUS_CLK)
3343 #define check_pow_403        check_pow_nocheck
3344
3345 static void init_proc_403 (CPUPPCState *env)
3346 {
3347     gen_spr_40x(env);
3348     gen_spr_401_403(env);
3349     gen_spr_403(env);
3350     gen_spr_403_real(env);
3351     init_excp_4xx_real(env);
3352     env->dcache_line_size = 32;
3353     env->icache_line_size = 32;
3354     /* Allocate hardware IRQ controller */
3355     ppc40x_irq_init(env);
3356 }
3357
3358 /* PowerPC 403 GCX                                                           */
3359 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING |                   \
3360                               PPC_DCR | PPC_WRTEE |                           \
3361                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3362                               PPC_CACHE_DCBZ |                                \
3363                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3364                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3365                               PPC_4xx_COMMON | PPC_40x_EXCP)
3366 #define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
3367 #define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
3368 #define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
3369 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3370 #define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
3371 #define POWERPC_FLAG_403GCX  (POWERPC_FLAG_CE | POWERPC_FLAG_PX |             \
3372                               POWERPC_FLAG_BUS_CLK)
3373 #define check_pow_403GCX     check_pow_nocheck
3374
3375 static void init_proc_403GCX (CPUPPCState *env)
3376 {
3377     gen_spr_40x(env);
3378     gen_spr_401_403(env);
3379     gen_spr_403(env);
3380     gen_spr_403_real(env);
3381     gen_spr_403_mmu(env);
3382     /* Bus access control */
3383     /* not emulated, as Qemu never does speculative access */
3384     spr_register(env, SPR_40x_SGR, "SGR",
3385                  SPR_NOACCESS, SPR_NOACCESS,
3386                  &spr_read_generic, &spr_write_generic,
3387                  0xFFFFFFFF);
3388     /* not emulated, as Qemu do not emulate caches */
3389     spr_register(env, SPR_40x_DCWR, "DCWR",
3390                  SPR_NOACCESS, SPR_NOACCESS,
3391                  &spr_read_generic, &spr_write_generic,
3392                  0x00000000);
3393     /* Memory management */
3394 #if !defined(CONFIG_USER_ONLY)
3395     env->nb_tlb = 64;
3396     env->nb_ways = 1;
3397     env->id_tlbs = 0;
3398 #endif
3399     init_excp_4xx_softmmu(env);
3400     env->dcache_line_size = 32;
3401     env->icache_line_size = 32;
3402     /* Allocate hardware IRQ controller */
3403     ppc40x_irq_init(env);
3404 }
3405
3406 /* PowerPC 405                                                               */
3407 #define POWERPC_INSNS_405    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3408                               PPC_DCR | PPC_WRTEE |                           \
3409                               PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |     \
3410                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3411                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3412                               PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3413                               PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3414 #define POWERPC_MSRM_405     (0x000000000006E630ULL)
3415 #define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
3416 #define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
3417 #define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
3418 #define POWERPC_BFDM_405     (bfd_mach_ppc_403)
3419 #define POWERPC_FLAG_405     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3420                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3421 #define check_pow_405        check_pow_nocheck
3422
3423 static void init_proc_405 (CPUPPCState *env)
3424 {
3425     /* Time base */
3426     gen_tbl(env);
3427     gen_spr_40x(env);
3428     gen_spr_405(env);
3429     /* Bus access control */
3430     /* not emulated, as Qemu never does speculative access */
3431     spr_register(env, SPR_40x_SGR, "SGR",
3432                  SPR_NOACCESS, SPR_NOACCESS,
3433                  &spr_read_generic, &spr_write_generic,
3434                  0xFFFFFFFF);
3435     /* not emulated, as Qemu do not emulate caches */
3436     spr_register(env, SPR_40x_DCWR, "DCWR",
3437                  SPR_NOACCESS, SPR_NOACCESS,
3438                  &spr_read_generic, &spr_write_generic,
3439                  0x00000000);
3440     /* Memory management */
3441 #if !defined(CONFIG_USER_ONLY)
3442     env->nb_tlb = 64;
3443     env->nb_ways = 1;
3444     env->id_tlbs = 0;
3445 #endif
3446     init_excp_4xx_softmmu(env);
3447     env->dcache_line_size = 32;
3448     env->icache_line_size = 32;
3449     /* Allocate hardware IRQ controller */
3450     ppc40x_irq_init(env);
3451 }
3452
3453 /* PowerPC 440 EP                                                            */
3454 #define POWERPC_INSNS_440EP  (PPC_INSNS_BASE | PPC_STRING |                   \
3455                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3456                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3457                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3458                               PPC_MEM_TLBSYNC | PPC_MFTB |                    \
3459                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3460                               PPC_440_SPEC)
3461 #define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
3462 #define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
3463 #define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
3464 #define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
3465 #define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
3466 #define POWERPC_FLAG_440EP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3467                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3468 #define check_pow_440EP      check_pow_nocheck
3469
3470 __attribute__ (( unused ))
3471 static void init_proc_440EP (CPUPPCState *env)
3472 {
3473     /* Time base */
3474     gen_tbl(env);
3475     gen_spr_BookE(env, 0x000000000000FFFFULL);
3476     gen_spr_440(env);
3477     gen_spr_usprgh(env);
3478     /* Processor identification */
3479     spr_register(env, SPR_BOOKE_PIR, "PIR",
3480                  SPR_NOACCESS, SPR_NOACCESS,
3481                  &spr_read_generic, &spr_write_pir,
3482                  0x00000000);
3483     /* XXX : not implemented */
3484     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3485                  SPR_NOACCESS, SPR_NOACCESS,
3486                  &spr_read_generic, &spr_write_generic,
3487                  0x00000000);
3488     /* XXX : not implemented */
3489     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3490                  SPR_NOACCESS, SPR_NOACCESS,
3491                  &spr_read_generic, &spr_write_generic,
3492                  0x00000000);
3493     /* XXX : not implemented */
3494     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3495                  SPR_NOACCESS, SPR_NOACCESS,
3496                  &spr_read_generic, &spr_write_generic,
3497                  0x00000000);
3498     /* XXX : not implemented */
3499     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3500                  SPR_NOACCESS, SPR_NOACCESS,
3501                  &spr_read_generic, &spr_write_generic,
3502                  0x00000000);
3503     /* XXX : not implemented */
3504     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3505                  SPR_NOACCESS, SPR_NOACCESS,
3506                  &spr_read_generic, &spr_write_generic,
3507                  0x00000000);
3508     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3509                  SPR_NOACCESS, SPR_NOACCESS,
3510                  &spr_read_generic, &spr_write_generic,
3511                  0x00000000);
3512     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3513                  SPR_NOACCESS, SPR_NOACCESS,
3514                  &spr_read_generic, &spr_write_generic,
3515                  0x00000000);
3516     /* XXX : not implemented */
3517     spr_register(env, SPR_440_CCR1, "CCR1",
3518                  SPR_NOACCESS, SPR_NOACCESS,
3519                  &spr_read_generic, &spr_write_generic,
3520                  0x00000000);
3521     /* Memory management */
3522 #if !defined(CONFIG_USER_ONLY)
3523     env->nb_tlb = 64;
3524     env->nb_ways = 1;
3525     env->id_tlbs = 0;
3526 #endif
3527     init_excp_BookE(env);
3528     env->dcache_line_size = 32;
3529     env->icache_line_size = 32;
3530     /* XXX: TODO: allocate internal IRQ controller */
3531 }
3532
3533 /* PowerPC 440 GP                                                            */
3534 #define POWERPC_INSNS_440GP  (PPC_INSNS_BASE | PPC_STRING |                   \
3535                               PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |  \
3536                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3537                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3538                               PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |       \
3539                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3540                               PPC_440_SPEC)
3541 #define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
3542 #define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
3543 #define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
3544 #define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
3545 #define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
3546 #define POWERPC_FLAG_440GP   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3547                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3548 #define check_pow_440GP      check_pow_nocheck
3549
3550 __attribute__ (( unused ))
3551 static void init_proc_440GP (CPUPPCState *env)
3552 {
3553     /* Time base */
3554     gen_tbl(env);
3555     gen_spr_BookE(env, 0x000000000000FFFFULL);
3556     gen_spr_440(env);
3557     gen_spr_usprgh(env);
3558     /* Processor identification */
3559     spr_register(env, SPR_BOOKE_PIR, "PIR",
3560                  SPR_NOACCESS, SPR_NOACCESS,
3561                  &spr_read_generic, &spr_write_pir,
3562                  0x00000000);
3563     /* XXX : not implemented */
3564     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3565                  SPR_NOACCESS, SPR_NOACCESS,
3566                  &spr_read_generic, &spr_write_generic,
3567                  0x00000000);
3568     /* XXX : not implemented */
3569     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3570                  SPR_NOACCESS, SPR_NOACCESS,
3571                  &spr_read_generic, &spr_write_generic,
3572                  0x00000000);
3573     /* XXX : not implemented */
3574     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3575                  SPR_NOACCESS, SPR_NOACCESS,
3576                  &spr_read_generic, &spr_write_generic,
3577                  0x00000000);
3578     /* XXX : not implemented */
3579     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3580                  SPR_NOACCESS, SPR_NOACCESS,
3581                  &spr_read_generic, &spr_write_generic,
3582                  0x00000000);
3583     /* Memory management */
3584 #if !defined(CONFIG_USER_ONLY)
3585     env->nb_tlb = 64;
3586     env->nb_ways = 1;
3587     env->id_tlbs = 0;
3588 #endif
3589     init_excp_BookE(env);
3590     env->dcache_line_size = 32;
3591     env->icache_line_size = 32;
3592     /* XXX: TODO: allocate internal IRQ controller */
3593 }
3594
3595 /* PowerPC 440x4                                                             */
3596 #define POWERPC_INSNS_440x4  (PPC_INSNS_BASE | PPC_STRING |                   \
3597                               PPC_DCR | PPC_WRTEE |                           \
3598                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3599                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3600                               PPC_MEM_TLBSYNC | PPC_MFTB |                    \
3601                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3602                               PPC_440_SPEC)
3603 #define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
3604 #define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
3605 #define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
3606 #define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
3607 #define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
3608 #define POWERPC_FLAG_440x4   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3609                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3610 #define check_pow_440x4      check_pow_nocheck
3611
3612 __attribute__ (( unused ))
3613 static void init_proc_440x4 (CPUPPCState *env)
3614 {
3615     /* Time base */
3616     gen_tbl(env);
3617     gen_spr_BookE(env, 0x000000000000FFFFULL);
3618     gen_spr_440(env);
3619     gen_spr_usprgh(env);
3620     /* Processor identification */
3621     spr_register(env, SPR_BOOKE_PIR, "PIR",
3622                  SPR_NOACCESS, SPR_NOACCESS,
3623                  &spr_read_generic, &spr_write_pir,
3624                  0x00000000);
3625     /* XXX : not implemented */
3626     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3627                  SPR_NOACCESS, SPR_NOACCESS,
3628                  &spr_read_generic, &spr_write_generic,
3629                  0x00000000);
3630     /* XXX : not implemented */
3631     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3632                  SPR_NOACCESS, SPR_NOACCESS,
3633                  &spr_read_generic, &spr_write_generic,
3634                  0x00000000);
3635     /* XXX : not implemented */
3636     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3637                  SPR_NOACCESS, SPR_NOACCESS,
3638                  &spr_read_generic, &spr_write_generic,
3639                  0x00000000);
3640     /* XXX : not implemented */
3641     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3642                  SPR_NOACCESS, SPR_NOACCESS,
3643                  &spr_read_generic, &spr_write_generic,
3644                  0x00000000);
3645     /* Memory management */
3646 #if !defined(CONFIG_USER_ONLY)
3647     env->nb_tlb = 64;
3648     env->nb_ways = 1;
3649     env->id_tlbs = 0;
3650 #endif
3651     init_excp_BookE(env);
3652     env->dcache_line_size = 32;
3653     env->icache_line_size = 32;
3654     /* XXX: TODO: allocate internal IRQ controller */
3655 }
3656
3657 /* PowerPC 440x5                                                             */
3658 #define POWERPC_INSNS_440x5  (PPC_INSNS_BASE | PPC_STRING |                   \
3659                               PPC_DCR | PPC_WRTEE | PPC_RFMCI |               \
3660                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3661                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3662                               PPC_MEM_TLBSYNC | PPC_MFTB |                    \
3663                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3664                               PPC_440_SPEC)
3665 #define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
3666 #define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
3667 #define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
3668 #define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
3669 #define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
3670 #define POWERPC_FLAG_440x5   (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |           \
3671                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3672 #define check_pow_440x5      check_pow_nocheck
3673
3674 static void init_proc_440x5 (CPUPPCState *env)
3675 {
3676     /* Time base */
3677     gen_tbl(env);
3678     gen_spr_BookE(env, 0x000000000000FFFFULL);
3679     gen_spr_440(env);
3680     gen_spr_usprgh(env);
3681     /* Processor identification */
3682     spr_register(env, SPR_BOOKE_PIR, "PIR",
3683                  SPR_NOACCESS, SPR_NOACCESS,
3684                  &spr_read_generic, &spr_write_pir,
3685                  0x00000000);
3686     /* XXX : not implemented */
3687     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3688                  SPR_NOACCESS, SPR_NOACCESS,
3689                  &spr_read_generic, &spr_write_generic,
3690                  0x00000000);
3691     /* XXX : not implemented */
3692     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3693                  SPR_NOACCESS, SPR_NOACCESS,
3694                  &spr_read_generic, &spr_write_generic,
3695                  0x00000000);
3696     /* XXX : not implemented */
3697     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3698                  SPR_NOACCESS, SPR_NOACCESS,
3699                  &spr_read_generic, &spr_write_generic,
3700                  0x00000000);
3701     /* XXX : not implemented */
3702     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3703                  SPR_NOACCESS, SPR_NOACCESS,
3704                  &spr_read_generic, &spr_write_generic,
3705                  0x00000000);
3706     /* XXX : not implemented */
3707     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3708                  SPR_NOACCESS, SPR_NOACCESS,
3709                  &spr_read_generic, &spr_write_generic,
3710                  0x00000000);
3711     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3712                  SPR_NOACCESS, SPR_NOACCESS,
3713                  &spr_read_generic, &spr_write_generic,
3714                  0x00000000);
3715     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3716                  SPR_NOACCESS, SPR_NOACCESS,
3717                  &spr_read_generic, &spr_write_generic,
3718                  0x00000000);
3719     /* XXX : not implemented */
3720     spr_register(env, SPR_440_CCR1, "CCR1",
3721                  SPR_NOACCESS, SPR_NOACCESS,
3722                  &spr_read_generic, &spr_write_generic,
3723                  0x00000000);
3724     /* Memory management */
3725 #if !defined(CONFIG_USER_ONLY)
3726     env->nb_tlb = 64;
3727     env->nb_ways = 1;
3728     env->id_tlbs = 0;
3729 #endif
3730     init_excp_BookE(env);
3731     env->dcache_line_size = 32;
3732     env->icache_line_size = 32;
3733     ppc40x_irq_init(env);
3734 }
3735
3736 /* PowerPC 460 (guessed)                                                     */
3737 #define POWERPC_INSNS_460    (PPC_INSNS_BASE | PPC_STRING |                   \
3738                               PPC_DCR | PPC_DCRX  | PPC_DCRUX |               \
3739                               PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |            \
3740                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3741                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3742                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3743                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3744                               PPC_440_SPEC)
3745 #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3746 #define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
3747 #define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
3748 #define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
3749 #define POWERPC_BFDM_460     (bfd_mach_ppc_403)
3750 #define POWERPC_FLAG_460     (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3751                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3752 #define check_pow_460        check_pow_nocheck
3753
3754 __attribute__ (( unused ))
3755 static void init_proc_460 (CPUPPCState *env)
3756 {
3757     /* Time base */
3758     gen_tbl(env);
3759     gen_spr_BookE(env, 0x000000000000FFFFULL);
3760     gen_spr_440(env);
3761     gen_spr_usprgh(env);
3762     /* Processor identification */
3763     spr_register(env, SPR_BOOKE_PIR, "PIR",
3764                  SPR_NOACCESS, SPR_NOACCESS,
3765                  &spr_read_generic, &spr_write_pir,
3766                  0x00000000);
3767     /* XXX : not implemented */
3768     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3769                  SPR_NOACCESS, SPR_NOACCESS,
3770                  &spr_read_generic, &spr_write_generic,
3771                  0x00000000);
3772     /* XXX : not implemented */
3773     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3774                  SPR_NOACCESS, SPR_NOACCESS,
3775                  &spr_read_generic, &spr_write_generic,
3776                  0x00000000);
3777     /* XXX : not implemented */
3778     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3779                  SPR_NOACCESS, SPR_NOACCESS,
3780                  &spr_read_generic, &spr_write_generic,
3781                  0x00000000);
3782     /* XXX : not implemented */
3783     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3784                  SPR_NOACCESS, SPR_NOACCESS,
3785                  &spr_read_generic, &spr_write_generic,
3786                  0x00000000);
3787     /* XXX : not implemented */
3788     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3789                  SPR_NOACCESS, SPR_NOACCESS,
3790                  &spr_read_generic, &spr_write_generic,
3791                  0x00000000);
3792     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3793                  SPR_NOACCESS, SPR_NOACCESS,
3794                  &spr_read_generic, &spr_write_generic,
3795                  0x00000000);
3796     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3797                  SPR_NOACCESS, SPR_NOACCESS,
3798                  &spr_read_generic, &spr_write_generic,
3799                  0x00000000);
3800     /* XXX : not implemented */
3801     spr_register(env, SPR_440_CCR1, "CCR1",
3802                  SPR_NOACCESS, SPR_NOACCESS,
3803                  &spr_read_generic, &spr_write_generic,
3804                  0x00000000);
3805     /* XXX : not implemented */
3806     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3807                  &spr_read_generic, &spr_write_generic,
3808                  &spr_read_generic, &spr_write_generic,
3809                  0x00000000);
3810     /* Memory management */
3811 #if !defined(CONFIG_USER_ONLY)
3812     env->nb_tlb = 64;
3813     env->nb_ways = 1;
3814     env->id_tlbs = 0;
3815 #endif
3816     init_excp_BookE(env);
3817     env->dcache_line_size = 32;
3818     env->icache_line_size = 32;
3819     /* XXX: TODO: allocate internal IRQ controller */
3820 }
3821
3822 /* PowerPC 460F (guessed)                                                    */
3823 #define POWERPC_INSNS_460F   (PPC_INSNS_BASE | PPC_STRING |                   \
3824                               PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |   \
3825                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
3826                               PPC_FLOAT_STFIWX | PPC_MFTB |                   \
3827                               PPC_DCR | PPC_DCRX | PPC_DCRUX |                \
3828                               PPC_WRTEE | PPC_MFAPIDI |                       \
3829                               PPC_CACHE | PPC_CACHE_ICBI |                    \
3830                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
3831                               PPC_MEM_TLBSYNC | PPC_TLBIVA |                  \
3832                               PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
3833                               PPC_440_SPEC)
3834 #define POWERPC_MSRM_460     (0x000000000006FF30ULL)
3835 #define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
3836 #define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
3837 #define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
3838 #define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
3839 #define POWERPC_FLAG_460F    (POWERPC_FLAG_CE | POWERPC_FLAG_DWE |            \
3840                               POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3841 #define check_pow_460F       check_pow_nocheck
3842
3843 __attribute__ (( unused ))
3844 static void init_proc_460F (CPUPPCState *env)
3845 {
3846     /* Time base */
3847     gen_tbl(env);
3848     gen_spr_BookE(env, 0x000000000000FFFFULL);
3849     gen_spr_440(env);
3850     gen_spr_usprgh(env);
3851     /* Processor identification */
3852     spr_register(env, SPR_BOOKE_PIR, "PIR",
3853                  SPR_NOACCESS, SPR_NOACCESS,
3854                  &spr_read_generic, &spr_write_pir,
3855                  0x00000000);
3856     /* XXX : not implemented */
3857     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3858                  SPR_NOACCESS, SPR_NOACCESS,
3859                  &spr_read_generic, &spr_write_generic,
3860                  0x00000000);
3861     /* XXX : not implemented */
3862     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3863                  SPR_NOACCESS, SPR_NOACCESS,
3864                  &spr_read_generic, &spr_write_generic,
3865                  0x00000000);
3866     /* XXX : not implemented */
3867     spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3868                  SPR_NOACCESS, SPR_NOACCESS,
3869                  &spr_read_generic, &spr_write_generic,
3870                  0x00000000);
3871     /* XXX : not implemented */
3872     spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3873                  SPR_NOACCESS, SPR_NOACCESS,
3874                  &spr_read_generic, &spr_write_generic,
3875                  0x00000000);
3876     /* XXX : not implemented */
3877     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3878                  SPR_NOACCESS, SPR_NOACCESS,
3879                  &spr_read_generic, &spr_write_generic,
3880                  0x00000000);
3881     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3882                  SPR_NOACCESS, SPR_NOACCESS,
3883                  &spr_read_generic, &spr_write_generic,
3884                  0x00000000);
3885     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3886                  SPR_NOACCESS, SPR_NOACCESS,
3887                  &spr_read_generic, &spr_write_generic,
3888                  0x00000000);
3889     /* XXX : not implemented */
3890     spr_register(env, SPR_440_CCR1, "CCR1",
3891                  SPR_NOACCESS, SPR_NOACCESS,
3892                  &spr_read_generic, &spr_write_generic,
3893                  0x00000000);
3894     /* XXX : not implemented */
3895     spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3896                  &spr_read_generic, &spr_write_generic,
3897                  &spr_read_generic, &spr_write_generic,
3898                  0x00000000);
3899     /* Memory management */
3900 #if !defined(CONFIG_USER_ONLY)
3901     env->nb_tlb = 64;
3902     env->nb_ways = 1;
3903     env->id_tlbs = 0;
3904 #endif
3905     init_excp_BookE(env);
3906     env->dcache_line_size = 32;
3907     env->icache_line_size = 32;
3908     /* XXX: TODO: allocate internal IRQ controller */
3909 }
3910
3911 /* Freescale 5xx cores (aka RCPU) */
3912 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING |                   \
3913                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3914                               PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3915                               PPC_MFTB)
3916 #define POWERPC_MSRM_MPC5xx  (0x000000000001FF43ULL)
3917 #define POWERPC_MMU_MPC5xx   (POWERPC_MMU_REAL)
3918 #define POWERPC_EXCP_MPC5xx  (POWERPC_EXCP_603)
3919 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3920 #define POWERPC_BFDM_MPC5xx  (bfd_mach_ppc_505)
3921 #define POWERPC_FLAG_MPC5xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3922                               POWERPC_FLAG_BUS_CLK)
3923 #define check_pow_MPC5xx     check_pow_none
3924
3925 __attribute__ (( unused ))
3926 static void init_proc_MPC5xx (CPUPPCState *env)
3927 {
3928     /* Time base */
3929     gen_tbl(env);
3930     gen_spr_5xx_8xx(env);
3931     gen_spr_5xx(env);
3932     init_excp_MPC5xx(env);
3933     env->dcache_line_size = 32;
3934     env->icache_line_size = 32;
3935     /* XXX: TODO: allocate internal IRQ controller */
3936 }
3937
3938 /* Freescale 8xx cores (aka PowerQUICC) */
3939 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING  |                  \
3940                               PPC_MEM_EIEIO | PPC_MEM_SYNC |                  \
3941                               PPC_CACHE_ICBI | PPC_MFTB)
3942 #define POWERPC_MSRM_MPC8xx  (0x000000000001F673ULL)
3943 #define POWERPC_MMU_MPC8xx   (POWERPC_MMU_MPC8xx)
3944 #define POWERPC_EXCP_MPC8xx  (POWERPC_EXCP_603)
3945 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3946 #define POWERPC_BFDM_MPC8xx  (bfd_mach_ppc_860)
3947 #define POWERPC_FLAG_MPC8xx  (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
3948                               POWERPC_FLAG_BUS_CLK)
3949 #define check_pow_MPC8xx     check_pow_none
3950
3951 __attribute__ (( unused ))
3952 static void init_proc_MPC8xx (CPUPPCState *env)
3953 {
3954     /* Time base */
3955     gen_tbl(env);
3956     gen_spr_5xx_8xx(env);
3957     gen_spr_8xx(env);
3958     init_excp_MPC8xx(env);
3959     env->dcache_line_size = 32;
3960     env->icache_line_size = 32;
3961     /* XXX: TODO: allocate internal IRQ controller */
3962 }
3963
3964 /* Freescale 82xx cores (aka PowerQUICC-II)                                  */
3965 /* PowerPC G2                                                                */
3966 #define POWERPC_INSNS_G2     (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
3967                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
3968                               PPC_FLOAT_STFIWX |                              \
3969                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
3970                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
3971                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3972                               PPC_SEGMENT | PPC_EXTERN)
3973 #define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3974 #define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3975 //#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3976 #define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3977 #define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3978 #define POWERPC_FLAG_G2      (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
3979                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3980 #define check_pow_G2         check_pow_hid0
3981
3982 static void init_proc_G2 (CPUPPCState *env)
3983 {
3984     gen_spr_ne_601(env);
3985     gen_spr_G2_755(env);
3986     gen_spr_G2(env);
3987     /* Time base */
3988     gen_tbl(env);
3989     /* External access control */
3990     /* XXX : not implemented */
3991     spr_register(env, SPR_EAR, "EAR",
3992                  SPR_NOACCESS, SPR_NOACCESS,
3993                  &spr_read_generic, &spr_write_generic,
3994                  0x00000000);
3995     /* Hardware implementation register */
3996     /* XXX : not implemented */
3997     spr_register(env, SPR_HID0, "HID0",
3998                  SPR_NOACCESS, SPR_NOACCESS,
3999                  &spr_read_generic, &spr_write_generic,
4000                  0x00000000);
4001     /* XXX : not implemented */
4002     spr_register(env, SPR_HID1, "HID1",
4003                  SPR_NOACCESS, SPR_NOACCESS,
4004                  &spr_read_generic, &spr_write_generic,
4005                  0x00000000);
4006     /* XXX : not implemented */
4007     spr_register(env, SPR_HID2, "HID2",
4008                  SPR_NOACCESS, SPR_NOACCESS,
4009                  &spr_read_generic, &spr_write_generic,
4010                  0x00000000);
4011     /* Memory management */
4012     gen_low_BATs(env);
4013     gen_high_BATs(env);
4014     gen_6xx_7xx_soft_tlb(env, 64, 2);
4015     init_excp_G2(env);
4016     env->dcache_line_size = 32;
4017     env->icache_line_size = 32;
4018     /* Allocate hardware IRQ controller */
4019     ppc6xx_irq_init(env);
4020 }
4021
4022 /* PowerPC G2LE                                                              */
4023 #define POWERPC_INSNS_G2LE   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4024                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4025                               PPC_FLOAT_STFIWX |                              \
4026                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4027                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4028                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4029                               PPC_SEGMENT | PPC_EXTERN)
4030 #define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
4031 #define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
4032 #define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
4033 #define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
4034 #define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
4035 #define POWERPC_FLAG_G2LE    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4036                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4037 #define check_pow_G2LE       check_pow_hid0
4038
4039 static void init_proc_G2LE (CPUPPCState *env)
4040 {
4041     gen_spr_ne_601(env);
4042     gen_spr_G2_755(env);
4043     gen_spr_G2(env);
4044     /* Time base */
4045     gen_tbl(env);
4046     /* External access control */
4047     /* XXX : not implemented */
4048     spr_register(env, SPR_EAR, "EAR",
4049                  SPR_NOACCESS, SPR_NOACCESS,
4050                  &spr_read_generic, &spr_write_generic,
4051                  0x00000000);
4052     /* Hardware implementation register */
4053     /* XXX : not implemented */
4054     spr_register(env, SPR_HID0, "HID0",
4055                  SPR_NOACCESS, SPR_NOACCESS,
4056                  &spr_read_generic, &spr_write_generic,
4057                  0x00000000);
4058     /* XXX : not implemented */
4059     spr_register(env, SPR_HID1, "HID1",
4060                  SPR_NOACCESS, SPR_NOACCESS,
4061                  &spr_read_generic, &spr_write_generic,
4062                  0x00000000);
4063     /* XXX : not implemented */
4064     spr_register(env, SPR_HID2, "HID2",
4065                  SPR_NOACCESS, SPR_NOACCESS,
4066                  &spr_read_generic, &spr_write_generic,
4067                  0x00000000);
4068     /* Memory management */
4069     gen_low_BATs(env);
4070     gen_high_BATs(env);
4071     gen_6xx_7xx_soft_tlb(env, 64, 2);
4072     init_excp_G2(env);
4073     env->dcache_line_size = 32;
4074     env->icache_line_size = 32;
4075     /* Allocate hardware IRQ controller */
4076     ppc6xx_irq_init(env);
4077 }
4078
4079 /* e200 core                                                                 */
4080 /* XXX: unimplemented instructions:
4081  * dcblc
4082  * dcbtlst
4083  * dcbtstls
4084  * icblc
4085  * icbtls
4086  * tlbivax
4087  * all SPE multiply-accumulate instructions
4088  */
4089 #define POWERPC_INSNS_e200   (PPC_INSNS_BASE | PPC_ISEL |                     \
4090                               PPC_SPE | PPC_SPE_SINGLE |                      \
4091                               PPC_WRTEE | PPC_RFDI |                          \
4092                               PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |   \
4093                               PPC_CACHE_DCBZ | PPC_CACHE_DCBA |               \
4094                               PPC_MEM_TLBSYNC | PPC_TLBIVAX |                 \
4095                               PPC_BOOKE)
4096 #define POWERPC_MSRM_e200    (0x000000000606FF30ULL)
4097 #define POWERPC_MMU_e200     (POWERPC_MMU_BOOKE_FSL)
4098 #define POWERPC_EXCP_e200    (POWERPC_EXCP_BOOKE)
4099 #define POWERPC_INPUT_e200   (PPC_FLAGS_INPUT_BookE)
4100 #define POWERPC_BFDM_e200    (bfd_mach_ppc_860)
4101 #define POWERPC_FLAG_e200    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |            \
4102                               POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |           \
4103                               POWERPC_FLAG_BUS_CLK)
4104 #define check_pow_e200       check_pow_hid0
4105
4106 __attribute__ (( unused ))
4107 static void init_proc_e200 (CPUPPCState *env)
4108 {
4109     /* Time base */
4110     gen_tbl(env);
4111     gen_spr_BookE(env, 0x000000070000FFFFULL);
4112     /* XXX : not implemented */
4113     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4114                  &spr_read_spefscr, &spr_write_spefscr,
4115                  &spr_read_spefscr, &spr_write_spefscr,
4116                  0x00000000);
4117     /* Memory management */
4118     gen_spr_BookE_FSL(env, 0x0000005D);
4119     /* XXX : not implemented */
4120     spr_register(env, SPR_HID0, "HID0",
4121                  SPR_NOACCESS, SPR_NOACCESS,
4122                  &spr_read_generic, &spr_write_generic,
4123                  0x00000000);
4124     /* XXX : not implemented */
4125     spr_register(env, SPR_HID1, "HID1",
4126                  SPR_NOACCESS, SPR_NOACCESS,
4127                  &spr_read_generic, &spr_write_generic,
4128                  0x00000000);
4129     /* XXX : not implemented */
4130     spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4131                  SPR_NOACCESS, SPR_NOACCESS,
4132                  &spr_read_generic, &spr_write_generic,
4133                  0x00000000);
4134     /* XXX : not implemented */
4135     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4136                  SPR_NOACCESS, SPR_NOACCESS,
4137                  &spr_read_generic, &spr_write_generic,
4138                  0x00000000);
4139     /* XXX : not implemented */
4140     spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4141                  SPR_NOACCESS, SPR_NOACCESS,
4142                  &spr_read_generic, &spr_write_generic,
4143                  0x00000000);
4144     /* XXX : not implemented */
4145     spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4146                  SPR_NOACCESS, SPR_NOACCESS,
4147                  &spr_read_generic, &spr_write_generic,
4148                  0x00000000);
4149     /* XXX : not implemented */
4150     spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4151                  SPR_NOACCESS, SPR_NOACCESS,
4152                  &spr_read_generic, &spr_write_generic,
4153                  0x00000000);
4154     /* XXX : not implemented */
4155     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4156                  SPR_NOACCESS, SPR_NOACCESS,
4157                  &spr_read_generic, &spr_write_generic,
4158                  0x00000000);
4159     /* XXX : not implemented */
4160     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4161                  SPR_NOACCESS, SPR_NOACCESS,
4162                  &spr_read_generic, &spr_write_generic,
4163                  0x00000000);
4164     /* XXX : not implemented */
4165     spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4166                  SPR_NOACCESS, SPR_NOACCESS,
4167                  &spr_read_generic, &spr_write_generic,
4168                  0x00000000);
4169     /* XXX : not implemented */
4170     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4171                  SPR_NOACCESS, SPR_NOACCESS,
4172                  &spr_read_generic, &spr_write_generic,
4173                  0x00000000);
4174     /* XXX : not implemented */
4175     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4176                  SPR_NOACCESS, SPR_NOACCESS,
4177                  &spr_read_generic, &spr_write_generic,
4178                  0x00000000);
4179     /* XXX : not implemented */
4180     spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4181                  SPR_NOACCESS, SPR_NOACCESS,
4182                  &spr_read_generic, &spr_write_generic,
4183                  0x00000000);
4184     /* XXX : not implemented */
4185     spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4186                  SPR_NOACCESS, SPR_NOACCESS,
4187                  &spr_read_generic, &spr_write_generic,
4188                  0x00000000);
4189     spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4190                  SPR_NOACCESS, SPR_NOACCESS,
4191                  &spr_read_generic, &spr_write_generic,
4192                  0x00000000);
4193     spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4194                  SPR_NOACCESS, SPR_NOACCESS,
4195                  &spr_read_generic, &spr_write_generic,
4196                  0x00000000);
4197 #if !defined(CONFIG_USER_ONLY)
4198     env->nb_tlb = 64;
4199     env->nb_ways = 1;
4200     env->id_tlbs = 0;
4201 #endif
4202     init_excp_e200(env);
4203     env->dcache_line_size = 32;
4204     env->icache_line_size = 32;
4205     /* XXX: TODO: allocate internal IRQ controller */
4206 }
4207
4208 /* e300 core                                                                 */
4209 #define POWERPC_INSNS_e300   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4210                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4211                               PPC_FLOAT_STFIWX |                              \
4212                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4213                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4214                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4215                               PPC_SEGMENT | PPC_EXTERN)
4216 #define POWERPC_MSRM_e300    (0x000000000007FFF3ULL)
4217 #define POWERPC_MMU_e300     (POWERPC_MMU_SOFT_6xx)
4218 #define POWERPC_EXCP_e300    (POWERPC_EXCP_603)
4219 #define POWERPC_INPUT_e300   (PPC_FLAGS_INPUT_6xx)
4220 #define POWERPC_BFDM_e300    (bfd_mach_ppc_603)
4221 #define POWERPC_FLAG_e300    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4222                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4223 #define check_pow_e300       check_pow_hid0
4224
4225 __attribute__ (( unused ))
4226 static void init_proc_e300 (CPUPPCState *env)
4227 {
4228     gen_spr_ne_601(env);
4229     gen_spr_603(env);
4230     /* Time base */
4231     gen_tbl(env);
4232     /* hardware implementation registers */
4233     /* XXX : not implemented */
4234     spr_register(env, SPR_HID0, "HID0",
4235                  SPR_NOACCESS, SPR_NOACCESS,
4236                  &spr_read_generic, &spr_write_generic,
4237                  0x00000000);
4238     /* XXX : not implemented */
4239     spr_register(env, SPR_HID1, "HID1",
4240                  SPR_NOACCESS, SPR_NOACCESS,
4241                  &spr_read_generic, &spr_write_generic,
4242                  0x00000000);
4243     /* XXX : not implemented */
4244     spr_register(env, SPR_HID2, "HID2",
4245                  SPR_NOACCESS, SPR_NOACCESS,
4246                  &spr_read_generic, &spr_write_generic,
4247                  0x00000000);
4248     /* Memory management */
4249     gen_low_BATs(env);
4250     gen_high_BATs(env);
4251     gen_6xx_7xx_soft_tlb(env, 64, 2);
4252     init_excp_603(env);
4253     env->dcache_line_size = 32;
4254     env->icache_line_size = 32;
4255     /* Allocate hardware IRQ controller */
4256     ppc6xx_irq_init(env);
4257 }
4258
4259 /* e500v1 core                                                               */
4260 #define POWERPC_INSNS_e500v1   (PPC_INSNS_BASE | PPC_ISEL |             \
4261                                 PPC_SPE | PPC_SPE_SINGLE |              \
4262                                 PPC_WRTEE | PPC_RFDI |                  \
4263                                 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4264                                 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
4265                                 PPC_MEM_TLBSYNC | PPC_TLBIVAX |         \
4266                                 PPC_BOOKE)
4267 #define POWERPC_MSRM_e500v1    (0x000000000606FF30ULL)
4268 #define POWERPC_MMU_e500v1     (POWERPC_MMU_BOOKE_FSL)
4269 #define POWERPC_EXCP_e500v1    (POWERPC_EXCP_BOOKE)
4270 #define POWERPC_INPUT_e500v1   (PPC_FLAGS_INPUT_BookE)
4271 #define POWERPC_BFDM_e500v1    (bfd_mach_ppc_860)
4272 #define POWERPC_FLAG_e500v1    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |    \
4273                                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |   \
4274                                 POWERPC_FLAG_BUS_CLK)
4275 #define check_pow_e500v1       check_pow_hid0
4276 #define init_proc_e500v1       init_proc_e500
4277
4278 /* e500v2 core                                                               */
4279 #define POWERPC_INSNS_e500v2   (PPC_INSNS_BASE | PPC_ISEL |             \
4280                                 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |   \
4281                                 PPC_WRTEE | PPC_RFDI |                  \
4282                                 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4283                                 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |       \
4284                                 PPC_MEM_TLBSYNC | PPC_TLBIVAX |         \
4285                                 PPC_BOOKE)
4286 #define POWERPC_MSRM_e500v2    (0x000000000606FF30ULL)
4287 #define POWERPC_MMU_e500v2     (POWERPC_MMU_BOOKE_FSL)
4288 #define POWERPC_EXCP_e500v2    (POWERPC_EXCP_BOOKE)
4289 #define POWERPC_INPUT_e500v2   (PPC_FLAGS_INPUT_BookE)
4290 #define POWERPC_BFDM_e500v2    (bfd_mach_ppc_860)
4291 #define POWERPC_FLAG_e500v2    (POWERPC_FLAG_SPE | POWERPC_FLAG_CE |    \
4292                                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |   \
4293                                 POWERPC_FLAG_BUS_CLK)
4294 #define check_pow_e500v2       check_pow_hid0
4295 #define init_proc_e500v2       init_proc_e500
4296
4297 static void init_proc_e500 (CPUPPCState *env)
4298 {
4299     /* Time base */
4300     gen_tbl(env);
4301     gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4302     /* Processor identification */
4303     spr_register(env, SPR_BOOKE_PIR, "PIR",
4304                  SPR_NOACCESS, SPR_NOACCESS,
4305                  &spr_read_generic, &spr_write_pir,
4306                  0x00000000);
4307     /* XXX : not implemented */
4308     spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4309                  &spr_read_spefscr, &spr_write_spefscr,
4310                  &spr_read_spefscr, &spr_write_spefscr,
4311                  0x00000000);
4312     /* Memory management */
4313 #if !defined(CONFIG_USER_ONLY)
4314     env->nb_pids = 3;
4315 #endif
4316     gen_spr_BookE_FSL(env, 0x0000005F);
4317     /* XXX : not implemented */
4318     spr_register(env, SPR_HID0, "HID0",
4319                  SPR_NOACCESS, SPR_NOACCESS,
4320                  &spr_read_generic, &spr_write_generic,
4321                  0x00000000);
4322     /* XXX : not implemented */
4323     spr_register(env, SPR_HID1, "HID1",
4324                  SPR_NOACCESS, SPR_NOACCESS,
4325                  &spr_read_generic, &spr_write_generic,
4326                  0x00000000);
4327     /* XXX : not implemented */
4328     spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4329                  SPR_NOACCESS, SPR_NOACCESS,
4330                  &spr_read_generic, &spr_write_generic,
4331                  0x00000000);
4332     /* XXX : not implemented */
4333     spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4334                  SPR_NOACCESS, SPR_NOACCESS,
4335                  &spr_read_generic, &spr_write_generic,
4336                  0x00000000);
4337     /* XXX : not implemented */
4338     spr_register(env, SPR_Exxx_MCAR, "MCAR",
4339                  SPR_NOACCESS, SPR_NOACCESS,
4340                  &spr_read_generic, &spr_write_generic,
4341                  0x00000000);
4342     /* XXX : not implemented */
4343     spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4344                  SPR_NOACCESS, SPR_NOACCESS,
4345                  &spr_read_generic, &spr_write_generic,
4346                  0x00000000);
4347     /* XXX : not implemented */
4348     spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4349                  SPR_NOACCESS, SPR_NOACCESS,
4350                  &spr_read_generic, &spr_write_generic,
4351                  0x00000000);
4352     /* XXX : not implemented */
4353     spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4354                  SPR_NOACCESS, SPR_NOACCESS,
4355                  &spr_read_generic, &spr_write_generic,
4356                  0x00000000);
4357     /* XXX : not implemented */
4358     spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4359                  SPR_NOACCESS, SPR_NOACCESS,
4360                  &spr_read_generic, &spr_write_generic,
4361                  0x00000000);
4362     /* XXX : not implemented */
4363     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4364                  SPR_NOACCESS, SPR_NOACCESS,
4365                  &spr_read_generic, &spr_write_generic,
4366                  0x00000000);
4367     /* XXX : not implemented */
4368     spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4369                  SPR_NOACCESS, SPR_NOACCESS,
4370                  &spr_read_generic, &spr_write_generic,
4371                  0x00000000);
4372     /* XXX : not implemented */
4373     spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4374                  SPR_NOACCESS, SPR_NOACCESS,
4375                  &spr_read_generic, &spr_write_generic,
4376                  0x00000000);
4377     /* XXX : not implemented */
4378     spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4379                  SPR_NOACCESS, SPR_NOACCESS,
4380                  &spr_read_generic, &spr_write_generic,
4381                  0x00000000);
4382     spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4383                  SPR_NOACCESS, SPR_NOACCESS,
4384                  &spr_read_generic, &spr_write_generic,
4385                  0x00000000);
4386     spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4387                  SPR_NOACCESS, SPR_NOACCESS,
4388                  &spr_read_generic, &spr_write_generic,
4389                  0x00000000);
4390 #if !defined(CONFIG_USER_ONLY)
4391     env->nb_tlb = 64;
4392     env->nb_ways = 1;
4393     env->id_tlbs = 0;
4394 #endif
4395     init_excp_e200(env);
4396     env->dcache_line_size = 32;
4397     env->icache_line_size = 32;
4398     /* Allocate hardware IRQ controller */
4399     ppce500_irq_init(env);
4400 }
4401
4402 /* Non-embedded PowerPC                                                      */
4403
4404 /* POWER : same as 601, without mfmsr, mfsr                                  */
4405 #if defined(TODO)
4406 #define POWERPC_INSNS_POWER  (XXX_TODO)
4407 /* POWER RSC (from RAD6000) */
4408 #define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
4409 #endif /* TODO */
4410
4411 /* PowerPC 601                                                               */
4412 #define POWERPC_INSNS_601    (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4413                               PPC_FLOAT |                                     \
4414                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4415                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4416                               PPC_SEGMENT | PPC_EXTERN)
4417 #define POWERPC_MSRM_601     (0x000000000000FD70ULL)
4418 #define POWERPC_MSRR_601     (0x0000000000001040ULL)
4419 //#define POWERPC_MMU_601      (POWERPC_MMU_601)
4420 //#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
4421 #define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
4422 #define POWERPC_BFDM_601     (bfd_mach_ppc_601)
4423 #define POWERPC_FLAG_601     (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4424 #define check_pow_601        check_pow_none
4425
4426 static void init_proc_601 (CPUPPCState *env)
4427 {
4428     gen_spr_ne_601(env);
4429     gen_spr_601(env);
4430     /* Hardware implementation registers */
4431     /* XXX : not implemented */
4432     spr_register(env, SPR_HID0, "HID0",
4433                  SPR_NOACCESS, SPR_NOACCESS,
4434                  &spr_read_generic, &spr_write_hid0_601,
4435                  0x80010080);
4436     /* XXX : not implemented */
4437     spr_register(env, SPR_HID1, "HID1",
4438                  SPR_NOACCESS, SPR_NOACCESS,
4439                  &spr_read_generic, &spr_write_generic,
4440                  0x00000000);
4441     /* XXX : not implemented */
4442     spr_register(env, SPR_601_HID2, "HID2",
4443                  SPR_NOACCESS, SPR_NOACCESS,
4444                  &spr_read_generic, &spr_write_generic,
4445                  0x00000000);
4446     /* XXX : not implemented */
4447     spr_register(env, SPR_601_HID5, "HID5",
4448                  SPR_NOACCESS, SPR_NOACCESS,
4449                  &spr_read_generic, &spr_write_generic,
4450                  0x00000000);
4451     /* Memory management */
4452     init_excp_601(env);
4453     /* XXX: beware that dcache line size is 64
4454      *      but dcbz uses 32 bytes "sectors"
4455      * XXX: this breaks clcs instruction !
4456      */
4457     env->dcache_line_size = 32;
4458     env->icache_line_size = 64;
4459     /* Allocate hardware IRQ controller */
4460     ppc6xx_irq_init(env);
4461 }
4462
4463 /* PowerPC 601v                                                              */
4464 #define POWERPC_INSNS_601v   (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |    \
4465                               PPC_FLOAT |                                     \
4466                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4467                               PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |  \
4468                               PPC_SEGMENT | PPC_EXTERN)
4469 #define POWERPC_MSRM_601v    (0x000000000000FD70ULL)
4470 #define POWERPC_MSRR_601v    (0x0000000000001040ULL)
4471 #define POWERPC_MMU_601v     (POWERPC_MMU_601)
4472 #define POWERPC_EXCP_601v    (POWERPC_EXCP_601)
4473 #define POWERPC_INPUT_601v   (PPC_FLAGS_INPUT_6xx)
4474 #define POWERPC_BFDM_601v    (bfd_mach_ppc_601)
4475 #define POWERPC_FLAG_601v    (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4476 #define check_pow_601v       check_pow_none
4477
4478 static void init_proc_601v (CPUPPCState *env)
4479 {
4480     init_proc_601(env);
4481     /* XXX : not implemented */
4482     spr_register(env, SPR_601_HID15, "HID15",
4483                  SPR_NOACCESS, SPR_NOACCESS,
4484                  &spr_read_generic, &spr_write_generic,
4485                  0x00000000);
4486 }
4487
4488 /* PowerPC 602                                                               */
4489 #define POWERPC_INSNS_602    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4490                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4491                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4492                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4493                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4494                               PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4495                               PPC_SEGMENT | PPC_602_SPEC)
4496 #define POWERPC_MSRM_602     (0x0000000000C7FF73ULL)
4497 /* XXX: 602 MMU is quite specific. Should add a special case */
4498 #define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
4499 //#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
4500 #define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
4501 #define POWERPC_BFDM_602     (bfd_mach_ppc_602)
4502 #define POWERPC_FLAG_602     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4503                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4504 #define check_pow_602        check_pow_hid0
4505
4506 static void init_proc_602 (CPUPPCState *env)
4507 {
4508     gen_spr_ne_601(env);
4509     gen_spr_602(env);
4510     /* Time base */
4511     gen_tbl(env);
4512     /* hardware implementation registers */
4513     /* XXX : not implemented */
4514     spr_register(env, SPR_HID0, "HID0",
4515                  SPR_NOACCESS, SPR_NOACCESS,
4516                  &spr_read_generic, &spr_write_generic,
4517                  0x00000000);
4518     /* XXX : not implemented */
4519     spr_register(env, SPR_HID1, "HID1",
4520                  SPR_NOACCESS, SPR_NOACCESS,
4521                  &spr_read_generic, &spr_write_generic,
4522                  0x00000000);
4523     /* Memory management */
4524     gen_low_BATs(env);
4525     gen_6xx_7xx_soft_tlb(env, 64, 2);
4526     init_excp_602(env);
4527     env->dcache_line_size = 32;
4528     env->icache_line_size = 32;
4529     /* Allocate hardware IRQ controller */
4530     ppc6xx_irq_init(env);
4531 }
4532
4533 /* PowerPC 603                                                               */
4534 #define POWERPC_INSNS_603    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4535                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4536                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4537                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4538                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4539                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4540                               PPC_SEGMENT | PPC_EXTERN)
4541 #define POWERPC_MSRM_603     (0x000000000007FF73ULL)
4542 #define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
4543 //#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
4544 #define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
4545 #define POWERPC_BFDM_603     (bfd_mach_ppc_603)
4546 #define POWERPC_FLAG_603     (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4547                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4548 #define check_pow_603        check_pow_hid0
4549
4550 static void init_proc_603 (CPUPPCState *env)
4551 {
4552     gen_spr_ne_601(env);
4553     gen_spr_603(env);
4554     /* Time base */
4555     gen_tbl(env);
4556     /* hardware implementation registers */
4557     /* XXX : not implemented */
4558     spr_register(env, SPR_HID0, "HID0",
4559                  SPR_NOACCESS, SPR_NOACCESS,
4560                  &spr_read_generic, &spr_write_generic,
4561                  0x00000000);
4562     /* XXX : not implemented */
4563     spr_register(env, SPR_HID1, "HID1",
4564                  SPR_NOACCESS, SPR_NOACCESS,
4565                  &spr_read_generic, &spr_write_generic,
4566                  0x00000000);
4567     /* Memory management */
4568     gen_low_BATs(env);
4569     gen_6xx_7xx_soft_tlb(env, 64, 2);
4570     init_excp_603(env);
4571     env->dcache_line_size = 32;
4572     env->icache_line_size = 32;
4573     /* Allocate hardware IRQ controller */
4574     ppc6xx_irq_init(env);
4575 }
4576
4577 /* PowerPC 603e                                                              */
4578 #define POWERPC_INSNS_603E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4579                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4580                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4581                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4582                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4583                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4584                               PPC_SEGMENT | PPC_EXTERN)
4585 #define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
4586 #define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
4587 //#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
4588 #define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
4589 #define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
4590 #define POWERPC_FLAG_603E    (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |           \
4591                               POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4592 #define check_pow_603E       check_pow_hid0
4593
4594 static void init_proc_603E (CPUPPCState *env)
4595 {
4596     gen_spr_ne_601(env);
4597     gen_spr_603(env);
4598     /* Time base */
4599     gen_tbl(env);
4600     /* hardware implementation registers */
4601     /* XXX : not implemented */
4602     spr_register(env, SPR_HID0, "HID0",
4603                  SPR_NOACCESS, SPR_NOACCESS,
4604                  &spr_read_generic, &spr_write_generic,
4605                  0x00000000);
4606     /* XXX : not implemented */
4607     spr_register(env, SPR_HID1, "HID1",
4608                  SPR_NOACCESS, SPR_NOACCESS,
4609                  &spr_read_generic, &spr_write_generic,
4610                  0x00000000);
4611     /* XXX : not implemented */
4612     spr_register(env, SPR_IABR, "IABR",
4613                  SPR_NOACCESS, SPR_NOACCESS,
4614                  &spr_read_generic, &spr_write_generic,
4615                  0x00000000);
4616     /* Memory management */
4617     gen_low_BATs(env);
4618     gen_6xx_7xx_soft_tlb(env, 64, 2);
4619     init_excp_603(env);
4620     env->dcache_line_size = 32;
4621     env->icache_line_size = 32;
4622     /* Allocate hardware IRQ controller */
4623     ppc6xx_irq_init(env);
4624 }
4625
4626 /* PowerPC 604                                                               */
4627 #define POWERPC_INSNS_604    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4628                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4629                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4630                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4631                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4632                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4633                               PPC_SEGMENT | PPC_EXTERN)
4634 #define POWERPC_MSRM_604     (0x000000000005FF77ULL)
4635 #define POWERPC_MMU_604      (POWERPC_MMU_32B)
4636 //#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
4637 #define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
4638 #define POWERPC_BFDM_604     (bfd_mach_ppc_604)
4639 #define POWERPC_FLAG_604     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4640                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4641 #define check_pow_604        check_pow_nocheck
4642
4643 static void init_proc_604 (CPUPPCState *env)
4644 {
4645     gen_spr_ne_601(env);
4646     gen_spr_604(env);
4647     /* Time base */
4648     gen_tbl(env);
4649     /* Hardware implementation registers */
4650     /* XXX : not implemented */
4651     spr_register(env, SPR_HID0, "HID0",
4652                  SPR_NOACCESS, SPR_NOACCESS,
4653                  &spr_read_generic, &spr_write_generic,
4654                  0x00000000);
4655     /* Memory management */
4656     gen_low_BATs(env);
4657     init_excp_604(env);
4658     env->dcache_line_size = 32;
4659     env->icache_line_size = 32;
4660     /* Allocate hardware IRQ controller */
4661     ppc6xx_irq_init(env);
4662 }
4663
4664 /* PowerPC 604E                                                              */
4665 #define POWERPC_INSNS_604E   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4666                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4667                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4668                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4669                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4670                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4671                               PPC_SEGMENT | PPC_EXTERN)
4672 #define POWERPC_MSRM_604E    (0x000000000005FF77ULL)
4673 #define POWERPC_MMU_604E     (POWERPC_MMU_32B)
4674 #define POWERPC_EXCP_604E    (POWERPC_EXCP_604)
4675 #define POWERPC_INPUT_604E   (PPC_FLAGS_INPUT_6xx)
4676 #define POWERPC_BFDM_604E    (bfd_mach_ppc_604)
4677 #define POWERPC_FLAG_604E    (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4678                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4679 #define check_pow_604E       check_pow_nocheck
4680
4681 static void init_proc_604E (CPUPPCState *env)
4682 {
4683     gen_spr_ne_601(env);
4684     gen_spr_604(env);
4685     /* XXX : not implemented */
4686     spr_register(env, SPR_MMCR1, "MMCR1",
4687                  SPR_NOACCESS, SPR_NOACCESS,
4688                  &spr_read_generic, &spr_write_generic,
4689                  0x00000000);
4690     /* XXX : not implemented */
4691     spr_register(env, SPR_PMC3, "PMC3",
4692                  SPR_NOACCESS, SPR_NOACCESS,
4693                  &spr_read_generic, &spr_write_generic,
4694                  0x00000000);
4695     /* XXX : not implemented */
4696     spr_register(env, SPR_PMC4, "PMC4",
4697                  SPR_NOACCESS, SPR_NOACCESS,
4698                  &spr_read_generic, &spr_write_generic,
4699                  0x00000000);
4700     /* Time base */
4701     gen_tbl(env);
4702     /* Hardware implementation registers */
4703     /* XXX : not implemented */
4704     spr_register(env, SPR_HID0, "HID0",
4705                  SPR_NOACCESS, SPR_NOACCESS,
4706                  &spr_read_generic, &spr_write_generic,
4707                  0x00000000);
4708     /* XXX : not implemented */
4709     spr_register(env, SPR_HID1, "HID1",
4710                  SPR_NOACCESS, SPR_NOACCESS,
4711                  &spr_read_generic, &spr_write_generic,
4712                  0x00000000);
4713     /* Memory management */
4714     gen_low_BATs(env);
4715     init_excp_604(env);
4716     env->dcache_line_size = 32;
4717     env->icache_line_size = 32;
4718     /* Allocate hardware IRQ controller */
4719     ppc6xx_irq_init(env);
4720 }
4721
4722 /* PowerPC 740                                                               */
4723 #define POWERPC_INSNS_740    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4724                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4725                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4726                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4727                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4728                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4729                               PPC_SEGMENT | PPC_EXTERN)
4730 #define POWERPC_MSRM_740     (0x000000000005FF77ULL)
4731 #define POWERPC_MMU_740      (POWERPC_MMU_32B)
4732 #define POWERPC_EXCP_740     (POWERPC_EXCP_7x0)
4733 #define POWERPC_INPUT_740    (PPC_FLAGS_INPUT_6xx)
4734 #define POWERPC_BFDM_740     (bfd_mach_ppc_750)
4735 #define POWERPC_FLAG_740     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4736                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4737 #define check_pow_740        check_pow_hid0
4738
4739 static void init_proc_740 (CPUPPCState *env)
4740 {
4741     gen_spr_ne_601(env);
4742     gen_spr_7xx(env);
4743     /* Time base */
4744     gen_tbl(env);
4745     /* Thermal management */
4746     gen_spr_thrm(env);
4747     /* Hardware implementation registers */
4748     /* XXX : not implemented */
4749     spr_register(env, SPR_HID0, "HID0",
4750                  SPR_NOACCESS, SPR_NOACCESS,
4751                  &spr_read_generic, &spr_write_generic,
4752                  0x00000000);
4753     /* XXX : not implemented */
4754     spr_register(env, SPR_HID1, "HID1",
4755                  SPR_NOACCESS, SPR_NOACCESS,
4756                  &spr_read_generic, &spr_write_generic,
4757                  0x00000000);
4758     /* Memory management */
4759     gen_low_BATs(env);
4760     init_excp_7x0(env);
4761     env->dcache_line_size = 32;
4762     env->icache_line_size = 32;
4763     /* Allocate hardware IRQ controller */
4764     ppc6xx_irq_init(env);
4765 }
4766
4767 /* PowerPC 750                                                               */
4768 #define POWERPC_INSNS_750    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4769                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4770                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4771                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4772                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4773                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4774                               PPC_SEGMENT | PPC_EXTERN)
4775 #define POWERPC_MSRM_750     (0x000000000005FF77ULL)
4776 #define POWERPC_MMU_750      (POWERPC_MMU_32B)
4777 #define POWERPC_EXCP_750     (POWERPC_EXCP_7x0)
4778 #define POWERPC_INPUT_750    (PPC_FLAGS_INPUT_6xx)
4779 #define POWERPC_BFDM_750     (bfd_mach_ppc_750)
4780 #define POWERPC_FLAG_750     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4781                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4782 #define check_pow_750        check_pow_hid0
4783
4784 static void init_proc_750 (CPUPPCState *env)
4785 {
4786     gen_spr_ne_601(env);
4787     gen_spr_7xx(env);
4788     /* XXX : not implemented */
4789     spr_register(env, SPR_L2CR, "L2CR",
4790                  SPR_NOACCESS, SPR_NOACCESS,
4791                  &spr_read_generic, &spr_write_generic,
4792                  0x00000000);
4793     /* Time base */
4794     gen_tbl(env);
4795     /* Thermal management */
4796     gen_spr_thrm(env);
4797     /* Hardware implementation registers */
4798     /* XXX : not implemented */
4799     spr_register(env, SPR_HID0, "HID0",
4800                  SPR_NOACCESS, SPR_NOACCESS,
4801                  &spr_read_generic, &spr_write_generic,
4802                  0x00000000);
4803     /* XXX : not implemented */
4804     spr_register(env, SPR_HID1, "HID1",
4805                  SPR_NOACCESS, SPR_NOACCESS,
4806                  &spr_read_generic, &spr_write_generic,
4807                  0x00000000);
4808     /* Memory management */
4809     gen_low_BATs(env);
4810     /* XXX: high BATs are also present but are known to be bugged on
4811      *      die version 1.x
4812      */
4813     init_excp_7x0(env);
4814     env->dcache_line_size = 32;
4815     env->icache_line_size = 32;
4816     /* Allocate hardware IRQ controller */
4817     ppc6xx_irq_init(env);
4818 }
4819
4820 /* PowerPC 750 CL                                                            */
4821 /* XXX: not implemented:
4822  * cache lock instructions:
4823  * dcbz_l
4824  * floating point paired instructions
4825  * psq_lux
4826  * psq_lx
4827  * psq_stux
4828  * psq_stx
4829  * ps_abs
4830  * ps_add
4831  * ps_cmpo0
4832  * ps_cmpo1
4833  * ps_cmpu0
4834  * ps_cmpu1
4835  * ps_div
4836  * ps_madd
4837  * ps_madds0
4838  * ps_madds1
4839  * ps_merge00
4840  * ps_merge01
4841  * ps_merge10
4842  * ps_merge11
4843  * ps_mr
4844  * ps_msub
4845  * ps_mul
4846  * ps_muls0
4847  * ps_muls1
4848  * ps_nabs
4849  * ps_neg
4850  * ps_nmadd
4851  * ps_nmsub
4852  * ps_res
4853  * ps_rsqrte
4854  * ps_sel
4855  * ps_sub
4856  * ps_sum0
4857  * ps_sum1
4858  */
4859 #define POWERPC_INSNS_750cl  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4860                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4861                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
4862                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
4863                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
4864                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
4865                               PPC_SEGMENT | PPC_EXTERN)
4866 #define POWERPC_MSRM_750cl   (0x000000000005FF77ULL)
4867 #define POWERPC_MMU_750cl    (POWERPC_MMU_32B)
4868 #define POWERPC_EXCP_750cl   (POWERPC_EXCP_7x0)
4869 #define POWERPC_INPUT_750cl  (PPC_FLAGS_INPUT_6xx)
4870 #define POWERPC_BFDM_750cl   (bfd_mach_ppc_750)
4871 #define POWERPC_FLAG_750cl   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
4872                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4873 #define check_pow_750cl      check_pow_hid0
4874
4875 static void init_proc_750cl (CPUPPCState *env)
4876 {
4877     gen_spr_ne_601(env);
4878     gen_spr_7xx(env);
4879     /* XXX : not implemented */
4880     spr_register(env, SPR_L2CR, "L2CR",
4881                  SPR_NOACCESS, SPR_NOACCESS,
4882                  &spr_read_generic, &spr_write_generic,
4883                  0x00000000);
4884     /* Time base */
4885     gen_tbl(env);
4886     /* Thermal management */
4887     /* Those registers are fake on 750CL */
4888     spr_register(env, SPR_THRM1, "THRM1",
4889                  SPR_NOACCESS, SPR_NOACCESS,
4890                  &spr_read_generic, &spr_write_generic,
4891                  0x00000000);
4892     spr_register(env, SPR_THRM2, "THRM2",
4893                  SPR_NOACCESS, SPR_NOACCESS,
4894                  &spr_read_generic, &spr_write_generic,
4895                  0x00000000);
4896     spr_register(env, SPR_THRM3, "THRM3",
4897                  SPR_NOACCESS, SPR_NOACCESS,
4898                  &spr_read_generic, &spr_write_generic,
4899                  0x00000000);
4900     /* XXX: not implemented */
4901     spr_register(env, SPR_750_TDCL, "TDCL",
4902                  SPR_NOACCESS, SPR_NOACCESS,
4903                  &spr_read_generic, &spr_write_generic,
4904                  0x00000000);
4905     spr_register(env, SPR_750_TDCH, "TDCH",
4906                  SPR_NOACCESS, SPR_NOACCESS,
4907                  &spr_read_generic, &spr_write_generic,
4908                  0x00000000);
4909     /* DMA */
4910     /* XXX : not implemented */
4911     spr_register(env, SPR_750_WPAR, "WPAR",
4912                  SPR_NOACCESS, SPR_NOACCESS,
4913                  &spr_read_generic, &spr_write_generic,
4914                  0x00000000);
4915     spr_register(env, SPR_750_DMAL, "DMAL",
4916                  SPR_NOACCESS, SPR_NOACCESS,
4917                  &spr_read_generic, &spr_write_generic,
4918                  0x00000000);
4919     spr_register(env, SPR_750_DMAU, "DMAU",
4920                  SPR_NOACCESS, SPR_NOACCESS,
4921                  &spr_read_generic, &spr_write_generic,
4922                  0x00000000);
4923     /* Hardware implementation registers */
4924     /* XXX : not implemented */
4925     spr_register(env, SPR_HID0, "HID0",
4926                  SPR_NOACCESS, SPR_NOACCESS,
4927                  &spr_read_generic, &spr_write_generic,
4928                  0x00000000);
4929     /* XXX : not implemented */
4930     spr_register(env, SPR_HID1, "HID1",
4931                  SPR_NOACCESS, SPR_NOACCESS,
4932                  &spr_read_generic, &spr_write_generic,
4933                  0x00000000);
4934     /* XXX : not implemented */
4935     spr_register(env, SPR_750CL_HID2, "HID2",
4936                  SPR_NOACCESS, SPR_NOACCESS,
4937                  &spr_read_generic, &spr_write_generic,
4938                  0x00000000);
4939     /* XXX : not implemented */
4940     spr_register(env, SPR_750CL_HID4, "HID4",
4941                  SPR_NOACCESS, SPR_NOACCESS,
4942                  &spr_read_generic, &spr_write_generic,
4943                  0x00000000);
4944     /* Quantization registers */
4945     /* XXX : not implemented */
4946     spr_register(env, SPR_750_GQR0, "GQR0",
4947                  SPR_NOACCESS, SPR_NOACCESS,
4948                  &spr_read_generic, &spr_write_generic,
4949                  0x00000000);
4950     /* XXX : not implemented */
4951     spr_register(env, SPR_750_GQR1, "GQR1",
4952                  SPR_NOACCESS, SPR_NOACCESS,
4953                  &spr_read_generic, &spr_write_generic,
4954                  0x00000000);
4955     /* XXX : not implemented */
4956     spr_register(env, SPR_750_GQR2, "GQR2",
4957                  SPR_NOACCESS, SPR_NOACCESS,
4958                  &spr_read_generic, &spr_write_generic,
4959                  0x00000000);
4960     /* XXX : not implemented */
4961     spr_register(env, SPR_750_GQR3, "GQR3",
4962                  SPR_NOACCESS, SPR_NOACCESS,
4963                  &spr_read_generic, &spr_write_generic,
4964                  0x00000000);
4965     /* XXX : not implemented */
4966     spr_register(env, SPR_750_GQR4, "GQR4",
4967                  SPR_NOACCESS, SPR_NOACCESS,
4968                  &spr_read_generic, &spr_write_generic,
4969                  0x00000000);
4970     /* XXX : not implemented */
4971     spr_register(env, SPR_750_GQR5, "GQR5",
4972                  SPR_NOACCESS, SPR_NOACCESS,
4973                  &spr_read_generic, &spr_write_generic,
4974                  0x00000000);
4975     /* XXX : not implemented */
4976     spr_register(env, SPR_750_GQR6, "GQR6",
4977                  SPR_NOACCESS, SPR_NOACCESS,
4978                  &spr_read_generic, &spr_write_generic,
4979                  0x00000000);
4980     /* XXX : not implemented */
4981     spr_register(env, SPR_750_GQR7, "GQR7",
4982                  SPR_NOACCESS, SPR_NOACCESS,
4983                  &spr_read_generic, &spr_write_generic,
4984                  0x00000000);
4985     /* Memory management */
4986     gen_low_BATs(env);
4987     /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4988     gen_high_BATs(env);
4989     init_excp_750cl(env);
4990     env->dcache_line_size = 32;
4991     env->icache_line_size = 32;
4992     /* Allocate hardware IRQ controller */
4993     ppc6xx_irq_init(env);
4994 }
4995
4996 /* PowerPC 750CX                                                             */
4997 #define POWERPC_INSNS_750cx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
4998                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
4999                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5000                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5001                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5002                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5003                               PPC_SEGMENT | PPC_EXTERN)
5004 #define POWERPC_MSRM_750cx   (0x000000000005FF77ULL)
5005 #define POWERPC_MMU_750cx    (POWERPC_MMU_32B)
5006 #define POWERPC_EXCP_750cx   (POWERPC_EXCP_7x0)
5007 #define POWERPC_INPUT_750cx  (PPC_FLAGS_INPUT_6xx)
5008 #define POWERPC_BFDM_750cx   (bfd_mach_ppc_750)
5009 #define POWERPC_FLAG_750cx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5010                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5011 #define check_pow_750cx      check_pow_hid0
5012
5013 static void init_proc_750cx (CPUPPCState *env)
5014 {
5015     gen_spr_ne_601(env);
5016     gen_spr_7xx(env);
5017     /* XXX : not implemented */
5018     spr_register(env, SPR_L2CR, "L2CR",
5019                  SPR_NOACCESS, SPR_NOACCESS,
5020                  &spr_read_generic, &spr_write_generic,
5021                  0x00000000);
5022     /* Time base */
5023     gen_tbl(env);
5024     /* Thermal management */
5025     gen_spr_thrm(env);
5026     /* This register is not implemented but is present for compatibility */
5027     spr_register(env, SPR_SDA, "SDA",
5028                  SPR_NOACCESS, SPR_NOACCESS,
5029                  &spr_read_generic, &spr_write_generic,
5030                  0x00000000);
5031     /* Hardware implementation registers */
5032     /* XXX : not implemented */
5033     spr_register(env, SPR_HID0, "HID0",
5034                  SPR_NOACCESS, SPR_NOACCESS,
5035                  &spr_read_generic, &spr_write_generic,
5036                  0x00000000);
5037     /* XXX : not implemented */
5038     spr_register(env, SPR_HID1, "HID1",
5039                  SPR_NOACCESS, SPR_NOACCESS,
5040                  &spr_read_generic, &spr_write_generic,
5041                  0x00000000);
5042     /* Memory management */
5043     gen_low_BATs(env);
5044     /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5045     gen_high_BATs(env);
5046     init_excp_750cx(env);
5047     env->dcache_line_size = 32;
5048     env->icache_line_size = 32;
5049     /* Allocate hardware IRQ controller */
5050     ppc6xx_irq_init(env);
5051 }
5052
5053 /* PowerPC 750FX                                                             */
5054 #define POWERPC_INSNS_750fx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5055                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5056                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5057                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5058                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5059                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5060                               PPC_SEGMENT  | PPC_EXTERN)
5061 #define POWERPC_MSRM_750fx   (0x000000000005FF77ULL)
5062 #define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
5063 #define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
5064 #define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
5065 #define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
5066 #define POWERPC_FLAG_750fx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5067                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5068 #define check_pow_750fx      check_pow_hid0
5069
5070 static void init_proc_750fx (CPUPPCState *env)
5071 {
5072     gen_spr_ne_601(env);
5073     gen_spr_7xx(env);
5074     /* XXX : not implemented */
5075     spr_register(env, SPR_L2CR, "L2CR",
5076                  SPR_NOACCESS, SPR_NOACCESS,
5077                  &spr_read_generic, &spr_write_generic,
5078                  0x00000000);
5079     /* Time base */
5080     gen_tbl(env);
5081     /* Thermal management */
5082     gen_spr_thrm(env);
5083     /* XXX : not implemented */
5084     spr_register(env, SPR_750_THRM4, "THRM4",
5085                  SPR_NOACCESS, SPR_NOACCESS,
5086                  &spr_read_generic, &spr_write_generic,
5087                  0x00000000);
5088     /* Hardware implementation registers */
5089     /* XXX : not implemented */
5090     spr_register(env, SPR_HID0, "HID0",
5091                  SPR_NOACCESS, SPR_NOACCESS,
5092                  &spr_read_generic, &spr_write_generic,
5093                  0x00000000);
5094     /* XXX : not implemented */
5095     spr_register(env, SPR_HID1, "HID1",
5096                  SPR_NOACCESS, SPR_NOACCESS,
5097                  &spr_read_generic, &spr_write_generic,
5098                  0x00000000);
5099     /* XXX : not implemented */
5100     spr_register(env, SPR_750FX_HID2, "HID2",
5101                  SPR_NOACCESS, SPR_NOACCESS,
5102                  &spr_read_generic, &spr_write_generic,
5103                  0x00000000);
5104     /* Memory management */
5105     gen_low_BATs(env);
5106     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5107     gen_high_BATs(env);
5108     init_excp_7x0(env);
5109     env->dcache_line_size = 32;
5110     env->icache_line_size = 32;
5111     /* Allocate hardware IRQ controller */
5112     ppc6xx_irq_init(env);
5113 }
5114
5115 /* PowerPC 750GX                                                             */
5116 #define POWERPC_INSNS_750gx  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5117                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5118                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5119                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5120                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5121                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5122                               PPC_SEGMENT  | PPC_EXTERN)
5123 #define POWERPC_MSRM_750gx   (0x000000000005FF77ULL)
5124 #define POWERPC_MMU_750gx    (POWERPC_MMU_32B)
5125 #define POWERPC_EXCP_750gx   (POWERPC_EXCP_7x0)
5126 #define POWERPC_INPUT_750gx  (PPC_FLAGS_INPUT_6xx)
5127 #define POWERPC_BFDM_750gx   (bfd_mach_ppc_750)
5128 #define POWERPC_FLAG_750gx   (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5129                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5130 #define check_pow_750gx      check_pow_hid0
5131
5132 static void init_proc_750gx (CPUPPCState *env)
5133 {
5134     gen_spr_ne_601(env);
5135     gen_spr_7xx(env);
5136     /* XXX : not implemented (XXX: different from 750fx) */
5137     spr_register(env, SPR_L2CR, "L2CR",
5138                  SPR_NOACCESS, SPR_NOACCESS,
5139                  &spr_read_generic, &spr_write_generic,
5140                  0x00000000);
5141     /* Time base */
5142     gen_tbl(env);
5143     /* Thermal management */
5144     gen_spr_thrm(env);
5145     /* XXX : not implemented */
5146     spr_register(env, SPR_750_THRM4, "THRM4",
5147                  SPR_NOACCESS, SPR_NOACCESS,
5148                  &spr_read_generic, &spr_write_generic,
5149                  0x00000000);
5150     /* Hardware implementation registers */
5151     /* XXX : not implemented (XXX: different from 750fx) */
5152     spr_register(env, SPR_HID0, "HID0",
5153                  SPR_NOACCESS, SPR_NOACCESS,
5154                  &spr_read_generic, &spr_write_generic,
5155                  0x00000000);
5156     /* XXX : not implemented */
5157     spr_register(env, SPR_HID1, "HID1",
5158                  SPR_NOACCESS, SPR_NOACCESS,
5159                  &spr_read_generic, &spr_write_generic,
5160                  0x00000000);
5161     /* XXX : not implemented (XXX: different from 750fx) */
5162     spr_register(env, SPR_750FX_HID2, "HID2",
5163                  SPR_NOACCESS, SPR_NOACCESS,
5164                  &spr_read_generic, &spr_write_generic,
5165                  0x00000000);
5166     /* Memory management */
5167     gen_low_BATs(env);
5168     /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5169     gen_high_BATs(env);
5170     init_excp_7x0(env);
5171     env->dcache_line_size = 32;
5172     env->icache_line_size = 32;
5173     /* Allocate hardware IRQ controller */
5174     ppc6xx_irq_init(env);
5175 }
5176
5177 /* PowerPC 745                                                               */
5178 #define POWERPC_INSNS_745    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5179                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5180                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5181                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5182                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5183                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5184                               PPC_SEGMENT | PPC_EXTERN)
5185 #define POWERPC_MSRM_745     (0x000000000005FF77ULL)
5186 #define POWERPC_MMU_745      (POWERPC_MMU_SOFT_6xx)
5187 #define POWERPC_EXCP_745     (POWERPC_EXCP_7x5)
5188 #define POWERPC_INPUT_745    (PPC_FLAGS_INPUT_6xx)
5189 #define POWERPC_BFDM_745     (bfd_mach_ppc_750)
5190 #define POWERPC_FLAG_745     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5191                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5192 #define check_pow_745        check_pow_hid0
5193
5194 static void init_proc_745 (CPUPPCState *env)
5195 {
5196     gen_spr_ne_601(env);
5197     gen_spr_7xx(env);
5198     gen_spr_G2_755(env);
5199     /* Time base */
5200     gen_tbl(env);
5201     /* Thermal management */
5202     gen_spr_thrm(env);
5203     /* Hardware implementation registers */
5204     /* XXX : not implemented */
5205     spr_register(env, SPR_HID0, "HID0",
5206                  SPR_NOACCESS, SPR_NOACCESS,
5207                  &spr_read_generic, &spr_write_generic,
5208                  0x00000000);
5209     /* XXX : not implemented */
5210     spr_register(env, SPR_HID1, "HID1",
5211                  SPR_NOACCESS, SPR_NOACCESS,
5212                  &spr_read_generic, &spr_write_generic,
5213                  0x00000000);
5214     /* XXX : not implemented */
5215     spr_register(env, SPR_HID2, "HID2",
5216                  SPR_NOACCESS, SPR_NOACCESS,
5217                  &spr_read_generic, &spr_write_generic,
5218                  0x00000000);
5219     /* Memory management */
5220     gen_low_BATs(env);
5221     gen_high_BATs(env);
5222     gen_6xx_7xx_soft_tlb(env, 64, 2);
5223     init_excp_7x5(env);
5224     env->dcache_line_size = 32;
5225     env->icache_line_size = 32;
5226     /* Allocate hardware IRQ controller */
5227     ppc6xx_irq_init(env);
5228 }
5229
5230 /* PowerPC 755                                                               */
5231 #define POWERPC_INSNS_755    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5232                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5233                               PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |          \
5234                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
5235                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5236                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5237                               PPC_SEGMENT | PPC_EXTERN)
5238 #define POWERPC_MSRM_755     (0x000000000005FF77ULL)
5239 #define POWERPC_MMU_755      (POWERPC_MMU_SOFT_6xx)
5240 #define POWERPC_EXCP_755     (POWERPC_EXCP_7x5)
5241 #define POWERPC_INPUT_755    (PPC_FLAGS_INPUT_6xx)
5242 #define POWERPC_BFDM_755     (bfd_mach_ppc_750)
5243 #define POWERPC_FLAG_755     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |             \
5244                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5245 #define check_pow_755        check_pow_hid0
5246
5247 static void init_proc_755 (CPUPPCState *env)
5248 {
5249     gen_spr_ne_601(env);
5250     gen_spr_7xx(env);
5251     gen_spr_G2_755(env);
5252     /* Time base */
5253     gen_tbl(env);
5254     /* L2 cache control */
5255     /* XXX : not implemented */
5256     spr_register(env, SPR_L2CR, "L2CR",
5257                  SPR_NOACCESS, SPR_NOACCESS,
5258                  &spr_read_generic, &spr_write_generic,
5259                  0x00000000);
5260     /* XXX : not implemented */
5261     spr_register(env, SPR_L2PMCR, "L2PMCR",
5262                  SPR_NOACCESS, SPR_NOACCESS,
5263                  &spr_read_generic, &spr_write_generic,
5264                  0x00000000);
5265     /* Thermal management */
5266     gen_spr_thrm(env);
5267     /* Hardware implementation registers */
5268     /* XXX : not implemented */
5269     spr_register(env, SPR_HID0, "HID0",
5270                  SPR_NOACCESS, SPR_NOACCESS,
5271                  &spr_read_generic, &spr_write_generic,
5272                  0x00000000);
5273     /* XXX : not implemented */
5274     spr_register(env, SPR_HID1, "HID1",
5275                  SPR_NOACCESS, SPR_NOACCESS,
5276                  &spr_read_generic, &spr_write_generic,
5277                  0x00000000);
5278     /* XXX : not implemented */
5279     spr_register(env, SPR_HID2, "HID2",
5280                  SPR_NOACCESS, SPR_NOACCESS,
5281                  &spr_read_generic, &spr_write_generic,
5282                  0x00000000);
5283     /* Memory management */
5284     gen_low_BATs(env);
5285     gen_high_BATs(env);
5286     gen_6xx_7xx_soft_tlb(env, 64, 2);
5287     init_excp_7x5(env);
5288     env->dcache_line_size = 32;
5289     env->icache_line_size = 32;
5290     /* Allocate hardware IRQ controller */
5291     ppc6xx_irq_init(env);
5292 }
5293
5294 /* PowerPC 7400 (aka G4)                                                     */
5295 #define POWERPC_INSNS_7400   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5296                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5297                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5298                               PPC_FLOAT_STFIWX |                              \
5299                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5300                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5301                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5302                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5303                               PPC_MEM_TLBIA |                                 \
5304                               PPC_SEGMENT | PPC_EXTERN |                      \
5305                               PPC_ALTIVEC)
5306 #define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
5307 #define POWERPC_MMU_7400     (POWERPC_MMU_32B)
5308 #define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
5309 #define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
5310 #define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
5311 #define POWERPC_FLAG_7400    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5312                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5313                               POWERPC_FLAG_BUS_CLK)
5314 #define check_pow_7400       check_pow_hid0
5315
5316 static void init_proc_7400 (CPUPPCState *env)
5317 {
5318     gen_spr_ne_601(env);
5319     gen_spr_7xx(env);
5320     /* Time base */
5321     gen_tbl(env);
5322     /* 74xx specific SPR */
5323     gen_spr_74xx(env);
5324     /* XXX : not implemented */
5325     spr_register(env, SPR_UBAMR, "UBAMR",
5326                  &spr_read_ureg, SPR_NOACCESS,
5327                  &spr_read_ureg, SPR_NOACCESS,
5328                  0x00000000);
5329     /* XXX: this seems not implemented on all revisions. */
5330     /* XXX : not implemented */
5331     spr_register(env, SPR_MSSCR1, "MSSCR1",
5332                  SPR_NOACCESS, SPR_NOACCESS,
5333                  &spr_read_generic, &spr_write_generic,
5334                  0x00000000);
5335     /* Thermal management */
5336     gen_spr_thrm(env);
5337     /* Memory management */
5338     gen_low_BATs(env);
5339     init_excp_7400(env);
5340     env->dcache_line_size = 32;
5341     env->icache_line_size = 32;
5342     /* Allocate hardware IRQ controller */
5343     ppc6xx_irq_init(env);
5344 }
5345
5346 /* PowerPC 7410 (aka G4)                                                     */
5347 #define POWERPC_INSNS_7410   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5348                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5349                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5350                               PPC_FLOAT_STFIWX |                              \
5351                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5352                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5353                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5354                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5355                               PPC_MEM_TLBIA |                                 \
5356                               PPC_SEGMENT | PPC_EXTERN |                      \
5357                               PPC_ALTIVEC)
5358 #define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
5359 #define POWERPC_MMU_7410     (POWERPC_MMU_32B)
5360 #define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
5361 #define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
5362 #define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
5363 #define POWERPC_FLAG_7410    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5364                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5365                               POWERPC_FLAG_BUS_CLK)
5366 #define check_pow_7410       check_pow_hid0
5367
5368 static void init_proc_7410 (CPUPPCState *env)
5369 {
5370     gen_spr_ne_601(env);
5371     gen_spr_7xx(env);
5372     /* Time base */
5373     gen_tbl(env);
5374     /* 74xx specific SPR */
5375     gen_spr_74xx(env);
5376     /* XXX : not implemented */
5377     spr_register(env, SPR_UBAMR, "UBAMR",
5378                  &spr_read_ureg, SPR_NOACCESS,
5379                  &spr_read_ureg, SPR_NOACCESS,
5380                  0x00000000);
5381     /* Thermal management */
5382     gen_spr_thrm(env);
5383     /* L2PMCR */
5384     /* XXX : not implemented */
5385     spr_register(env, SPR_L2PMCR, "L2PMCR",
5386                  SPR_NOACCESS, SPR_NOACCESS,
5387                  &spr_read_generic, &spr_write_generic,
5388                  0x00000000);
5389     /* LDSTDB */
5390     /* XXX : not implemented */
5391     spr_register(env, SPR_LDSTDB, "LDSTDB",
5392                  SPR_NOACCESS, SPR_NOACCESS,
5393                  &spr_read_generic, &spr_write_generic,
5394                  0x00000000);
5395     /* Memory management */
5396     gen_low_BATs(env);
5397     init_excp_7400(env);
5398     env->dcache_line_size = 32;
5399     env->icache_line_size = 32;
5400     /* Allocate hardware IRQ controller */
5401     ppc6xx_irq_init(env);
5402 }
5403
5404 /* PowerPC 7440 (aka G4)                                                     */
5405 #define POWERPC_INSNS_7440   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5406                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5407                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5408                               PPC_FLOAT_STFIWX |                              \
5409                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5410                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5411                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5412                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5413                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5414                               PPC_SEGMENT | PPC_EXTERN |                      \
5415                               PPC_ALTIVEC)
5416 #define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
5417 #define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
5418 #define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
5419 #define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
5420 #define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
5421 #define POWERPC_FLAG_7440    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5422                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5423                               POWERPC_FLAG_BUS_CLK)
5424 #define check_pow_7440       check_pow_hid0_74xx
5425
5426 __attribute__ (( unused ))
5427 static void init_proc_7440 (CPUPPCState *env)
5428 {
5429     gen_spr_ne_601(env);
5430     gen_spr_7xx(env);
5431     /* Time base */
5432     gen_tbl(env);
5433     /* 74xx specific SPR */
5434     gen_spr_74xx(env);
5435     /* XXX : not implemented */
5436     spr_register(env, SPR_UBAMR, "UBAMR",
5437                  &spr_read_ureg, SPR_NOACCESS,
5438                  &spr_read_ureg, SPR_NOACCESS,
5439                  0x00000000);
5440     /* LDSTCR */
5441     /* XXX : not implemented */
5442     spr_register(env, SPR_LDSTCR, "LDSTCR",
5443                  SPR_NOACCESS, SPR_NOACCESS,
5444                  &spr_read_generic, &spr_write_generic,
5445                  0x00000000);
5446     /* ICTRL */
5447     /* XXX : not implemented */
5448     spr_register(env, SPR_ICTRL, "ICTRL",
5449                  SPR_NOACCESS, SPR_NOACCESS,
5450                  &spr_read_generic, &spr_write_generic,
5451                  0x00000000);
5452     /* MSSSR0 */
5453     /* XXX : not implemented */
5454     spr_register(env, SPR_MSSSR0, "MSSSR0",
5455                  SPR_NOACCESS, SPR_NOACCESS,
5456                  &spr_read_generic, &spr_write_generic,
5457                  0x00000000);
5458     /* PMC */
5459     /* XXX : not implemented */
5460     spr_register(env, SPR_PMC5, "PMC5",
5461                  SPR_NOACCESS, SPR_NOACCESS,
5462                  &spr_read_generic, &spr_write_generic,
5463                  0x00000000);
5464     /* XXX : not implemented */
5465     spr_register(env, SPR_UPMC5, "UPMC5",
5466                  &spr_read_ureg, SPR_NOACCESS,
5467                  &spr_read_ureg, SPR_NOACCESS,
5468                  0x00000000);
5469     /* XXX : not implemented */
5470     spr_register(env, SPR_PMC6, "PMC6",
5471                  SPR_NOACCESS, SPR_NOACCESS,
5472                  &spr_read_generic, &spr_write_generic,
5473                  0x00000000);
5474     /* XXX : not implemented */
5475     spr_register(env, SPR_UPMC6, "UPMC6",
5476                  &spr_read_ureg, SPR_NOACCESS,
5477                  &spr_read_ureg, SPR_NOACCESS,
5478                  0x00000000);
5479     /* Memory management */
5480     gen_low_BATs(env);
5481     gen_74xx_soft_tlb(env, 128, 2);
5482     init_excp_7450(env);
5483     env->dcache_line_size = 32;
5484     env->icache_line_size = 32;
5485     /* Allocate hardware IRQ controller */
5486     ppc6xx_irq_init(env);
5487 }
5488
5489 /* PowerPC 7450 (aka G4)                                                     */
5490 #define POWERPC_INSNS_7450   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5491                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5492                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5493                               PPC_FLOAT_STFIWX |                              \
5494                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5495                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5496                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5497                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5498                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5499                               PPC_SEGMENT | PPC_EXTERN |                      \
5500                               PPC_ALTIVEC)
5501 #define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
5502 #define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
5503 #define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
5504 #define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
5505 #define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
5506 #define POWERPC_FLAG_7450    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5507                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5508                               POWERPC_FLAG_BUS_CLK)
5509 #define check_pow_7450       check_pow_hid0_74xx
5510
5511 __attribute__ (( unused ))
5512 static void init_proc_7450 (CPUPPCState *env)
5513 {
5514     gen_spr_ne_601(env);
5515     gen_spr_7xx(env);
5516     /* Time base */
5517     gen_tbl(env);
5518     /* 74xx specific SPR */
5519     gen_spr_74xx(env);
5520     /* Level 3 cache control */
5521     gen_l3_ctrl(env);
5522     /* L3ITCR1 */
5523     /* XXX : not implemented */
5524     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5525                  SPR_NOACCESS, SPR_NOACCESS,
5526                  &spr_read_generic, &spr_write_generic,
5527                  0x00000000);
5528     /* L3ITCR2 */
5529     /* XXX : not implemented */
5530     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5531                  SPR_NOACCESS, SPR_NOACCESS,
5532                  &spr_read_generic, &spr_write_generic,
5533                  0x00000000);
5534     /* L3ITCR3 */
5535     /* XXX : not implemented */
5536     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5537                  SPR_NOACCESS, SPR_NOACCESS,
5538                  &spr_read_generic, &spr_write_generic,
5539                  0x00000000);
5540     /* L3OHCR */
5541     /* XXX : not implemented */
5542     spr_register(env, SPR_L3OHCR, "L3OHCR",
5543                  SPR_NOACCESS, SPR_NOACCESS,
5544                  &spr_read_generic, &spr_write_generic,
5545                  0x00000000);
5546     /* XXX : not implemented */
5547     spr_register(env, SPR_UBAMR, "UBAMR",
5548                  &spr_read_ureg, SPR_NOACCESS,
5549                  &spr_read_ureg, SPR_NOACCESS,
5550                  0x00000000);
5551     /* LDSTCR */
5552     /* XXX : not implemented */
5553     spr_register(env, SPR_LDSTCR, "LDSTCR",
5554                  SPR_NOACCESS, SPR_NOACCESS,
5555                  &spr_read_generic, &spr_write_generic,
5556                  0x00000000);
5557     /* ICTRL */
5558     /* XXX : not implemented */
5559     spr_register(env, SPR_ICTRL, "ICTRL",
5560                  SPR_NOACCESS, SPR_NOACCESS,
5561                  &spr_read_generic, &spr_write_generic,
5562                  0x00000000);
5563     /* MSSSR0 */
5564     /* XXX : not implemented */
5565     spr_register(env, SPR_MSSSR0, "MSSSR0",
5566                  SPR_NOACCESS, SPR_NOACCESS,
5567                  &spr_read_generic, &spr_write_generic,
5568                  0x00000000);
5569     /* PMC */
5570     /* XXX : not implemented */
5571     spr_register(env, SPR_PMC5, "PMC5",
5572                  SPR_NOACCESS, SPR_NOACCESS,
5573                  &spr_read_generic, &spr_write_generic,
5574                  0x00000000);
5575     /* XXX : not implemented */
5576     spr_register(env, SPR_UPMC5, "UPMC5",
5577                  &spr_read_ureg, SPR_NOACCESS,
5578                  &spr_read_ureg, SPR_NOACCESS,
5579                  0x00000000);
5580     /* XXX : not implemented */
5581     spr_register(env, SPR_PMC6, "PMC6",
5582                  SPR_NOACCESS, SPR_NOACCESS,
5583                  &spr_read_generic, &spr_write_generic,
5584                  0x00000000);
5585     /* XXX : not implemented */
5586     spr_register(env, SPR_UPMC6, "UPMC6",
5587                  &spr_read_ureg, SPR_NOACCESS,
5588                  &spr_read_ureg, SPR_NOACCESS,
5589                  0x00000000);
5590     /* Memory management */
5591     gen_low_BATs(env);
5592     gen_74xx_soft_tlb(env, 128, 2);
5593     init_excp_7450(env);
5594     env->dcache_line_size = 32;
5595     env->icache_line_size = 32;
5596     /* Allocate hardware IRQ controller */
5597     ppc6xx_irq_init(env);
5598 }
5599
5600 /* PowerPC 7445 (aka G4)                                                     */
5601 #define POWERPC_INSNS_7445   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5602                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5603                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5604                               PPC_FLOAT_STFIWX |                              \
5605                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5606                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5607                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5608                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5609                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5610                               PPC_SEGMENT | PPC_EXTERN |                      \
5611                               PPC_ALTIVEC)
5612 #define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
5613 #define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
5614 #define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
5615 #define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
5616 #define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
5617 #define POWERPC_FLAG_7445    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5618                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5619                               POWERPC_FLAG_BUS_CLK)
5620 #define check_pow_7445       check_pow_hid0_74xx
5621
5622 __attribute__ (( unused ))
5623 static void init_proc_7445 (CPUPPCState *env)
5624 {
5625     gen_spr_ne_601(env);
5626     gen_spr_7xx(env);
5627     /* Time base */
5628     gen_tbl(env);
5629     /* 74xx specific SPR */
5630     gen_spr_74xx(env);
5631     /* LDSTCR */
5632     /* XXX : not implemented */
5633     spr_register(env, SPR_LDSTCR, "LDSTCR",
5634                  SPR_NOACCESS, SPR_NOACCESS,
5635                  &spr_read_generic, &spr_write_generic,
5636                  0x00000000);
5637     /* ICTRL */
5638     /* XXX : not implemented */
5639     spr_register(env, SPR_ICTRL, "ICTRL",
5640                  SPR_NOACCESS, SPR_NOACCESS,
5641                  &spr_read_generic, &spr_write_generic,
5642                  0x00000000);
5643     /* MSSSR0 */
5644     /* XXX : not implemented */
5645     spr_register(env, SPR_MSSSR0, "MSSSR0",
5646                  SPR_NOACCESS, SPR_NOACCESS,
5647                  &spr_read_generic, &spr_write_generic,
5648                  0x00000000);
5649     /* PMC */
5650     /* XXX : not implemented */
5651     spr_register(env, SPR_PMC5, "PMC5",
5652                  SPR_NOACCESS, SPR_NOACCESS,
5653                  &spr_read_generic, &spr_write_generic,
5654                  0x00000000);
5655     /* XXX : not implemented */
5656     spr_register(env, SPR_UPMC5, "UPMC5",
5657                  &spr_read_ureg, SPR_NOACCESS,
5658                  &spr_read_ureg, SPR_NOACCESS,
5659                  0x00000000);
5660     /* XXX : not implemented */
5661     spr_register(env, SPR_PMC6, "PMC6",
5662                  SPR_NOACCESS, SPR_NOACCESS,
5663                  &spr_read_generic, &spr_write_generic,
5664                  0x00000000);
5665     /* XXX : not implemented */
5666     spr_register(env, SPR_UPMC6, "UPMC6",
5667                  &spr_read_ureg, SPR_NOACCESS,
5668                  &spr_read_ureg, SPR_NOACCESS,
5669                  0x00000000);
5670     /* SPRGs */
5671     spr_register(env, SPR_SPRG4, "SPRG4",
5672                  SPR_NOACCESS, SPR_NOACCESS,
5673                  &spr_read_generic, &spr_write_generic,
5674                  0x00000000);
5675     spr_register(env, SPR_USPRG4, "USPRG4",
5676                  &spr_read_ureg, SPR_NOACCESS,
5677                  &spr_read_ureg, SPR_NOACCESS,
5678                  0x00000000);
5679     spr_register(env, SPR_SPRG5, "SPRG5",
5680                  SPR_NOACCESS, SPR_NOACCESS,
5681                  &spr_read_generic, &spr_write_generic,
5682                  0x00000000);
5683     spr_register(env, SPR_USPRG5, "USPRG5",
5684                  &spr_read_ureg, SPR_NOACCESS,
5685                  &spr_read_ureg, SPR_NOACCESS,
5686                  0x00000000);
5687     spr_register(env, SPR_SPRG6, "SPRG6",
5688                  SPR_NOACCESS, SPR_NOACCESS,
5689                  &spr_read_generic, &spr_write_generic,
5690                  0x00000000);
5691     spr_register(env, SPR_USPRG6, "USPRG6",
5692                  &spr_read_ureg, SPR_NOACCESS,
5693                  &spr_read_ureg, SPR_NOACCESS,
5694                  0x00000000);
5695     spr_register(env, SPR_SPRG7, "SPRG7",
5696                  SPR_NOACCESS, SPR_NOACCESS,
5697                  &spr_read_generic, &spr_write_generic,
5698                  0x00000000);
5699     spr_register(env, SPR_USPRG7, "USPRG7",
5700                  &spr_read_ureg, SPR_NOACCESS,
5701                  &spr_read_ureg, SPR_NOACCESS,
5702                  0x00000000);
5703     /* Memory management */
5704     gen_low_BATs(env);
5705     gen_high_BATs(env);
5706     gen_74xx_soft_tlb(env, 128, 2);
5707     init_excp_7450(env);
5708     env->dcache_line_size = 32;
5709     env->icache_line_size = 32;
5710     /* Allocate hardware IRQ controller */
5711     ppc6xx_irq_init(env);
5712 }
5713
5714 /* PowerPC 7455 (aka G4)                                                     */
5715 #define POWERPC_INSNS_7455   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5716                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5717                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5718                               PPC_FLOAT_STFIWX |                              \
5719                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5720                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5721                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5722                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5723                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5724                               PPC_SEGMENT | PPC_EXTERN |                      \
5725                               PPC_ALTIVEC)
5726 #define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
5727 #define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
5728 #define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
5729 #define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
5730 #define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
5731 #define POWERPC_FLAG_7455    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5732                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5733                               POWERPC_FLAG_BUS_CLK)
5734 #define check_pow_7455       check_pow_hid0_74xx
5735
5736 __attribute__ (( unused ))
5737 static void init_proc_7455 (CPUPPCState *env)
5738 {
5739     gen_spr_ne_601(env);
5740     gen_spr_7xx(env);
5741     /* Time base */
5742     gen_tbl(env);
5743     /* 74xx specific SPR */
5744     gen_spr_74xx(env);
5745     /* Level 3 cache control */
5746     gen_l3_ctrl(env);
5747     /* LDSTCR */
5748     /* XXX : not implemented */
5749     spr_register(env, SPR_LDSTCR, "LDSTCR",
5750                  SPR_NOACCESS, SPR_NOACCESS,
5751                  &spr_read_generic, &spr_write_generic,
5752                  0x00000000);
5753     /* ICTRL */
5754     /* XXX : not implemented */
5755     spr_register(env, SPR_ICTRL, "ICTRL",
5756                  SPR_NOACCESS, SPR_NOACCESS,
5757                  &spr_read_generic, &spr_write_generic,
5758                  0x00000000);
5759     /* MSSSR0 */
5760     /* XXX : not implemented */
5761     spr_register(env, SPR_MSSSR0, "MSSSR0",
5762                  SPR_NOACCESS, SPR_NOACCESS,
5763                  &spr_read_generic, &spr_write_generic,
5764                  0x00000000);
5765     /* PMC */
5766     /* XXX : not implemented */
5767     spr_register(env, SPR_PMC5, "PMC5",
5768                  SPR_NOACCESS, SPR_NOACCESS,
5769                  &spr_read_generic, &spr_write_generic,
5770                  0x00000000);
5771     /* XXX : not implemented */
5772     spr_register(env, SPR_UPMC5, "UPMC5",
5773                  &spr_read_ureg, SPR_NOACCESS,
5774                  &spr_read_ureg, SPR_NOACCESS,
5775                  0x00000000);
5776     /* XXX : not implemented */
5777     spr_register(env, SPR_PMC6, "PMC6",
5778                  SPR_NOACCESS, SPR_NOACCESS,
5779                  &spr_read_generic, &spr_write_generic,
5780                  0x00000000);
5781     /* XXX : not implemented */
5782     spr_register(env, SPR_UPMC6, "UPMC6",
5783                  &spr_read_ureg, SPR_NOACCESS,
5784                  &spr_read_ureg, SPR_NOACCESS,
5785                  0x00000000);
5786     /* SPRGs */
5787     spr_register(env, SPR_SPRG4, "SPRG4",
5788                  SPR_NOACCESS, SPR_NOACCESS,
5789                  &spr_read_generic, &spr_write_generic,
5790                  0x00000000);
5791     spr_register(env, SPR_USPRG4, "USPRG4",
5792                  &spr_read_ureg, SPR_NOACCESS,
5793                  &spr_read_ureg, SPR_NOACCESS,
5794                  0x00000000);
5795     spr_register(env, SPR_SPRG5, "SPRG5",
5796                  SPR_NOACCESS, SPR_NOACCESS,
5797                  &spr_read_generic, &spr_write_generic,
5798                  0x00000000);
5799     spr_register(env, SPR_USPRG5, "USPRG5",
5800                  &spr_read_ureg, SPR_NOACCESS,
5801                  &spr_read_ureg, SPR_NOACCESS,
5802                  0x00000000);
5803     spr_register(env, SPR_SPRG6, "SPRG6",
5804                  SPR_NOACCESS, SPR_NOACCESS,
5805                  &spr_read_generic, &spr_write_generic,
5806                  0x00000000);
5807     spr_register(env, SPR_USPRG6, "USPRG6",
5808                  &spr_read_ureg, SPR_NOACCESS,
5809                  &spr_read_ureg, SPR_NOACCESS,
5810                  0x00000000);
5811     spr_register(env, SPR_SPRG7, "SPRG7",
5812                  SPR_NOACCESS, SPR_NOACCESS,
5813                  &spr_read_generic, &spr_write_generic,
5814                  0x00000000);
5815     spr_register(env, SPR_USPRG7, "USPRG7",
5816                  &spr_read_ureg, SPR_NOACCESS,
5817                  &spr_read_ureg, SPR_NOACCESS,
5818                  0x00000000);
5819     /* Memory management */
5820     gen_low_BATs(env);
5821     gen_high_BATs(env);
5822     gen_74xx_soft_tlb(env, 128, 2);
5823     init_excp_7450(env);
5824     env->dcache_line_size = 32;
5825     env->icache_line_size = 32;
5826     /* Allocate hardware IRQ controller */
5827     ppc6xx_irq_init(env);
5828 }
5829
5830 /* PowerPC 7457 (aka G4)                                                     */
5831 #define POWERPC_INSNS_7457   (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5832                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5833                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5834                               PPC_FLOAT_STFIWX |                              \
5835                               PPC_CACHE | PPC_CACHE_ICBI |                    \
5836                               PPC_CACHE_DCBA | PPC_CACHE_DCBZ |               \
5837                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5838                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5839                               PPC_MEM_TLBIA | PPC_74xx_TLB |                  \
5840                               PPC_SEGMENT | PPC_EXTERN |                      \
5841                               PPC_ALTIVEC)
5842 #define POWERPC_MSRM_7457    (0x000000000205FF77ULL)
5843 #define POWERPC_MMU_7457     (POWERPC_MMU_SOFT_74xx)
5844 #define POWERPC_EXCP_7457    (POWERPC_EXCP_74xx)
5845 #define POWERPC_INPUT_7457   (PPC_FLAGS_INPUT_6xx)
5846 #define POWERPC_BFDM_7457    (bfd_mach_ppc_7400)
5847 #define POWERPC_FLAG_7457    (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5848                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5849                               POWERPC_FLAG_BUS_CLK)
5850 #define check_pow_7457       check_pow_hid0_74xx
5851
5852 __attribute__ (( unused ))
5853 static void init_proc_7457 (CPUPPCState *env)
5854 {
5855     gen_spr_ne_601(env);
5856     gen_spr_7xx(env);
5857     /* Time base */
5858     gen_tbl(env);
5859     /* 74xx specific SPR */
5860     gen_spr_74xx(env);
5861     /* Level 3 cache control */
5862     gen_l3_ctrl(env);
5863     /* L3ITCR1 */
5864     /* XXX : not implemented */
5865     spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5866                  SPR_NOACCESS, SPR_NOACCESS,
5867                  &spr_read_generic, &spr_write_generic,
5868                  0x00000000);
5869     /* L3ITCR2 */
5870     /* XXX : not implemented */
5871     spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5872                  SPR_NOACCESS, SPR_NOACCESS,
5873                  &spr_read_generic, &spr_write_generic,
5874                  0x00000000);
5875     /* L3ITCR3 */
5876     /* XXX : not implemented */
5877     spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5878                  SPR_NOACCESS, SPR_NOACCESS,
5879                  &spr_read_generic, &spr_write_generic,
5880                  0x00000000);
5881     /* L3OHCR */
5882     /* XXX : not implemented */
5883     spr_register(env, SPR_L3OHCR, "L3OHCR",
5884                  SPR_NOACCESS, SPR_NOACCESS,
5885                  &spr_read_generic, &spr_write_generic,
5886                  0x00000000);
5887     /* LDSTCR */
5888     /* XXX : not implemented */
5889     spr_register(env, SPR_LDSTCR, "LDSTCR",
5890                  SPR_NOACCESS, SPR_NOACCESS,
5891                  &spr_read_generic, &spr_write_generic,
5892                  0x00000000);
5893     /* ICTRL */
5894     /* XXX : not implemented */
5895     spr_register(env, SPR_ICTRL, "ICTRL",
5896                  SPR_NOACCESS, SPR_NOACCESS,
5897                  &spr_read_generic, &spr_write_generic,
5898                  0x00000000);
5899     /* MSSSR0 */
5900     /* XXX : not implemented */
5901     spr_register(env, SPR_MSSSR0, "MSSSR0",
5902                  SPR_NOACCESS, SPR_NOACCESS,
5903                  &spr_read_generic, &spr_write_generic,
5904                  0x00000000);
5905     /* PMC */
5906     /* XXX : not implemented */
5907     spr_register(env, SPR_PMC5, "PMC5",
5908                  SPR_NOACCESS, SPR_NOACCESS,
5909                  &spr_read_generic, &spr_write_generic,
5910                  0x00000000);
5911     /* XXX : not implemented */
5912     spr_register(env, SPR_UPMC5, "UPMC5",
5913                  &spr_read_ureg, SPR_NOACCESS,
5914                  &spr_read_ureg, SPR_NOACCESS,
5915                  0x00000000);
5916     /* XXX : not implemented */
5917     spr_register(env, SPR_PMC6, "PMC6",
5918                  SPR_NOACCESS, SPR_NOACCESS,
5919                  &spr_read_generic, &spr_write_generic,
5920                  0x00000000);
5921     /* XXX : not implemented */
5922     spr_register(env, SPR_UPMC6, "UPMC6",
5923                  &spr_read_ureg, SPR_NOACCESS,
5924                  &spr_read_ureg, SPR_NOACCESS,
5925                  0x00000000);
5926     /* SPRGs */
5927     spr_register(env, SPR_SPRG4, "SPRG4",
5928                  SPR_NOACCESS, SPR_NOACCESS,
5929                  &spr_read_generic, &spr_write_generic,
5930                  0x00000000);
5931     spr_register(env, SPR_USPRG4, "USPRG4",
5932                  &spr_read_ureg, SPR_NOACCESS,
5933                  &spr_read_ureg, SPR_NOACCESS,
5934                  0x00000000);
5935     spr_register(env, SPR_SPRG5, "SPRG5",
5936                  SPR_NOACCESS, SPR_NOACCESS,
5937                  &spr_read_generic, &spr_write_generic,
5938                  0x00000000);
5939     spr_register(env, SPR_USPRG5, "USPRG5",
5940                  &spr_read_ureg, SPR_NOACCESS,
5941                  &spr_read_ureg, SPR_NOACCESS,
5942                  0x00000000);
5943     spr_register(env, SPR_SPRG6, "SPRG6",
5944                  SPR_NOACCESS, SPR_NOACCESS,
5945                  &spr_read_generic, &spr_write_generic,
5946                  0x00000000);
5947     spr_register(env, SPR_USPRG6, "USPRG6",
5948                  &spr_read_ureg, SPR_NOACCESS,
5949                  &spr_read_ureg, SPR_NOACCESS,
5950                  0x00000000);
5951     spr_register(env, SPR_SPRG7, "SPRG7",
5952                  SPR_NOACCESS, SPR_NOACCESS,
5953                  &spr_read_generic, &spr_write_generic,
5954                  0x00000000);
5955     spr_register(env, SPR_USPRG7, "USPRG7",
5956                  &spr_read_ureg, SPR_NOACCESS,
5957                  &spr_read_ureg, SPR_NOACCESS,
5958                  0x00000000);
5959     /* Memory management */
5960     gen_low_BATs(env);
5961     gen_high_BATs(env);
5962     gen_74xx_soft_tlb(env, 128, 2);
5963     init_excp_7450(env);
5964     env->dcache_line_size = 32;
5965     env->icache_line_size = 32;
5966     /* Allocate hardware IRQ controller */
5967     ppc6xx_irq_init(env);
5968 }
5969
5970 #if defined (TARGET_PPC64)
5971 /* PowerPC 970                                                               */
5972 #define POWERPC_INSNS_970    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
5973                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
5974                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
5975                               PPC_FLOAT_STFIWX |                              \
5976                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
5977                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
5978                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
5979                               PPC_64B | PPC_ALTIVEC |                         \
5980                               PPC_SEGMENT_64B | PPC_SLBI)
5981 #define POWERPC_MSRM_970     (0x900000000204FF36ULL)
5982 #define POWERPC_MMU_970      (POWERPC_MMU_64B)
5983 //#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
5984 #define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
5985 #define POWERPC_BFDM_970     (bfd_mach_ppc64)
5986 #define POWERPC_FLAG_970     (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
5987                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
5988                               POWERPC_FLAG_BUS_CLK)
5989
5990 #if defined(CONFIG_USER_ONLY)
5991 #define POWERPC970_HID5_INIT 0x00000080
5992 #else
5993 #define POWERPC970_HID5_INIT 0x00000000
5994 #endif
5995
5996 static int check_pow_970 (CPUPPCState *env)
5997 {
5998     if (env->spr[SPR_HID0] & 0x00600000)
5999         return 1;
6000
6001     return 0;
6002 }
6003
6004 static void init_proc_970 (CPUPPCState *env)
6005 {
6006     gen_spr_ne_601(env);
6007     gen_spr_7xx(env);
6008     /* Time base */
6009     gen_tbl(env);
6010     /* Hardware implementation registers */
6011     /* XXX : not implemented */
6012     spr_register(env, SPR_HID0, "HID0",
6013                  SPR_NOACCESS, SPR_NOACCESS,
6014                  &spr_read_generic, &spr_write_clear,
6015                  0x60000000);
6016     /* XXX : not implemented */
6017     spr_register(env, SPR_HID1, "HID1",
6018                  SPR_NOACCESS, SPR_NOACCESS,
6019                  &spr_read_generic, &spr_write_generic,
6020                  0x00000000);
6021     /* XXX : not implemented */
6022     spr_register(env, SPR_750FX_HID2, "HID2",
6023                  SPR_NOACCESS, SPR_NOACCESS,
6024                  &spr_read_generic, &spr_write_generic,
6025                  0x00000000);
6026     /* XXX : not implemented */
6027     spr_register(env, SPR_970_HID5, "HID5",
6028                  SPR_NOACCESS, SPR_NOACCESS,
6029                  &spr_read_generic, &spr_write_generic,
6030                  POWERPC970_HID5_INIT);
6031     /* XXX : not implemented */
6032     spr_register(env, SPR_L2CR, "L2CR",
6033                  SPR_NOACCESS, SPR_NOACCESS,
6034                  &spr_read_generic, &spr_write_generic,
6035                  0x00000000);
6036     /* Memory management */
6037     /* XXX: not correct */
6038     gen_low_BATs(env);
6039     /* XXX : not implemented */
6040     spr_register(env, SPR_MMUCFG, "MMUCFG",
6041                  SPR_NOACCESS, SPR_NOACCESS,
6042                  &spr_read_generic, SPR_NOACCESS,
6043                  0x00000000); /* TOFIX */
6044     /* XXX : not implemented */
6045     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6046                  SPR_NOACCESS, SPR_NOACCESS,
6047                  &spr_read_generic, &spr_write_generic,
6048                  0x00000000); /* TOFIX */
6049     spr_register(env, SPR_HIOR, "SPR_HIOR",
6050                  SPR_NOACCESS, SPR_NOACCESS,
6051                  &spr_read_hior, &spr_write_hior,
6052                  0x00000000);
6053 #if !defined(CONFIG_USER_ONLY)
6054     env->slb_nr = 32;
6055 #endif
6056     init_excp_970(env);
6057     env->dcache_line_size = 128;
6058     env->icache_line_size = 128;
6059     /* Allocate hardware IRQ controller */
6060     ppc970_irq_init(env);
6061     /* Can't find information on what this should be on reset.  This
6062      * value is the one used by 74xx processors. */
6063     vscr_init(env, 0x00010000);
6064 }
6065
6066 /* PowerPC 970FX (aka G5)                                                    */
6067 #define POWERPC_INSNS_970FX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6068                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6069                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6070                               PPC_FLOAT_STFIWX |                              \
6071                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6072                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6073                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6074                               PPC_64B | PPC_ALTIVEC |                         \
6075                               PPC_SEGMENT_64B | PPC_SLBI)
6076 #define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
6077 #define POWERPC_MMU_970FX    (POWERPC_MMU_64B)
6078 #define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
6079 #define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
6080 #define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
6081 #define POWERPC_FLAG_970FX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6082                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6083                               POWERPC_FLAG_BUS_CLK)
6084
6085 static int check_pow_970FX (CPUPPCState *env)
6086 {
6087     if (env->spr[SPR_HID0] & 0x00600000)
6088         return 1;
6089
6090     return 0;
6091 }
6092
6093 static void init_proc_970FX (CPUPPCState *env)
6094 {
6095     gen_spr_ne_601(env);
6096     gen_spr_7xx(env);
6097     /* Time base */
6098     gen_tbl(env);
6099     /* Hardware implementation registers */
6100     /* XXX : not implemented */
6101     spr_register(env, SPR_HID0, "HID0",
6102                  SPR_NOACCESS, SPR_NOACCESS,
6103                  &spr_read_generic, &spr_write_clear,
6104                  0x60000000);
6105     /* XXX : not implemented */
6106     spr_register(env, SPR_HID1, "HID1",
6107                  SPR_NOACCESS, SPR_NOACCESS,
6108                  &spr_read_generic, &spr_write_generic,
6109                  0x00000000);
6110     /* XXX : not implemented */
6111     spr_register(env, SPR_750FX_HID2, "HID2",
6112                  SPR_NOACCESS, SPR_NOACCESS,
6113                  &spr_read_generic, &spr_write_generic,
6114                  0x00000000);
6115     /* XXX : not implemented */
6116     spr_register(env, SPR_970_HID5, "HID5",
6117                  SPR_NOACCESS, SPR_NOACCESS,
6118                  &spr_read_generic, &spr_write_generic,
6119                  POWERPC970_HID5_INIT);
6120     /* XXX : not implemented */
6121     spr_register(env, SPR_L2CR, "L2CR",
6122                  SPR_NOACCESS, SPR_NOACCESS,
6123                  &spr_read_generic, &spr_write_generic,
6124                  0x00000000);
6125     /* Memory management */
6126     /* XXX: not correct */
6127     gen_low_BATs(env);
6128     /* XXX : not implemented */
6129     spr_register(env, SPR_MMUCFG, "MMUCFG",
6130                  SPR_NOACCESS, SPR_NOACCESS,
6131                  &spr_read_generic, SPR_NOACCESS,
6132                  0x00000000); /* TOFIX */
6133     /* XXX : not implemented */
6134     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6135                  SPR_NOACCESS, SPR_NOACCESS,
6136                  &spr_read_generic, &spr_write_generic,
6137                  0x00000000); /* TOFIX */
6138     spr_register(env, SPR_HIOR, "SPR_HIOR",
6139                  SPR_NOACCESS, SPR_NOACCESS,
6140                  &spr_read_hior, &spr_write_hior,
6141                  0x00000000);
6142     spr_register(env, SPR_CTRL, "SPR_CTRL",
6143                  SPR_NOACCESS, SPR_NOACCESS,
6144                  &spr_read_generic, &spr_write_generic,
6145                  0x00000000);
6146     spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6147                  SPR_NOACCESS, SPR_NOACCESS,
6148                  &spr_read_generic, &spr_write_generic,
6149                  0x00000000);
6150     spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6151                  &spr_read_generic, &spr_write_generic,
6152                  &spr_read_generic, &spr_write_generic,
6153                  0x00000000);
6154 #if !defined(CONFIG_USER_ONLY)
6155     env->slb_nr = 64;
6156 #endif
6157     init_excp_970(env);
6158     env->dcache_line_size = 128;
6159     env->icache_line_size = 128;
6160     /* Allocate hardware IRQ controller */
6161     ppc970_irq_init(env);
6162     /* Can't find information on what this should be on reset.  This
6163      * value is the one used by 74xx processors. */
6164     vscr_init(env, 0x00010000);
6165 }
6166
6167 /* PowerPC 970 GX                                                            */
6168 #define POWERPC_INSNS_970GX  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6169                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6170                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6171                               PPC_FLOAT_STFIWX |                              \
6172                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6173                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6174                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6175                               PPC_64B | PPC_ALTIVEC |                         \
6176                               PPC_SEGMENT_64B | PPC_SLBI)
6177 #define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
6178 #define POWERPC_MMU_970GX    (POWERPC_MMU_64B)
6179 #define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
6180 #define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
6181 #define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
6182 #define POWERPC_FLAG_970GX   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6183                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6184                               POWERPC_FLAG_BUS_CLK)
6185
6186 static int check_pow_970GX (CPUPPCState *env)
6187 {
6188     if (env->spr[SPR_HID0] & 0x00600000)
6189         return 1;
6190
6191     return 0;
6192 }
6193
6194 static void init_proc_970GX (CPUPPCState *env)
6195 {
6196     gen_spr_ne_601(env);
6197     gen_spr_7xx(env);
6198     /* Time base */
6199     gen_tbl(env);
6200     /* Hardware implementation registers */
6201     /* XXX : not implemented */
6202     spr_register(env, SPR_HID0, "HID0",
6203                  SPR_NOACCESS, SPR_NOACCESS,
6204                  &spr_read_generic, &spr_write_clear,
6205                  0x60000000);
6206     /* XXX : not implemented */
6207     spr_register(env, SPR_HID1, "HID1",
6208                  SPR_NOACCESS, SPR_NOACCESS,
6209                  &spr_read_generic, &spr_write_generic,
6210                  0x00000000);
6211     /* XXX : not implemented */
6212     spr_register(env, SPR_750FX_HID2, "HID2",
6213                  SPR_NOACCESS, SPR_NOACCESS,
6214                  &spr_read_generic, &spr_write_generic,
6215                  0x00000000);
6216     /* XXX : not implemented */
6217     spr_register(env, SPR_970_HID5, "HID5",
6218                  SPR_NOACCESS, SPR_NOACCESS,
6219                  &spr_read_generic, &spr_write_generic,
6220                  POWERPC970_HID5_INIT);
6221     /* XXX : not implemented */
6222     spr_register(env, SPR_L2CR, "L2CR",
6223                  SPR_NOACCESS, SPR_NOACCESS,
6224                  &spr_read_generic, &spr_write_generic,
6225                  0x00000000);
6226     /* Memory management */
6227     /* XXX: not correct */
6228     gen_low_BATs(env);
6229     /* XXX : not implemented */
6230     spr_register(env, SPR_MMUCFG, "MMUCFG",
6231                  SPR_NOACCESS, SPR_NOACCESS,
6232                  &spr_read_generic, SPR_NOACCESS,
6233                  0x00000000); /* TOFIX */
6234     /* XXX : not implemented */
6235     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6236                  SPR_NOACCESS, SPR_NOACCESS,
6237                  &spr_read_generic, &spr_write_generic,
6238                  0x00000000); /* TOFIX */
6239     spr_register(env, SPR_HIOR, "SPR_HIOR",
6240                  SPR_NOACCESS, SPR_NOACCESS,
6241                  &spr_read_hior, &spr_write_hior,
6242                  0x00000000);
6243 #if !defined(CONFIG_USER_ONLY)
6244     env->slb_nr = 32;
6245 #endif
6246     init_excp_970(env);
6247     env->dcache_line_size = 128;
6248     env->icache_line_size = 128;
6249     /* Allocate hardware IRQ controller */
6250     ppc970_irq_init(env);
6251     /* Can't find information on what this should be on reset.  This
6252      * value is the one used by 74xx processors. */
6253     vscr_init(env, 0x00010000);
6254 }
6255
6256 /* PowerPC 970 MP                                                            */
6257 #define POWERPC_INSNS_970MP  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6258                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6259                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6260                               PPC_FLOAT_STFIWX |                              \
6261                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6262                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6263                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6264                               PPC_64B | PPC_ALTIVEC |                         \
6265                               PPC_SEGMENT_64B | PPC_SLBI)
6266 #define POWERPC_MSRM_970MP   (0x900000000204FF36ULL)
6267 #define POWERPC_MMU_970MP    (POWERPC_MMU_64B)
6268 #define POWERPC_EXCP_970MP   (POWERPC_EXCP_970)
6269 #define POWERPC_INPUT_970MP  (PPC_FLAGS_INPUT_970)
6270 #define POWERPC_BFDM_970MP   (bfd_mach_ppc64)
6271 #define POWERPC_FLAG_970MP   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6272                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6273                               POWERPC_FLAG_BUS_CLK)
6274
6275 static int check_pow_970MP (CPUPPCState *env)
6276 {
6277     if (env->spr[SPR_HID0] & 0x01C00000)
6278         return 1;
6279
6280     return 0;
6281 }
6282
6283 static void init_proc_970MP (CPUPPCState *env)
6284 {
6285     gen_spr_ne_601(env);
6286     gen_spr_7xx(env);
6287     /* Time base */
6288     gen_tbl(env);
6289     /* Hardware implementation registers */
6290     /* XXX : not implemented */
6291     spr_register(env, SPR_HID0, "HID0",
6292                  SPR_NOACCESS, SPR_NOACCESS,
6293                  &spr_read_generic, &spr_write_clear,
6294                  0x60000000);
6295     /* XXX : not implemented */
6296     spr_register(env, SPR_HID1, "HID1",
6297                  SPR_NOACCESS, SPR_NOACCESS,
6298                  &spr_read_generic, &spr_write_generic,
6299                  0x00000000);
6300     /* XXX : not implemented */
6301     spr_register(env, SPR_750FX_HID2, "HID2",
6302                  SPR_NOACCESS, SPR_NOACCESS,
6303                  &spr_read_generic, &spr_write_generic,
6304                  0x00000000);
6305     /* XXX : not implemented */
6306     spr_register(env, SPR_970_HID5, "HID5",
6307                  SPR_NOACCESS, SPR_NOACCESS,
6308                  &spr_read_generic, &spr_write_generic,
6309                  POWERPC970_HID5_INIT);
6310     /* XXX : not implemented */
6311     spr_register(env, SPR_L2CR, "L2CR",
6312                  SPR_NOACCESS, SPR_NOACCESS,
6313                  &spr_read_generic, &spr_write_generic,
6314                  0x00000000);
6315     /* Memory management */
6316     /* XXX: not correct */
6317     gen_low_BATs(env);
6318     /* XXX : not implemented */
6319     spr_register(env, SPR_MMUCFG, "MMUCFG",
6320                  SPR_NOACCESS, SPR_NOACCESS,
6321                  &spr_read_generic, SPR_NOACCESS,
6322                  0x00000000); /* TOFIX */
6323     /* XXX : not implemented */
6324     spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6325                  SPR_NOACCESS, SPR_NOACCESS,
6326                  &spr_read_generic, &spr_write_generic,
6327                  0x00000000); /* TOFIX */
6328     spr_register(env, SPR_HIOR, "SPR_HIOR",
6329                  SPR_NOACCESS, SPR_NOACCESS,
6330                  &spr_read_hior, &spr_write_hior,
6331                  0x00000000);
6332 #if !defined(CONFIG_USER_ONLY)
6333     env->slb_nr = 32;
6334 #endif
6335     init_excp_970(env);
6336     env->dcache_line_size = 128;
6337     env->icache_line_size = 128;
6338     /* Allocate hardware IRQ controller */
6339     ppc970_irq_init(env);
6340     /* Can't find information on what this should be on reset.  This
6341      * value is the one used by 74xx processors. */
6342     vscr_init(env, 0x00010000);
6343 }
6344
6345 #if defined(TARGET_PPC64)
6346 /* POWER7 */
6347 #define POWERPC_INSNS_POWER7  (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6348                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6349                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6350                               PPC_FLOAT_STFIWX |                              \
6351                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT |  \
6352                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6353                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6354                               PPC_64B | PPC_ALTIVEC |                         \
6355                               PPC_SEGMENT_64B | PPC_SLBI |                    \
6356                               PPC_POPCNTB | PPC_POPCNTWD)
6357 #define POWERPC_MSRM_POWER7   (0x800000000204FF36ULL)
6358 #define POWERPC_MMU_POWER7    (POWERPC_MMU_2_06)
6359 #define POWERPC_EXCP_POWER7   (POWERPC_EXCP_POWER7)
6360 #define POWERPC_INPUT_POWER7  (PPC_FLAGS_INPUT_POWER7)
6361 #define POWERPC_BFDM_POWER7   (bfd_mach_ppc64)
6362 #define POWERPC_FLAG_POWER7   (POWERPC_FLAG_VRE | POWERPC_FLAG_SE |            \
6363                               POWERPC_FLAG_BE | POWERPC_FLAG_PMM |            \
6364                               POWERPC_FLAG_BUS_CLK)
6365 #define check_pow_POWER7    check_pow_nocheck
6366
6367 static void init_proc_POWER7 (CPUPPCState *env)
6368 {
6369     gen_spr_ne_601(env);
6370     gen_spr_7xx(env);
6371     /* Time base */
6372     gen_tbl(env);
6373 #if !defined(CONFIG_USER_ONLY)
6374     /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6375     spr_register(env, SPR_PURR,   "PURR",
6376                  &spr_read_purr, SPR_NOACCESS,
6377                  &spr_read_purr, SPR_NOACCESS,
6378                  0x00000000);
6379     spr_register(env, SPR_SPURR,   "SPURR",
6380                  &spr_read_purr, SPR_NOACCESS,
6381                  &spr_read_purr, SPR_NOACCESS,
6382                  0x00000000);
6383 #endif /* !CONFIG_USER_ONLY */
6384     /* Memory management */
6385     /* XXX : not implemented */
6386     spr_register(env, SPR_MMUCFG, "MMUCFG",
6387                  SPR_NOACCESS, SPR_NOACCESS,
6388                  &spr_read_generic, SPR_NOACCESS,
6389                  0x00000000); /* TOFIX */
6390     /* XXX : not implemented */
6391     spr_register(env, SPR_CTRL, "SPR_CTRLT",
6392                  SPR_NOACCESS, SPR_NOACCESS,
6393                  &spr_read_generic, &spr_write_generic,
6394                  0x80800000);
6395     spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6396                  SPR_NOACCESS, SPR_NOACCESS,
6397                  &spr_read_generic, &spr_write_generic,
6398                  0x80800000);
6399     spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6400                  &spr_read_generic, &spr_write_generic,
6401                  &spr_read_generic, &spr_write_generic,
6402                  0x00000000);
6403 #if !defined(CONFIG_USER_ONLY)
6404     env->slb_nr = 32;
6405 #endif
6406     init_excp_POWER7(env);
6407     env->dcache_line_size = 128;
6408     env->icache_line_size = 128;
6409     /* Allocate hardware IRQ controller */
6410     ppcPOWER7_irq_init(env);
6411     /* Can't find information on what this should be on reset.  This
6412      * value is the one used by 74xx processors. */
6413     vscr_init(env, 0x00010000);
6414 }
6415 #endif /* TARGET_PPC64 */
6416
6417 /* PowerPC 620                                                               */
6418 #define POWERPC_INSNS_620    (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |        \
6419                               PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |   \
6420                               PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |           \
6421                               PPC_FLOAT_STFIWX |                              \
6422                               PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |   \
6423                               PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
6424                               PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |               \
6425                               PPC_SEGMENT | PPC_EXTERN |                      \
6426                               PPC_64B | PPC_SLBI)
6427 #define POWERPC_MSRM_620     (0x800000000005FF77ULL)
6428 //#define POWERPC_MMU_620      (POWERPC_MMU_620)
6429 #define POWERPC_EXCP_620     (POWERPC_EXCP_970)
6430 #define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_6xx)
6431 #define POWERPC_BFDM_620     (bfd_mach_ppc64)
6432 #define POWERPC_FLAG_620     (POWERPC_FLAG_SE | POWERPC_FLAG_BE |            \
6433                               POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
6434 #define check_pow_620        check_pow_nocheck /* Check this */
6435
6436 __attribute__ (( unused ))
6437 static void init_proc_620 (CPUPPCState *env)
6438 {
6439     gen_spr_ne_601(env);
6440     gen_spr_620(env);
6441     /* Time base */
6442     gen_tbl(env);
6443     /* Hardware implementation registers */
6444     /* XXX : not implemented */
6445     spr_register(env, SPR_HID0, "HID0",
6446                  SPR_NOACCESS, SPR_NOACCESS,
6447                  &spr_read_generic, &spr_write_generic,
6448                  0x00000000);
6449     /* Memory management */
6450     gen_low_BATs(env);
6451     init_excp_620(env);
6452     env->dcache_line_size = 64;
6453     env->icache_line_size = 64;
6454     /* Allocate hardware IRQ controller */
6455     ppc6xx_irq_init(env);
6456 }
6457 #endif /* defined (TARGET_PPC64) */
6458
6459 /* Default 32 bits PowerPC target will be 604 */
6460 #define CPU_POWERPC_PPC32     CPU_POWERPC_604
6461 #define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
6462 #define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
6463 #define POWERPC_MMU_PPC32     POWERPC_MMU_604
6464 #define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
6465 #define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
6466 #define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
6467 #define POWERPC_FLAG_PPC32    POWERPC_FLAG_604
6468 #define check_pow_PPC32       check_pow_604
6469 #define init_proc_PPC32       init_proc_604
6470
6471 /* Default 64 bits PowerPC target will be 970 FX */
6472 #define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
6473 #define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
6474 #define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
6475 #define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
6476 #define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
6477 #define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
6478 #define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
6479 #define POWERPC_FLAG_PPC64    POWERPC_FLAG_970FX
6480 #define check_pow_PPC64       check_pow_970FX
6481 #define init_proc_PPC64       init_proc_970FX
6482
6483 /* Default PowerPC target will be PowerPC 32 */
6484 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6485 #define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC64
6486 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6487 #define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC64
6488 #define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC64
6489 #define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC64
6490 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6491 #define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC64
6492 #define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC64
6493 #define check_pow_DEFAULT     check_pow_PPC64
6494 #define init_proc_DEFAULT     init_proc_PPC64
6495 #else
6496 #define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC32
6497 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6498 #define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC32
6499 #define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC32
6500 #define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC32
6501 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6502 #define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC32
6503 #define POWERPC_FLAG_DEFAULT  POWERPC_FLAG_PPC32
6504 #define check_pow_DEFAULT     check_pow_PPC32
6505 #define init_proc_DEFAULT     init_proc_PPC32
6506 #endif
6507
6508 /*****************************************************************************/
6509 /* PVR definitions for most known PowerPC                                    */
6510 enum {
6511     /* PowerPC 401 family */
6512     /* Generic PowerPC 401 */
6513 #define CPU_POWERPC_401              CPU_POWERPC_401G2
6514     /* PowerPC 401 cores */
6515     CPU_POWERPC_401A1              = 0x00210000,
6516     CPU_POWERPC_401B2              = 0x00220000,
6517 #if 0
6518     CPU_POWERPC_401B3              = xxx,
6519 #endif
6520     CPU_POWERPC_401C2              = 0x00230000,
6521     CPU_POWERPC_401D2              = 0x00240000,
6522     CPU_POWERPC_401E2              = 0x00250000,
6523     CPU_POWERPC_401F2              = 0x00260000,
6524     CPU_POWERPC_401G2              = 0x00270000,
6525     /* PowerPC 401 microcontrolers */
6526 #if 0
6527     CPU_POWERPC_401GF              = xxx,
6528 #endif
6529 #define CPU_POWERPC_IOP480           CPU_POWERPC_401B2
6530     /* IBM Processor for Network Resources */
6531     CPU_POWERPC_COBRA              = 0x10100000, /* XXX: 405 ? */
6532 #if 0
6533     CPU_POWERPC_XIPCHIP            = xxx,
6534 #endif
6535     /* PowerPC 403 family */
6536     /* Generic PowerPC 403 */
6537 #define CPU_POWERPC_403              CPU_POWERPC_403GC
6538     /* PowerPC 403 microcontrollers */
6539     CPU_POWERPC_403GA              = 0x00200011,
6540     CPU_POWERPC_403GB              = 0x00200100,
6541     CPU_POWERPC_403GC              = 0x00200200,
6542     CPU_POWERPC_403GCX             = 0x00201400,
6543 #if 0
6544     CPU_POWERPC_403GP              = xxx,
6545 #endif
6546     /* PowerPC 405 family */
6547     /* Generic PowerPC 405 */
6548 #define CPU_POWERPC_405              CPU_POWERPC_405D4
6549     /* PowerPC 405 cores */
6550 #if 0
6551     CPU_POWERPC_405A3              = xxx,
6552 #endif
6553 #if 0
6554     CPU_POWERPC_405A4              = xxx,
6555 #endif
6556 #if 0
6557     CPU_POWERPC_405B3              = xxx,
6558 #endif
6559 #if 0
6560     CPU_POWERPC_405B4              = xxx,
6561 #endif
6562 #if 0
6563     CPU_POWERPC_405C3              = xxx,
6564 #endif
6565 #if 0
6566     CPU_POWERPC_405C4              = xxx,
6567 #endif
6568     CPU_POWERPC_405D2              = 0x20010000,
6569 #if 0
6570     CPU_POWERPC_405D3              = xxx,
6571 #endif
6572     CPU_POWERPC_405D4              = 0x41810000,
6573 #if 0
6574     CPU_POWERPC_405D5              = xxx,
6575 #endif
6576 #if 0
6577     CPU_POWERPC_405E4              = xxx,
6578 #endif
6579 #if 0
6580     CPU_POWERPC_405F4              = xxx,
6581 #endif
6582 #if 0
6583     CPU_POWERPC_405F5              = xxx,
6584 #endif
6585 #if 0
6586     CPU_POWERPC_405F6              = xxx,
6587 #endif
6588     /* PowerPC 405 microcontrolers */
6589     /* XXX: missing 0x200108a0 */
6590 #define CPU_POWERPC_405CR            CPU_POWERPC_405CRc
6591     CPU_POWERPC_405CRa             = 0x40110041,
6592     CPU_POWERPC_405CRb             = 0x401100C5,
6593     CPU_POWERPC_405CRc             = 0x40110145,
6594     CPU_POWERPC_405EP              = 0x51210950,
6595 #if 0
6596     CPU_POWERPC_405EXr             = xxx,
6597 #endif
6598     CPU_POWERPC_405EZ              = 0x41511460, /* 0x51210950 ? */
6599 #if 0
6600     CPU_POWERPC_405FX              = xxx,
6601 #endif
6602 #define CPU_POWERPC_405GP            CPU_POWERPC_405GPd
6603     CPU_POWERPC_405GPa             = 0x40110000,
6604     CPU_POWERPC_405GPb             = 0x40110040,
6605     CPU_POWERPC_405GPc             = 0x40110082,
6606     CPU_POWERPC_405GPd             = 0x401100C4,
6607 #define CPU_POWERPC_405GPe           CPU_POWERPC_405CRc
6608     CPU_POWERPC_405GPR             = 0x50910951,
6609 #if 0
6610     CPU_POWERPC_405H               = xxx,
6611 #endif
6612 #if 0
6613     CPU_POWERPC_405L               = xxx,
6614 #endif
6615     CPU_POWERPC_405LP              = 0x41F10000,
6616 #if 0
6617     CPU_POWERPC_405PM              = xxx,
6618 #endif
6619 #if 0
6620     CPU_POWERPC_405PS              = xxx,
6621 #endif
6622 #if 0
6623     CPU_POWERPC_405S               = xxx,
6624 #endif
6625     /* IBM network processors */
6626     CPU_POWERPC_NPE405H            = 0x414100C0,
6627     CPU_POWERPC_NPE405H2           = 0x41410140,
6628     CPU_POWERPC_NPE405L            = 0x416100C0,
6629     CPU_POWERPC_NPE4GS3            = 0x40B10000,
6630 #if 0
6631     CPU_POWERPC_NPCxx1             = xxx,
6632 #endif
6633 #if 0
6634     CPU_POWERPC_NPR161             = xxx,
6635 #endif
6636 #if 0
6637     CPU_POWERPC_LC77700            = xxx,
6638 #endif
6639     /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6640 #if 0
6641     CPU_POWERPC_STB01000           = xxx,
6642 #endif
6643 #if 0
6644     CPU_POWERPC_STB01010           = xxx,
6645 #endif
6646 #if 0
6647     CPU_POWERPC_STB0210            = xxx, /* 401B3 */
6648 #endif
6649     CPU_POWERPC_STB03              = 0x40310000, /* 0x40130000 ? */
6650 #if 0
6651     CPU_POWERPC_STB043             = xxx,
6652 #endif
6653 #if 0
6654     CPU_POWERPC_STB045             = xxx,
6655 #endif
6656     CPU_POWERPC_STB04              = 0x41810000,
6657     CPU_POWERPC_STB25              = 0x51510950,
6658 #if 0
6659     CPU_POWERPC_STB130             = xxx,
6660 #endif
6661     /* Xilinx cores */
6662     CPU_POWERPC_X2VP4              = 0x20010820,
6663 #define CPU_POWERPC_X2VP7            CPU_POWERPC_X2VP4
6664     CPU_POWERPC_X2VP20             = 0x20010860,
6665 #define CPU_POWERPC_X2VP50           CPU_POWERPC_X2VP20
6666 #if 0
6667     CPU_POWERPC_ZL10310            = xxx,
6668 #endif
6669 #if 0
6670     CPU_POWERPC_ZL10311            = xxx,
6671 #endif
6672 #if 0
6673     CPU_POWERPC_ZL10320            = xxx,
6674 #endif
6675 #if 0
6676     CPU_POWERPC_ZL10321            = xxx,
6677 #endif
6678     /* PowerPC 440 family */
6679     /* Generic PowerPC 440 */
6680 #define CPU_POWERPC_440              CPU_POWERPC_440GXf
6681     /* PowerPC 440 cores */
6682 #if 0
6683     CPU_POWERPC_440A4              = xxx,
6684 #endif
6685     CPU_POWERPC_440_XILINX         = 0x7ff21910,
6686 #if 0
6687     CPU_POWERPC_440A5              = xxx,
6688 #endif
6689 #if 0
6690     CPU_POWERPC_440B4              = xxx,
6691 #endif
6692 #if 0
6693     CPU_POWERPC_440F5              = xxx,
6694 #endif
6695 #if 0
6696     CPU_POWERPC_440G5              = xxx,
6697 #endif
6698 #if 0
6699     CPU_POWERPC_440H4              = xxx,
6700 #endif
6701 #if 0
6702     CPU_POWERPC_440H6              = xxx,
6703 #endif
6704     /* PowerPC 440 microcontrolers */
6705 #define CPU_POWERPC_440EP            CPU_POWERPC_440EPb
6706     CPU_POWERPC_440EPa             = 0x42221850,
6707     CPU_POWERPC_440EPb             = 0x422218D3,
6708 #define CPU_POWERPC_440GP            CPU_POWERPC_440GPc
6709     CPU_POWERPC_440GPb             = 0x40120440,
6710     CPU_POWERPC_440GPc             = 0x40120481,
6711 #define CPU_POWERPC_440GR            CPU_POWERPC_440GRa
6712 #define CPU_POWERPC_440GRa           CPU_POWERPC_440EPb
6713     CPU_POWERPC_440GRX             = 0x200008D0,
6714 #define CPU_POWERPC_440EPX           CPU_POWERPC_440GRX
6715 #define CPU_POWERPC_440GX            CPU_POWERPC_440GXf
6716     CPU_POWERPC_440GXa             = 0x51B21850,
6717     CPU_POWERPC_440GXb             = 0x51B21851,
6718     CPU_POWERPC_440GXc             = 0x51B21892,
6719     CPU_POWERPC_440GXf             = 0x51B21894,
6720 #if 0
6721     CPU_POWERPC_440S               = xxx,
6722 #endif
6723     CPU_POWERPC_440SP              = 0x53221850,
6724     CPU_POWERPC_440SP2             = 0x53221891,
6725     CPU_POWERPC_440SPE             = 0x53421890,
6726     /* PowerPC 460 family */
6727 #if 0
6728     /* Generic PowerPC 464 */
6729 #define CPU_POWERPC_464              CPU_POWERPC_464H90
6730 #endif
6731     /* PowerPC 464 microcontrolers */
6732 #if 0
6733     CPU_POWERPC_464H90             = xxx,
6734 #endif
6735 #if 0
6736     CPU_POWERPC_464H90FP           = xxx,
6737 #endif
6738     /* Freescale embedded PowerPC cores */
6739     /* PowerPC MPC 5xx cores (aka RCPU) */
6740     CPU_POWERPC_MPC5xx             = 0x00020020,
6741 #define CPU_POWERPC_MGT560           CPU_POWERPC_MPC5xx
6742 #define CPU_POWERPC_MPC509           CPU_POWERPC_MPC5xx
6743 #define CPU_POWERPC_MPC533           CPU_POWERPC_MPC5xx
6744 #define CPU_POWERPC_MPC534           CPU_POWERPC_MPC5xx
6745 #define CPU_POWERPC_MPC555           CPU_POWERPC_MPC5xx
6746 #define CPU_POWERPC_MPC556           CPU_POWERPC_MPC5xx
6747 #define CPU_POWERPC_MPC560           CPU_POWERPC_MPC5xx
6748 #define CPU_POWERPC_MPC561           CPU_POWERPC_MPC5xx
6749 #define CPU_POWERPC_MPC562           CPU_POWERPC_MPC5xx
6750 #define CPU_POWERPC_MPC563           CPU_POWERPC_MPC5xx
6751 #define CPU_POWERPC_MPC564           CPU_POWERPC_MPC5xx
6752 #define CPU_POWERPC_MPC565           CPU_POWERPC_MPC5xx
6753 #define CPU_POWERPC_MPC566           CPU_POWERPC_MPC5xx
6754     /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6755     CPU_POWERPC_MPC8xx             = 0x00500000,
6756 #define CPU_POWERPC_MGT823           CPU_POWERPC_MPC8xx
6757 #define CPU_POWERPC_MPC821           CPU_POWERPC_MPC8xx
6758 #define CPU_POWERPC_MPC823           CPU_POWERPC_MPC8xx
6759 #define CPU_POWERPC_MPC850           CPU_POWERPC_MPC8xx
6760 #define CPU_POWERPC_MPC852T          CPU_POWERPC_MPC8xx
6761 #define CPU_POWERPC_MPC855T          CPU_POWERPC_MPC8xx
6762 #define CPU_POWERPC_MPC857           CPU_POWERPC_MPC8xx
6763 #define CPU_POWERPC_MPC859           CPU_POWERPC_MPC8xx
6764 #define CPU_POWERPC_MPC860           CPU_POWERPC_MPC8xx
6765 #define CPU_POWERPC_MPC862           CPU_POWERPC_MPC8xx
6766 #define CPU_POWERPC_MPC866           CPU_POWERPC_MPC8xx
6767 #define CPU_POWERPC_MPC870           CPU_POWERPC_MPC8xx
6768 #define CPU_POWERPC_MPC875           CPU_POWERPC_MPC8xx
6769 #define CPU_POWERPC_MPC880           CPU_POWERPC_MPC8xx
6770 #define CPU_POWERPC_MPC885           CPU_POWERPC_MPC8xx
6771     /* G2 cores (aka PowerQUICC-II) */
6772     CPU_POWERPC_G2                 = 0x00810011,
6773     CPU_POWERPC_G2H4               = 0x80811010,
6774     CPU_POWERPC_G2gp               = 0x80821010,
6775     CPU_POWERPC_G2ls               = 0x90810010,
6776     CPU_POWERPC_MPC603             = 0x00810100,
6777     CPU_POWERPC_G2_HIP3            = 0x00810101,
6778     CPU_POWERPC_G2_HIP4            = 0x80811014,
6779     /*   G2_LE core (aka PowerQUICC-II) */
6780     CPU_POWERPC_G2LE               = 0x80820010,
6781     CPU_POWERPC_G2LEgp             = 0x80822010,
6782     CPU_POWERPC_G2LEls             = 0xA0822010,
6783     CPU_POWERPC_G2LEgp1            = 0x80822011,
6784     CPU_POWERPC_G2LEgp3            = 0x80822013,
6785     /* MPC52xx microcontrollers  */
6786     /* XXX: MPC 5121 ? */
6787 #define CPU_POWERPC_MPC52xx          CPU_POWERPC_MPC5200
6788 #define CPU_POWERPC_MPC5200          CPU_POWERPC_MPC5200_v12
6789 #define CPU_POWERPC_MPC5200_v10      CPU_POWERPC_G2LEgp1
6790 #define CPU_POWERPC_MPC5200_v11      CPU_POWERPC_G2LEgp1
6791 #define CPU_POWERPC_MPC5200_v12      CPU_POWERPC_G2LEgp1
6792 #define CPU_POWERPC_MPC5200B         CPU_POWERPC_MPC5200B_v21
6793 #define CPU_POWERPC_MPC5200B_v20     CPU_POWERPC_G2LEgp1
6794 #define CPU_POWERPC_MPC5200B_v21     CPU_POWERPC_G2LEgp1
6795     /* MPC82xx microcontrollers */
6796 #define CPU_POWERPC_MPC82xx          CPU_POWERPC_MPC8280
6797 #define CPU_POWERPC_MPC8240          CPU_POWERPC_MPC603
6798 #define CPU_POWERPC_MPC8241          CPU_POWERPC_G2_HIP4
6799 #define CPU_POWERPC_MPC8245          CPU_POWERPC_G2_HIP4
6800 #define CPU_POWERPC_MPC8247          CPU_POWERPC_G2LEgp3
6801 #define CPU_POWERPC_MPC8248          CPU_POWERPC_G2LEgp3
6802 #define CPU_POWERPC_MPC8250          CPU_POWERPC_MPC8250_HiP4
6803 #define CPU_POWERPC_MPC8250_HiP3     CPU_POWERPC_G2_HIP3
6804 #define CPU_POWERPC_MPC8250_HiP4     CPU_POWERPC_G2_HIP4
6805 #define CPU_POWERPC_MPC8255          CPU_POWERPC_MPC8255_HiP4
6806 #define CPU_POWERPC_MPC8255_HiP3     CPU_POWERPC_G2_HIP3
6807 #define CPU_POWERPC_MPC8255_HiP4     CPU_POWERPC_G2_HIP4
6808 #define CPU_POWERPC_MPC8260          CPU_POWERPC_MPC8260_HiP4
6809 #define CPU_POWERPC_MPC8260_HiP3     CPU_POWERPC_G2_HIP3
6810 #define CPU_POWERPC_MPC8260_HiP4     CPU_POWERPC_G2_HIP4
6811 #define CPU_POWERPC_MPC8264          CPU_POWERPC_MPC8264_HiP4
6812 #define CPU_POWERPC_MPC8264_HiP3     CPU_POWERPC_G2_HIP3
6813 #define CPU_POWERPC_MPC8264_HiP4     CPU_POWERPC_G2_HIP4
6814 #define CPU_POWERPC_MPC8265          CPU_POWERPC_MPC8265_HiP4
6815 #define CPU_POWERPC_MPC8265_HiP3     CPU_POWERPC_G2_HIP3
6816 #define CPU_POWERPC_MPC8265_HiP4     CPU_POWERPC_G2_HIP4
6817 #define CPU_POWERPC_MPC8266          CPU_POWERPC_MPC8266_HiP4
6818 #define CPU_POWERPC_MPC8266_HiP3     CPU_POWERPC_G2_HIP3
6819 #define CPU_POWERPC_MPC8266_HiP4     CPU_POWERPC_G2_HIP4
6820 #define CPU_POWERPC_MPC8270          CPU_POWERPC_G2LEgp3
6821 #define CPU_POWERPC_MPC8271          CPU_POWERPC_G2LEgp3
6822 #define CPU_POWERPC_MPC8272          CPU_POWERPC_G2LEgp3
6823 #define CPU_POWERPC_MPC8275          CPU_POWERPC_G2LEgp3
6824 #define CPU_POWERPC_MPC8280          CPU_POWERPC_G2LEgp3
6825     /* e200 family */
6826     /* e200 cores */
6827 #define CPU_POWERPC_e200             CPU_POWERPC_e200z6
6828 #if 0
6829     CPU_POWERPC_e200z0             = xxx,
6830 #endif
6831 #if 0
6832     CPU_POWERPC_e200z1             = xxx,
6833 #endif
6834 #if 0 /* ? */
6835     CPU_POWERPC_e200z3             = 0x81120000,
6836 #endif
6837     CPU_POWERPC_e200z5             = 0x81000000,
6838     CPU_POWERPC_e200z6             = 0x81120000,
6839     /* MPC55xx microcontrollers */
6840 #define CPU_POWERPC_MPC55xx          CPU_POWERPC_MPC5567
6841 #if 0
6842 #define CPU_POWERPC_MPC5514E         CPU_POWERPC_MPC5514E_v1
6843 #define CPU_POWERPC_MPC5514E_v0      CPU_POWERPC_e200z0
6844 #define CPU_POWERPC_MPC5514E_v1      CPU_POWERPC_e200z1
6845 #define CPU_POWERPC_MPC5514G         CPU_POWERPC_MPC5514G_v1
6846 #define CPU_POWERPC_MPC5514G_v0      CPU_POWERPC_e200z0
6847 #define CPU_POWERPC_MPC5514G_v1      CPU_POWERPC_e200z1
6848 #define CPU_POWERPC_MPC5515S         CPU_POWERPC_e200z1
6849 #define CPU_POWERPC_MPC5516E         CPU_POWERPC_MPC5516E_v1
6850 #define CPU_POWERPC_MPC5516E_v0      CPU_POWERPC_e200z0
6851 #define CPU_POWERPC_MPC5516E_v1      CPU_POWERPC_e200z1
6852 #define CPU_POWERPC_MPC5516G         CPU_POWERPC_MPC5516G_v1
6853 #define CPU_POWERPC_MPC5516G_v0      CPU_POWERPC_e200z0
6854 #define CPU_POWERPC_MPC5516G_v1      CPU_POWERPC_e200z1
6855 #define CPU_POWERPC_MPC5516S         CPU_POWERPC_e200z1
6856 #endif
6857 #if 0
6858 #define CPU_POWERPC_MPC5533          CPU_POWERPC_e200z3
6859 #define CPU_POWERPC_MPC5534          CPU_POWERPC_e200z3
6860 #endif
6861 #define CPU_POWERPC_MPC5553          CPU_POWERPC_e200z6
6862 #define CPU_POWERPC_MPC5554          CPU_POWERPC_e200z6
6863 #define CPU_POWERPC_MPC5561          CPU_POWERPC_e200z6
6864 #define CPU_POWERPC_MPC5565          CPU_POWERPC_e200z6
6865 #define CPU_POWERPC_MPC5566          CPU_POWERPC_e200z6
6866 #define CPU_POWERPC_MPC5567          CPU_POWERPC_e200z6
6867     /* e300 family */
6868     /* e300 cores */
6869 #define CPU_POWERPC_e300             CPU_POWERPC_e300c3
6870     CPU_POWERPC_e300c1             = 0x00830010,
6871     CPU_POWERPC_e300c2             = 0x00840010,
6872     CPU_POWERPC_e300c3             = 0x00850010,
6873     CPU_POWERPC_e300c4             = 0x00860010,
6874     /* MPC83xx microcontrollers */
6875 #define CPU_POWERPC_MPC831x          CPU_POWERPC_e300c3
6876 #define CPU_POWERPC_MPC832x          CPU_POWERPC_e300c2
6877 #define CPU_POWERPC_MPC834x          CPU_POWERPC_e300c1
6878 #define CPU_POWERPC_MPC835x          CPU_POWERPC_e300c1
6879 #define CPU_POWERPC_MPC836x          CPU_POWERPC_e300c1
6880 #define CPU_POWERPC_MPC837x          CPU_POWERPC_e300c4
6881     /* e500 family */
6882     /* e500 cores  */
6883 #define CPU_POWERPC_e500             CPU_POWERPC_e500v2_v22
6884 #define CPU_POWERPC_e500v1           CPU_POWERPC_e500v1_v20
6885 #define CPU_POWERPC_e500v2           CPU_POWERPC_e500v2_v22
6886     CPU_POWERPC_e500v1_v10         = 0x80200010,
6887     CPU_POWERPC_e500v1_v20         = 0x80200020,
6888     CPU_POWERPC_e500v2_v10         = 0x80210010,
6889     CPU_POWERPC_e500v2_v11         = 0x80210011,
6890     CPU_POWERPC_e500v2_v20         = 0x80210020,
6891     CPU_POWERPC_e500v2_v21         = 0x80210021,
6892     CPU_POWERPC_e500v2_v22         = 0x80210022,
6893     CPU_POWERPC_e500v2_v30         = 0x80210030,
6894     /* MPC85xx microcontrollers */
6895 #define CPU_POWERPC_MPC8533          CPU_POWERPC_MPC8533_v11
6896 #define CPU_POWERPC_MPC8533_v10      CPU_POWERPC_e500v2_v21
6897 #define CPU_POWERPC_MPC8533_v11      CPU_POWERPC_e500v2_v22
6898 #define CPU_POWERPC_MPC8533E         CPU_POWERPC_MPC8533E_v11
6899 #define CPU_POWERPC_MPC8533E_v10     CPU_POWERPC_e500v2_v21
6900 #define CPU_POWERPC_MPC8533E_v11     CPU_POWERPC_e500v2_v22
6901 #define CPU_POWERPC_MPC8540          CPU_POWERPC_MPC8540_v21
6902 #define CPU_POWERPC_MPC8540_v10      CPU_POWERPC_e500v1_v10
6903 #define CPU_POWERPC_MPC8540_v20      CPU_POWERPC_e500v1_v20
6904 #define CPU_POWERPC_MPC8540_v21      CPU_POWERPC_e500v1_v20
6905 #define CPU_POWERPC_MPC8541          CPU_POWERPC_MPC8541_v11
6906 #define CPU_POWERPC_MPC8541_v10      CPU_POWERPC_e500v1_v20
6907 #define CPU_POWERPC_MPC8541_v11      CPU_POWERPC_e500v1_v20
6908 #define CPU_POWERPC_MPC8541E         CPU_POWERPC_MPC8541E_v11
6909 #define CPU_POWERPC_MPC8541E_v10     CPU_POWERPC_e500v1_v20
6910 #define CPU_POWERPC_MPC8541E_v11     CPU_POWERPC_e500v1_v20
6911 #define CPU_POWERPC_MPC8543          CPU_POWERPC_MPC8543_v21
6912 #define CPU_POWERPC_MPC8543_v10      CPU_POWERPC_e500v2_v10
6913 #define CPU_POWERPC_MPC8543_v11      CPU_POWERPC_e500v2_v11
6914 #define CPU_POWERPC_MPC8543_v20      CPU_POWERPC_e500v2_v20
6915 #define CPU_POWERPC_MPC8543_v21      CPU_POWERPC_e500v2_v21
6916 #define CPU_POWERPC_MPC8543E         CPU_POWERPC_MPC8543E_v21
6917 #define CPU_POWERPC_MPC8543E_v10     CPU_POWERPC_e500v2_v10
6918 #define CPU_POWERPC_MPC8543E_v11     CPU_POWERPC_e500v2_v11
6919 #define CPU_POWERPC_MPC8543E_v20     CPU_POWERPC_e500v2_v20
6920 #define CPU_POWERPC_MPC8543E_v21     CPU_POWERPC_e500v2_v21
6921 #define CPU_POWERPC_MPC8544          CPU_POWERPC_MPC8544_v11
6922 #define CPU_POWERPC_MPC8544_v10      CPU_POWERPC_e500v2_v21
6923 #define CPU_POWERPC_MPC8544_v11      CPU_POWERPC_e500v2_v22
6924 #define CPU_POWERPC_MPC8544E_v11     CPU_POWERPC_e500v2_v22
6925 #define CPU_POWERPC_MPC8544E         CPU_POWERPC_MPC8544E_v11
6926 #define CPU_POWERPC_MPC8544E_v10     CPU_POWERPC_e500v2_v21
6927 #define CPU_POWERPC_MPC8545          CPU_POWERPC_MPC8545_v21
6928 #define CPU_POWERPC_MPC8545_v10      CPU_POWERPC_e500v2_v10
6929 #define CPU_POWERPC_MPC8545_v20      CPU_POWERPC_e500v2_v20
6930 #define CPU_POWERPC_MPC8545_v21      CPU_POWERPC_e500v2_v21
6931 #define CPU_POWERPC_MPC8545E         CPU_POWERPC_MPC8545E_v21
6932 #define CPU_POWERPC_MPC8545E_v10     CPU_POWERPC_e500v2_v10
6933 #define CPU_POWERPC_MPC8545E_v20     CPU_POWERPC_e500v2_v20
6934 #define CPU_POWERPC_MPC8545E_v21     CPU_POWERPC_e500v2_v21
6935 #define CPU_POWERPC_MPC8547E         CPU_POWERPC_MPC8545E_v21
6936 #define CPU_POWERPC_MPC8547E_v10     CPU_POWERPC_e500v2_v10
6937 #define CPU_POWERPC_MPC8547E_v20     CPU_POWERPC_e500v2_v20
6938 #define CPU_POWERPC_MPC8547E_v21     CPU_POWERPC_e500v2_v21
6939 #define CPU_POWERPC_MPC8548          CPU_POWERPC_MPC8548_v21
6940 #define CPU_POWERPC_MPC8548_v10      CPU_POWERPC_e500v2_v10
6941 #define CPU_POWERPC_MPC8548_v11      CPU_POWERPC_e500v2_v11
6942 #define CPU_POWERPC_MPC8548_v20      CPU_POWERPC_e500v2_v20
6943 #define CPU_POWERPC_MPC8548_v21      CPU_POWERPC_e500v2_v21
6944 #define CPU_POWERPC_MPC8548E         CPU_POWERPC_MPC8548E_v21
6945 #define CPU_POWERPC_MPC8548E_v10     CPU_POWERPC_e500v2_v10
6946 #define CPU_POWERPC_MPC8548E_v11     CPU_POWERPC_e500v2_v11
6947 #define CPU_POWERPC_MPC8548E_v20     CPU_POWERPC_e500v2_v20
6948 #define CPU_POWERPC_MPC8548E_v21     CPU_POWERPC_e500v2_v21
6949 #define CPU_POWERPC_MPC8555          CPU_POWERPC_MPC8555_v11
6950 #define CPU_POWERPC_MPC8555_v10      CPU_POWERPC_e500v2_v10
6951 #define CPU_POWERPC_MPC8555_v11      CPU_POWERPC_e500v2_v11
6952 #define CPU_POWERPC_MPC8555E         CPU_POWERPC_MPC8555E_v11
6953 #define CPU_POWERPC_MPC8555E_v10     CPU_POWERPC_e500v2_v10
6954 #define CPU_POWERPC_MPC8555E_v11     CPU_POWERPC_e500v2_v11
6955 #define CPU_POWERPC_MPC8560          CPU_POWERPC_MPC8560_v21
6956 #define CPU_POWERPC_MPC8560_v10      CPU_POWERPC_e500v2_v10
6957 #define CPU_POWERPC_MPC8560_v20      CPU_POWERPC_e500v2_v20
6958 #define CPU_POWERPC_MPC8560_v21      CPU_POWERPC_e500v2_v21
6959 #define CPU_POWERPC_MPC8567          CPU_POWERPC_e500v2_v22
6960 #define CPU_POWERPC_MPC8567E         CPU_POWERPC_e500v2_v22
6961 #define CPU_POWERPC_MPC8568          CPU_POWERPC_e500v2_v22
6962 #define CPU_POWERPC_MPC8568E         CPU_POWERPC_e500v2_v22
6963 #define CPU_POWERPC_MPC8572          CPU_POWERPC_e500v2_v30
6964 #define CPU_POWERPC_MPC8572E         CPU_POWERPC_e500v2_v30
6965     /* e600 family */
6966     /* e600 cores */
6967     CPU_POWERPC_e600               = 0x80040010,
6968     /* MPC86xx microcontrollers */
6969 #define CPU_POWERPC_MPC8610          CPU_POWERPC_e600
6970 #define CPU_POWERPC_MPC8641          CPU_POWERPC_e600
6971 #define CPU_POWERPC_MPC8641D         CPU_POWERPC_e600
6972     /* PowerPC 6xx cores */
6973 #define CPU_POWERPC_601              CPU_POWERPC_601_v2
6974     CPU_POWERPC_601_v0             = 0x00010001,
6975     CPU_POWERPC_601_v1             = 0x00010001,
6976 #define CPU_POWERPC_601v             CPU_POWERPC_601_v2
6977     CPU_POWERPC_601_v2             = 0x00010002,
6978     CPU_POWERPC_602                = 0x00050100,
6979     CPU_POWERPC_603                = 0x00030100,
6980 #define CPU_POWERPC_603E             CPU_POWERPC_603E_v41
6981     CPU_POWERPC_603E_v11           = 0x00060101,
6982     CPU_POWERPC_603E_v12           = 0x00060102,
6983     CPU_POWERPC_603E_v13           = 0x00060103,
6984     CPU_POWERPC_603E_v14           = 0x00060104,
6985     CPU_POWERPC_603E_v22           = 0x00060202,
6986     CPU_POWERPC_603E_v3            = 0x00060300,
6987     CPU_POWERPC_603E_v4            = 0x00060400,
6988     CPU_POWERPC_603E_v41           = 0x00060401,
6989     CPU_POWERPC_603E7t             = 0x00071201,
6990     CPU_POWERPC_603E7v             = 0x00070100,
6991     CPU_POWERPC_603E7v1            = 0x00070101,
6992     CPU_POWERPC_603E7v2            = 0x00070201,
6993     CPU_POWERPC_603E7              = 0x00070200,
6994     CPU_POWERPC_603P               = 0x00070000,
6995 #define CPU_POWERPC_603R             CPU_POWERPC_603E7t
6996     /* XXX: missing 0x00040303 (604) */
6997     CPU_POWERPC_604                = 0x00040103,
6998 #define CPU_POWERPC_604E             CPU_POWERPC_604E_v24
6999     /* XXX: missing 0x00091203 */
7000     /* XXX: missing 0x00092110 */
7001     /* XXX: missing 0x00092120 */
7002     CPU_POWERPC_604E_v10           = 0x00090100,
7003     CPU_POWERPC_604E_v22           = 0x00090202,
7004     CPU_POWERPC_604E_v24           = 0x00090204,
7005     /* XXX: missing 0x000a0100 */
7006     /* XXX: missing 0x00093102 */
7007     CPU_POWERPC_604R               = 0x000a0101,
7008 #if 0
7009     CPU_POWERPC_604EV              = xxx, /* XXX: same as 604R ? */
7010 #endif
7011     /* PowerPC 740/750 cores (aka G3) */
7012     /* XXX: missing 0x00084202 */
7013 #define CPU_POWERPC_7x0              CPU_POWERPC_7x0_v31
7014     CPU_POWERPC_7x0_v10            = 0x00080100,
7015     CPU_POWERPC_7x0_v20            = 0x00080200,
7016     CPU_POWERPC_7x0_v21            = 0x00080201,
7017     CPU_POWERPC_7x0_v22            = 0x00080202,
7018     CPU_POWERPC_7x0_v30            = 0x00080300,
7019     CPU_POWERPC_7x0_v31            = 0x00080301,
7020     CPU_POWERPC_740E               = 0x00080100,
7021     CPU_POWERPC_750E               = 0x00080200,
7022     CPU_POWERPC_7x0P               = 0x10080000,
7023     /* XXX: missing 0x00087010 (CL ?) */
7024 #define CPU_POWERPC_750CL            CPU_POWERPC_750CL_v20
7025     CPU_POWERPC_750CL_v10          = 0x00087200,
7026     CPU_POWERPC_750CL_v20          = 0x00087210, /* aka rev E */
7027 #define CPU_POWERPC_750CX            CPU_POWERPC_750CX_v22
7028     CPU_POWERPC_750CX_v10          = 0x00082100,
7029     CPU_POWERPC_750CX_v20          = 0x00082200,
7030     CPU_POWERPC_750CX_v21          = 0x00082201,
7031     CPU_POWERPC_750CX_v22          = 0x00082202,
7032 #define CPU_POWERPC_750CXE           CPU_POWERPC_750CXE_v31b
7033     CPU_POWERPC_750CXE_v21         = 0x00082211,
7034     CPU_POWERPC_750CXE_v22         = 0x00082212,
7035     CPU_POWERPC_750CXE_v23         = 0x00082213,
7036     CPU_POWERPC_750CXE_v24         = 0x00082214,
7037     CPU_POWERPC_750CXE_v24b        = 0x00083214,
7038     CPU_POWERPC_750CXE_v30         = 0x00082310,
7039     CPU_POWERPC_750CXE_v31         = 0x00082311,
7040     CPU_POWERPC_750CXE_v31b        = 0x00083311,
7041     CPU_POWERPC_750CXR             = 0x00083410,
7042     CPU_POWERPC_750FL              = 0x70000203,
7043 #define CPU_POWERPC_750FX            CPU_POWERPC_750FX_v23
7044     CPU_POWERPC_750FX_v10          = 0x70000100,
7045     CPU_POWERPC_750FX_v20          = 0x70000200,
7046     CPU_POWERPC_750FX_v21          = 0x70000201,
7047     CPU_POWERPC_750FX_v22          = 0x70000202,
7048     CPU_POWERPC_750FX_v23          = 0x70000203,
7049     CPU_POWERPC_750GL              = 0x70020102,
7050 #define CPU_POWERPC_750GX            CPU_POWERPC_750GX_v12
7051     CPU_POWERPC_750GX_v10          = 0x70020100,
7052     CPU_POWERPC_750GX_v11          = 0x70020101,
7053     CPU_POWERPC_750GX_v12          = 0x70020102,
7054 #define CPU_POWERPC_750L             CPU_POWERPC_750L_v32 /* Aka LoneStar */
7055     CPU_POWERPC_750L_v20           = 0x00088200,
7056     CPU_POWERPC_750L_v21           = 0x00088201,
7057     CPU_POWERPC_750L_v22           = 0x00088202,
7058     CPU_POWERPC_750L_v30           = 0x00088300,
7059     CPU_POWERPC_750L_v32           = 0x00088302,
7060     /* PowerPC 745/755 cores */
7061 #define CPU_POWERPC_7x5              CPU_POWERPC_7x5_v28
7062     CPU_POWERPC_7x5_v10            = 0x00083100,
7063     CPU_POWERPC_7x5_v11            = 0x00083101,
7064     CPU_POWERPC_7x5_v20            = 0x00083200,
7065     CPU_POWERPC_7x5_v21            = 0x00083201,
7066     CPU_POWERPC_7x5_v22            = 0x00083202, /* aka D */
7067     CPU_POWERPC_7x5_v23            = 0x00083203, /* aka E */
7068     CPU_POWERPC_7x5_v24            = 0x00083204,
7069     CPU_POWERPC_7x5_v25            = 0x00083205,
7070     CPU_POWERPC_7x5_v26            = 0x00083206,
7071     CPU_POWERPC_7x5_v27            = 0x00083207,
7072     CPU_POWERPC_7x5_v28            = 0x00083208,
7073 #if 0
7074     CPU_POWERPC_7x5P               = xxx,
7075 #endif
7076     /* PowerPC 74xx cores (aka G4) */
7077     /* XXX: missing 0x000C1101 */
7078 #define CPU_POWERPC_7400             CPU_POWERPC_7400_v29
7079     CPU_POWERPC_7400_v10           = 0x000C0100,
7080     CPU_POWERPC_7400_v11           = 0x000C0101,
7081     CPU_POWERPC_7400_v20           = 0x000C0200,
7082     CPU_POWERPC_7400_v21           = 0x000C0201,
7083     CPU_POWERPC_7400_v22           = 0x000C0202,
7084     CPU_POWERPC_7400_v26           = 0x000C0206,
7085     CPU_POWERPC_7400_v27           = 0x000C0207,
7086     CPU_POWERPC_7400_v28           = 0x000C0208,
7087     CPU_POWERPC_7400_v29           = 0x000C0209,
7088 #define CPU_POWERPC_7410             CPU_POWERPC_7410_v14
7089     CPU_POWERPC_7410_v10           = 0x800C1100,
7090     CPU_POWERPC_7410_v11           = 0x800C1101,
7091     CPU_POWERPC_7410_v12           = 0x800C1102, /* aka C */
7092     CPU_POWERPC_7410_v13           = 0x800C1103, /* aka D */
7093     CPU_POWERPC_7410_v14           = 0x800C1104, /* aka E */
7094 #define CPU_POWERPC_7448             CPU_POWERPC_7448_v21
7095     CPU_POWERPC_7448_v10           = 0x80040100,
7096     CPU_POWERPC_7448_v11           = 0x80040101,
7097     CPU_POWERPC_7448_v20           = 0x80040200,
7098     CPU_POWERPC_7448_v21           = 0x80040201,
7099 #define CPU_POWERPC_7450             CPU_POWERPC_7450_v21
7100     CPU_POWERPC_7450_v10           = 0x80000100,
7101     CPU_POWERPC_7450_v11           = 0x80000101,
7102     CPU_POWERPC_7450_v12           = 0x80000102,
7103     CPU_POWERPC_7450_v20           = 0x80000200, /* aka A, B, C, D: 2.04 */
7104     CPU_POWERPC_7450_v21           = 0x80000201, /* aka E */
7105 #define CPU_POWERPC_74x1             CPU_POWERPC_74x1_v23
7106     CPU_POWERPC_74x1_v23           = 0x80000203, /* aka G: 2.3 */
7107     /* XXX: this entry might be a bug in some documentation */
7108     CPU_POWERPC_74x1_v210          = 0x80000210, /* aka G: 2.3 ? */
7109 #define CPU_POWERPC_74x5             CPU_POWERPC_74x5_v32
7110     CPU_POWERPC_74x5_v10           = 0x80010100,
7111     /* XXX: missing 0x80010200 */
7112     CPU_POWERPC_74x5_v21           = 0x80010201, /* aka C: 2.1 */
7113     CPU_POWERPC_74x5_v32           = 0x80010302,
7114     CPU_POWERPC_74x5_v33           = 0x80010303, /* aka F: 3.3 */
7115     CPU_POWERPC_74x5_v34           = 0x80010304, /* aka G: 3.4 */
7116 #define CPU_POWERPC_74x7             CPU_POWERPC_74x7_v12
7117     CPU_POWERPC_74x7_v10           = 0x80020100, /* aka A: 1.0 */
7118     CPU_POWERPC_74x7_v11           = 0x80020101, /* aka B: 1.1 */
7119     CPU_POWERPC_74x7_v12           = 0x80020102, /* aka C: 1.2 */
7120 #define CPU_POWERPC_74x7A            CPU_POWERPC_74x7A_v12
7121     CPU_POWERPC_74x7A_v10          = 0x80030100, /* aka A: 1.0 */
7122     CPU_POWERPC_74x7A_v11          = 0x80030101, /* aka B: 1.1 */
7123     CPU_POWERPC_74x7A_v12          = 0x80030102, /* aka C: 1.2 */
7124     /* 64 bits PowerPC */
7125 #if defined(TARGET_PPC64)
7126     CPU_POWERPC_620                = 0x00140000,
7127     CPU_POWERPC_630                = 0x00400000,
7128     CPU_POWERPC_631                = 0x00410104,
7129     CPU_POWERPC_POWER4             = 0x00350000,
7130     CPU_POWERPC_POWER4P            = 0x00380000,
7131      /* XXX: missing 0x003A0201 */
7132     CPU_POWERPC_POWER5             = 0x003A0203,
7133 #define CPU_POWERPC_POWER5GR         CPU_POWERPC_POWER5
7134     CPU_POWERPC_POWER5P            = 0x003B0000,
7135 #define CPU_POWERPC_POWER5GS         CPU_POWERPC_POWER5P
7136     CPU_POWERPC_POWER6             = 0x003E0000,
7137     CPU_POWERPC_POWER6_5           = 0x0F000001, /* POWER6 in POWER5 mode */
7138     CPU_POWERPC_POWER6A            = 0x0F000002,
7139 #define CPU_POWERPC_POWER7           CPU_POWERPC_POWER7_v20
7140     CPU_POWERPC_POWER7_v20         = 0x003F0200,
7141     CPU_POWERPC_970                = 0x00390202,
7142 #define CPU_POWERPC_970FX            CPU_POWERPC_970FX_v31
7143     CPU_POWERPC_970FX_v10          = 0x00391100,
7144     CPU_POWERPC_970FX_v20          = 0x003C0200,
7145     CPU_POWERPC_970FX_v21          = 0x003C0201,
7146     CPU_POWERPC_970FX_v30          = 0x003C0300,
7147     CPU_POWERPC_970FX_v31          = 0x003C0301,
7148     CPU_POWERPC_970GX              = 0x00450000,
7149 #define CPU_POWERPC_970MP            CPU_POWERPC_970MP_v11
7150     CPU_POWERPC_970MP_v10          = 0x00440100,
7151     CPU_POWERPC_970MP_v11          = 0x00440101,
7152 #define CPU_POWERPC_CELL             CPU_POWERPC_CELL_v32
7153     CPU_POWERPC_CELL_v10           = 0x00700100,
7154     CPU_POWERPC_CELL_v20           = 0x00700400,
7155     CPU_POWERPC_CELL_v30           = 0x00700500,
7156     CPU_POWERPC_CELL_v31           = 0x00700501,
7157 #define CPU_POWERPC_CELL_v32         CPU_POWERPC_CELL_v31
7158     CPU_POWERPC_RS64               = 0x00330000,
7159     CPU_POWERPC_RS64II             = 0x00340000,
7160     CPU_POWERPC_RS64III            = 0x00360000,
7161     CPU_POWERPC_RS64IV             = 0x00370000,
7162 #endif /* defined(TARGET_PPC64) */
7163     /* Original POWER */
7164     /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7165      * POWER2 (RIOS2) & RSC2 (P2SC) here
7166      */
7167 #if 0
7168     CPU_POWER                      = xxx, /* 0x20000 ? 0x30000 for RSC ? */
7169 #endif
7170 #if 0
7171     CPU_POWER2                     = xxx, /* 0x40000 ? */
7172 #endif
7173     /* PA Semi core */
7174     CPU_POWERPC_PA6T               = 0x00900000,
7175 };
7176
7177 /* System version register (used on MPC 8xxx)                                */
7178 enum {
7179     POWERPC_SVR_NONE               = 0x00000000,
7180 #define POWERPC_SVR_52xx             POWERPC_SVR_5200
7181 #define POWERPC_SVR_5200             POWERPC_SVR_5200_v12
7182     POWERPC_SVR_5200_v10           = 0x80110010,
7183     POWERPC_SVR_5200_v11           = 0x80110011,
7184     POWERPC_SVR_5200_v12           = 0x80110012,
7185 #define POWERPC_SVR_5200B            POWERPC_SVR_5200B_v21
7186     POWERPC_SVR_5200B_v20          = 0x80110020,
7187     POWERPC_SVR_5200B_v21          = 0x80110021,
7188 #define POWERPC_SVR_55xx             POWERPC_SVR_5567
7189 #if 0
7190     POWERPC_SVR_5533               = xxx,
7191 #endif
7192 #if 0
7193     POWERPC_SVR_5534               = xxx,
7194 #endif
7195 #if 0
7196     POWERPC_SVR_5553               = xxx,
7197 #endif
7198 #if 0
7199     POWERPC_SVR_5554               = xxx,
7200 #endif
7201 #if 0
7202     POWERPC_SVR_5561               = xxx,
7203 #endif
7204 #if 0
7205     POWERPC_SVR_5565               = xxx,
7206 #endif
7207 #if 0
7208     POWERPC_SVR_5566               = xxx,
7209 #endif
7210 #if 0
7211     POWERPC_SVR_5567               = xxx,
7212 #endif
7213 #if 0
7214     POWERPC_SVR_8313               = xxx,
7215 #endif
7216 #if 0
7217     POWERPC_SVR_8313E              = xxx,
7218 #endif
7219 #if 0
7220     POWERPC_SVR_8314               = xxx,
7221 #endif
7222 #if 0
7223     POWERPC_SVR_8314E              = xxx,
7224 #endif
7225 #if 0
7226     POWERPC_SVR_8315               = xxx,
7227 #endif
7228 #if 0
7229     POWERPC_SVR_8315E              = xxx,
7230 #endif
7231 #if 0
7232     POWERPC_SVR_8321               = xxx,
7233 #endif
7234 #if 0
7235     POWERPC_SVR_8321E              = xxx,
7236 #endif
7237 #if 0
7238     POWERPC_SVR_8323               = xxx,
7239 #endif
7240 #if 0
7241     POWERPC_SVR_8323E              = xxx,
7242 #endif
7243     POWERPC_SVR_8343               = 0x80570010,
7244     POWERPC_SVR_8343A              = 0x80570030,
7245     POWERPC_SVR_8343E              = 0x80560010,
7246     POWERPC_SVR_8343EA             = 0x80560030,
7247 #define POWERPC_SVR_8347             POWERPC_SVR_8347T
7248     POWERPC_SVR_8347P              = 0x80550010, /* PBGA package */
7249     POWERPC_SVR_8347T              = 0x80530010, /* TBGA package */
7250 #define POWERPC_SVR_8347A            POWERPC_SVR_8347AT
7251     POWERPC_SVR_8347AP             = 0x80550030, /* PBGA package */
7252     POWERPC_SVR_8347AT             = 0x80530030, /* TBGA package */
7253 #define POWERPC_SVR_8347E            POWERPC_SVR_8347ET
7254     POWERPC_SVR_8347EP             = 0x80540010, /* PBGA package */
7255     POWERPC_SVR_8347ET             = 0x80520010, /* TBGA package */
7256 #define POWERPC_SVR_8347EA            POWERPC_SVR_8347EAT
7257     POWERPC_SVR_8347EAP            = 0x80540030, /* PBGA package */
7258     POWERPC_SVR_8347EAT            = 0x80520030, /* TBGA package */
7259     POWERPC_SVR_8349               = 0x80510010,
7260     POWERPC_SVR_8349A              = 0x80510030,
7261     POWERPC_SVR_8349E              = 0x80500010,
7262     POWERPC_SVR_8349EA             = 0x80500030,
7263 #if 0
7264     POWERPC_SVR_8358E              = xxx,
7265 #endif
7266 #if 0
7267     POWERPC_SVR_8360E              = xxx,
7268 #endif
7269 #define POWERPC_SVR_E500             0x40000000
7270     POWERPC_SVR_8377               = 0x80C70010 | POWERPC_SVR_E500,
7271     POWERPC_SVR_8377E              = 0x80C60010 | POWERPC_SVR_E500,
7272     POWERPC_SVR_8378               = 0x80C50010 | POWERPC_SVR_E500,
7273     POWERPC_SVR_8378E              = 0x80C40010 | POWERPC_SVR_E500,
7274     POWERPC_SVR_8379               = 0x80C30010 | POWERPC_SVR_E500,
7275     POWERPC_SVR_8379E              = 0x80C00010 | POWERPC_SVR_E500,
7276 #define POWERPC_SVR_8533             POWERPC_SVR_8533_v11
7277     POWERPC_SVR_8533_v10           = 0x80340010 | POWERPC_SVR_E500,
7278     POWERPC_SVR_8533_v11           = 0x80340011 | POWERPC_SVR_E500,
7279 #define POWERPC_SVR_8533E            POWERPC_SVR_8533E_v11
7280     POWERPC_SVR_8533E_v10          = 0x803C0010 | POWERPC_SVR_E500,
7281     POWERPC_SVR_8533E_v11          = 0x803C0011 | POWERPC_SVR_E500,
7282 #define POWERPC_SVR_8540             POWERPC_SVR_8540_v21
7283     POWERPC_SVR_8540_v10           = 0x80300010 | POWERPC_SVR_E500,
7284     POWERPC_SVR_8540_v20           = 0x80300020 | POWERPC_SVR_E500,
7285     POWERPC_SVR_8540_v21           = 0x80300021 | POWERPC_SVR_E500,
7286 #define POWERPC_SVR_8541             POWERPC_SVR_8541_v11
7287     POWERPC_SVR_8541_v10           = 0x80720010 | POWERPC_SVR_E500,
7288     POWERPC_SVR_8541_v11           = 0x80720011 | POWERPC_SVR_E500,
7289 #define POWERPC_SVR_8541E            POWERPC_SVR_8541E_v11
7290     POWERPC_SVR_8541E_v10          = 0x807A0010 | POWERPC_SVR_E500,
7291     POWERPC_SVR_8541E_v11          = 0x807A0011 | POWERPC_SVR_E500,
7292 #define POWERPC_SVR_8543             POWERPC_SVR_8543_v21
7293     POWERPC_SVR_8543_v10           = 0x80320010 | POWERPC_SVR_E500,
7294     POWERPC_SVR_8543_v11           = 0x80320011 | POWERPC_SVR_E500,
7295     POWERPC_SVR_8543_v20           = 0x80320020 | POWERPC_SVR_E500,
7296     POWERPC_SVR_8543_v21           = 0x80320021 | POWERPC_SVR_E500,
7297 #define POWERPC_SVR_8543E            POWERPC_SVR_8543E_v21
7298     POWERPC_SVR_8543E_v10          = 0x803A0010 | POWERPC_SVR_E500,
7299     POWERPC_SVR_8543E_v11          = 0x803A0011 | POWERPC_SVR_E500,
7300     POWERPC_SVR_8543E_v20          = 0x803A0020 | POWERPC_SVR_E500,
7301     POWERPC_SVR_8543E_v21          = 0x803A0021 | POWERPC_SVR_E500,
7302 #define POWERPC_SVR_8544             POWERPC_SVR_8544_v11
7303     POWERPC_SVR_8544_v10           = 0x80340110 | POWERPC_SVR_E500,
7304     POWERPC_SVR_8544_v11           = 0x80340111 | POWERPC_SVR_E500,
7305 #define POWERPC_SVR_8544E            POWERPC_SVR_8544E_v11
7306     POWERPC_SVR_8544E_v10          = 0x803C0110 | POWERPC_SVR_E500,
7307     POWERPC_SVR_8544E_v11          = 0x803C0111 | POWERPC_SVR_E500,
7308 #define POWERPC_SVR_8545             POWERPC_SVR_8545_v21
7309     POWERPC_SVR_8545_v20           = 0x80310220 | POWERPC_SVR_E500,
7310     POWERPC_SVR_8545_v21           = 0x80310221 | POWERPC_SVR_E500,
7311 #define POWERPC_SVR_8545E            POWERPC_SVR_8545E_v21
7312     POWERPC_SVR_8545E_v20          = 0x80390220 | POWERPC_SVR_E500,
7313     POWERPC_SVR_8545E_v21          = 0x80390221 | POWERPC_SVR_E500,
7314 #define POWERPC_SVR_8547E            POWERPC_SVR_8547E_v21
7315     POWERPC_SVR_8547E_v20          = 0x80390120 | POWERPC_SVR_E500,
7316     POWERPC_SVR_8547E_v21          = 0x80390121 | POWERPC_SVR_E500,
7317 #define POWERPC_SVR_8548             POWERPC_SVR_8548_v21
7318     POWERPC_SVR_8548_v10           = 0x80310010 | POWERPC_SVR_E500,
7319     POWERPC_SVR_8548_v11           = 0x80310011 | POWERPC_SVR_E500,
7320     POWERPC_SVR_8548_v20           = 0x80310020 | POWERPC_SVR_E500,
7321     POWERPC_SVR_8548_v21           = 0x80310021 | POWERPC_SVR_E500,
7322 #define POWERPC_SVR_8548E            POWERPC_SVR_8548E_v21
7323     POWERPC_SVR_8548E_v10          = 0x80390010 | POWERPC_SVR_E500,
7324     POWERPC_SVR_8548E_v11          = 0x80390011 | POWERPC_SVR_E500,
7325     POWERPC_SVR_8548E_v20          = 0x80390020 | POWERPC_SVR_E500,
7326     POWERPC_SVR_8548E_v21          = 0x80390021 | POWERPC_SVR_E500,
7327 #define POWERPC_SVR_8555             POWERPC_SVR_8555_v11
7328     POWERPC_SVR_8555_v10           = 0x80710010 | POWERPC_SVR_E500,
7329     POWERPC_SVR_8555_v11           = 0x80710011 | POWERPC_SVR_E500,
7330 #define POWERPC_SVR_8555E            POWERPC_SVR_8555_v11
7331     POWERPC_SVR_8555E_v10          = 0x80790010 | POWERPC_SVR_E500,
7332     POWERPC_SVR_8555E_v11          = 0x80790011 | POWERPC_SVR_E500,
7333 #define POWERPC_SVR_8560             POWERPC_SVR_8560_v21
7334     POWERPC_SVR_8560_v10           = 0x80700010 | POWERPC_SVR_E500,
7335     POWERPC_SVR_8560_v20           = 0x80700020 | POWERPC_SVR_E500,
7336     POWERPC_SVR_8560_v21           = 0x80700021 | POWERPC_SVR_E500,
7337     POWERPC_SVR_8567               = 0x80750111 | POWERPC_SVR_E500,
7338     POWERPC_SVR_8567E              = 0x807D0111 | POWERPC_SVR_E500,
7339     POWERPC_SVR_8568               = 0x80750011 | POWERPC_SVR_E500,
7340     POWERPC_SVR_8568E              = 0x807D0011 | POWERPC_SVR_E500,
7341     POWERPC_SVR_8572               = 0x80E00010 | POWERPC_SVR_E500,
7342     POWERPC_SVR_8572E              = 0x80E80010 | POWERPC_SVR_E500,
7343 #if 0
7344     POWERPC_SVR_8610               = xxx,
7345 #endif
7346     POWERPC_SVR_8641               = 0x80900021,
7347     POWERPC_SVR_8641D              = 0x80900121,
7348 };
7349
7350 /*****************************************************************************/
7351 /* PowerPC CPU definitions                                                   */
7352 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type)                             \
7353     {                                                                         \
7354         .name        = _name,                                                 \
7355         .pvr         = _pvr,                                                  \
7356         .svr         = _svr,                                                  \
7357         .insns_flags = glue(POWERPC_INSNS_,_type),                            \
7358         .msr_mask    = glue(POWERPC_MSRM_,_type),                             \
7359         .mmu_model   = glue(POWERPC_MMU_,_type),                              \
7360         .excp_model  = glue(POWERPC_EXCP_,_type),                             \
7361         .bus_model   = glue(POWERPC_INPUT_,_type),                            \
7362         .bfd_mach    = glue(POWERPC_BFDM_,_type),                             \
7363         .flags       = glue(POWERPC_FLAG_,_type),                             \
7364         .init_proc   = &glue(init_proc_,_type),                               \
7365         .check_pow   = &glue(check_pow_,_type),                               \
7366     }
7367 #define POWERPC_DEF(_name, _pvr, _type)                                       \
7368 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
7369
7370 static const ppc_def_t ppc_defs[] = {
7371     /* Embedded PowerPC                                                      */
7372     /* PowerPC 401 family                                                    */
7373     /* Generic PowerPC 401 */
7374     POWERPC_DEF("401",           CPU_POWERPC_401,                    401),
7375     /* PowerPC 401 cores                                                     */
7376     /* PowerPC 401A1 */
7377     POWERPC_DEF("401A1",         CPU_POWERPC_401A1,                  401),
7378     /* PowerPC 401B2                                                         */
7379     POWERPC_DEF("401B2",         CPU_POWERPC_401B2,                  401x2),
7380 #if defined (TODO)
7381     /* PowerPC 401B3                                                         */
7382     POWERPC_DEF("401B3",         CPU_POWERPC_401B3,                  401x3),
7383 #endif
7384     /* PowerPC 401C2                                                         */
7385     POWERPC_DEF("401C2",         CPU_POWERPC_401C2,                  401x2),
7386     /* PowerPC 401D2                                                         */
7387     POWERPC_DEF("401D2",         CPU_POWERPC_401D2,                  401x2),
7388     /* PowerPC 401E2                                                         */
7389     POWERPC_DEF("401E2",         CPU_POWERPC_401E2,                  401x2),
7390     /* PowerPC 401F2                                                         */
7391     POWERPC_DEF("401F2",         CPU_POWERPC_401F2,                  401x2),
7392     /* PowerPC 401G2                                                         */
7393     /* XXX: to be checked */
7394     POWERPC_DEF("401G2",         CPU_POWERPC_401G2,                  401x2),
7395     /* PowerPC 401 microcontrolers                                           */
7396 #if defined (TODO)
7397     /* PowerPC 401GF                                                         */
7398     POWERPC_DEF("401GF",         CPU_POWERPC_401GF,                  401),
7399 #endif
7400     /* IOP480 (401 microcontroler)                                           */
7401     POWERPC_DEF("IOP480",        CPU_POWERPC_IOP480,                 IOP480),
7402     /* IBM Processor for Network Resources                                   */
7403     POWERPC_DEF("Cobra",         CPU_POWERPC_COBRA,                  401),
7404 #if defined (TODO)
7405     POWERPC_DEF("Xipchip",       CPU_POWERPC_XIPCHIP,                401),
7406 #endif
7407     /* PowerPC 403 family                                                    */
7408     /* Generic PowerPC 403                                                   */
7409     POWERPC_DEF("403",           CPU_POWERPC_403,                    403),
7410     /* PowerPC 403 microcontrolers                                           */
7411     /* PowerPC 403 GA                                                        */
7412     POWERPC_DEF("403GA",         CPU_POWERPC_403GA,                  403),
7413     /* PowerPC 403 GB                                                        */
7414     POWERPC_DEF("403GB",         CPU_POWERPC_403GB,                  403),
7415     /* PowerPC 403 GC                                                        */
7416     POWERPC_DEF("403GC",         CPU_POWERPC_403GC,                  403),
7417     /* PowerPC 403 GCX                                                       */
7418     POWERPC_DEF("403GCX",        CPU_POWERPC_403GCX,                 403GCX),
7419 #if defined (TODO)
7420     /* PowerPC 403 GP                                                        */
7421     POWERPC_DEF("403GP",         CPU_POWERPC_403GP,                  403),
7422 #endif
7423     /* PowerPC 405 family                                                    */
7424     /* Generic PowerPC 405                                                   */
7425     POWERPC_DEF("405",           CPU_POWERPC_405,                    405),
7426     /* PowerPC 405 cores                                                     */
7427 #if defined (TODO)
7428     /* PowerPC 405 A3                                                        */
7429     POWERPC_DEF("405A3",         CPU_POWERPC_405A3,                  405),
7430 #endif
7431 #if defined (TODO)
7432     /* PowerPC 405 A4                                                        */
7433     POWERPC_DEF("405A4",         CPU_POWERPC_405A4,                  405),
7434 #endif
7435 #if defined (TODO)
7436     /* PowerPC 405 B3                                                        */
7437     POWERPC_DEF("405B3",         CPU_POWERPC_405B3,                  405),
7438 #endif
7439 #if defined (TODO)
7440     /* PowerPC 405 B4                                                        */
7441     POWERPC_DEF("405B4",         CPU_POWERPC_405B4,                  405),
7442 #endif
7443 #if defined (TODO)
7444     /* PowerPC 405 C3                                                        */
7445     POWERPC_DEF("405C3",         CPU_POWERPC_405C3,                  405),
7446 #endif
7447 #if defined (TODO)
7448     /* PowerPC 405 C4                                                        */
7449     POWERPC_DEF("405C4",         CPU_POWERPC_405C4,                  405),
7450 #endif
7451     /* PowerPC 405 D2                                                        */
7452     POWERPC_DEF("405D2",         CPU_POWERPC_405D2,                  405),
7453 #if defined (TODO)
7454     /* PowerPC 405 D3                                                        */
7455     POWERPC_DEF("405D3",         CPU_POWERPC_405D3,                  405),
7456 #endif
7457     /* PowerPC 405 D4                                                        */
7458     POWERPC_DEF("405D4",         CPU_POWERPC_405D4,                  405),
7459 #if defined (TODO)
7460     /* PowerPC 405 D5                                                        */
7461     POWERPC_DEF("405D5",         CPU_POWERPC_405D5,                  405),
7462 #endif
7463 #if defined (TODO)
7464     /* PowerPC 405 E4                                                        */
7465     POWERPC_DEF("405E4",         CPU_POWERPC_405E4,                  405),
7466 #endif
7467 #if defined (TODO)
7468     /* PowerPC 405 F4                                                        */
7469     POWERPC_DEF("405F4",         CPU_POWERPC_405F4,                  405),
7470 #endif
7471 #if defined (TODO)
7472     /* PowerPC 405 F5                                                        */
7473     POWERPC_DEF("405F5",         CPU_POWERPC_405F5,                  405),
7474 #endif
7475 #if defined (TODO)
7476     /* PowerPC 405 F6                                                        */
7477     POWERPC_DEF("405F6",         CPU_POWERPC_405F6,                  405),
7478 #endif
7479     /* PowerPC 405 microcontrolers                                           */
7480     /* PowerPC 405 CR                                                        */
7481     POWERPC_DEF("405CR",         CPU_POWERPC_405CR,                  405),
7482     /* PowerPC 405 CRa                                                       */
7483     POWERPC_DEF("405CRa",        CPU_POWERPC_405CRa,                 405),
7484     /* PowerPC 405 CRb                                                       */
7485     POWERPC_DEF("405CRb",        CPU_POWERPC_405CRb,                 405),
7486     /* PowerPC 405 CRc                                                       */
7487     POWERPC_DEF("405CRc",        CPU_POWERPC_405CRc,                 405),
7488     /* PowerPC 405 EP                                                        */
7489     POWERPC_DEF("405EP",         CPU_POWERPC_405EP,                  405),
7490 #if defined(TODO)
7491     /* PowerPC 405 EXr                                                       */
7492     POWERPC_DEF("405EXr",        CPU_POWERPC_405EXr,                 405),
7493 #endif
7494     /* PowerPC 405 EZ                                                        */
7495     POWERPC_DEF("405EZ",         CPU_POWERPC_405EZ,                  405),
7496 #if defined(TODO)
7497     /* PowerPC 405 FX                                                        */
7498     POWERPC_DEF("405FX",         CPU_POWERPC_405FX,                  405),
7499 #endif
7500     /* PowerPC 405 GP                                                        */
7501     POWERPC_DEF("405GP",         CPU_POWERPC_405GP,                  405),
7502     /* PowerPC 405 GPa                                                       */
7503     POWERPC_DEF("405GPa",        CPU_POWERPC_405GPa,                 405),
7504     /* PowerPC 405 GPb                                                       */
7505     POWERPC_DEF("405GPb",        CPU_POWERPC_405GPb,                 405),
7506     /* PowerPC 405 GPc                                                       */
7507     POWERPC_DEF("405GPc",        CPU_POWERPC_405GPc,                 405),
7508     /* PowerPC 405 GPd                                                       */
7509     POWERPC_DEF("405GPd",        CPU_POWERPC_405GPd,                 405),
7510     /* PowerPC 405 GPe                                                       */
7511     POWERPC_DEF("405GPe",        CPU_POWERPC_405GPe,                 405),
7512     /* PowerPC 405 GPR                                                       */
7513     POWERPC_DEF("405GPR",        CPU_POWERPC_405GPR,                 405),
7514 #if defined(TODO)
7515     /* PowerPC 405 H                                                         */
7516     POWERPC_DEF("405H",          CPU_POWERPC_405H,                   405),
7517 #endif
7518 #if defined(TODO)
7519     /* PowerPC 405 L                                                         */
7520     POWERPC_DEF("405L",          CPU_POWERPC_405L,                   405),
7521 #endif
7522     /* PowerPC 405 LP                                                        */
7523     POWERPC_DEF("405LP",         CPU_POWERPC_405LP,                  405),
7524 #if defined(TODO)
7525     /* PowerPC 405 PM                                                        */
7526     POWERPC_DEF("405PM",         CPU_POWERPC_405PM,                  405),
7527 #endif
7528 #if defined(TODO)
7529     /* PowerPC 405 PS                                                        */
7530     POWERPC_DEF("405PS",         CPU_POWERPC_405PS,                  405),
7531 #endif
7532 #if defined(TODO)
7533     /* PowerPC 405 S                                                         */
7534     POWERPC_DEF("405S",          CPU_POWERPC_405S,                   405),
7535 #endif
7536     /* Npe405 H                                                              */
7537     POWERPC_DEF("Npe405H",       CPU_POWERPC_NPE405H,                405),
7538     /* Npe405 H2                                                             */
7539     POWERPC_DEF("Npe405H2",      CPU_POWERPC_NPE405H2,               405),
7540     /* Npe405 L                                                              */
7541     POWERPC_DEF("Npe405L",       CPU_POWERPC_NPE405L,                405),
7542     /* Npe4GS3                                                               */
7543     POWERPC_DEF("Npe4GS3",       CPU_POWERPC_NPE4GS3,                405),
7544 #if defined (TODO)
7545     POWERPC_DEF("Npcxx1",        CPU_POWERPC_NPCxx1,                 405),
7546 #endif
7547 #if defined (TODO)
7548     POWERPC_DEF("Npr161",        CPU_POWERPC_NPR161,                 405),
7549 #endif
7550 #if defined (TODO)
7551     /* PowerPC LC77700 (Sanyo)                                               */
7552     POWERPC_DEF("LC77700",       CPU_POWERPC_LC77700,                405),
7553 #endif
7554     /* PowerPC 401/403/405 based set-top-box microcontrolers                 */
7555 #if defined (TODO)
7556     /* STB010000                                                             */
7557     POWERPC_DEF("STB01000",      CPU_POWERPC_STB01000,               401x2),
7558 #endif
7559 #if defined (TODO)
7560     /* STB01010                                                              */
7561     POWERPC_DEF("STB01010",      CPU_POWERPC_STB01010,               401x2),
7562 #endif
7563 #if defined (TODO)
7564     /* STB0210                                                               */
7565     POWERPC_DEF("STB0210",       CPU_POWERPC_STB0210,                401x3),
7566 #endif
7567     /* STB03xx                                                               */
7568     POWERPC_DEF("STB03",         CPU_POWERPC_STB03,                  405),
7569 #if defined (TODO)
7570     /* STB043x                                                               */
7571     POWERPC_DEF("STB043",        CPU_POWERPC_STB043,                 405),
7572 #endif
7573 #if defined (TODO)
7574     /* STB045x                                                               */
7575     POWERPC_DEF("STB045",        CPU_POWERPC_STB045,                 405),
7576 #endif
7577     /* STB04xx                                                               */
7578     POWERPC_DEF("STB04",         CPU_POWERPC_STB04,                  405),
7579     /* STB25xx                                                               */
7580     POWERPC_DEF("STB25",         CPU_POWERPC_STB25,                  405),
7581 #if defined (TODO)
7582     /* STB130                                                                */
7583     POWERPC_DEF("STB130",        CPU_POWERPC_STB130,                 405),
7584 #endif
7585     /* Xilinx PowerPC 405 cores                                              */
7586     POWERPC_DEF("x2vp4",         CPU_POWERPC_X2VP4,                  405),
7587     POWERPC_DEF("x2vp7",         CPU_POWERPC_X2VP7,                  405),
7588     POWERPC_DEF("x2vp20",        CPU_POWERPC_X2VP20,                 405),
7589     POWERPC_DEF("x2vp50",        CPU_POWERPC_X2VP50,                 405),
7590 #if defined (TODO)
7591     /* Zarlink ZL10310                                                       */
7592     POWERPC_DEF("zl10310",       CPU_POWERPC_ZL10310,                405),
7593 #endif
7594 #if defined (TODO)
7595     /* Zarlink ZL10311                                                       */
7596     POWERPC_DEF("zl10311",       CPU_POWERPC_ZL10311,                405),
7597 #endif
7598 #if defined (TODO)
7599     /* Zarlink ZL10320                                                       */
7600     POWERPC_DEF("zl10320",       CPU_POWERPC_ZL10320,                405),
7601 #endif
7602 #if defined (TODO)
7603     /* Zarlink ZL10321                                                       */
7604     POWERPC_DEF("zl10321",       CPU_POWERPC_ZL10321,                405),
7605 #endif
7606     /* PowerPC 440 family                                                    */
7607 #if defined(TODO_USER_ONLY)
7608     /* Generic PowerPC 440                                                   */
7609     POWERPC_DEF("440",           CPU_POWERPC_440,                    440GP),
7610 #endif
7611     /* PowerPC 440 cores                                                     */
7612 #if defined (TODO)
7613     /* PowerPC 440 A4                                                        */
7614     POWERPC_DEF("440A4",         CPU_POWERPC_440A4,                  440x4),
7615 #endif
7616     /* PowerPC 440 Xilinx 5                                                  */
7617     POWERPC_DEF("440-Xilinx",    CPU_POWERPC_440_XILINX,             440x5),
7618 #if defined (TODO)
7619     /* PowerPC 440 A5                                                        */
7620     POWERPC_DEF("440A5",         CPU_POWERPC_440A5,                  440x5),
7621 #endif
7622 #if defined (TODO)
7623     /* PowerPC 440 B4                                                        */
7624     POWERPC_DEF("440B4",         CPU_POWERPC_440B4,                  440x4),
7625 #endif
7626 #if defined (TODO)
7627     /* PowerPC 440 G4                                                        */
7628     POWERPC_DEF("440G4",         CPU_POWERPC_440G4,                  440x4),
7629 #endif
7630 #if defined (TODO)
7631     /* PowerPC 440 F5                                                        */
7632     POWERPC_DEF("440F5",         CPU_POWERPC_440F5,                  440x5),
7633 #endif
7634 #if defined (TODO)
7635     /* PowerPC 440 G5                                                        */
7636     POWERPC_DEF("440G5",         CPU_POWERPC_440G5,                  440x5),
7637 #endif
7638 #if defined (TODO)
7639     /* PowerPC 440H4                                                         */
7640     POWERPC_DEF("440H4",         CPU_POWERPC_440H4,                  440x4),
7641 #endif
7642 #if defined (TODO)
7643     /* PowerPC 440H6                                                         */
7644     POWERPC_DEF("440H6",         CPU_POWERPC_440H6,                  440Gx5),
7645 #endif
7646     /* PowerPC 440 microcontrolers                                           */
7647 #if defined(TODO_USER_ONLY)
7648     /* PowerPC 440 EP                                                        */
7649     POWERPC_DEF("440EP",         CPU_POWERPC_440EP,                  440EP),
7650 #endif
7651 #if defined(TODO_USER_ONLY)
7652     /* PowerPC 440 EPa                                                       */
7653     POWERPC_DEF("440EPa",        CPU_POWERPC_440EPa,                 440EP),
7654 #endif
7655 #if defined(TODO_USER_ONLY)
7656     /* PowerPC 440 EPb                                                       */
7657     POWERPC_DEF("440EPb",        CPU_POWERPC_440EPb,                 440EP),
7658 #endif
7659 #if defined(TODO_USER_ONLY)
7660     /* PowerPC 440 EPX                                                       */
7661     POWERPC_DEF("440EPX",        CPU_POWERPC_440EPX,                 440EP),
7662 #endif
7663 #if defined(TODO_USER_ONLY)
7664     /* PowerPC 440 GP                                                        */
7665     POWERPC_DEF("440GP",         CPU_POWERPC_440GP,                  440GP),
7666 #endif
7667 #if defined(TODO_USER_ONLY)
7668     /* PowerPC 440 GPb                                                       */
7669     POWERPC_DEF("440GPb",        CPU_POWERPC_440GPb,                 440GP),
7670 #endif
7671 #if defined(TODO_USER_ONLY)
7672     /* PowerPC 440 GPc                                                       */
7673     POWERPC_DEF("440GPc",        CPU_POWERPC_440GPc,                 440GP),
7674 #endif
7675 #if defined(TODO_USER_ONLY)
7676     /* PowerPC 440 GR                                                        */
7677     POWERPC_DEF("440GR",         CPU_POWERPC_440GR,                  440x5),
7678 #endif
7679 #if defined(TODO_USER_ONLY)
7680     /* PowerPC 440 GRa                                                       */
7681     POWERPC_DEF("440GRa",        CPU_POWERPC_440GRa,                 440x5),
7682 #endif
7683 #if defined(TODO_USER_ONLY)
7684     /* PowerPC 440 GRX                                                       */
7685     POWERPC_DEF("440GRX",        CPU_POWERPC_440GRX,                 440x5),
7686 #endif
7687 #if defined(TODO_USER_ONLY)
7688     /* PowerPC 440 GX                                                        */
7689     POWERPC_DEF("440GX",         CPU_POWERPC_440GX,                  440EP),
7690 #endif
7691 #if defined(TODO_USER_ONLY)
7692     /* PowerPC 440 GXa                                                       */
7693     POWERPC_DEF("440GXa",        CPU_POWERPC_440GXa,                 440EP),
7694 #endif
7695 #if defined(TODO_USER_ONLY)
7696     /* PowerPC 440 GXb                                                       */
7697     POWERPC_DEF("440GXb",        CPU_POWERPC_440GXb,                 440EP),
7698 #endif
7699 #if defined(TODO_USER_ONLY)
7700     /* PowerPC 440 GXc                                                       */
7701     POWERPC_DEF("440GXc",        CPU_POWERPC_440GXc,                 440EP),
7702 #endif
7703 #if defined(TODO_USER_ONLY)
7704     /* PowerPC 440 GXf                                                       */
7705     POWERPC_DEF("440GXf",        CPU_POWERPC_440GXf,                 440EP),
7706 #endif
7707 #if defined(TODO)
7708     /* PowerPC 440 S                                                         */
7709     POWERPC_DEF("440S",          CPU_POWERPC_440S,                   440),
7710 #endif
7711 #if defined(TODO_USER_ONLY)
7712     /* PowerPC 440 SP                                                        */
7713     POWERPC_DEF("440SP",         CPU_POWERPC_440SP,                  440EP),
7714 #endif
7715 #if defined(TODO_USER_ONLY)
7716     /* PowerPC 440 SP2                                                       */
7717     POWERPC_DEF("440SP2",        CPU_POWERPC_440SP2,                 440EP),
7718 #endif
7719 #if defined(TODO_USER_ONLY)
7720     /* PowerPC 440 SPE                                                       */
7721     POWERPC_DEF("440SPE",        CPU_POWERPC_440SPE,                 440EP),
7722 #endif
7723     /* PowerPC 460 family                                                    */
7724 #if defined (TODO)
7725     /* Generic PowerPC 464                                                   */
7726     POWERPC_DEF("464",           CPU_POWERPC_464,                    460),
7727 #endif
7728     /* PowerPC 464 microcontrolers                                           */
7729 #if defined (TODO)
7730     /* PowerPC 464H90                                                        */
7731     POWERPC_DEF("464H90",        CPU_POWERPC_464H90,                 460),
7732 #endif
7733 #if defined (TODO)
7734     /* PowerPC 464H90F                                                       */
7735     POWERPC_DEF("464H90F",       CPU_POWERPC_464H90F,                460F),
7736 #endif
7737     /* Freescale embedded PowerPC cores                                      */
7738     /* MPC5xx family (aka RCPU)                                              */
7739 #if defined(TODO_USER_ONLY)
7740     /* Generic MPC5xx core                                                   */
7741     POWERPC_DEF("MPC5xx",        CPU_POWERPC_MPC5xx,                 MPC5xx),
7742 #endif
7743 #if defined(TODO_USER_ONLY)
7744     /* Codename for MPC5xx core                                              */
7745     POWERPC_DEF("RCPU",          CPU_POWERPC_MPC5xx,                 MPC5xx),
7746 #endif
7747     /* MPC5xx microcontrollers                                               */
7748 #if defined(TODO_USER_ONLY)
7749     /* MGT560                                                                */
7750     POWERPC_DEF("MGT560",        CPU_POWERPC_MGT560,                 MPC5xx),
7751 #endif
7752 #if defined(TODO_USER_ONLY)
7753     /* MPC509                                                                */
7754     POWERPC_DEF("MPC509",        CPU_POWERPC_MPC509,                 MPC5xx),
7755 #endif
7756 #if defined(TODO_USER_ONLY)
7757     /* MPC533                                                                */
7758     POWERPC_DEF("MPC533",        CPU_POWERPC_MPC533,                 MPC5xx),
7759 #endif
7760 #if defined(TODO_USER_ONLY)
7761     /* MPC534                                                                */
7762     POWERPC_DEF("MPC534",        CPU_POWERPC_MPC534,                 MPC5xx),
7763 #endif
7764 #if defined(TODO_USER_ONLY)
7765     /* MPC555                                                                */
7766     POWERPC_DEF("MPC555",        CPU_POWERPC_MPC555,                 MPC5xx),
7767 #endif
7768 #if defined(TODO_USER_ONLY)
7769     /* MPC556                                                                */
7770     POWERPC_DEF("MPC556",        CPU_POWERPC_MPC556,                 MPC5xx),
7771 #endif
7772 #if defined(TODO_USER_ONLY)
7773     /* MPC560                                                                */
7774     POWERPC_DEF("MPC560",        CPU_POWERPC_MPC560,                 MPC5xx),
7775 #endif
7776 #if defined(TODO_USER_ONLY)
7777     /* MPC561                                                                */
7778     POWERPC_DEF("MPC561",        CPU_POWERPC_MPC561,                 MPC5xx),
7779 #endif
7780 #if defined(TODO_USER_ONLY)
7781     /* MPC562                                                                */
7782     POWERPC_DEF("MPC562",        CPU_POWERPC_MPC562,                 MPC5xx),
7783 #endif
7784 #if defined(TODO_USER_ONLY)
7785     /* MPC563                                                                */
7786     POWERPC_DEF("MPC563",        CPU_POWERPC_MPC563,                 MPC5xx),
7787 #endif
7788 #if defined(TODO_USER_ONLY)
7789     /* MPC564                                                                */
7790     POWERPC_DEF("MPC564",        CPU_POWERPC_MPC564,                 MPC5xx),
7791 #endif
7792 #if defined(TODO_USER_ONLY)
7793     /* MPC565                                                                */
7794     POWERPC_DEF("MPC565",        CPU_POWERPC_MPC565,                 MPC5xx),
7795 #endif
7796 #if defined(TODO_USER_ONLY)
7797     /* MPC566                                                                */
7798     POWERPC_DEF("MPC566",        CPU_POWERPC_MPC566,                 MPC5xx),
7799 #endif
7800     /* MPC8xx family (aka PowerQUICC)                                        */
7801 #if defined(TODO_USER_ONLY)
7802     /* Generic MPC8xx core                                                   */
7803     POWERPC_DEF("MPC8xx",        CPU_POWERPC_MPC8xx,                 MPC8xx),
7804 #endif
7805 #if defined(TODO_USER_ONLY)
7806     /* Codename for MPC8xx core                                              */
7807     POWERPC_DEF("PowerQUICC",    CPU_POWERPC_MPC8xx,                 MPC8xx),
7808 #endif
7809     /* MPC8xx microcontrollers                                               */
7810 #if defined(TODO_USER_ONLY)
7811     /* MGT823                                                                */
7812     POWERPC_DEF("MGT823",        CPU_POWERPC_MGT823,                 MPC8xx),
7813 #endif
7814 #if defined(TODO_USER_ONLY)
7815     /* MPC821                                                                */
7816     POWERPC_DEF("MPC821",        CPU_POWERPC_MPC821,                 MPC8xx),
7817 #endif
7818 #if defined(TODO_USER_ONLY)
7819     /* MPC823                                                                */
7820     POWERPC_DEF("MPC823",        CPU_POWERPC_MPC823,                 MPC8xx),
7821 #endif
7822 #if defined(TODO_USER_ONLY)
7823     /* MPC850                                                                */
7824     POWERPC_DEF("MPC850",        CPU_POWERPC_MPC850,                 MPC8xx),
7825 #endif
7826 #if defined(TODO_USER_ONLY)
7827     /* MPC852T                                                               */
7828     POWERPC_DEF("MPC852T",       CPU_POWERPC_MPC852T,                MPC8xx),
7829 #endif
7830 #if defined(TODO_USER_ONLY)
7831     /* MPC855T                                                               */
7832     POWERPC_DEF("MPC855T",       CPU_POWERPC_MPC855T,                MPC8xx),
7833 #endif
7834 #if defined(TODO_USER_ONLY)
7835     /* MPC857                                                                */
7836     POWERPC_DEF("MPC857",        CPU_POWERPC_MPC857,                 MPC8xx),
7837 #endif
7838 #if defined(TODO_USER_ONLY)
7839     /* MPC859                                                                */
7840     POWERPC_DEF("MPC859",        CPU_POWERPC_MPC859,                 MPC8xx),
7841 #endif
7842 #if defined(TODO_USER_ONLY)
7843     /* MPC860                                                                */
7844     POWERPC_DEF("MPC860",        CPU_POWERPC_MPC860,                 MPC8xx),
7845 #endif
7846 #if defined(TODO_USER_ONLY)
7847     /* MPC862                                                                */
7848     POWERPC_DEF("MPC862",        CPU_POWERPC_MPC862,                 MPC8xx),
7849 #endif
7850 #if defined(TODO_USER_ONLY)
7851     /* MPC866                                                                */
7852     POWERPC_DEF("MPC866",        CPU_POWERPC_MPC866,                 MPC8xx),
7853 #endif
7854 #if defined(TODO_USER_ONLY)
7855     /* MPC870                                                                */
7856     POWERPC_DEF("MPC870",        CPU_POWERPC_MPC870,                 MPC8xx),
7857 #endif
7858 #if defined(TODO_USER_ONLY)
7859     /* MPC875                                                                */
7860     POWERPC_DEF("MPC875",        CPU_POWERPC_MPC875,                 MPC8xx),
7861 #endif
7862 #if defined(TODO_USER_ONLY)
7863     /* MPC880                                                                */
7864     POWERPC_DEF("MPC880",        CPU_POWERPC_MPC880,                 MPC8xx),
7865 #endif
7866 #if defined(TODO_USER_ONLY)
7867     /* MPC885                                                                */
7868     POWERPC_DEF("MPC885",        CPU_POWERPC_MPC885,                 MPC8xx),
7869 #endif
7870     /* MPC82xx family (aka PowerQUICC-II)                                    */
7871     /* Generic MPC52xx core                                                  */
7872     POWERPC_DEF_SVR("MPC52xx",
7873                     CPU_POWERPC_MPC52xx,      POWERPC_SVR_52xx,      G2LE),
7874     /* Generic MPC82xx core                                                  */
7875     POWERPC_DEF("MPC82xx",       CPU_POWERPC_MPC82xx,                G2),
7876     /* Codename for MPC82xx                                                  */
7877     POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx,                G2),
7878     /* PowerPC G2 core                                                       */
7879     POWERPC_DEF("G2",            CPU_POWERPC_G2,                     G2),
7880     /* PowerPC G2 H4 core                                                    */
7881     POWERPC_DEF("G2H4",          CPU_POWERPC_G2H4,                   G2),
7882     /* PowerPC G2 GP core                                                    */
7883     POWERPC_DEF("G2GP",          CPU_POWERPC_G2gp,                   G2),
7884     /* PowerPC G2 LS core                                                    */
7885     POWERPC_DEF("G2LS",          CPU_POWERPC_G2ls,                   G2),
7886     /* PowerPC G2 HiP3 core                                                  */
7887     POWERPC_DEF("G2HiP3",        CPU_POWERPC_G2_HIP3,                G2),
7888     /* PowerPC G2 HiP4 core                                                  */
7889     POWERPC_DEF("G2HiP4",        CPU_POWERPC_G2_HIP4,                G2),
7890     /* PowerPC MPC603 core                                                   */
7891     POWERPC_DEF("MPC603",        CPU_POWERPC_MPC603,                 603E),
7892     /* PowerPC G2le core (same as G2 plus little-endian mode support)        */
7893     POWERPC_DEF("G2le",          CPU_POWERPC_G2LE,                   G2LE),
7894     /* PowerPC G2LE GP core                                                  */
7895     POWERPC_DEF("G2leGP",        CPU_POWERPC_G2LEgp,                 G2LE),
7896     /* PowerPC G2LE LS core                                                  */
7897     POWERPC_DEF("G2leLS",        CPU_POWERPC_G2LEls,                 G2LE),
7898     /* PowerPC G2LE GP1 core                                                 */
7899     POWERPC_DEF("G2leGP1",       CPU_POWERPC_G2LEgp1,                G2LE),
7900     /* PowerPC G2LE GP3 core                                                 */
7901     POWERPC_DEF("G2leGP3",       CPU_POWERPC_G2LEgp1,                G2LE),
7902     /* PowerPC MPC603 microcontrollers                                       */
7903     /* MPC8240                                                               */
7904     POWERPC_DEF("MPC8240",       CPU_POWERPC_MPC8240,                603E),
7905     /* PowerPC G2 microcontrollers                                           */
7906 #if defined(TODO)
7907     /* MPC5121                                                               */
7908     POWERPC_DEF_SVR("MPC5121",
7909                     CPU_POWERPC_MPC5121,      POWERPC_SVR_5121,      G2LE),
7910 #endif
7911     /* MPC5200                                                               */
7912     POWERPC_DEF_SVR("MPC5200",
7913                     CPU_POWERPC_MPC5200,      POWERPC_SVR_5200,      G2LE),
7914     /* MPC5200 v1.0                                                          */
7915     POWERPC_DEF_SVR("MPC5200_v10",
7916                     CPU_POWERPC_MPC5200_v10,  POWERPC_SVR_5200_v10,  G2LE),
7917     /* MPC5200 v1.1                                                          */
7918     POWERPC_DEF_SVR("MPC5200_v11",
7919                     CPU_POWERPC_MPC5200_v11,  POWERPC_SVR_5200_v11,  G2LE),
7920     /* MPC5200 v1.2                                                          */
7921     POWERPC_DEF_SVR("MPC5200_v12",
7922                     CPU_POWERPC_MPC5200_v12,  POWERPC_SVR_5200_v12,  G2LE),
7923     /* MPC5200B                                                              */
7924     POWERPC_DEF_SVR("MPC5200B",
7925                     CPU_POWERPC_MPC5200B,     POWERPC_SVR_5200B,     G2LE),
7926     /* MPC5200B v2.0                                                         */
7927     POWERPC_DEF_SVR("MPC5200B_v20",
7928                     CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7929     /* MPC5200B v2.1                                                         */
7930     POWERPC_DEF_SVR("MPC5200B_v21",
7931                     CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7932     /* MPC8241                                                               */
7933     POWERPC_DEF("MPC8241",       CPU_POWERPC_MPC8241,                G2),
7934     /* MPC8245                                                               */
7935     POWERPC_DEF("MPC8245",       CPU_POWERPC_MPC8245,                G2),
7936     /* MPC8247                                                               */
7937     POWERPC_DEF("MPC8247",       CPU_POWERPC_MPC8247,                G2LE),
7938     /* MPC8248                                                               */
7939     POWERPC_DEF("MPC8248",       CPU_POWERPC_MPC8248,                G2LE),
7940     /* MPC8250                                                               */
7941     POWERPC_DEF("MPC8250",       CPU_POWERPC_MPC8250,                G2),
7942     /* MPC8250 HiP3                                                          */
7943     POWERPC_DEF("MPC8250_HiP3",  CPU_POWERPC_MPC8250_HiP3,           G2),
7944     /* MPC8250 HiP4                                                          */
7945     POWERPC_DEF("MPC8250_HiP4",  CPU_POWERPC_MPC8250_HiP4,           G2),
7946     /* MPC8255                                                               */
7947     POWERPC_DEF("MPC8255",       CPU_POWERPC_MPC8255,                G2),
7948     /* MPC8255 HiP3                                                          */
7949     POWERPC_DEF("MPC8255_HiP3",  CPU_POWERPC_MPC8255_HiP3,           G2),
7950     /* MPC8255 HiP4                                                          */
7951     POWERPC_DEF("MPC8255_HiP4",  CPU_POWERPC_MPC8255_HiP4,           G2),
7952     /* MPC8260                                                               */
7953     POWERPC_DEF("MPC8260",       CPU_POWERPC_MPC8260,                G2),
7954     /* MPC8260 HiP3                                                          */
7955     POWERPC_DEF("MPC8260_HiP3",  CPU_POWERPC_MPC8260_HiP3,           G2),
7956     /* MPC8260 HiP4                                                          */
7957     POWERPC_DEF("MPC8260_HiP4",  CPU_POWERPC_MPC8260_HiP4,           G2),
7958     /* MPC8264                                                               */
7959     POWERPC_DEF("MPC8264",       CPU_POWERPC_MPC8264,                G2),
7960     /* MPC8264 HiP3                                                          */
7961     POWERPC_DEF("MPC8264_HiP3",  CPU_POWERPC_MPC8264_HiP3,           G2),
7962     /* MPC8264 HiP4                                                          */
7963     POWERPC_DEF("MPC8264_HiP4",  CPU_POWERPC_MPC8264_HiP4,           G2),
7964     /* MPC8265                                                               */
7965     POWERPC_DEF("MPC8265",       CPU_POWERPC_MPC8265,                G2),
7966     /* MPC8265 HiP3                                                          */
7967     POWERPC_DEF("MPC8265_HiP3",  CPU_POWERPC_MPC8265_HiP3,           G2),
7968     /* MPC8265 HiP4                                                          */
7969     POWERPC_DEF("MPC8265_HiP4",  CPU_POWERPC_MPC8265_HiP4,           G2),
7970     /* MPC8266                                                               */
7971     POWERPC_DEF("MPC8266",       CPU_POWERPC_MPC8266,                G2),
7972     /* MPC8266 HiP3                                                          */
7973     POWERPC_DEF("MPC8266_HiP3",  CPU_POWERPC_MPC8266_HiP3,           G2),
7974     /* MPC8266 HiP4                                                          */
7975     POWERPC_DEF("MPC8266_HiP4",  CPU_POWERPC_MPC8266_HiP4,           G2),
7976     /* MPC8270                                                               */
7977     POWERPC_DEF("MPC8270",       CPU_POWERPC_MPC8270,                G2LE),
7978     /* MPC8271                                                               */
7979     POWERPC_DEF("MPC8271",       CPU_POWERPC_MPC8271,                G2LE),
7980     /* MPC8272                                                               */
7981     POWERPC_DEF("MPC8272",       CPU_POWERPC_MPC8272,                G2LE),
7982     /* MPC8275                                                               */
7983     POWERPC_DEF("MPC8275",       CPU_POWERPC_MPC8275,                G2LE),
7984     /* MPC8280                                                               */
7985     POWERPC_DEF("MPC8280",       CPU_POWERPC_MPC8280,                G2LE),
7986     /* e200 family                                                           */
7987     /* Generic PowerPC e200 core                                             */
7988     POWERPC_DEF("e200",          CPU_POWERPC_e200,                   e200),
7989     /* Generic MPC55xx core                                                  */
7990 #if defined (TODO)
7991     POWERPC_DEF_SVR("MPC55xx",
7992                     CPU_POWERPC_MPC55xx,      POWERPC_SVR_55xx,      e200),
7993 #endif
7994 #if defined (TODO)
7995     /* PowerPC e200z0 core                                                   */
7996     POWERPC_DEF("e200z0",        CPU_POWERPC_e200z0,                 e200),
7997 #endif
7998 #if defined (TODO)
7999     /* PowerPC e200z1 core                                                   */
8000     POWERPC_DEF("e200z1",        CPU_POWERPC_e200z1,                 e200),
8001 #endif
8002 #if defined (TODO)
8003     /* PowerPC e200z3 core                                                   */
8004     POWERPC_DEF("e200z3",        CPU_POWERPC_e200z3,                 e200),
8005 #endif
8006     /* PowerPC e200z5 core                                                   */
8007     POWERPC_DEF("e200z5",        CPU_POWERPC_e200z5,                 e200),
8008     /* PowerPC e200z6 core                                                   */
8009     POWERPC_DEF("e200z6",        CPU_POWERPC_e200z6,                 e200),
8010     /* PowerPC e200 microcontrollers                                         */
8011 #if defined (TODO)
8012     /* MPC5514E                                                              */
8013     POWERPC_DEF_SVR("MPC5514E",
8014                     CPU_POWERPC_MPC5514E,     POWERPC_SVR_5514E,     e200),
8015 #endif
8016 #if defined (TODO)
8017     /* MPC5514E v0                                                           */
8018     POWERPC_DEF_SVR("MPC5514E_v0",
8019                     CPU_POWERPC_MPC5514E_v0,  POWERPC_SVR_5514E_v0,  e200),
8020 #endif
8021 #if defined (TODO)
8022     /* MPC5514E v1                                                           */
8023     POWERPC_DEF_SVR("MPC5514E_v1",
8024                     CPU_POWERPC_MPC5514E_v1,  POWERPC_SVR_5514E_v1,  e200),
8025 #endif
8026 #if defined (TODO)
8027     /* MPC5514G                                                              */
8028     POWERPC_DEF_SVR("MPC5514G",
8029                     CPU_POWERPC_MPC5514G,     POWERPC_SVR_5514G,     e200),
8030 #endif
8031 #if defined (TODO)
8032     /* MPC5514G v0                                                           */
8033     POWERPC_DEF_SVR("MPC5514G_v0",
8034                     CPU_POWERPC_MPC5514G_v0,  POWERPC_SVR_5514G_v0,  e200),
8035 #endif
8036 #if defined (TODO)
8037     /* MPC5514G v1                                                           */
8038     POWERPC_DEF_SVR("MPC5514G_v1",
8039                     CPU_POWERPC_MPC5514G_v1,  POWERPC_SVR_5514G_v1,  e200),
8040 #endif
8041 #if defined (TODO)
8042     /* MPC5515S                                                              */
8043     POWERPC_DEF_SVR("MPC5515S",
8044                     CPU_POWERPC_MPC5515S,     POWERPC_SVR_5515S,     e200),
8045 #endif
8046 #if defined (TODO)
8047     /* MPC5516E                                                              */
8048     POWERPC_DEF_SVR("MPC5516E",
8049                     CPU_POWERPC_MPC5516E,     POWERPC_SVR_5516E,     e200),
8050 #endif
8051 #if defined (TODO)
8052     /* MPC5516E v0                                                           */
8053     POWERPC_DEF_SVR("MPC5516E_v0",
8054                     CPU_POWERPC_MPC5516E_v0,  POWERPC_SVR_5516E_v0,  e200),
8055 #endif
8056 #if defined (TODO)
8057     /* MPC5516E v1                                                           */
8058     POWERPC_DEF_SVR("MPC5516E_v1",
8059                     CPU_POWERPC_MPC5516E_v1,  POWERPC_SVR_5516E_v1,  e200),
8060 #endif
8061 #if defined (TODO)
8062     /* MPC5516G                                                              */
8063     POWERPC_DEF_SVR("MPC5516G",
8064                     CPU_POWERPC_MPC5516G,     POWERPC_SVR_5516G,     e200),
8065 #endif
8066 #if defined (TODO)
8067     /* MPC5516G v0                                                           */
8068     POWERPC_DEF_SVR("MPC5516G_v0",
8069                     CPU_POWERPC_MPC5516G_v0,  POWERPC_SVR_5516G_v0,  e200),
8070 #endif
8071 #if defined (TODO)
8072     /* MPC5516G v1                                                           */
8073     POWERPC_DEF_SVR("MPC5516G_v1",
8074                     CPU_POWERPC_MPC5516G_v1,  POWERPC_SVR_5516G_v1,  e200),
8075 #endif
8076 #if defined (TODO)
8077     /* MPC5516S                                                              */
8078     POWERPC_DEF_SVR("MPC5516S",
8079                     CPU_POWERPC_MPC5516S,     POWERPC_SVR_5516S,     e200),
8080 #endif
8081 #if defined (TODO)
8082     /* MPC5533                                                               */
8083     POWERPC_DEF_SVR("MPC5533",
8084                     CPU_POWERPC_MPC5533,      POWERPC_SVR_5533,      e200),
8085 #endif
8086 #if defined (TODO)
8087     /* MPC5534                                                               */
8088     POWERPC_DEF_SVR("MPC5534",
8089                     CPU_POWERPC_MPC5534,      POWERPC_SVR_5534,      e200),
8090 #endif
8091 #if defined (TODO)
8092     /* MPC5553                                                               */
8093     POWERPC_DEF_SVR("MPC5553",
8094                     CPU_POWERPC_MPC5553,      POWERPC_SVR_5553,      e200),
8095 #endif
8096 #if defined (TODO)
8097     /* MPC5554                                                               */
8098     POWERPC_DEF_SVR("MPC5554",
8099                     CPU_POWERPC_MPC5554,      POWERPC_SVR_5554,      e200),
8100 #endif
8101 #if defined (TODO)
8102     /* MPC5561                                                               */
8103     POWERPC_DEF_SVR("MPC5561",
8104                     CPU_POWERPC_MPC5561,      POWERPC_SVR_5561,      e200),
8105 #endif
8106 #if defined (TODO)
8107     /* MPC5565                                                               */
8108     POWERPC_DEF_SVR("MPC5565",
8109                     CPU_POWERPC_MPC5565,      POWERPC_SVR_5565,      e200),
8110 #endif
8111 #if defined (TODO)
8112     /* MPC5566                                                               */
8113     POWERPC_DEF_SVR("MPC5566",
8114                     CPU_POWERPC_MPC5566,      POWERPC_SVR_5566,      e200),
8115 #endif
8116 #if defined (TODO)
8117     /* MPC5567                                                               */
8118     POWERPC_DEF_SVR("MPC5567",
8119                     CPU_POWERPC_MPC5567,      POWERPC_SVR_5567,      e200),
8120 #endif
8121     /* e300 family                                                           */
8122     /* Generic PowerPC e300 core                                             */
8123     POWERPC_DEF("e300",          CPU_POWERPC_e300,                   e300),
8124     /* PowerPC e300c1 core                                                   */
8125     POWERPC_DEF("e300c1",        CPU_POWERPC_e300c1,                 e300),
8126     /* PowerPC e300c2 core                                                   */
8127     POWERPC_DEF("e300c2",        CPU_POWERPC_e300c2,                 e300),
8128     /* PowerPC e300c3 core                                                   */
8129     POWERPC_DEF("e300c3",        CPU_POWERPC_e300c3,                 e300),
8130     /* PowerPC e300c4 core                                                   */
8131     POWERPC_DEF("e300c4",        CPU_POWERPC_e300c4,                 e300),
8132     /* PowerPC e300 microcontrollers                                         */
8133 #if defined (TODO)
8134     /* MPC8313                                                               */
8135     POWERPC_DEF_SVR("MPC8313",
8136                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8313,      e300),
8137 #endif
8138 #if defined (TODO)
8139     /* MPC8313E                                                              */
8140     POWERPC_DEF_SVR("MPC8313E",
8141                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8313E,     e300),
8142 #endif
8143 #if defined (TODO)
8144     /* MPC8314                                                               */
8145     POWERPC_DEF_SVR("MPC8314",
8146                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8314,      e300),
8147 #endif
8148 #if defined (TODO)
8149     /* MPC8314E                                                              */
8150     POWERPC_DEF_SVR("MPC8314E",
8151                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8314E,     e300),
8152 #endif
8153 #if defined (TODO)
8154     /* MPC8315                                                               */
8155     POWERPC_DEF_SVR("MPC8315",
8156                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8315,      e300),
8157 #endif
8158 #if defined (TODO)
8159     /* MPC8315E                                                              */
8160     POWERPC_DEF_SVR("MPC8315E",
8161                     CPU_POWERPC_MPC831x,      POWERPC_SVR_8315E,     e300),
8162 #endif
8163 #if defined (TODO)
8164     /* MPC8321                                                               */
8165     POWERPC_DEF_SVR("MPC8321",
8166                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8321,      e300),
8167 #endif
8168 #if defined (TODO)
8169     /* MPC8321E                                                              */
8170     POWERPC_DEF_SVR("MPC8321E",
8171                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8321E,     e300),
8172 #endif
8173 #if defined (TODO)
8174     /* MPC8323                                                               */
8175     POWERPC_DEF_SVR("MPC8323",
8176                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8323,      e300),
8177 #endif
8178 #if defined (TODO)
8179     /* MPC8323E                                                              */
8180     POWERPC_DEF_SVR("MPC8323E",
8181                     CPU_POWERPC_MPC832x,      POWERPC_SVR_8323E,     e300),
8182 #endif
8183     /* MPC8343                                                               */
8184     POWERPC_DEF_SVR("MPC8343",
8185                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343,      e300),
8186     /* MPC8343A                                                              */
8187     POWERPC_DEF_SVR("MPC8343A",
8188                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343A,     e300),
8189     /* MPC8343E                                                              */
8190     POWERPC_DEF_SVR("MPC8343E",
8191                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343E,     e300),
8192     /* MPC8343EA                                                             */
8193     POWERPC_DEF_SVR("MPC8343EA",
8194                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8343EA,    e300),
8195     /* MPC8347                                                               */
8196     POWERPC_DEF_SVR("MPC8347",
8197                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347,      e300),
8198     /* MPC8347T                                                              */
8199     POWERPC_DEF_SVR("MPC8347T",
8200                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347T,     e300),
8201     /* MPC8347P                                                              */
8202     POWERPC_DEF_SVR("MPC8347P",
8203                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347P,     e300),
8204     /* MPC8347A                                                              */
8205     POWERPC_DEF_SVR("MPC8347A",
8206                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347A,     e300),
8207     /* MPC8347AT                                                             */
8208     POWERPC_DEF_SVR("MPC8347AT",
8209                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347AT,    e300),
8210     /* MPC8347AP                                                             */
8211     POWERPC_DEF_SVR("MPC8347AP",
8212                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347AP,    e300),
8213     /* MPC8347E                                                              */
8214     POWERPC_DEF_SVR("MPC8347E",
8215                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347E,     e300),
8216     /* MPC8347ET                                                             */
8217     POWERPC_DEF_SVR("MPC8347ET",
8218                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347ET,    e300),
8219     /* MPC8343EP                                                             */
8220     POWERPC_DEF_SVR("MPC8347EP",
8221                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EP,    e300),
8222     /* MPC8347EA                                                             */
8223     POWERPC_DEF_SVR("MPC8347EA",
8224                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EA,    e300),
8225     /* MPC8347EAT                                                            */
8226     POWERPC_DEF_SVR("MPC8347EAT",
8227                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EAT,   e300),
8228     /* MPC8343EAP                                                            */
8229     POWERPC_DEF_SVR("MPC8347EAP",
8230                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8347EAP,   e300),
8231     /* MPC8349                                                               */
8232     POWERPC_DEF_SVR("MPC8349",
8233                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349,      e300),
8234     /* MPC8349A                                                              */
8235     POWERPC_DEF_SVR("MPC8349A",
8236                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349A,     e300),
8237     /* MPC8349E                                                              */
8238     POWERPC_DEF_SVR("MPC8349E",
8239                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349E,     e300),
8240     /* MPC8349EA                                                             */
8241     POWERPC_DEF_SVR("MPC8349EA",
8242                     CPU_POWERPC_MPC834x,      POWERPC_SVR_8349EA,    e300),
8243 #if defined (TODO)
8244     /* MPC8358E                                                              */
8245     POWERPC_DEF_SVR("MPC8358E",
8246                     CPU_POWERPC_MPC835x,      POWERPC_SVR_8358E,     e300),
8247 #endif
8248 #if defined (TODO)
8249     /* MPC8360E                                                              */
8250     POWERPC_DEF_SVR("MPC8360E",
8251                     CPU_POWERPC_MPC836x,      POWERPC_SVR_8360E,     e300),
8252 #endif
8253     /* MPC8377                                                               */
8254     POWERPC_DEF_SVR("MPC8377",
8255                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8377,      e300),
8256     /* MPC8377E                                                              */
8257     POWERPC_DEF_SVR("MPC8377E",
8258                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8377E,     e300),
8259     /* MPC8378                                                               */
8260     POWERPC_DEF_SVR("MPC8378",
8261                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8378,      e300),
8262     /* MPC8378E                                                              */
8263     POWERPC_DEF_SVR("MPC8378E",
8264                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8378E,     e300),
8265     /* MPC8379                                                               */
8266     POWERPC_DEF_SVR("MPC8379",
8267                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8379,      e300),
8268     /* MPC8379E                                                              */
8269     POWERPC_DEF_SVR("MPC8379E",
8270                     CPU_POWERPC_MPC837x,      POWERPC_SVR_8379E,     e300),
8271     /* e500 family                                                           */
8272     /* PowerPC e500 core                                                     */
8273     POWERPC_DEF("e500",          CPU_POWERPC_e500v2_v22,             e500v2),
8274     /* PowerPC e500v1 core                                                   */
8275     POWERPC_DEF("e500v1",        CPU_POWERPC_e500v1,                 e500v1),
8276     /* PowerPC e500 v1.0 core                                                */
8277     POWERPC_DEF("e500_v10",      CPU_POWERPC_e500v1_v10,             e500v1),
8278     /* PowerPC e500 v2.0 core                                                */
8279     POWERPC_DEF("e500_v20",      CPU_POWERPC_e500v1_v20,             e500v1),
8280     /* PowerPC e500v2 core                                                   */
8281     POWERPC_DEF("e500v2",        CPU_POWERPC_e500v2,                 e500v2),
8282     /* PowerPC e500v2 v1.0 core                                              */
8283     POWERPC_DEF("e500v2_v10",    CPU_POWERPC_e500v2_v10,             e500v2),
8284     /* PowerPC e500v2 v2.0 core                                              */
8285     POWERPC_DEF("e500v2_v20",    CPU_POWERPC_e500v2_v20,             e500v2),
8286     /* PowerPC e500v2 v2.1 core                                              */
8287     POWERPC_DEF("e500v2_v21",    CPU_POWERPC_e500v2_v21,             e500v2),
8288     /* PowerPC e500v2 v2.2 core                                              */
8289     POWERPC_DEF("e500v2_v22",    CPU_POWERPC_e500v2_v22,             e500v2),
8290     /* PowerPC e500v2 v3.0 core                                              */
8291     POWERPC_DEF("e500v2_v30",    CPU_POWERPC_e500v2_v30,             e500v2),
8292     /* PowerPC e500 microcontrollers                                         */
8293     /* MPC8533                                                               */
8294     POWERPC_DEF_SVR("MPC8533",
8295                     CPU_POWERPC_MPC8533,      POWERPC_SVR_8533,      e500v2),
8296     /* MPC8533 v1.0                                                          */
8297     POWERPC_DEF_SVR("MPC8533_v10",
8298                     CPU_POWERPC_MPC8533_v10,  POWERPC_SVR_8533_v10,  e500v2),
8299     /* MPC8533 v1.1                                                          */
8300     POWERPC_DEF_SVR("MPC8533_v11",
8301                     CPU_POWERPC_MPC8533_v11,  POWERPC_SVR_8533_v11,  e500v2),
8302     /* MPC8533E                                                              */
8303     POWERPC_DEF_SVR("MPC8533E",
8304                     CPU_POWERPC_MPC8533E,     POWERPC_SVR_8533E,     e500v2),
8305     /* MPC8533E v1.0                                                         */
8306     POWERPC_DEF_SVR("MPC8533E_v10",
8307                     CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
8308     POWERPC_DEF_SVR("MPC8533E_v11",
8309                     CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
8310     /* MPC8540                                                               */
8311     POWERPC_DEF_SVR("MPC8540",
8312                     CPU_POWERPC_MPC8540,      POWERPC_SVR_8540,      e500v1),
8313     /* MPC8540 v1.0                                                          */
8314     POWERPC_DEF_SVR("MPC8540_v10",
8315                     CPU_POWERPC_MPC8540_v10,  POWERPC_SVR_8540_v10,  e500v1),
8316     /* MPC8540 v2.0                                                          */
8317     POWERPC_DEF_SVR("MPC8540_v20",
8318                     CPU_POWERPC_MPC8540_v20,  POWERPC_SVR_8540_v20,  e500v1),
8319     /* MPC8540 v2.1                                                          */
8320     POWERPC_DEF_SVR("MPC8540_v21",
8321                     CPU_POWERPC_MPC8540_v21,  POWERPC_SVR_8540_v21,  e500v1),
8322     /* MPC8541                                                               */
8323     POWERPC_DEF_SVR("MPC8541",
8324                     CPU_POWERPC_MPC8541,      POWERPC_SVR_8541,      e500v1),
8325     /* MPC8541 v1.0                                                          */
8326     POWERPC_DEF_SVR("MPC8541_v10",
8327                     CPU_POWERPC_MPC8541_v10,  POWERPC_SVR_8541_v10,  e500v1),
8328     /* MPC8541 v1.1                                                          */
8329     POWERPC_DEF_SVR("MPC8541_v11",
8330                     CPU_POWERPC_MPC8541_v11,  POWERPC_SVR_8541_v11,  e500v1),
8331     /* MPC8541E                                                              */
8332     POWERPC_DEF_SVR("MPC8541E",
8333                     CPU_POWERPC_MPC8541E,     POWERPC_SVR_8541E,     e500v1),
8334     /* MPC8541E v1.0                                                         */
8335     POWERPC_DEF_SVR("MPC8541E_v10",
8336                     CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
8337     /* MPC8541E v1.1                                                         */
8338     POWERPC_DEF_SVR("MPC8541E_v11",
8339                     CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
8340     /* MPC8543                                                               */
8341     POWERPC_DEF_SVR("MPC8543",
8342                     CPU_POWERPC_MPC8543,      POWERPC_SVR_8543,      e500v2),
8343     /* MPC8543 v1.0                                                          */
8344     POWERPC_DEF_SVR("MPC8543_v10",
8345                     CPU_POWERPC_MPC8543_v10,  POWERPC_SVR_8543_v10,  e500v2),
8346     /* MPC8543 v1.1                                                          */
8347     POWERPC_DEF_SVR("MPC8543_v11",
8348                     CPU_POWERPC_MPC8543_v11,  POWERPC_SVR_8543_v11,  e500v2),
8349     /* MPC8543 v2.0                                                          */
8350     POWERPC_DEF_SVR("MPC8543_v20",
8351                     CPU_POWERPC_MPC8543_v20,  POWERPC_SVR_8543_v20,  e500v2),
8352     /* MPC8543 v2.1                                                          */
8353     POWERPC_DEF_SVR("MPC8543_v21",
8354                     CPU_POWERPC_MPC8543_v21,  POWERPC_SVR_8543_v21,  e500v2),
8355     /* MPC8543E                                                              */
8356     POWERPC_DEF_SVR("MPC8543E",
8357                     CPU_POWERPC_MPC8543E,     POWERPC_SVR_8543E,     e500v2),
8358     /* MPC8543E v1.0                                                         */
8359     POWERPC_DEF_SVR("MPC8543E_v10",
8360                     CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
8361     /* MPC8543E v1.1                                                         */
8362     POWERPC_DEF_SVR("MPC8543E_v11",
8363                     CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
8364     /* MPC8543E v2.0                                                         */
8365     POWERPC_DEF_SVR("MPC8543E_v20",
8366                     CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
8367     /* MPC8543E v2.1                                                         */
8368     POWERPC_DEF_SVR("MPC8543E_v21",
8369                     CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
8370     /* MPC8544                                                               */
8371     POWERPC_DEF_SVR("MPC8544",
8372                     CPU_POWERPC_MPC8544,      POWERPC_SVR_8544,      e500v2),
8373     /* MPC8544 v1.0                                                          */
8374     POWERPC_DEF_SVR("MPC8544_v10",
8375                     CPU_POWERPC_MPC8544_v10,  POWERPC_SVR_8544_v10,  e500v2),
8376     /* MPC8544 v1.1                                                          */
8377     POWERPC_DEF_SVR("MPC8544_v11",
8378                     CPU_POWERPC_MPC8544_v11,  POWERPC_SVR_8544_v11,  e500v2),
8379     /* MPC8544E                                                              */
8380     POWERPC_DEF_SVR("MPC8544E",
8381                     CPU_POWERPC_MPC8544E,     POWERPC_SVR_8544E,     e500v2),
8382     /* MPC8544E v1.0                                                         */
8383     POWERPC_DEF_SVR("MPC8544E_v10",
8384                     CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
8385     /* MPC8544E v1.1                                                         */
8386     POWERPC_DEF_SVR("MPC8544E_v11",
8387                     CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
8388     /* MPC8545                                                               */
8389     POWERPC_DEF_SVR("MPC8545",
8390                     CPU_POWERPC_MPC8545,      POWERPC_SVR_8545,      e500v2),
8391     /* MPC8545 v2.0                                                          */
8392     POWERPC_DEF_SVR("MPC8545_v20",
8393                     CPU_POWERPC_MPC8545_v20,  POWERPC_SVR_8545_v20,  e500v2),
8394     /* MPC8545 v2.1                                                          */
8395     POWERPC_DEF_SVR("MPC8545_v21",
8396                     CPU_POWERPC_MPC8545_v21,  POWERPC_SVR_8545_v21,  e500v2),
8397     /* MPC8545E                                                              */
8398     POWERPC_DEF_SVR("MPC8545E",
8399                     CPU_POWERPC_MPC8545E,     POWERPC_SVR_8545E,     e500v2),
8400     /* MPC8545E v2.0                                                         */
8401     POWERPC_DEF_SVR("MPC8545E_v20",
8402                     CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
8403     /* MPC8545E v2.1                                                         */
8404     POWERPC_DEF_SVR("MPC8545E_v21",
8405                     CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
8406     /* MPC8547E                                                              */
8407     POWERPC_DEF_SVR("MPC8547E",
8408                     CPU_POWERPC_MPC8547E,     POWERPC_SVR_8547E,     e500v2),
8409     /* MPC8547E v2.0                                                         */
8410     POWERPC_DEF_SVR("MPC8547E_v20",
8411                     CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
8412     /* MPC8547E v2.1                                                         */
8413     POWERPC_DEF_SVR("MPC8547E_v21",
8414                     CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
8415     /* MPC8548                                                               */
8416     POWERPC_DEF_SVR("MPC8548",
8417                     CPU_POWERPC_MPC8548,      POWERPC_SVR_8548,      e500v2),
8418     /* MPC8548 v1.0                                                          */
8419     POWERPC_DEF_SVR("MPC8548_v10",
8420                     CPU_POWERPC_MPC8548_v10,  POWERPC_SVR_8548_v10,  e500v2),
8421     /* MPC8548 v1.1                                                          */
8422     POWERPC_DEF_SVR("MPC8548_v11",
8423                     CPU_POWERPC_MPC8548_v11,  POWERPC_SVR_8548_v11,  e500v2),
8424     /* MPC8548 v2.0                                                          */
8425     POWERPC_DEF_SVR("MPC8548_v20",
8426                     CPU_POWERPC_MPC8548_v20,  POWERPC_SVR_8548_v20,  e500v2),
8427     /* MPC8548 v2.1                                                          */
8428     POWERPC_DEF_SVR("MPC8548_v21",
8429                     CPU_POWERPC_MPC8548_v21,  POWERPC_SVR_8548_v21,  e500v2),
8430     /* MPC8548E                                                              */
8431     POWERPC_DEF_SVR("MPC8548E",
8432                     CPU_POWERPC_MPC8548E,     POWERPC_SVR_8548E,     e500v2),
8433     /* MPC8548E v1.0                                                         */
8434     POWERPC_DEF_SVR("MPC8548E_v10",
8435                     CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
8436     /* MPC8548E v1.1                                                         */
8437     POWERPC_DEF_SVR("MPC8548E_v11",
8438                     CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
8439     /* MPC8548E v2.0                                                         */
8440     POWERPC_DEF_SVR("MPC8548E_v20",
8441                     CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
8442     /* MPC8548E v2.1                                                         */
8443     POWERPC_DEF_SVR("MPC8548E_v21",
8444                     CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
8445     /* MPC8555                                                               */
8446     POWERPC_DEF_SVR("MPC8555",
8447                     CPU_POWERPC_MPC8555,      POWERPC_SVR_8555,      e500v2),
8448     /* MPC8555 v1.0                                                          */
8449     POWERPC_DEF_SVR("MPC8555_v10",
8450                     CPU_POWERPC_MPC8555_v10,  POWERPC_SVR_8555_v10,  e500v2),
8451     /* MPC8555 v1.1                                                          */
8452     POWERPC_DEF_SVR("MPC8555_v11",
8453                     CPU_POWERPC_MPC8555_v11,  POWERPC_SVR_8555_v11,  e500v2),
8454     /* MPC8555E                                                              */
8455     POWERPC_DEF_SVR("MPC8555E",
8456                     CPU_POWERPC_MPC8555E,     POWERPC_SVR_8555E,     e500v2),
8457     /* MPC8555E v1.0                                                         */
8458     POWERPC_DEF_SVR("MPC8555E_v10",
8459                     CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
8460     /* MPC8555E v1.1                                                         */
8461     POWERPC_DEF_SVR("MPC8555E_v11",
8462                     CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
8463     /* MPC8560                                                               */
8464     POWERPC_DEF_SVR("MPC8560",
8465                     CPU_POWERPC_MPC8560,      POWERPC_SVR_8560,      e500v2),
8466     /* MPC8560 v1.0                                                          */
8467     POWERPC_DEF_SVR("MPC8560_v10",
8468                     CPU_POWERPC_MPC8560_v10,  POWERPC_SVR_8560_v10,  e500v2),
8469     /* MPC8560 v2.0                                                          */
8470     POWERPC_DEF_SVR("MPC8560_v20",
8471                     CPU_POWERPC_MPC8560_v20,  POWERPC_SVR_8560_v20,  e500v2),
8472     /* MPC8560 v2.1                                                          */
8473     POWERPC_DEF_SVR("MPC8560_v21",
8474                     CPU_POWERPC_MPC8560_v21,  POWERPC_SVR_8560_v21,  e500v2),
8475     /* MPC8567                                                               */
8476     POWERPC_DEF_SVR("MPC8567",
8477                     CPU_POWERPC_MPC8567,      POWERPC_SVR_8567,      e500v2),
8478     /* MPC8567E                                                              */
8479     POWERPC_DEF_SVR("MPC8567E",
8480                     CPU_POWERPC_MPC8567E,     POWERPC_SVR_8567E,     e500v2),
8481     /* MPC8568                                                               */
8482     POWERPC_DEF_SVR("MPC8568",
8483                     CPU_POWERPC_MPC8568,      POWERPC_SVR_8568,      e500v2),
8484     /* MPC8568E                                                              */
8485     POWERPC_DEF_SVR("MPC8568E",
8486                     CPU_POWERPC_MPC8568E,     POWERPC_SVR_8568E,     e500v2),
8487     /* MPC8572                                                               */
8488     POWERPC_DEF_SVR("MPC8572",
8489                     CPU_POWERPC_MPC8572,      POWERPC_SVR_8572,      e500v2),
8490     /* MPC8572E                                                              */
8491     POWERPC_DEF_SVR("MPC8572E",
8492                     CPU_POWERPC_MPC8572E,     POWERPC_SVR_8572E,     e500v2),
8493     /* e600 family                                                           */
8494     /* PowerPC e600 core                                                     */
8495     POWERPC_DEF("e600",          CPU_POWERPC_e600,                   7400),
8496     /* PowerPC e600 microcontrollers                                         */
8497 #if defined (TODO)
8498     /* MPC8610                                                               */
8499     POWERPC_DEF_SVR("MPC8610",
8500                     CPU_POWERPC_MPC8610,      POWERPC_SVR_8610,      7400),
8501 #endif
8502     /* MPC8641                                                               */
8503     POWERPC_DEF_SVR("MPC8641",
8504                     CPU_POWERPC_MPC8641,      POWERPC_SVR_8641,      7400),
8505     /* MPC8641D                                                              */
8506     POWERPC_DEF_SVR("MPC8641D",
8507                     CPU_POWERPC_MPC8641D,     POWERPC_SVR_8641D,     7400),
8508     /* 32 bits "classic" PowerPC                                             */
8509     /* PowerPC 6xx family                                                    */
8510     /* PowerPC 601                                                           */
8511     POWERPC_DEF("601",           CPU_POWERPC_601,                    601v),
8512     /* PowerPC 601v0                                                         */
8513     POWERPC_DEF("601_v0",        CPU_POWERPC_601_v0,                 601),
8514     /* PowerPC 601v1                                                         */
8515     POWERPC_DEF("601_v1",        CPU_POWERPC_601_v1,                 601),
8516     /* PowerPC 601v                                                          */
8517     POWERPC_DEF("601v",          CPU_POWERPC_601v,                   601v),
8518     /* PowerPC 601v2                                                         */
8519     POWERPC_DEF("601_v2",        CPU_POWERPC_601_v2,                 601v),
8520     /* PowerPC 602                                                           */
8521     POWERPC_DEF("602",           CPU_POWERPC_602,                    602),
8522     /* PowerPC 603                                                           */
8523     POWERPC_DEF("603",           CPU_POWERPC_603,                    603),
8524     /* Code name for PowerPC 603                                             */
8525     POWERPC_DEF("Vanilla",       CPU_POWERPC_603,                    603),
8526     /* PowerPC 603e (aka PID6)                                               */
8527     POWERPC_DEF("603e",          CPU_POWERPC_603E,                   603E),
8528     /* Code name for PowerPC 603e                                            */
8529     POWERPC_DEF("Stretch",       CPU_POWERPC_603E,                   603E),
8530     /* PowerPC 603e v1.1                                                     */
8531     POWERPC_DEF("603e_v1.1",     CPU_POWERPC_603E_v11,               603E),
8532     /* PowerPC 603e v1.2                                                     */
8533     POWERPC_DEF("603e_v1.2",     CPU_POWERPC_603E_v12,               603E),
8534     /* PowerPC 603e v1.3                                                     */
8535     POWERPC_DEF("603e_v1.3",     CPU_POWERPC_603E_v13,               603E),
8536     /* PowerPC 603e v1.4                                                     */
8537     POWERPC_DEF("603e_v1.4",     CPU_POWERPC_603E_v14,               603E),
8538     /* PowerPC 603e v2.2                                                     */
8539     POWERPC_DEF("603e_v2.2",     CPU_POWERPC_603E_v22,               603E),
8540     /* PowerPC 603e v3                                                       */
8541     POWERPC_DEF("603e_v3",       CPU_POWERPC_603E_v3,                603E),
8542     /* PowerPC 603e v4                                                       */
8543     POWERPC_DEF("603e_v4",       CPU_POWERPC_603E_v4,                603E),
8544     /* PowerPC 603e v4.1                                                     */
8545     POWERPC_DEF("603e_v4.1",     CPU_POWERPC_603E_v41,               603E),
8546     /* PowerPC 603e (aka PID7)                                               */
8547     POWERPC_DEF("603e7",         CPU_POWERPC_603E7,                  603E),
8548     /* PowerPC 603e7t                                                        */
8549     POWERPC_DEF("603e7t",        CPU_POWERPC_603E7t,                 603E),
8550     /* PowerPC 603e7v                                                        */
8551     POWERPC_DEF("603e7v",        CPU_POWERPC_603E7v,                 603E),
8552     /* Code name for PowerPC 603ev                                           */
8553     POWERPC_DEF("Vaillant",      CPU_POWERPC_603E7v,                 603E),
8554     /* PowerPC 603e7v1                                                       */
8555     POWERPC_DEF("603e7v1",       CPU_POWERPC_603E7v1,                603E),
8556     /* PowerPC 603e7v2                                                       */
8557     POWERPC_DEF("603e7v2",       CPU_POWERPC_603E7v2,                603E),
8558     /* PowerPC 603p (aka PID7v)                                              */
8559     POWERPC_DEF("603p",          CPU_POWERPC_603P,                   603E),
8560     /* PowerPC 603r (aka PID7t)                                              */
8561     POWERPC_DEF("603r",          CPU_POWERPC_603R,                   603E),
8562     /* Code name for PowerPC 603r                                            */
8563     POWERPC_DEF("Goldeneye",     CPU_POWERPC_603R,                   603E),
8564     /* PowerPC 604                                                           */
8565     POWERPC_DEF("604",           CPU_POWERPC_604,                    604),
8566     /* PowerPC 604e (aka PID9)                                               */
8567     POWERPC_DEF("604e",          CPU_POWERPC_604E,                   604E),
8568     /* Code name for PowerPC 604e                                            */
8569     POWERPC_DEF("Sirocco",       CPU_POWERPC_604E,                   604E),
8570     /* PowerPC 604e v1.0                                                     */
8571     POWERPC_DEF("604e_v1.0",     CPU_POWERPC_604E_v10,               604E),
8572     /* PowerPC 604e v2.2                                                     */
8573     POWERPC_DEF("604e_v2.2",     CPU_POWERPC_604E_v22,               604E),
8574     /* PowerPC 604e v2.4                                                     */
8575     POWERPC_DEF("604e_v2.4",     CPU_POWERPC_604E_v24,               604E),
8576     /* PowerPC 604r (aka PIDA)                                               */
8577     POWERPC_DEF("604r",          CPU_POWERPC_604R,                   604E),
8578     /* Code name for PowerPC 604r                                            */
8579     POWERPC_DEF("Mach5",         CPU_POWERPC_604R,                   604E),
8580 #if defined(TODO)
8581     /* PowerPC 604ev                                                         */
8582     POWERPC_DEF("604ev",         CPU_POWERPC_604EV,                  604E),
8583 #endif
8584     /* PowerPC 7xx family                                                    */
8585     /* Generic PowerPC 740 (G3)                                              */
8586     POWERPC_DEF("740",           CPU_POWERPC_7x0,                    740),
8587     /* Code name for PowerPC 740                                             */
8588     POWERPC_DEF("Arthur",        CPU_POWERPC_7x0,                    740),
8589     /* Generic PowerPC 750 (G3)                                              */
8590     POWERPC_DEF("750",           CPU_POWERPC_7x0,                    750),
8591     /* Code name for PowerPC 750                                             */
8592     POWERPC_DEF("Typhoon",       CPU_POWERPC_7x0,                    750),
8593     /* PowerPC 740/750 is also known as G3                                   */
8594     POWERPC_DEF("G3",            CPU_POWERPC_7x0,                    750),
8595     /* PowerPC 740 v1.0 (G3)                                                 */
8596     POWERPC_DEF("740_v1.0",      CPU_POWERPC_7x0_v10,                740),
8597     /* PowerPC 750 v1.0 (G3)                                                 */
8598     POWERPC_DEF("750_v1.0",      CPU_POWERPC_7x0_v10,                750),
8599     /* PowerPC 740 v2.0 (G3)                                                 */
8600     POWERPC_DEF("740_v2.0",      CPU_POWERPC_7x0_v20,                740),
8601     /* PowerPC 750 v2.0 (G3)                                                 */
8602     POWERPC_DEF("750_v2.0",      CPU_POWERPC_7x0_v20,                750),
8603     /* PowerPC 740 v2.1 (G3)                                                 */
8604     POWERPC_DEF("740_v2.1",      CPU_POWERPC_7x0_v21,                740),
8605     /* PowerPC 750 v2.1 (G3)                                                 */
8606     POWERPC_DEF("750_v2.1",      CPU_POWERPC_7x0_v21,                750),
8607     /* PowerPC 740 v2.2 (G3)                                                 */
8608     POWERPC_DEF("740_v2.2",      CPU_POWERPC_7x0_v22,                740),
8609     /* PowerPC 750 v2.2 (G3)                                                 */
8610     POWERPC_DEF("750_v2.2",      CPU_POWERPC_7x0_v22,                750),
8611     /* PowerPC 740 v3.0 (G3)                                                 */
8612     POWERPC_DEF("740_v3.0",      CPU_POWERPC_7x0_v30,                740),
8613     /* PowerPC 750 v3.0 (G3)                                                 */
8614     POWERPC_DEF("750_v3.0",      CPU_POWERPC_7x0_v30,                750),
8615     /* PowerPC 740 v3.1 (G3)                                                 */
8616     POWERPC_DEF("740_v3.1",      CPU_POWERPC_7x0_v31,                740),
8617     /* PowerPC 750 v3.1 (G3)                                                 */
8618     POWERPC_DEF("750_v3.1",      CPU_POWERPC_7x0_v31,                750),
8619     /* PowerPC 740E (G3)                                                     */
8620     POWERPC_DEF("740e",          CPU_POWERPC_740E,                   740),
8621     /* PowerPC 750E (G3)                                                     */
8622     POWERPC_DEF("750e",          CPU_POWERPC_750E,                   750),
8623     /* PowerPC 740P (G3)                                                     */
8624     POWERPC_DEF("740p",          CPU_POWERPC_7x0P,                   740),
8625     /* PowerPC 750P (G3)                                                     */
8626     POWERPC_DEF("750p",          CPU_POWERPC_7x0P,                   750),
8627     /* Code name for PowerPC 740P/750P (G3)                                  */
8628     POWERPC_DEF("Conan/Doyle",   CPU_POWERPC_7x0P,                   750),
8629     /* PowerPC 750CL (G3 embedded)                                           */
8630     POWERPC_DEF("750cl",         CPU_POWERPC_750CL,                  750cl),
8631     /* PowerPC 750CL v1.0                                                    */
8632     POWERPC_DEF("750cl_v1.0",    CPU_POWERPC_750CL_v10,              750cl),
8633     /* PowerPC 750CL v2.0                                                    */
8634     POWERPC_DEF("750cl_v2.0",    CPU_POWERPC_750CL_v20,              750cl),
8635     /* PowerPC 750CX (G3 embedded)                                           */
8636     POWERPC_DEF("750cx",         CPU_POWERPC_750CX,                  750cx),
8637     /* PowerPC 750CX v1.0 (G3 embedded)                                      */
8638     POWERPC_DEF("750cx_v1.0",    CPU_POWERPC_750CX_v10,              750cx),
8639     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
8640     POWERPC_DEF("750cx_v2.0",    CPU_POWERPC_750CX_v20,              750cx),
8641     /* PowerPC 750CX v2.1 (G3 embedded)                                      */
8642     POWERPC_DEF("750cx_v2.1",    CPU_POWERPC_750CX_v21,              750cx),
8643     /* PowerPC 750CX v2.2 (G3 embedded)                                      */
8644     POWERPC_DEF("750cx_v2.2",    CPU_POWERPC_750CX_v22,              750cx),
8645     /* PowerPC 750CXe (G3 embedded)                                          */
8646     POWERPC_DEF("750cxe",        CPU_POWERPC_750CXE,                 750cx),
8647     /* PowerPC 750CXe v2.1 (G3 embedded)                                     */
8648     POWERPC_DEF("750cxe_v2.1",   CPU_POWERPC_750CXE_v21,             750cx),
8649     /* PowerPC 750CXe v2.2 (G3 embedded)                                     */
8650     POWERPC_DEF("750cxe_v2.2",   CPU_POWERPC_750CXE_v22,             750cx),
8651     /* PowerPC 750CXe v2.3 (G3 embedded)                                     */
8652     POWERPC_DEF("750cxe_v2.3",   CPU_POWERPC_750CXE_v23,             750cx),
8653     /* PowerPC 750CXe v2.4 (G3 embedded)                                     */
8654     POWERPC_DEF("750cxe_v2.4",   CPU_POWERPC_750CXE_v24,             750cx),
8655     /* PowerPC 750CXe v2.4b (G3 embedded)                                    */
8656     POWERPC_DEF("750cxe_v2.4b",  CPU_POWERPC_750CXE_v24b,            750cx),
8657     /* PowerPC 750CXe v3.0 (G3 embedded)                                     */
8658     POWERPC_DEF("750cxe_v3.0",   CPU_POWERPC_750CXE_v30,             750cx),
8659     /* PowerPC 750CXe v3.1 (G3 embedded)                                     */
8660     POWERPC_DEF("750cxe_v3.1",   CPU_POWERPC_750CXE_v31,             750cx),
8661     /* PowerPC 750CXe v3.1b (G3 embedded)                                    */
8662     POWERPC_DEF("750cxe_v3.1b",  CPU_POWERPC_750CXE_v31b,            750cx),
8663     /* PowerPC 750CXr (G3 embedded)                                          */
8664     POWERPC_DEF("750cxr",        CPU_POWERPC_750CXR,                 750cx),
8665     /* PowerPC 750FL (G3 embedded)                                           */
8666     POWERPC_DEF("750fl",         CPU_POWERPC_750FL,                  750fx),
8667     /* PowerPC 750FX (G3 embedded)                                           */
8668     POWERPC_DEF("750fx",         CPU_POWERPC_750FX,                  750fx),
8669     /* PowerPC 750FX v1.0 (G3 embedded)                                      */
8670     POWERPC_DEF("750fx_v1.0",    CPU_POWERPC_750FX_v10,              750fx),
8671     /* PowerPC 750FX v2.0 (G3 embedded)                                      */
8672     POWERPC_DEF("750fx_v2.0",    CPU_POWERPC_750FX_v20,              750fx),
8673     /* PowerPC 750FX v2.1 (G3 embedded)                                      */
8674     POWERPC_DEF("750fx_v2.1",    CPU_POWERPC_750FX_v21,              750fx),
8675     /* PowerPC 750FX v2.2 (G3 embedded)                                      */
8676     POWERPC_DEF("750fx_v2.2",    CPU_POWERPC_750FX_v22,              750fx),
8677     /* PowerPC 750FX v2.3 (G3 embedded)                                      */
8678     POWERPC_DEF("750fx_v2.3",    CPU_POWERPC_750FX_v23,              750fx),
8679     /* PowerPC 750GL (G3 embedded)                                           */
8680     POWERPC_DEF("750gl",         CPU_POWERPC_750GL,                  750gx),
8681     /* PowerPC 750GX (G3 embedded)                                           */
8682     POWERPC_DEF("750gx",         CPU_POWERPC_750GX,                  750gx),
8683     /* PowerPC 750GX v1.0 (G3 embedded)                                      */
8684     POWERPC_DEF("750gx_v1.0",    CPU_POWERPC_750GX_v10,              750gx),
8685     /* PowerPC 750GX v1.1 (G3 embedded)                                      */
8686     POWERPC_DEF("750gx_v1.1",    CPU_POWERPC_750GX_v11,              750gx),
8687     /* PowerPC 750GX v1.2 (G3 embedded)                                      */
8688     POWERPC_DEF("750gx_v1.2",    CPU_POWERPC_750GX_v12,              750gx),
8689     /* PowerPC 750L (G3 embedded)                                            */
8690     POWERPC_DEF("750l",          CPU_POWERPC_750L,                   750),
8691     /* Code name for PowerPC 750L (G3 embedded)                              */
8692     POWERPC_DEF("LoneStar",      CPU_POWERPC_750L,                   750),
8693     /* PowerPC 750L v2.0 (G3 embedded)                                       */
8694     POWERPC_DEF("750l_v2.0",     CPU_POWERPC_750L_v20,               750),
8695     /* PowerPC 750L v2.1 (G3 embedded)                                       */
8696     POWERPC_DEF("750l_v2.1",     CPU_POWERPC_750L_v21,               750),
8697     /* PowerPC 750L v2.2 (G3 embedded)                                       */
8698     POWERPC_DEF("750l_v2.2",     CPU_POWERPC_750L_v22,               750),
8699     /* PowerPC 750L v3.0 (G3 embedded)                                       */
8700     POWERPC_DEF("750l_v3.0",     CPU_POWERPC_750L_v30,               750),
8701     /* PowerPC 750L v3.2 (G3 embedded)                                       */
8702     POWERPC_DEF("750l_v3.2",     CPU_POWERPC_750L_v32,               750),
8703     /* Generic PowerPC 745                                                   */
8704     POWERPC_DEF("745",           CPU_POWERPC_7x5,                    745),
8705     /* Generic PowerPC 755                                                   */
8706     POWERPC_DEF("755",           CPU_POWERPC_7x5,                    755),
8707     /* Code name for PowerPC 745/755                                         */
8708     POWERPC_DEF("Goldfinger",    CPU_POWERPC_7x5,                    755),
8709     /* PowerPC 745 v1.0                                                      */
8710     POWERPC_DEF("745_v1.0",      CPU_POWERPC_7x5_v10,                745),
8711     /* PowerPC 755 v1.0                                                      */
8712     POWERPC_DEF("755_v1.0",      CPU_POWERPC_7x5_v10,                755),
8713     /* PowerPC 745 v1.1                                                      */
8714     POWERPC_DEF("745_v1.1",      CPU_POWERPC_7x5_v11,                745),
8715     /* PowerPC 755 v1.1                                                      */
8716     POWERPC_DEF("755_v1.1",      CPU_POWERPC_7x5_v11,                755),
8717     /* PowerPC 745 v2.0                                                      */
8718     POWERPC_DEF("745_v2.0",      CPU_POWERPC_7x5_v20,                745),
8719     /* PowerPC 755 v2.0                                                      */
8720     POWERPC_DEF("755_v2.0",      CPU_POWERPC_7x5_v20,                755),
8721     /* PowerPC 745 v2.1                                                      */
8722     POWERPC_DEF("745_v2.1",      CPU_POWERPC_7x5_v21,                745),
8723     /* PowerPC 755 v2.1                                                      */
8724     POWERPC_DEF("755_v2.1",      CPU_POWERPC_7x5_v21,                755),
8725     /* PowerPC 745 v2.2                                                      */
8726     POWERPC_DEF("745_v2.2",      CPU_POWERPC_7x5_v22,                745),
8727     /* PowerPC 755 v2.2                                                      */
8728     POWERPC_DEF("755_v2.2",      CPU_POWERPC_7x5_v22,                755),
8729     /* PowerPC 745 v2.3                                                      */
8730     POWERPC_DEF("745_v2.3",      CPU_POWERPC_7x5_v23,                745),
8731     /* PowerPC 755 v2.3                                                      */
8732     POWERPC_DEF("755_v2.3",      CPU_POWERPC_7x5_v23,                755),
8733     /* PowerPC 745 v2.4                                                      */
8734     POWERPC_DEF("745_v2.4",      CPU_POWERPC_7x5_v24,                745),
8735     /* PowerPC 755 v2.4                                                      */
8736     POWERPC_DEF("755_v2.4",      CPU_POWERPC_7x5_v24,                755),
8737     /* PowerPC 745 v2.5                                                      */
8738     POWERPC_DEF("745_v2.5",      CPU_POWERPC_7x5_v25,                745),
8739     /* PowerPC 755 v2.5                                                      */
8740     POWERPC_DEF("755_v2.5",      CPU_POWERPC_7x5_v25,                755),
8741     /* PowerPC 745 v2.6                                                      */
8742     POWERPC_DEF("745_v2.6",      CPU_POWERPC_7x5_v26,                745),
8743     /* PowerPC 755 v2.6                                                      */
8744     POWERPC_DEF("755_v2.6",      CPU_POWERPC_7x5_v26,                755),
8745     /* PowerPC 745 v2.7                                                      */
8746     POWERPC_DEF("745_v2.7",      CPU_POWERPC_7x5_v27,                745),
8747     /* PowerPC 755 v2.7                                                      */
8748     POWERPC_DEF("755_v2.7",      CPU_POWERPC_7x5_v27,                755),
8749     /* PowerPC 745 v2.8                                                      */
8750     POWERPC_DEF("745_v2.8",      CPU_POWERPC_7x5_v28,                745),
8751     /* PowerPC 755 v2.8                                                      */
8752     POWERPC_DEF("755_v2.8",      CPU_POWERPC_7x5_v28,                755),
8753 #if defined (TODO)
8754     /* PowerPC 745P (G3)                                                     */
8755     POWERPC_DEF("745p",          CPU_POWERPC_7x5P,                   745),
8756     /* PowerPC 755P (G3)                                                     */
8757     POWERPC_DEF("755p",          CPU_POWERPC_7x5P,                   755),
8758 #endif
8759     /* PowerPC 74xx family                                                   */
8760     /* PowerPC 7400 (G4)                                                     */
8761     POWERPC_DEF("7400",          CPU_POWERPC_7400,                   7400),
8762     /* Code name for PowerPC 7400                                            */
8763     POWERPC_DEF("Max",           CPU_POWERPC_7400,                   7400),
8764     /* PowerPC 74xx is also well known as G4                                 */
8765     POWERPC_DEF("G4",            CPU_POWERPC_7400,                   7400),
8766     /* PowerPC 7400 v1.0 (G4)                                                */
8767     POWERPC_DEF("7400_v1.0",     CPU_POWERPC_7400_v10,               7400),
8768     /* PowerPC 7400 v1.1 (G4)                                                */
8769     POWERPC_DEF("7400_v1.1",     CPU_POWERPC_7400_v11,               7400),
8770     /* PowerPC 7400 v2.0 (G4)                                                */
8771     POWERPC_DEF("7400_v2.0",     CPU_POWERPC_7400_v20,               7400),
8772     /* PowerPC 7400 v2.1 (G4)                                                */
8773     POWERPC_DEF("7400_v2.1",     CPU_POWERPC_7400_v21,               7400),
8774     /* PowerPC 7400 v2.2 (G4)                                                */
8775     POWERPC_DEF("7400_v2.2",     CPU_POWERPC_7400_v22,               7400),
8776     /* PowerPC 7400 v2.6 (G4)                                                */
8777     POWERPC_DEF("7400_v2.6",     CPU_POWERPC_7400_v26,               7400),
8778     /* PowerPC 7400 v2.7 (G4)                                                */
8779     POWERPC_DEF("7400_v2.7",     CPU_POWERPC_7400_v27,               7400),
8780     /* PowerPC 7400 v2.8 (G4)                                                */
8781     POWERPC_DEF("7400_v2.8",     CPU_POWERPC_7400_v28,               7400),
8782     /* PowerPC 7400 v2.9 (G4)                                                */
8783     POWERPC_DEF("7400_v2.9",     CPU_POWERPC_7400_v29,               7400),
8784     /* PowerPC 7410 (G4)                                                     */
8785     POWERPC_DEF("7410",          CPU_POWERPC_7410,                   7410),
8786     /* Code name for PowerPC 7410                                            */
8787     POWERPC_DEF("Nitro",         CPU_POWERPC_7410,                   7410),
8788     /* PowerPC 7410 v1.0 (G4)                                                */
8789     POWERPC_DEF("7410_v1.0",     CPU_POWERPC_7410_v10,               7410),
8790     /* PowerPC 7410 v1.1 (G4)                                                */
8791     POWERPC_DEF("7410_v1.1",     CPU_POWERPC_7410_v11,               7410),
8792     /* PowerPC 7410 v1.2 (G4)                                                */
8793     POWERPC_DEF("7410_v1.2",     CPU_POWERPC_7410_v12,               7410),
8794     /* PowerPC 7410 v1.3 (G4)                                                */
8795     POWERPC_DEF("7410_v1.3",     CPU_POWERPC_7410_v13,               7410),
8796     /* PowerPC 7410 v1.4 (G4)                                                */
8797     POWERPC_DEF("7410_v1.4",     CPU_POWERPC_7410_v14,               7410),
8798     /* PowerPC 7448 (G4)                                                     */
8799     POWERPC_DEF("7448",          CPU_POWERPC_7448,                   7400),
8800     /* PowerPC 7448 v1.0 (G4)                                                */
8801     POWERPC_DEF("7448_v1.0",     CPU_POWERPC_7448_v10,               7400),
8802     /* PowerPC 7448 v1.1 (G4)                                                */
8803     POWERPC_DEF("7448_v1.1",     CPU_POWERPC_7448_v11,               7400),
8804     /* PowerPC 7448 v2.0 (G4)                                                */
8805     POWERPC_DEF("7448_v2.0",     CPU_POWERPC_7448_v20,               7400),
8806     /* PowerPC 7448 v2.1 (G4)                                                */
8807     POWERPC_DEF("7448_v2.1",     CPU_POWERPC_7448_v21,               7400),
8808     /* PowerPC 7450 (G4)                                                     */
8809     POWERPC_DEF("7450",          CPU_POWERPC_7450,                   7450),
8810     /* Code name for PowerPC 7450                                            */
8811     POWERPC_DEF("Vger",          CPU_POWERPC_7450,                   7450),
8812     /* PowerPC 7450 v1.0 (G4)                                                */
8813     POWERPC_DEF("7450_v1.0",     CPU_POWERPC_7450_v10,               7450),
8814     /* PowerPC 7450 v1.1 (G4)                                                */
8815     POWERPC_DEF("7450_v1.1",     CPU_POWERPC_7450_v11,               7450),
8816     /* PowerPC 7450 v1.2 (G4)                                                */
8817     POWERPC_DEF("7450_v1.2",     CPU_POWERPC_7450_v12,               7450),
8818     /* PowerPC 7450 v2.0 (G4)                                                */
8819     POWERPC_DEF("7450_v2.0",     CPU_POWERPC_7450_v20,               7450),
8820     /* PowerPC 7450 v2.1 (G4)                                                */
8821     POWERPC_DEF("7450_v2.1",     CPU_POWERPC_7450_v21,               7450),
8822     /* PowerPC 7441 (G4)                                                     */
8823     POWERPC_DEF("7441",          CPU_POWERPC_74x1,                   7440),
8824     /* PowerPC 7451 (G4)                                                     */
8825     POWERPC_DEF("7451",          CPU_POWERPC_74x1,                   7450),
8826     /* PowerPC 7441 v2.1 (G4)                                                */
8827     POWERPC_DEF("7441_v2.1",     CPU_POWERPC_7450_v21,               7440),
8828     /* PowerPC 7441 v2.3 (G4)                                                */
8829     POWERPC_DEF("7441_v2.3",     CPU_POWERPC_74x1_v23,               7440),
8830     /* PowerPC 7451 v2.3 (G4)                                                */
8831     POWERPC_DEF("7451_v2.3",     CPU_POWERPC_74x1_v23,               7450),
8832     /* PowerPC 7441 v2.10 (G4)                                                */
8833     POWERPC_DEF("7441_v2.10",    CPU_POWERPC_74x1_v210,              7440),
8834     /* PowerPC 7451 v2.10 (G4)                                               */
8835     POWERPC_DEF("7451_v2.10",    CPU_POWERPC_74x1_v210,              7450),
8836     /* PowerPC 7445 (G4)                                                     */
8837     POWERPC_DEF("7445",          CPU_POWERPC_74x5,                   7445),
8838     /* PowerPC 7455 (G4)                                                     */
8839     POWERPC_DEF("7455",          CPU_POWERPC_74x5,                   7455),
8840     /* Code name for PowerPC 7445/7455                                       */
8841     POWERPC_DEF("Apollo6",       CPU_POWERPC_74x5,                   7455),
8842     /* PowerPC 7445 v1.0 (G4)                                                */
8843     POWERPC_DEF("7445_v1.0",     CPU_POWERPC_74x5_v10,               7445),
8844     /* PowerPC 7455 v1.0 (G4)                                                */
8845     POWERPC_DEF("7455_v1.0",     CPU_POWERPC_74x5_v10,               7455),
8846     /* PowerPC 7445 v2.1 (G4)                                                */
8847     POWERPC_DEF("7445_v2.1",     CPU_POWERPC_74x5_v21,               7445),
8848     /* PowerPC 7455 v2.1 (G4)                                                */
8849     POWERPC_DEF("7455_v2.1",     CPU_POWERPC_74x5_v21,               7455),
8850     /* PowerPC 7445 v3.2 (G4)                                                */
8851     POWERPC_DEF("7445_v3.2",     CPU_POWERPC_74x5_v32,               7445),
8852     /* PowerPC 7455 v3.2 (G4)                                                */
8853     POWERPC_DEF("7455_v3.2",     CPU_POWERPC_74x5_v32,               7455),
8854     /* PowerPC 7445 v3.3 (G4)                                                */
8855     POWERPC_DEF("7445_v3.3",     CPU_POWERPC_74x5_v33,               7445),
8856     /* PowerPC 7455 v3.3 (G4)                                                */
8857     POWERPC_DEF("7455_v3.3",     CPU_POWERPC_74x5_v33,               7455),
8858     /* PowerPC 7445 v3.4 (G4)                                                */
8859     POWERPC_DEF("7445_v3.4",     CPU_POWERPC_74x5_v34,               7445),
8860     /* PowerPC 7455 v3.4 (G4)                                                */
8861     POWERPC_DEF("7455_v3.4",     CPU_POWERPC_74x5_v34,               7455),
8862     /* PowerPC 7447 (G4)                                                     */
8863     POWERPC_DEF("7447",          CPU_POWERPC_74x7,                   7445),
8864     /* PowerPC 7457 (G4)                                                     */
8865     POWERPC_DEF("7457",          CPU_POWERPC_74x7,                   7455),
8866     /* Code name for PowerPC 7447/7457                                       */
8867     POWERPC_DEF("Apollo7",       CPU_POWERPC_74x7,                   7455),
8868     /* PowerPC 7447 v1.0 (G4)                                                */
8869     POWERPC_DEF("7447_v1.0",     CPU_POWERPC_74x7_v10,               7445),
8870     /* PowerPC 7457 v1.0 (G4)                                                */
8871     POWERPC_DEF("7457_v1.0",     CPU_POWERPC_74x7_v10,               7455),
8872     /* PowerPC 7447 v1.1 (G4)                                                */
8873     POWERPC_DEF("7447_v1.1",     CPU_POWERPC_74x7_v11,               7445),
8874     /* PowerPC 7457 v1.1 (G4)                                                */
8875     POWERPC_DEF("7457_v1.1",     CPU_POWERPC_74x7_v11,               7455),
8876     /* PowerPC 7457 v1.2 (G4)                                                */
8877     POWERPC_DEF("7457_v1.2",     CPU_POWERPC_74x7_v12,               7455),
8878     /* PowerPC 7447A (G4)                                                    */
8879     POWERPC_DEF("7447A",         CPU_POWERPC_74x7A,                  7445),
8880     /* PowerPC 7457A (G4)                                                    */
8881     POWERPC_DEF("7457A",         CPU_POWERPC_74x7A,                  7455),
8882     /* PowerPC 7447A v1.0 (G4)                                               */
8883     POWERPC_DEF("7447A_v1.0",    CPU_POWERPC_74x7A_v10,              7445),
8884     /* PowerPC 7457A v1.0 (G4)                                               */
8885     POWERPC_DEF("7457A_v1.0",    CPU_POWERPC_74x7A_v10,              7455),
8886     /* Code name for PowerPC 7447A/7457A                                     */
8887     POWERPC_DEF("Apollo7PM",     CPU_POWERPC_74x7A_v10,              7455),
8888     /* PowerPC 7447A v1.1 (G4)                                               */
8889     POWERPC_DEF("7447A_v1.1",    CPU_POWERPC_74x7A_v11,              7445),
8890     /* PowerPC 7457A v1.1 (G4)                                               */
8891     POWERPC_DEF("7457A_v1.1",    CPU_POWERPC_74x7A_v11,              7455),
8892     /* PowerPC 7447A v1.2 (G4)                                               */
8893     POWERPC_DEF("7447A_v1.2",    CPU_POWERPC_74x7A_v12,              7445),
8894     /* PowerPC 7457A v1.2 (G4)                                               */
8895     POWERPC_DEF("7457A_v1.2",    CPU_POWERPC_74x7A_v12,              7455),
8896     /* 64 bits PowerPC                                                       */
8897 #if defined (TARGET_PPC64)
8898     /* PowerPC 620                                                           */
8899     POWERPC_DEF("620",           CPU_POWERPC_620,                    620),
8900     /* Code name for PowerPC 620                                             */
8901     POWERPC_DEF("Trident",       CPU_POWERPC_620,                    620),
8902 #if defined (TODO)
8903     /* PowerPC 630 (POWER3)                                                  */
8904     POWERPC_DEF("630",           CPU_POWERPC_630,                    630),
8905     POWERPC_DEF("POWER3",        CPU_POWERPC_630,                    630),
8906     /* Code names for POWER3                                                 */
8907     POWERPC_DEF("Boxer",         CPU_POWERPC_630,                    630),
8908     POWERPC_DEF("Dino",          CPU_POWERPC_630,                    630),
8909 #endif
8910 #if defined (TODO)
8911     /* PowerPC 631 (Power 3+)                                                */
8912     POWERPC_DEF("631",           CPU_POWERPC_631,                    631),
8913     POWERPC_DEF("POWER3+",       CPU_POWERPC_631,                    631),
8914 #endif
8915 #if defined (TODO)
8916     /* POWER4                                                                */
8917     POWERPC_DEF("POWER4",        CPU_POWERPC_POWER4,                 POWER4),
8918 #endif
8919 #if defined (TODO)
8920     /* POWER4p                                                               */
8921     POWERPC_DEF("POWER4+",       CPU_POWERPC_POWER4P,                POWER4P),
8922 #endif
8923 #if defined (TODO)
8924     /* POWER5                                                                */
8925     POWERPC_DEF("POWER5",        CPU_POWERPC_POWER5,                 POWER5),
8926     /* POWER5GR                                                              */
8927     POWERPC_DEF("POWER5gr",      CPU_POWERPC_POWER5GR,               POWER5),
8928 #endif
8929 #if defined (TODO)
8930     /* POWER5+                                                               */
8931     POWERPC_DEF("POWER5+",       CPU_POWERPC_POWER5P,                POWER5P),
8932     /* POWER5GS                                                              */
8933     POWERPC_DEF("POWER5gs",      CPU_POWERPC_POWER5GS,               POWER5P),
8934 #endif
8935 #if defined (TODO)
8936     /* POWER6                                                                */
8937     POWERPC_DEF("POWER6",        CPU_POWERPC_POWER6,                 POWER6),
8938     /* POWER6 running in POWER5 mode                                         */
8939     POWERPC_DEF("POWER6_5",      CPU_POWERPC_POWER6_5,               POWER5),
8940     /* POWER6A                                                               */
8941     POWERPC_DEF("POWER6A",       CPU_POWERPC_POWER6A,                POWER6),
8942 #endif
8943     /* POWER7                                                                */
8944     POWERPC_DEF("POWER7",        CPU_POWERPC_POWER7,                 POWER7),
8945     POWERPC_DEF("POWER7_v2.0",   CPU_POWERPC_POWER7_v20,             POWER7),
8946     /* PowerPC 970                                                           */
8947     POWERPC_DEF("970",           CPU_POWERPC_970,                    970),
8948     /* PowerPC 970FX (G5)                                                    */
8949     POWERPC_DEF("970fx",         CPU_POWERPC_970FX,                  970FX),
8950     /* PowerPC 970FX v1.0 (G5)                                               */
8951     POWERPC_DEF("970fx_v1.0",    CPU_POWERPC_970FX_v10,              970FX),
8952     /* PowerPC 970FX v2.0 (G5)                                               */
8953     POWERPC_DEF("970fx_v2.0",    CPU_POWERPC_970FX_v20,              970FX),
8954     /* PowerPC 970FX v2.1 (G5)                                               */
8955     POWERPC_DEF("970fx_v2.1",    CPU_POWERPC_970FX_v21,              970FX),
8956     /* PowerPC 970FX v3.0 (G5)                                               */
8957     POWERPC_DEF("970fx_v3.0",    CPU_POWERPC_970FX_v30,              970FX),
8958     /* PowerPC 970FX v3.1 (G5)                                               */
8959     POWERPC_DEF("970fx_v3.1",    CPU_POWERPC_970FX_v31,              970FX),
8960     /* PowerPC 970GX (G5)                                                    */
8961     POWERPC_DEF("970gx",         CPU_POWERPC_970GX,                  970GX),
8962     /* PowerPC 970MP                                                         */
8963     POWERPC_DEF("970mp",         CPU_POWERPC_970MP,                  970MP),
8964     /* PowerPC 970MP v1.0                                                    */
8965     POWERPC_DEF("970mp_v1.0",    CPU_POWERPC_970MP_v10,              970MP),
8966     /* PowerPC 970MP v1.1                                                    */
8967     POWERPC_DEF("970mp_v1.1",    CPU_POWERPC_970MP_v11,              970MP),
8968 #if defined (TODO)
8969     /* PowerPC Cell                                                          */
8970     POWERPC_DEF("Cell",          CPU_POWERPC_CELL,                   970),
8971 #endif
8972 #if defined (TODO)
8973     /* PowerPC Cell v1.0                                                     */
8974     POWERPC_DEF("Cell_v1.0",     CPU_POWERPC_CELL_v10,               970),
8975 #endif
8976 #if defined (TODO)
8977     /* PowerPC Cell v2.0                                                     */
8978     POWERPC_DEF("Cell_v2.0",     CPU_POWERPC_CELL_v20,               970),
8979 #endif
8980 #if defined (TODO)
8981     /* PowerPC Cell v3.0                                                     */
8982     POWERPC_DEF("Cell_v3.0",     CPU_POWERPC_CELL_v30,               970),
8983 #endif
8984 #if defined (TODO)
8985     /* PowerPC Cell v3.1                                                     */
8986     POWERPC_DEF("Cell_v3.1",     CPU_POWERPC_CELL_v31,               970),
8987 #endif
8988 #if defined (TODO)
8989     /* PowerPC Cell v3.2                                                     */
8990     POWERPC_DEF("Cell_v3.2",     CPU_POWERPC_CELL_v32,               970),
8991 #endif
8992 #if defined (TODO)
8993     /* RS64 (Apache/A35)                                                     */
8994     /* This one seems to support the whole POWER2 instruction set
8995      * and the PowerPC 64 one.
8996      */
8997     /* What about A10 & A30 ? */
8998     POWERPC_DEF("RS64",          CPU_POWERPC_RS64,                   RS64),
8999     POWERPC_DEF("Apache",        CPU_POWERPC_RS64,                   RS64),
9000     POWERPC_DEF("A35",           CPU_POWERPC_RS64,                   RS64),
9001 #endif
9002 #if defined (TODO)
9003     /* RS64-II (NorthStar/A50)                                               */
9004     POWERPC_DEF("RS64-II",       CPU_POWERPC_RS64II,                 RS64),
9005     POWERPC_DEF("NorthStar",     CPU_POWERPC_RS64II,                 RS64),
9006     POWERPC_DEF("A50",           CPU_POWERPC_RS64II,                 RS64),
9007 #endif
9008 #if defined (TODO)
9009     /* RS64-III (Pulsar)                                                     */
9010     POWERPC_DEF("RS64-III",      CPU_POWERPC_RS64III,                RS64),
9011     POWERPC_DEF("Pulsar",        CPU_POWERPC_RS64III,                RS64),
9012 #endif
9013 #if defined (TODO)
9014     /* RS64-IV (IceStar/IStar/SStar)                                         */
9015     POWERPC_DEF("RS64-IV",       CPU_POWERPC_RS64IV,                 RS64),
9016     POWERPC_DEF("IceStar",       CPU_POWERPC_RS64IV,                 RS64),
9017     POWERPC_DEF("IStar",         CPU_POWERPC_RS64IV,                 RS64),
9018     POWERPC_DEF("SStar",         CPU_POWERPC_RS64IV,                 RS64),
9019 #endif
9020 #endif /* defined (TARGET_PPC64) */
9021     /* POWER                                                                 */
9022 #if defined (TODO)
9023     /* Original POWER                                                        */
9024     POWERPC_DEF("POWER",         CPU_POWERPC_POWER,                  POWER),
9025     POWERPC_DEF("RIOS",          CPU_POWERPC_POWER,                  POWER),
9026     POWERPC_DEF("RSC",           CPU_POWERPC_POWER,                  POWER),
9027     POWERPC_DEF("RSC3308",       CPU_POWERPC_POWER,                  POWER),
9028     POWERPC_DEF("RSC4608",       CPU_POWERPC_POWER,                  POWER),
9029 #endif
9030 #if defined (TODO)
9031     /* POWER2                                                                */
9032     POWERPC_DEF("POWER2",        CPU_POWERPC_POWER2,                 POWER),
9033     POWERPC_DEF("RSC2",          CPU_POWERPC_POWER2,                 POWER),
9034     POWERPC_DEF("P2SC",          CPU_POWERPC_POWER2,                 POWER),
9035 #endif
9036     /* PA semi cores                                                         */
9037 #if defined (TODO)
9038     /* PA PA6T */
9039     POWERPC_DEF("PA6T",          CPU_POWERPC_PA6T,                   PA6T),
9040 #endif
9041     /* Generic PowerPCs                                                      */
9042 #if defined (TARGET_PPC64)
9043     POWERPC_DEF("ppc64",         CPU_POWERPC_PPC64,                  PPC64),
9044 #endif
9045     POWERPC_DEF("ppc32",         CPU_POWERPC_PPC32,                  PPC32),
9046     POWERPC_DEF("ppc",           CPU_POWERPC_DEFAULT,                DEFAULT),
9047     /* Fallback                                                              */
9048     POWERPC_DEF("default",       CPU_POWERPC_DEFAULT,                DEFAULT),
9049 };
9050
9051 /*****************************************************************************/
9052 /* Generic CPU instantiation routine                                         */
9053 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
9054 {
9055 #if !defined(CONFIG_USER_ONLY)
9056     int i;
9057
9058     env->irq_inputs = NULL;
9059     /* Set all exception vectors to an invalid address */
9060     for (i = 0; i < POWERPC_EXCP_NB; i++)
9061         env->excp_vectors[i] = (target_ulong)(-1ULL);
9062     env->hreset_excp_prefix = 0x00000000;
9063     env->ivor_mask = 0x00000000;
9064     env->ivpr_mask = 0x00000000;
9065     /* Default MMU definitions */
9066     env->nb_BATs = 0;
9067     env->nb_tlb = 0;
9068     env->nb_ways = 0;
9069 #endif
9070     /* Register SPR common to all PowerPC implementations */
9071     gen_spr_generic(env);
9072     spr_register(env, SPR_PVR, "PVR",
9073                  /* Linux permits userspace to read PVR */
9074 #if defined(CONFIG_LINUX_USER)
9075                  &spr_read_generic,
9076 #else
9077                  SPR_NOACCESS,
9078 #endif
9079                  SPR_NOACCESS,
9080                  &spr_read_generic, SPR_NOACCESS,
9081                  def->pvr);
9082     /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9083     if (def->svr != POWERPC_SVR_NONE) {
9084         if (def->svr & POWERPC_SVR_E500) {
9085             spr_register(env, SPR_E500_SVR, "SVR",
9086                          SPR_NOACCESS, SPR_NOACCESS,
9087                          &spr_read_generic, SPR_NOACCESS,
9088                          def->svr & ~POWERPC_SVR_E500);
9089         } else {
9090             spr_register(env, SPR_SVR, "SVR",
9091                          SPR_NOACCESS, SPR_NOACCESS,
9092                          &spr_read_generic, SPR_NOACCESS,
9093                          def->svr);
9094         }
9095     }
9096     /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9097     (*def->init_proc)(env);
9098 #if !defined(CONFIG_USER_ONLY)
9099     env->excp_prefix = env->hreset_excp_prefix;
9100 #endif
9101     /* MSR bits & flags consistency checks */
9102     if (env->msr_mask & (1 << 25)) {
9103         switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9104         case POWERPC_FLAG_SPE:
9105         case POWERPC_FLAG_VRE:
9106             break;
9107         default:
9108             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9109                     "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9110             exit(1);
9111         }
9112     } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9113         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9114                 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9115         exit(1);
9116     }
9117     if (env->msr_mask & (1 << 17)) {
9118         switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9119         case POWERPC_FLAG_TGPR:
9120         case POWERPC_FLAG_CE:
9121             break;
9122         default:
9123             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9124                     "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9125             exit(1);
9126         }
9127     } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9128         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9129                 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9130         exit(1);
9131     }
9132     if (env->msr_mask & (1 << 10)) {
9133         switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9134                               POWERPC_FLAG_UBLE)) {
9135         case POWERPC_FLAG_SE:
9136         case POWERPC_FLAG_DWE:
9137         case POWERPC_FLAG_UBLE:
9138             break;
9139         default:
9140             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9141                     "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9142                     "POWERPC_FLAG_UBLE\n");
9143             exit(1);
9144         }
9145     } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9146                              POWERPC_FLAG_UBLE)) {
9147         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9148                 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9149                 "POWERPC_FLAG_UBLE\n");
9150             exit(1);
9151     }
9152     if (env->msr_mask & (1 << 9)) {
9153         switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9154         case POWERPC_FLAG_BE:
9155         case POWERPC_FLAG_DE:
9156             break;
9157         default:
9158             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9159                     "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9160             exit(1);
9161         }
9162     } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9163         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9164                 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9165         exit(1);
9166     }
9167     if (env->msr_mask & (1 << 2)) {
9168         switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9169         case POWERPC_FLAG_PX:
9170         case POWERPC_FLAG_PMM:
9171             break;
9172         default:
9173             fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9174                     "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9175             exit(1);
9176         }
9177     } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9178         fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9179                 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9180         exit(1);
9181     }
9182     if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9183         fprintf(stderr, "PowerPC flags inconsistency\n"
9184                 "Should define the time-base and decrementer clock source\n");
9185         exit(1);
9186     }
9187     /* Allocate TLBs buffer when needed */
9188 #if !defined(CONFIG_USER_ONLY)
9189     if (env->nb_tlb != 0) {
9190         int nb_tlb = env->nb_tlb;
9191         if (env->id_tlbs != 0)
9192             nb_tlb *= 2;
9193         env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
9194         /* Pre-compute some useful values */
9195         env->tlb_per_way = env->nb_tlb / env->nb_ways;
9196     }
9197     if (env->irq_inputs == NULL) {
9198         fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9199                 " Attempt Qemu to crash very soon !\n");
9200     }
9201 #endif
9202     if (env->check_pow == NULL) {
9203         fprintf(stderr, "WARNING: no power management check handler "
9204                 "registered.\n"
9205                 " Attempt Qemu to crash very soon !\n");
9206     }
9207 }
9208
9209 #if defined(PPC_DUMP_CPU)
9210 static void dump_ppc_sprs (CPUPPCState *env)
9211 {
9212     ppc_spr_t *spr;
9213 #if !defined(CONFIG_USER_ONLY)
9214     uint32_t sr, sw;
9215 #endif
9216     uint32_t ur, uw;
9217     int i, j, n;
9218
9219     printf("Special purpose registers:\n");
9220     for (i = 0; i < 32; i++) {
9221         for (j = 0; j < 32; j++) {
9222             n = (i << 5) | j;
9223             spr = &env->spr_cb[n];
9224             uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9225             ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9226 #if !defined(CONFIG_USER_ONLY)
9227             sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9228             sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9229             if (sw || sr || uw || ur) {
9230                 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9231                        (i << 5) | j, (i << 5) | j, spr->name,
9232                        sw ? 'w' : '-', sr ? 'r' : '-',
9233                        uw ? 'w' : '-', ur ? 'r' : '-');
9234             }
9235 #else
9236             if (uw || ur) {
9237                 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9238                        (i << 5) | j, (i << 5) | j, spr->name,
9239                        uw ? 'w' : '-', ur ? 'r' : '-');
9240             }
9241 #endif
9242         }
9243     }
9244     fflush(stdout);
9245     fflush(stderr);
9246 }
9247 #endif
9248
9249 /*****************************************************************************/
9250 #include <stdlib.h>
9251 #include <string.h>
9252
9253 /* Opcode types */
9254 enum {
9255     PPC_DIRECT   = 0, /* Opcode routine        */
9256     PPC_INDIRECT = 1, /* Indirect opcode table */
9257 };
9258
9259 static inline int is_indirect_opcode (void *handler)
9260 {
9261     return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9262 }
9263
9264 static inline opc_handler_t **ind_table(void *handler)
9265 {
9266     return (opc_handler_t **)((unsigned long)handler & ~3);
9267 }
9268
9269 /* Instruction table creation */
9270 /* Opcodes tables creation */
9271 static void fill_new_table (opc_handler_t **table, int len)
9272 {
9273     int i;
9274
9275     for (i = 0; i < len; i++)
9276         table[i] = &invalid_handler;
9277 }
9278
9279 static int create_new_table (opc_handler_t **table, unsigned char idx)
9280 {
9281     opc_handler_t **tmp;
9282
9283     tmp = malloc(0x20 * sizeof(opc_handler_t));
9284     fill_new_table(tmp, 0x20);
9285     table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
9286
9287     return 0;
9288 }
9289
9290 static int insert_in_table (opc_handler_t **table, unsigned char idx,
9291                             opc_handler_t *handler)
9292 {
9293     if (table[idx] != &invalid_handler)
9294         return -1;
9295     table[idx] = handler;
9296
9297     return 0;
9298 }
9299
9300 static int register_direct_insn (opc_handler_t **ppc_opcodes,
9301                                  unsigned char idx, opc_handler_t *handler)
9302 {
9303     if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9304         printf("*** ERROR: opcode %02x already assigned in main "
9305                "opcode table\n", idx);
9306 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9307         printf("           Registered handler '%s' - new handler '%s'\n",
9308                ppc_opcodes[idx]->oname, handler->oname);
9309 #endif
9310         return -1;
9311     }
9312
9313     return 0;
9314 }
9315
9316 static int register_ind_in_table (opc_handler_t **table,
9317                                   unsigned char idx1, unsigned char idx2,
9318                                   opc_handler_t *handler)
9319 {
9320     if (table[idx1] == &invalid_handler) {
9321         if (create_new_table(table, idx1) < 0) {
9322             printf("*** ERROR: unable to create indirect table "
9323                    "idx=%02x\n", idx1);
9324             return -1;
9325         }
9326     } else {
9327         if (!is_indirect_opcode(table[idx1])) {
9328             printf("*** ERROR: idx %02x already assigned to a direct "
9329                    "opcode\n", idx1);
9330 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9331             printf("           Registered handler '%s' - new handler '%s'\n",
9332                    ind_table(table[idx1])[idx2]->oname, handler->oname);
9333 #endif
9334             return -1;
9335         }
9336     }
9337     if (handler != NULL &&
9338         insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9339         printf("*** ERROR: opcode %02x already assigned in "
9340                "opcode table %02x\n", idx2, idx1);
9341 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9342         printf("           Registered handler '%s' - new handler '%s'\n",
9343                ind_table(table[idx1])[idx2]->oname, handler->oname);
9344 #endif
9345         return -1;
9346     }
9347
9348     return 0;
9349 }
9350
9351 static int register_ind_insn (opc_handler_t **ppc_opcodes,
9352                               unsigned char idx1, unsigned char idx2,
9353                               opc_handler_t *handler)
9354 {
9355     int ret;
9356
9357     ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9358
9359     return ret;
9360 }
9361
9362 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
9363                                  unsigned char idx1, unsigned char idx2,
9364                                  unsigned char idx3, opc_handler_t *handler)
9365 {
9366     if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9367         printf("*** ERROR: unable to join indirect table idx "
9368                "[%02x-%02x]\n", idx1, idx2);
9369         return -1;
9370     }
9371     if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9372                               handler) < 0) {
9373         printf("*** ERROR: unable to insert opcode "
9374                "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9375         return -1;
9376     }
9377
9378     return 0;
9379 }
9380
9381 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
9382 {
9383     if (insn->opc2 != 0xFF) {
9384         if (insn->opc3 != 0xFF) {
9385             if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9386                                      insn->opc3, &insn->handler) < 0)
9387                 return -1;
9388         } else {
9389             if (register_ind_insn(ppc_opcodes, insn->opc1,
9390                                   insn->opc2, &insn->handler) < 0)
9391                 return -1;
9392         }
9393     } else {
9394         if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9395             return -1;
9396     }
9397
9398     return 0;
9399 }
9400
9401 static int test_opcode_table (opc_handler_t **table, int len)
9402 {
9403     int i, count, tmp;
9404
9405     for (i = 0, count = 0; i < len; i++) {
9406         /* Consistency fixup */
9407         if (table[i] == NULL)
9408             table[i] = &invalid_handler;
9409         if (table[i] != &invalid_handler) {
9410             if (is_indirect_opcode(table[i])) {
9411                 tmp = test_opcode_table(ind_table(table[i]), 0x20);
9412                 if (tmp == 0) {
9413                     free(table[i]);
9414                     table[i] = &invalid_handler;
9415                 } else {
9416                     count++;
9417                 }
9418             } else {
9419                 count++;
9420             }
9421         }
9422     }
9423
9424     return count;
9425 }
9426
9427 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
9428 {
9429     if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9430         printf("*** WARNING: no opcode defined !\n");
9431 }
9432
9433 /*****************************************************************************/
9434 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
9435 {
9436     opcode_t *opc;
9437
9438     fill_new_table(env->opcodes, 0x40);
9439     for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
9440         if ((opc->handler.type & def->insns_flags) != 0) {
9441             if (register_insn(env->opcodes, opc) < 0) {
9442                 printf("*** ERROR initializing PowerPC instruction "
9443                        "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9444                        opc->opc3);
9445                 return -1;
9446             }
9447         }
9448     }
9449     fix_opcode_tables(env->opcodes);
9450     fflush(stdout);
9451     fflush(stderr);
9452
9453     return 0;
9454 }
9455
9456 #if defined(PPC_DUMP_CPU)
9457 static void dump_ppc_insns (CPUPPCState *env)
9458 {
9459     opc_handler_t **table, *handler;
9460     const char *p, *q;
9461     uint8_t opc1, opc2, opc3;
9462
9463     printf("Instructions set:\n");
9464     /* opc1 is 6 bits long */
9465     for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9466         table = env->opcodes;
9467         handler = table[opc1];
9468         if (is_indirect_opcode(handler)) {
9469             /* opc2 is 5 bits long */
9470             for (opc2 = 0; opc2 < 0x20; opc2++) {
9471                 table = env->opcodes;
9472                 handler = env->opcodes[opc1];
9473                 table = ind_table(handler);
9474                 handler = table[opc2];
9475                 if (is_indirect_opcode(handler)) {
9476                     table = ind_table(handler);
9477                     /* opc3 is 5 bits long */
9478                     for (opc3 = 0; opc3 < 0x20; opc3++) {
9479                         handler = table[opc3];
9480                         if (handler->handler != &gen_invalid) {
9481                             /* Special hack to properly dump SPE insns */
9482                             p = strchr(handler->oname, '_');
9483                             if (p == NULL) {
9484                                 printf("INSN: %02x %02x %02x (%02d %04d) : "
9485                                        "%s\n",
9486                                        opc1, opc2, opc3, opc1,
9487                                        (opc3 << 5) | opc2,
9488                                        handler->oname);
9489                             } else {
9490                                 q = "speundef";
9491                                 if ((p - handler->oname) != strlen(q) ||
9492                                     memcmp(handler->oname, q, strlen(q)) != 0) {
9493                                     /* First instruction */
9494                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
9495                                            "%.*s\n",
9496                                            opc1, opc2 << 1, opc3, opc1,
9497                                            (opc3 << 6) | (opc2 << 1),
9498                                            (int)(p - handler->oname),
9499                                            handler->oname);
9500                                 }
9501                                 if (strcmp(p + 1, q) != 0) {
9502                                     /* Second instruction */
9503                                     printf("INSN: %02x %02x %02x (%02d %04d) : "
9504                                            "%s\n",
9505                                            opc1, (opc2 << 1) | 1, opc3, opc1,
9506                                            (opc3 << 6) | (opc2 << 1) | 1,
9507                                            p + 1);
9508                                 }
9509                             }
9510                         }
9511                     }
9512                 } else {
9513                     if (handler->handler != &gen_invalid) {
9514                         printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9515                                opc1, opc2, opc1, opc2, handler->oname);
9516                     }
9517                 }
9518             }
9519         } else {
9520             if (handler->handler != &gen_invalid) {
9521                 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9522                        opc1, opc1, handler->oname);
9523             }
9524         }
9525     }
9526 }
9527 #endif
9528
9529 static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9530 {
9531     if (n < 32) {
9532         stfq_p(mem_buf, env->fpr[n]);
9533         return 8;
9534     }
9535     if (n == 32) {
9536         /* FPSCR not implemented  */
9537         memset(mem_buf, 0, 4);
9538         return 4;
9539     }
9540     return 0;
9541 }
9542
9543 static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9544 {
9545     if (n < 32) {
9546         env->fpr[n] = ldfq_p(mem_buf);
9547         return 8;
9548     }
9549     if (n == 32) {
9550         /* FPSCR not implemented  */
9551         return 4;
9552     }
9553     return 0;
9554 }
9555
9556 static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9557 {
9558     if (n < 32) {
9559 #ifdef HOST_WORDS_BIGENDIAN
9560         stq_p(mem_buf, env->avr[n].u64[0]);
9561         stq_p(mem_buf+8, env->avr[n].u64[1]);
9562 #else
9563         stq_p(mem_buf, env->avr[n].u64[1]);
9564         stq_p(mem_buf+8, env->avr[n].u64[0]);
9565 #endif
9566         return 16;
9567     }
9568     if (n == 32) {
9569         stl_p(mem_buf, env->vscr);
9570         return 4;
9571     }
9572     if (n == 33) {
9573         stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9574         return 4;
9575     }
9576     return 0;
9577 }
9578
9579 static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9580 {
9581     if (n < 32) {
9582 #ifdef HOST_WORDS_BIGENDIAN
9583         env->avr[n].u64[0] = ldq_p(mem_buf);
9584         env->avr[n].u64[1] = ldq_p(mem_buf+8);
9585 #else
9586         env->avr[n].u64[1] = ldq_p(mem_buf);
9587         env->avr[n].u64[0] = ldq_p(mem_buf+8);
9588 #endif
9589         return 16;
9590     }
9591     if (n == 32) {
9592         env->vscr = ldl_p(mem_buf);
9593         return 4;
9594     }
9595     if (n == 33) {
9596         env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9597         return 4;
9598     }
9599     return 0;
9600 }
9601
9602 static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9603 {
9604     if (n < 32) {
9605 #if defined(TARGET_PPC64)
9606         stl_p(mem_buf, env->gpr[n] >> 32);
9607 #else
9608         stl_p(mem_buf, env->gprh[n]);
9609 #endif
9610         return 4;
9611     }
9612     if (n == 32) {
9613         stq_p(mem_buf, env->spe_acc);
9614         return 8;
9615     }
9616     if (n == 33) {
9617         stl_p(mem_buf, env->spe_fscr);
9618         return 4;
9619     }
9620     return 0;
9621 }
9622
9623 static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9624 {
9625     if (n < 32) {
9626 #if defined(TARGET_PPC64)
9627         target_ulong lo = (uint32_t)env->gpr[n];
9628         target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9629         env->gpr[n] = lo | hi;
9630 #else
9631         env->gprh[n] = ldl_p(mem_buf);
9632 #endif
9633         return 4;
9634     }
9635     if (n == 32) {
9636         env->spe_acc = ldq_p(mem_buf);
9637         return 8;
9638     }
9639     if (n == 33) {
9640         env->spe_fscr = ldl_p(mem_buf);
9641         return 4;
9642     }
9643     return 0;
9644 }
9645
9646 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9647 {
9648     env->msr_mask = def->msr_mask;
9649     env->mmu_model = def->mmu_model;
9650     env->excp_model = def->excp_model;
9651     env->bus_model = def->bus_model;
9652     env->insns_flags = def->insns_flags;
9653     env->flags = def->flags;
9654     env->bfd_mach = def->bfd_mach;
9655     env->check_pow = def->check_pow;
9656     if (create_ppc_opcodes(env, def) < 0)
9657         return -1;
9658     init_ppc_proc(env, def);
9659
9660     if (def->insns_flags & PPC_FLOAT) {
9661         gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9662                                  33, "power-fpu.xml", 0);
9663     }
9664     if (def->insns_flags & PPC_ALTIVEC) {
9665         gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9666                                  34, "power-altivec.xml", 0);
9667     }
9668     if (def->insns_flags & PPC_SPE) {
9669         gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9670                                  34, "power-spe.xml", 0);
9671     }
9672
9673 #if defined(PPC_DUMP_CPU)
9674     {
9675         const char *mmu_model, *excp_model, *bus_model;
9676         switch (env->mmu_model) {
9677         case POWERPC_MMU_32B:
9678             mmu_model = "PowerPC 32";
9679             break;
9680         case POWERPC_MMU_SOFT_6xx:
9681             mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9682             break;
9683         case POWERPC_MMU_SOFT_74xx:
9684             mmu_model = "PowerPC 74xx with software driven TLBs";
9685             break;
9686         case POWERPC_MMU_SOFT_4xx:
9687             mmu_model = "PowerPC 4xx with software driven TLBs";
9688             break;
9689         case POWERPC_MMU_SOFT_4xx_Z:
9690             mmu_model = "PowerPC 4xx with software driven TLBs "
9691                 "and zones protections";
9692             break;
9693         case POWERPC_MMU_REAL:
9694             mmu_model = "PowerPC real mode only";
9695             break;
9696         case POWERPC_MMU_MPC8xx:
9697             mmu_model = "PowerPC MPC8xx";
9698             break;
9699         case POWERPC_MMU_BOOKE:
9700             mmu_model = "PowerPC BookE";
9701             break;
9702         case POWERPC_MMU_BOOKE_FSL:
9703             mmu_model = "PowerPC BookE FSL";
9704             break;
9705         case POWERPC_MMU_601:
9706             mmu_model = "PowerPC 601";
9707             break;
9708 #if defined (TARGET_PPC64)
9709         case POWERPC_MMU_64B:
9710             mmu_model = "PowerPC 64";
9711             break;
9712         case POWERPC_MMU_620:
9713             mmu_model = "PowerPC 620";
9714             break;
9715 #endif
9716         default:
9717             mmu_model = "Unknown or invalid";
9718             break;
9719         }
9720         switch (env->excp_model) {
9721         case POWERPC_EXCP_STD:
9722             excp_model = "PowerPC";
9723             break;
9724         case POWERPC_EXCP_40x:
9725             excp_model = "PowerPC 40x";
9726             break;
9727         case POWERPC_EXCP_601:
9728             excp_model = "PowerPC 601";
9729             break;
9730         case POWERPC_EXCP_602:
9731             excp_model = "PowerPC 602";
9732             break;
9733         case POWERPC_EXCP_603:
9734             excp_model = "PowerPC 603";
9735             break;
9736         case POWERPC_EXCP_603E:
9737             excp_model = "PowerPC 603e";
9738             break;
9739         case POWERPC_EXCP_604:
9740             excp_model = "PowerPC 604";
9741             break;
9742         case POWERPC_EXCP_7x0:
9743             excp_model = "PowerPC 740/750";
9744             break;
9745         case POWERPC_EXCP_7x5:
9746             excp_model = "PowerPC 745/755";
9747             break;
9748         case POWERPC_EXCP_74xx:
9749             excp_model = "PowerPC 74xx";
9750             break;
9751         case POWERPC_EXCP_BOOKE:
9752             excp_model = "PowerPC BookE";
9753             break;
9754 #if defined (TARGET_PPC64)
9755         case POWERPC_EXCP_970:
9756             excp_model = "PowerPC 970";
9757             break;
9758 #endif
9759         default:
9760             excp_model = "Unknown or invalid";
9761             break;
9762         }
9763         switch (env->bus_model) {
9764         case PPC_FLAGS_INPUT_6xx:
9765             bus_model = "PowerPC 6xx";
9766             break;
9767         case PPC_FLAGS_INPUT_BookE:
9768             bus_model = "PowerPC BookE";
9769             break;
9770         case PPC_FLAGS_INPUT_405:
9771             bus_model = "PowerPC 405";
9772             break;
9773         case PPC_FLAGS_INPUT_401:
9774             bus_model = "PowerPC 401/403";
9775             break;
9776         case PPC_FLAGS_INPUT_RCPU:
9777             bus_model = "RCPU / MPC8xx";
9778             break;
9779 #if defined (TARGET_PPC64)
9780         case PPC_FLAGS_INPUT_970:
9781             bus_model = "PowerPC 970";
9782             break;
9783 #endif
9784         default:
9785             bus_model = "Unknown or invalid";
9786             break;
9787         }
9788         printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9789                "    MMU model        : %s\n",
9790                def->name, def->pvr, def->msr_mask, mmu_model);
9791 #if !defined(CONFIG_USER_ONLY)
9792         if (env->tlb != NULL) {
9793             printf("                       %d %s TLB in %d ways\n",
9794                    env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9795                    env->nb_ways);
9796         }
9797 #endif
9798         printf("    Exceptions model : %s\n"
9799                "    Bus model        : %s\n",
9800                excp_model, bus_model);
9801         printf("    MSR features     :\n");
9802         if (env->flags & POWERPC_FLAG_SPE)
9803             printf("                        signal processing engine enable"
9804                    "\n");
9805         else if (env->flags & POWERPC_FLAG_VRE)
9806             printf("                        vector processor enable\n");
9807         if (env->flags & POWERPC_FLAG_TGPR)
9808             printf("                        temporary GPRs\n");
9809         else if (env->flags & POWERPC_FLAG_CE)
9810             printf("                        critical input enable\n");
9811         if (env->flags & POWERPC_FLAG_SE)
9812             printf("                        single-step trace mode\n");
9813         else if (env->flags & POWERPC_FLAG_DWE)
9814             printf("                        debug wait enable\n");
9815         else if (env->flags & POWERPC_FLAG_UBLE)
9816             printf("                        user BTB lock enable\n");
9817         if (env->flags & POWERPC_FLAG_BE)
9818             printf("                        branch-step trace mode\n");
9819         else if (env->flags & POWERPC_FLAG_DE)
9820             printf("                        debug interrupt enable\n");
9821         if (env->flags & POWERPC_FLAG_PX)
9822             printf("                        inclusive protection\n");
9823         else if (env->flags & POWERPC_FLAG_PMM)
9824             printf("                        performance monitor mark\n");
9825         if (env->flags == POWERPC_FLAG_NONE)
9826             printf("                        none\n");
9827         printf("    Time-base/decrementer clock source: %s\n",
9828                env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9829     }
9830     dump_ppc_insns(env);
9831     dump_ppc_sprs(env);
9832     fflush(stdout);
9833 #endif
9834
9835     return 0;
9836 }
9837
9838 static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
9839 {
9840     const ppc_def_t *ret;
9841     uint32_t pvr_rev;
9842     int i, best, match, best_match, max;
9843
9844     ret = NULL;
9845     max = ARRAY_SIZE(ppc_defs);
9846     best = -1;
9847     pvr_rev = pvr & 0xFFFF;
9848     /* We want all specified bits to match */
9849     best_match = 32 - ctz32(pvr_rev);
9850     for (i = 0; i < max; i++) {
9851         /* We check that the 16 higher bits are the same to ensure the CPU
9852          * model will be the choosen one.
9853          */
9854         if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9855             /* We want as much as possible of the low-level 16 bits
9856              * to be the same but we allow inexact matches.
9857              */
9858             match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9859             /* We check '>=' instead of '>' because the PPC_defs table
9860              * is ordered by increasing revision.
9861              * Then, we will match the higher revision compatible
9862              * with the requested PVR
9863              */
9864             if (match >= best_match) {
9865                 best = i;
9866                 best_match = match;
9867             }
9868         }
9869     }
9870     if (best != -1)
9871         ret = &ppc_defs[best];
9872
9873     return ret;
9874 }
9875
9876 #include <ctype.h>
9877
9878 const ppc_def_t *cpu_ppc_find_by_name (const char *name)
9879 {
9880     const ppc_def_t *ret;
9881     const char *p;
9882     int i, max, len;
9883
9884     /* Check if the given name is a PVR */
9885     len = strlen(name);
9886     if (len == 10 && name[0] == '0' && name[1] == 'x') {
9887         p = name + 2;
9888         goto check_pvr;
9889     } else if (len == 8) {
9890         p = name;
9891     check_pvr:
9892         for (i = 0; i < 8; i++) {
9893             if (!qemu_isxdigit(*p++))
9894                 break;
9895         }
9896         if (i == 8)
9897             return ppc_find_by_pvr(strtoul(name, NULL, 16));
9898     }
9899     ret = NULL;
9900     max = ARRAY_SIZE(ppc_defs);
9901     for (i = 0; i < max; i++) {
9902         if (strcasecmp(name, ppc_defs[i].name) == 0) {
9903             ret = &ppc_defs[i];
9904             break;
9905         }
9906     }
9907
9908     return ret;
9909 }
9910
9911 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
9912 {
9913     int i, max;
9914
9915     max = ARRAY_SIZE(ppc_defs);
9916     for (i = 0; i < max; i++) {
9917         (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9918                        ppc_defs[i].name, ppc_defs[i].pvr);
9919     }
9920 }