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Merge tag 'v2.12.0-rc0'
[qemu/ar7.git] / target / m68k / translate.c
blob72c8fc1d0ff8d09a778a222b3a943a3f5c5babd8
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/log.h"
27 #include "exec/cpu_ldst.h"
28 #include "exec/translator.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/log.h"
35 #include "fpu/softfloat.h"
36
37
38 //#define DEBUG_DISPATCH 1
39
40 #define DEFO32(name, offset) static TCGv QREG_##name;
41 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
42 #include "qregs.def"
43 #undef DEFO32
44 #undef DEFO64
45
46 static TCGv_i32 cpu_halted;
47 static TCGv_i32 cpu_exception_index;
48
49 static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
50 static TCGv cpu_dregs[8];
51 static TCGv cpu_aregs[8];
52 static TCGv_i64 cpu_macc[4];
53
54 #define REG(insn, pos) (((insn) >> (pos)) & 7)
55 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
56 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
57 #define MACREG(acc) cpu_macc[acc]
58 #define QREG_SP get_areg(s, 7)
59
60 static TCGv NULL_QREG;
61 #define IS_NULL_QREG(t) (t == NULL_QREG)
62 /* Used to distinguish stores from bad addressing modes. */
63 static TCGv store_dummy;
64
65 #include "exec/gen-icount.h"
66
67 void m68k_tcg_init(void)
68 {
69 char *p;
70 int i;
71
72 #define DEFO32(name, offset) \
73 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
74 offsetof(CPUM68KState, offset), #name);
75 #define DEFO64(name, offset) \
76 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
77 offsetof(CPUM68KState, offset), #name);
78 #include "qregs.def"
79 #undef DEFO32
80 #undef DEFO64
81
82 cpu_halted = tcg_global_mem_new_i32(cpu_env,
83 -offsetof(M68kCPU, env) +
84 offsetof(CPUState, halted), "HALTED");
85 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
86 -offsetof(M68kCPU, env) +
87 offsetof(CPUState, exception_index),
88 "EXCEPTION");
89
90 p = cpu_reg_names;
91 for (i = 0; i < 8; i++) {
92 sprintf(p, "D%d", i);
93 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
94 offsetof(CPUM68KState, dregs[i]), p);
95 p += 3;
96 sprintf(p, "A%d", i);
97 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
98 offsetof(CPUM68KState, aregs[i]), p);
99 p += 3;
100 }
101 for (i = 0; i < 4; i++) {
102 sprintf(p, "ACC%d", i);
103 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
104 offsetof(CPUM68KState, macc[i]), p);
105 p += 5;
106 }
107
108 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
109 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
110 }
111
112 /* internal defines */
113 typedef struct DisasContext {
114 CPUM68KState *env;
115 target_ulong insn_pc; /* Start of the current instruction. */
116 target_ulong pc;
117 int is_jmp;
118 CCOp cc_op; /* Current CC operation */
119 int cc_op_synced;
120 struct TranslationBlock *tb;
121 int singlestep_enabled;
122 TCGv_i64 mactmp;
123 int done_mac;
124 int writeback_mask;
125 TCGv writeback[8];
126 #define MAX_TO_RELEASE 8
127 int release_count;
128 TCGv release[MAX_TO_RELEASE];
129 } DisasContext;
130
131 static void init_release_array(DisasContext *s)
132 {
133 #ifdef CONFIG_DEBUG_TCG
134 memset(s->release, 0, sizeof(s->release));
135 #endif
136 s->release_count = 0;
137 }
138
139 static void do_release(DisasContext *s)
140 {
141 int i;
142 for (i = 0; i < s->release_count; i++) {
143 tcg_temp_free(s->release[i]);
144 }
145 init_release_array(s);
146 }
147
148 static TCGv mark_to_release(DisasContext *s, TCGv tmp)
149 {
150 g_assert(s->release_count < MAX_TO_RELEASE);
151 return s->release[s->release_count++] = tmp;
152 }
153
154 static TCGv get_areg(DisasContext *s, unsigned regno)
155 {
156 if (s->writeback_mask & (1 << regno)) {
157 return s->writeback[regno];
158 } else {
159 return cpu_aregs[regno];
160 }
161 }
162
163 static void delay_set_areg(DisasContext *s, unsigned regno,
164 TCGv val, bool give_temp)
165 {
166 if (s->writeback_mask & (1 << regno)) {
167 if (give_temp) {
168 tcg_temp_free(s->writeback[regno]);
169 s->writeback[regno] = val;
170 } else {
171 tcg_gen_mov_i32(s->writeback[regno], val);
172 }
173 } else {
174 s->writeback_mask |= 1 << regno;
175 if (give_temp) {
176 s->writeback[regno] = val;
177 } else {
178 TCGv tmp = tcg_temp_new();
179 s->writeback[regno] = tmp;
180 tcg_gen_mov_i32(tmp, val);
181 }
182 }
183 }
184
185 static void do_writebacks(DisasContext *s)
186 {
187 unsigned mask = s->writeback_mask;
188 if (mask) {
189 s->writeback_mask = 0;
190 do {
191 unsigned regno = ctz32(mask);
192 tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]);
193 tcg_temp_free(s->writeback[regno]);
194 mask &= mask - 1;
195 } while (mask);
196 }
197 }
198
199 /* is_jmp field values */
200 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
201 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
202 #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
203 #define DISAS_JUMP_NEXT DISAS_TARGET_3
204
205 #if defined(CONFIG_USER_ONLY)
206 #define IS_USER(s) 1
207 #else
208 #define IS_USER(s) (!(s->tb->flags & TB_FLAGS_MSR_S))
209 #define SFC_INDEX(s) ((s->tb->flags & TB_FLAGS_SFC_S) ? \
210 MMU_KERNEL_IDX : MMU_USER_IDX)
211 #define DFC_INDEX(s) ((s->tb->flags & TB_FLAGS_DFC_S) ? \
212 MMU_KERNEL_IDX : MMU_USER_IDX)
213 #endif
214
215 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
216
217 #ifdef DEBUG_DISPATCH
218 #define DISAS_INSN(name) \
219 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
220 uint16_t insn); \
221 static void disas_##name(CPUM68KState *env, DisasContext *s, \
222 uint16_t insn) \
223 { \
224 qemu_log("Dispatch " #name "\n"); \
225 real_disas_##name(env, s, insn); \
226 } \
227 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
228 uint16_t insn)
229 #else
230 #define DISAS_INSN(name) \
231 static void disas_##name(CPUM68KState *env, DisasContext *s, \
232 uint16_t insn)
233 #endif
234
235 static const uint8_t cc_op_live[CC_OP_NB] = {
236 [CC_OP_DYNAMIC] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
237 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
238 [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V,
239 [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V,
240 [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V,
241 [CC_OP_LOGIC] = CCF_X | CCF_N
242 };
243
244 static void set_cc_op(DisasContext *s, CCOp op)
245 {
246 CCOp old_op = s->cc_op;
247 int dead;
248
249 if (old_op == op) {
250 return;
251 }
252 s->cc_op = op;
253 s->cc_op_synced = 0;
254
255 /* Discard CC computation that will no longer be used.
256 Note that X and N are never dead. */
257 dead = cc_op_live[old_op] & ~cc_op_live[op];
258 if (dead & CCF_C) {
259 tcg_gen_discard_i32(QREG_CC_C);
260 }
261 if (dead & CCF_Z) {
262 tcg_gen_discard_i32(QREG_CC_Z);
263 }
264 if (dead & CCF_V) {
265 tcg_gen_discard_i32(QREG_CC_V);
266 }
267 }
268
269 /* Update the CPU env CC_OP state. */
270 static void update_cc_op(DisasContext *s)
271 {
272 if (!s->cc_op_synced) {
273 s->cc_op_synced = 1;
274 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
275 }
276 }
277
278 /* Generate a jump to an immediate address. */
279 static void gen_jmp_im(DisasContext *s, uint32_t dest)
280 {
281 update_cc_op(s);
282 tcg_gen_movi_i32(QREG_PC, dest);
283 s->is_jmp = DISAS_JUMP;
284 }
285
286 /* Generate a jump to the address in qreg DEST. */
287 static void gen_jmp(DisasContext *s, TCGv dest)
288 {
289 update_cc_op(s);
290 tcg_gen_mov_i32(QREG_PC, dest);
291 s->is_jmp = DISAS_JUMP;
292 }
293
294 static void gen_raise_exception(int nr)
295 {
296 TCGv_i32 tmp = tcg_const_i32(nr);
297
298 gen_helper_raise_exception(cpu_env, tmp);
299 tcg_temp_free_i32(tmp);
300 }
301
302 static void gen_exception(DisasContext *s, uint32_t where, int nr)
303 {
304 gen_jmp_im(s, where);
305 gen_raise_exception(nr);
306 }
307
308 static inline void gen_addr_fault(DisasContext *s)
309 {
310 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
311 }
312
313 /* Generate a load from the specified address. Narrow values are
314 sign extended to full register width. */
315 static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
316 int sign, int index)
317 {
318 TCGv tmp;
319 tmp = tcg_temp_new_i32();
320 switch(opsize) {
321 case OS_BYTE:
322 if (sign)
323 tcg_gen_qemu_ld8s(tmp, addr, index);
324 else
325 tcg_gen_qemu_ld8u(tmp, addr, index);
326 break;
327 case OS_WORD:
328 if (sign)
329 tcg_gen_qemu_ld16s(tmp, addr, index);
330 else
331 tcg_gen_qemu_ld16u(tmp, addr, index);
332 break;
333 case OS_LONG:
334 tcg_gen_qemu_ld32u(tmp, addr, index);
335 break;
336 default:
337 g_assert_not_reached();
338 }
339 return tmp;
340 }
341
342 /* Generate a store. */
343 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val,
344 int index)
345 {
346 switch(opsize) {
347 case OS_BYTE:
348 tcg_gen_qemu_st8(val, addr, index);
349 break;
350 case OS_WORD:
351 tcg_gen_qemu_st16(val, addr, index);
352 break;
353 case OS_LONG:
354 tcg_gen_qemu_st32(val, addr, index);
355 break;
356 default:
357 g_assert_not_reached();
358 }
359 }
360
361 typedef enum {
362 EA_STORE,
363 EA_LOADU,
364 EA_LOADS
365 } ea_what;
366
367 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
368 otherwise generate a store. */
369 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
370 ea_what what, int index)
371 {
372 if (what == EA_STORE) {
373 gen_store(s, opsize, addr, val, index);
374 return store_dummy;
375 } else {
376 return mark_to_release(s, gen_load(s, opsize, addr,
377 what == EA_LOADS, index));
378 }
379 }
380
381 /* Read a 16-bit immediate constant */
382 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
383 {
384 uint16_t im;
385 im = cpu_lduw_code(env, s->pc);
386 s->pc += 2;
387 return im;
388 }
389
390 /* Read an 8-bit immediate constant */
391 static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
392 {
393 return read_im16(env, s);
394 }
395
396 /* Read a 32-bit immediate constant. */
397 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
398 {
399 uint32_t im;
400 im = read_im16(env, s) << 16;
401 im |= 0xffff & read_im16(env, s);
402 return im;
403 }
404
405 /* Read a 64-bit immediate constant. */
406 static inline uint64_t read_im64(CPUM68KState *env, DisasContext *s)
407 {
408 uint64_t im;
409 im = (uint64_t)read_im32(env, s) << 32;
410 im |= (uint64_t)read_im32(env, s);
411 return im;
412 }
413
414 /* Calculate and address index. */
415 static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
416 {
417 TCGv add;
418 int scale;
419
420 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
421 if ((ext & 0x800) == 0) {
422 tcg_gen_ext16s_i32(tmp, add);
423 add = tmp;
424 }
425 scale = (ext >> 9) & 3;
426 if (scale != 0) {
427 tcg_gen_shli_i32(tmp, add, scale);
428 add = tmp;
429 }
430 return add;
431 }
432
433 /* Handle a base + index + displacement effective addresss.
434 A NULL_QREG base means pc-relative. */
435 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
436 {
437 uint32_t offset;
438 uint16_t ext;
439 TCGv add;
440 TCGv tmp;
441 uint32_t bd, od;
442
443 offset = s->pc;
444 ext = read_im16(env, s);
445
446 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
447 return NULL_QREG;
448
449 if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
450 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
451 ext &= ~(3 << 9);
452 }
453
454 if (ext & 0x100) {
455 /* full extension word format */
456 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
457 return NULL_QREG;
458
459 if ((ext & 0x30) > 0x10) {
460 /* base displacement */
461 if ((ext & 0x30) == 0x20) {
462 bd = (int16_t)read_im16(env, s);
463 } else {
464 bd = read_im32(env, s);
465 }
466 } else {
467 bd = 0;
468 }
469 tmp = mark_to_release(s, tcg_temp_new());
470 if ((ext & 0x44) == 0) {
471 /* pre-index */
472 add = gen_addr_index(s, ext, tmp);
473 } else {
474 add = NULL_QREG;
475 }
476 if ((ext & 0x80) == 0) {
477 /* base not suppressed */
478 if (IS_NULL_QREG(base)) {
479 base = mark_to_release(s, tcg_const_i32(offset + bd));
480 bd = 0;
481 }
482 if (!IS_NULL_QREG(add)) {
483 tcg_gen_add_i32(tmp, add, base);
484 add = tmp;
485 } else {
486 add = base;
487 }
488 }
489 if (!IS_NULL_QREG(add)) {
490 if (bd != 0) {
491 tcg_gen_addi_i32(tmp, add, bd);
492 add = tmp;
493 }
494 } else {
495 add = mark_to_release(s, tcg_const_i32(bd));
496 }
497 if ((ext & 3) != 0) {
498 /* memory indirect */
499 base = mark_to_release(s, gen_load(s, OS_LONG, add, 0, IS_USER(s)));
500 if ((ext & 0x44) == 4) {
501 add = gen_addr_index(s, ext, tmp);
502 tcg_gen_add_i32(tmp, add, base);
503 add = tmp;
504 } else {
505 add = base;
506 }
507 if ((ext & 3) > 1) {
508 /* outer displacement */
509 if ((ext & 3) == 2) {
510 od = (int16_t)read_im16(env, s);
511 } else {
512 od = read_im32(env, s);
513 }
514 } else {
515 od = 0;
516 }
517 if (od != 0) {
518 tcg_gen_addi_i32(tmp, add, od);
519 add = tmp;
520 }
521 }
522 } else {
523 /* brief extension word format */
524 tmp = mark_to_release(s, tcg_temp_new());
525 add = gen_addr_index(s, ext, tmp);
526 if (!IS_NULL_QREG(base)) {
527 tcg_gen_add_i32(tmp, add, base);
528 if ((int8_t)ext)
529 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
530 } else {
531 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
532 }
533 add = tmp;
534 }
535 return add;
536 }
537
538 /* Sign or zero extend a value. */
539
540 static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
541 {
542 switch (opsize) {
543 case OS_BYTE:
544 if (sign) {
545 tcg_gen_ext8s_i32(res, val);
546 } else {
547 tcg_gen_ext8u_i32(res, val);
548 }
549 break;
550 case OS_WORD:
551 if (sign) {
552 tcg_gen_ext16s_i32(res, val);
553 } else {
554 tcg_gen_ext16u_i32(res, val);
555 }
556 break;
557 case OS_LONG:
558 tcg_gen_mov_i32(res, val);
559 break;
560 default:
561 g_assert_not_reached();
562 }
563 }
564
565 /* Evaluate all the CC flags. */
566
567 static void gen_flush_flags(DisasContext *s)
568 {
569 TCGv t0, t1;
570
571 switch (s->cc_op) {
572 case CC_OP_FLAGS:
573 return;
574
575 case CC_OP_ADDB:
576 case CC_OP_ADDW:
577 case CC_OP_ADDL:
578 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
579 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
580 /* Compute signed overflow for addition. */
581 t0 = tcg_temp_new();
582 t1 = tcg_temp_new();
583 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
584 gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1);
585 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
586 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
587 tcg_temp_free(t0);
588 tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
589 tcg_temp_free(t1);
590 break;
591
592 case CC_OP_SUBB:
593 case CC_OP_SUBW:
594 case CC_OP_SUBL:
595 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
596 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
597 /* Compute signed overflow for subtraction. */
598 t0 = tcg_temp_new();
599 t1 = tcg_temp_new();
600 tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
601 gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1);
602 tcg_gen_xor_i32(t1, QREG_CC_N, t0);
603 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
604 tcg_temp_free(t0);
605 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
606 tcg_temp_free(t1);
607 break;
608
609 case CC_OP_CMPB:
610 case CC_OP_CMPW:
611 case CC_OP_CMPL:
612 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
613 tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
614 gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1);
615 /* Compute signed overflow for subtraction. */
616 t0 = tcg_temp_new();
617 tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
618 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
619 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
620 tcg_temp_free(t0);
621 tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
622 break;
623
624 case CC_OP_LOGIC:
625 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
626 tcg_gen_movi_i32(QREG_CC_C, 0);
627 tcg_gen_movi_i32(QREG_CC_V, 0);
628 break;
629
630 case CC_OP_DYNAMIC:
631 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
632 s->cc_op_synced = 1;
633 break;
634
635 default:
636 t0 = tcg_const_i32(s->cc_op);
637 gen_helper_flush_flags(cpu_env, t0);
638 tcg_temp_free(t0);
639 s->cc_op_synced = 1;
640 break;
641 }
642
643 /* Note that flush_flags also assigned to env->cc_op. */
644 s->cc_op = CC_OP_FLAGS;
645 }
646
647 static inline TCGv gen_extend(DisasContext *s, TCGv val, int opsize, int sign)
648 {
649 TCGv tmp;
650
651 if (opsize == OS_LONG) {
652 tmp = val;
653 } else {
654 tmp = mark_to_release(s, tcg_temp_new());
655 gen_ext(tmp, val, opsize, sign);
656 }
657
658 return tmp;
659 }
660
661 static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
662 {
663 gen_ext(QREG_CC_N, val, opsize, 1);
664 set_cc_op(s, CC_OP_LOGIC);
665 }
666
667 static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize)
668 {
669 tcg_gen_mov_i32(QREG_CC_N, dest);
670 tcg_gen_mov_i32(QREG_CC_V, src);
671 set_cc_op(s, CC_OP_CMPB + opsize);
672 }
673
674 static void gen_update_cc_add(TCGv dest, TCGv src, int opsize)
675 {
676 gen_ext(QREG_CC_N, dest, opsize, 1);
677 tcg_gen_mov_i32(QREG_CC_V, src);
678 }
679
680 static inline int opsize_bytes(int opsize)
681 {
682 switch (opsize) {
683 case OS_BYTE: return 1;
684 case OS_WORD: return 2;
685 case OS_LONG: return 4;
686 case OS_SINGLE: return 4;
687 case OS_DOUBLE: return 8;
688 case OS_EXTENDED: return 12;
689 case OS_PACKED: return 12;
690 default:
691 g_assert_not_reached();
692 }
693 }
694
695 static inline int insn_opsize(int insn)
696 {
697 switch ((insn >> 6) & 3) {
698 case 0: return OS_BYTE;
699 case 1: return OS_WORD;
700 case 2: return OS_LONG;
701 default:
702 g_assert_not_reached();
703 }
704 /* Should never happen. */
705 return -1;
706 }
707
708 static inline int ext_opsize(int ext, int pos)
709 {
710 switch ((ext >> pos) & 7) {
711 case 0: return OS_LONG;
712 case 1: return OS_SINGLE;
713 case 2: return OS_EXTENDED;
714 case 3: return OS_PACKED;
715 case 4: return OS_WORD;
716 case 5: return OS_DOUBLE;
717 case 6: return OS_BYTE;
718 default:
719 g_assert_not_reached();
720 }
721 }
722
723 /* Assign value to a register. If the width is less than the register width
724 only the low part of the register is set. */
725 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
726 {
727 TCGv tmp;
728 switch (opsize) {
729 case OS_BYTE:
730 tcg_gen_andi_i32(reg, reg, 0xffffff00);
731 tmp = tcg_temp_new();
732 tcg_gen_ext8u_i32(tmp, val);
733 tcg_gen_or_i32(reg, reg, tmp);
734 tcg_temp_free(tmp);
735 break;
736 case OS_WORD:
737 tcg_gen_andi_i32(reg, reg, 0xffff0000);
738 tmp = tcg_temp_new();
739 tcg_gen_ext16u_i32(tmp, val);
740 tcg_gen_or_i32(reg, reg, tmp);
741 tcg_temp_free(tmp);
742 break;
743 case OS_LONG:
744 case OS_SINGLE:
745 tcg_gen_mov_i32(reg, val);
746 break;
747 default:
748 g_assert_not_reached();
749 }
750 }
751
752 /* Generate code for an "effective address". Does not adjust the base
753 register for autoincrement addressing modes. */
754 static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
755 int mode, int reg0, int opsize)
756 {
757 TCGv reg;
758 TCGv tmp;
759 uint16_t ext;
760 uint32_t offset;
761
762 switch (mode) {
763 case 0: /* Data register direct. */
764 case 1: /* Address register direct. */
765 return NULL_QREG;
766 case 3: /* Indirect postincrement. */
767 if (opsize == OS_UNSIZED) {
768 return NULL_QREG;
769 }
770 /* fallthru */
771 case 2: /* Indirect register */
772 return get_areg(s, reg0);
773 case 4: /* Indirect predecrememnt. */
774 if (opsize == OS_UNSIZED) {
775 return NULL_QREG;
776 }
777 reg = get_areg(s, reg0);
778 tmp = mark_to_release(s, tcg_temp_new());
779 if (reg0 == 7 && opsize == OS_BYTE &&
780 m68k_feature(s->env, M68K_FEATURE_M68000)) {
781 tcg_gen_subi_i32(tmp, reg, 2);
782 } else {
783 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
784 }
785 return tmp;
786 case 5: /* Indirect displacement. */
787 reg = get_areg(s, reg0);
788 tmp = mark_to_release(s, tcg_temp_new());
789 ext = read_im16(env, s);
790 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
791 return tmp;
792 case 6: /* Indirect index + displacement. */
793 reg = get_areg(s, reg0);
794 return gen_lea_indexed(env, s, reg);
795 case 7: /* Other */
796 switch (reg0) {
797 case 0: /* Absolute short. */
798 offset = (int16_t)read_im16(env, s);
799 return mark_to_release(s, tcg_const_i32(offset));
800 case 1: /* Absolute long. */
801 offset = read_im32(env, s);
802 return mark_to_release(s, tcg_const_i32(offset));
803 case 2: /* pc displacement */
804 offset = s->pc;
805 offset += (int16_t)read_im16(env, s);
806 return mark_to_release(s, tcg_const_i32(offset));
807 case 3: /* pc index+displacement. */
808 return gen_lea_indexed(env, s, NULL_QREG);
809 case 4: /* Immediate. */
810 default:
811 return NULL_QREG;
812 }
813 }
814 /* Should never happen. */
815 return NULL_QREG;
816 }
817
818 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
819 int opsize)
820 {
821 int mode = extract32(insn, 3, 3);
822 int reg0 = REG(insn, 0);
823 return gen_lea_mode(env, s, mode, reg0, opsize);
824 }
825
826 /* Generate code to load/store a value from/into an EA. If WHAT > 0 this is
827 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
828 ADDRP is non-null for readwrite operands. */
829 static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
830 int opsize, TCGv val, TCGv *addrp, ea_what what,
831 int index)
832 {
833 TCGv reg, tmp, result;
834 int32_t offset;
835
836 switch (mode) {
837 case 0: /* Data register direct. */
838 reg = cpu_dregs[reg0];
839 if (what == EA_STORE) {
840 gen_partset_reg(opsize, reg, val);
841 return store_dummy;
842 } else {
843 return gen_extend(s, reg, opsize, what == EA_LOADS);
844 }
845 case 1: /* Address register direct. */
846 reg = get_areg(s, reg0);
847 if (what == EA_STORE) {
848 tcg_gen_mov_i32(reg, val);
849 return store_dummy;
850 } else {
851 return gen_extend(s, reg, opsize, what == EA_LOADS);
852 }
853 case 2: /* Indirect register */
854 reg = get_areg(s, reg0);
855 return gen_ldst(s, opsize, reg, val, what, index);
856 case 3: /* Indirect postincrement. */
857 reg = get_areg(s, reg0);
858 result = gen_ldst(s, opsize, reg, val, what, index);
859 if (what == EA_STORE || !addrp) {
860 TCGv tmp = tcg_temp_new();
861 if (reg0 == 7 && opsize == OS_BYTE &&
862 m68k_feature(s->env, M68K_FEATURE_M68000)) {
863 tcg_gen_addi_i32(tmp, reg, 2);
864 } else {
865 tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
866 }
867 delay_set_areg(s, reg0, tmp, true);
868 }
869 return result;
870 case 4: /* Indirect predecrememnt. */
871 if (addrp && what == EA_STORE) {
872 tmp = *addrp;
873 } else {
874 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
875 if (IS_NULL_QREG(tmp)) {
876 return tmp;
877 }
878 if (addrp) {
879 *addrp = tmp;
880 }
881 }
882 result = gen_ldst(s, opsize, tmp, val, what, index);
883 if (what == EA_STORE || !addrp) {
884 delay_set_areg(s, reg0, tmp, false);
885 }
886 return result;
887 case 5: /* Indirect displacement. */
888 case 6: /* Indirect index + displacement. */
889 do_indirect:
890 if (addrp && what == EA_STORE) {
891 tmp = *addrp;
892 } else {
893 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
894 if (IS_NULL_QREG(tmp)) {
895 return tmp;
896 }
897 if (addrp) {
898 *addrp = tmp;
899 }
900 }
901 return gen_ldst(s, opsize, tmp, val, what, index);
902 case 7: /* Other */
903 switch (reg0) {
904 case 0: /* Absolute short. */
905 case 1: /* Absolute long. */
906 case 2: /* pc displacement */
907 case 3: /* pc index+displacement. */
908 goto do_indirect;
909 case 4: /* Immediate. */
910 /* Sign extend values for consistency. */
911 switch (opsize) {
912 case OS_BYTE:
913 if (what == EA_LOADS) {
914 offset = (int8_t)read_im8(env, s);
915 } else {
916 offset = read_im8(env, s);
917 }
918 break;
919 case OS_WORD:
920 if (what == EA_LOADS) {
921 offset = (int16_t)read_im16(env, s);
922 } else {
923 offset = read_im16(env, s);
924 }
925 break;
926 case OS_LONG:
927 offset = read_im32(env, s);
928 break;
929 default:
930 g_assert_not_reached();
931 }
932 return mark_to_release(s, tcg_const_i32(offset));
933 default:
934 return NULL_QREG;
935 }
936 }
937 /* Should never happen. */
938 return NULL_QREG;
939 }
940
941 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
942 int opsize, TCGv val, TCGv *addrp, ea_what what, int index)
943 {
944 int mode = extract32(insn, 3, 3);
945 int reg0 = REG(insn, 0);
946 return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what, index);
947 }
948
949 static TCGv_ptr gen_fp_ptr(int freg)
950 {
951 TCGv_ptr fp = tcg_temp_new_ptr();
952 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg]));
953 return fp;
954 }
955
956 static TCGv_ptr gen_fp_result_ptr(void)
957 {
958 TCGv_ptr fp = tcg_temp_new_ptr();
959 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result));
960 return fp;
961 }
962
963 static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src)
964 {
965 TCGv t32;
966 TCGv_i64 t64;
967
968 t32 = tcg_temp_new();
969 tcg_gen_ld16u_i32(t32, src, offsetof(FPReg, l.upper));
970 tcg_gen_st16_i32(t32, dest, offsetof(FPReg, l.upper));
971 tcg_temp_free(t32);
972
973 t64 = tcg_temp_new_i64();
974 tcg_gen_ld_i64(t64, src, offsetof(FPReg, l.lower));
975 tcg_gen_st_i64(t64, dest, offsetof(FPReg, l.lower));
976 tcg_temp_free_i64(t64);
977 }
978
979 static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
980 int index)
981 {
982 TCGv tmp;
983 TCGv_i64 t64;
984
985 t64 = tcg_temp_new_i64();
986 tmp = tcg_temp_new();
987 switch (opsize) {
988 case OS_BYTE:
989 tcg_gen_qemu_ld8s(tmp, addr, index);
990 gen_helper_exts32(cpu_env, fp, tmp);
991 break;
992 case OS_WORD:
993 tcg_gen_qemu_ld16s(tmp, addr, index);
994 gen_helper_exts32(cpu_env, fp, tmp);
995 break;
996 case OS_LONG:
997 tcg_gen_qemu_ld32u(tmp, addr, index);
998 gen_helper_exts32(cpu_env, fp, tmp);
999 break;
1000 case OS_SINGLE:
1001 tcg_gen_qemu_ld32u(tmp, addr, index);
1002 gen_helper_extf32(cpu_env, fp, tmp);
1003 break;
1004 case OS_DOUBLE:
1005 tcg_gen_qemu_ld64(t64, addr, index);
1006 gen_helper_extf64(cpu_env, fp, t64);
1007 break;
1008 case OS_EXTENDED:
1009 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1010 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1011 break;
1012 }
1013 tcg_gen_qemu_ld32u(tmp, addr, index);
1014 tcg_gen_shri_i32(tmp, tmp, 16);
1015 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1016 tcg_gen_addi_i32(tmp, addr, 4);
1017 tcg_gen_qemu_ld64(t64, tmp, index);
1018 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1019 break;
1020 case OS_PACKED:
1021 /* unimplemented data type on 68040/ColdFire
1022 * FIXME if needed for another FPU
1023 */
1024 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1025 break;
1026 default:
1027 g_assert_not_reached();
1028 }
1029 tcg_temp_free(tmp);
1030 tcg_temp_free_i64(t64);
1031 }
1032
1033 static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
1034 int index)
1035 {
1036 TCGv tmp;
1037 TCGv_i64 t64;
1038
1039 t64 = tcg_temp_new_i64();
1040 tmp = tcg_temp_new();
1041 switch (opsize) {
1042 case OS_BYTE:
1043 gen_helper_reds32(tmp, cpu_env, fp);
1044 tcg_gen_qemu_st8(tmp, addr, index);
1045 break;
1046 case OS_WORD:
1047 gen_helper_reds32(tmp, cpu_env, fp);
1048 tcg_gen_qemu_st16(tmp, addr, index);
1049 break;
1050 case OS_LONG:
1051 gen_helper_reds32(tmp, cpu_env, fp);
1052 tcg_gen_qemu_st32(tmp, addr, index);
1053 break;
1054 case OS_SINGLE:
1055 gen_helper_redf32(tmp, cpu_env, fp);
1056 tcg_gen_qemu_st32(tmp, addr, index);
1057 break;
1058 case OS_DOUBLE:
1059 gen_helper_redf64(t64, cpu_env, fp);
1060 tcg_gen_qemu_st64(t64, addr, index);
1061 break;
1062 case OS_EXTENDED:
1063 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1064 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1065 break;
1066 }
1067 tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
1068 tcg_gen_shli_i32(tmp, tmp, 16);
1069 tcg_gen_qemu_st32(tmp, addr, index);
1070 tcg_gen_addi_i32(tmp, addr, 4);
1071 tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
1072 tcg_gen_qemu_st64(t64, tmp, index);
1073 break;
1074 case OS_PACKED:
1075 /* unimplemented data type on 68040/ColdFire
1076 * FIXME if needed for another FPU
1077 */
1078 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1079 break;
1080 default:
1081 g_assert_not_reached();
1082 }
1083 tcg_temp_free(tmp);
1084 tcg_temp_free_i64(t64);
1085 }
1086
1087 static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr,
1088 TCGv_ptr fp, ea_what what, int index)
1089 {
1090 if (what == EA_STORE) {
1091 gen_store_fp(s, opsize, addr, fp, index);
1092 } else {
1093 gen_load_fp(s, opsize, addr, fp, index);
1094 }
1095 }
1096
1097 static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
1098 int reg0, int opsize, TCGv_ptr fp, ea_what what,
1099 int index)
1100 {
1101 TCGv reg, addr, tmp;
1102 TCGv_i64 t64;
1103
1104 switch (mode) {
1105 case 0: /* Data register direct. */
1106 reg = cpu_dregs[reg0];
1107 if (what == EA_STORE) {
1108 switch (opsize) {
1109 case OS_BYTE:
1110 case OS_WORD:
1111 case OS_LONG:
1112 gen_helper_reds32(reg, cpu_env, fp);
1113 break;
1114 case OS_SINGLE:
1115 gen_helper_redf32(reg, cpu_env, fp);
1116 break;
1117 default:
1118 g_assert_not_reached();
1119 }
1120 } else {
1121 tmp = tcg_temp_new();
1122 switch (opsize) {
1123 case OS_BYTE:
1124 tcg_gen_ext8s_i32(tmp, reg);
1125 gen_helper_exts32(cpu_env, fp, tmp);
1126 break;
1127 case OS_WORD:
1128 tcg_gen_ext16s_i32(tmp, reg);
1129 gen_helper_exts32(cpu_env, fp, tmp);
1130 break;
1131 case OS_LONG:
1132 gen_helper_exts32(cpu_env, fp, reg);
1133 break;
1134 case OS_SINGLE:
1135 gen_helper_extf32(cpu_env, fp, reg);
1136 break;
1137 default:
1138 g_assert_not_reached();
1139 }
1140 tcg_temp_free(tmp);
1141 }
1142 return 0;
1143 case 1: /* Address register direct. */
1144 return -1;
1145 case 2: /* Indirect register */
1146 addr = get_areg(s, reg0);
1147 gen_ldst_fp(s, opsize, addr, fp, what, index);
1148 return 0;
1149 case 3: /* Indirect postincrement. */
1150 addr = cpu_aregs[reg0];
1151 gen_ldst_fp(s, opsize, addr, fp, what, index);
1152 tcg_gen_addi_i32(addr, addr, opsize_bytes(opsize));
1153 return 0;
1154 case 4: /* Indirect predecrememnt. */
1155 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1156 if (IS_NULL_QREG(addr)) {
1157 return -1;
1158 }
1159 gen_ldst_fp(s, opsize, addr, fp, what, index);
1160 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
1161 return 0;
1162 case 5: /* Indirect displacement. */
1163 case 6: /* Indirect index + displacement. */
1164 do_indirect:
1165 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1166 if (IS_NULL_QREG(addr)) {
1167 return -1;
1168 }
1169 gen_ldst_fp(s, opsize, addr, fp, what, index);
1170 return 0;
1171 case 7: /* Other */
1172 switch (reg0) {
1173 case 0: /* Absolute short. */
1174 case 1: /* Absolute long. */
1175 case 2: /* pc displacement */
1176 case 3: /* pc index+displacement. */
1177 goto do_indirect;
1178 case 4: /* Immediate. */
1179 if (what == EA_STORE) {
1180 return -1;
1181 }
1182 switch (opsize) {
1183 case OS_BYTE:
1184 tmp = tcg_const_i32((int8_t)read_im8(env, s));
1185 gen_helper_exts32(cpu_env, fp, tmp);
1186 tcg_temp_free(tmp);
1187 break;
1188 case OS_WORD:
1189 tmp = tcg_const_i32((int16_t)read_im16(env, s));
1190 gen_helper_exts32(cpu_env, fp, tmp);
1191 tcg_temp_free(tmp);
1192 break;
1193 case OS_LONG:
1194 tmp = tcg_const_i32(read_im32(env, s));
1195 gen_helper_exts32(cpu_env, fp, tmp);
1196 tcg_temp_free(tmp);
1197 break;
1198 case OS_SINGLE:
1199 tmp = tcg_const_i32(read_im32(env, s));
1200 gen_helper_extf32(cpu_env, fp, tmp);
1201 tcg_temp_free(tmp);
1202 break;
1203 case OS_DOUBLE:
1204 t64 = tcg_const_i64(read_im64(env, s));
1205 gen_helper_extf64(cpu_env, fp, t64);
1206 tcg_temp_free_i64(t64);
1207 break;
1208 case OS_EXTENDED:
1209 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1210 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1211 break;
1212 }
1213 tmp = tcg_const_i32(read_im32(env, s) >> 16);
1214 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1215 tcg_temp_free(tmp);
1216 t64 = tcg_const_i64(read_im64(env, s));
1217 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1218 tcg_temp_free_i64(t64);
1219 break;
1220 case OS_PACKED:
1221 /* unimplemented data type on 68040/ColdFire
1222 * FIXME if needed for another FPU
1223 */
1224 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1225 break;
1226 default:
1227 g_assert_not_reached();
1228 }
1229 return 0;
1230 default:
1231 return -1;
1232 }
1233 }
1234 return -1;
1235 }
1236
1237 static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn,
1238 int opsize, TCGv_ptr fp, ea_what what, int index)
1239 {
1240 int mode = extract32(insn, 3, 3);
1241 int reg0 = REG(insn, 0);
1242 return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what, index);
1243 }
1244
1245 typedef struct {
1246 TCGCond tcond;
1247 bool g1;
1248 bool g2;
1249 TCGv v1;
1250 TCGv v2;
1251 } DisasCompare;
1252
1253 static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
1254 {
1255 TCGv tmp, tmp2;
1256 TCGCond tcond;
1257 CCOp op = s->cc_op;
1258
1259 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1260 if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
1261 c->g1 = c->g2 = 1;
1262 c->v1 = QREG_CC_N;
1263 c->v2 = QREG_CC_V;
1264 switch (cond) {
1265 case 2: /* HI */
1266 case 3: /* LS */
1267 tcond = TCG_COND_LEU;
1268 goto done;
1269 case 4: /* CC */
1270 case 5: /* CS */
1271 tcond = TCG_COND_LTU;
1272 goto done;
1273 case 6: /* NE */
1274 case 7: /* EQ */
1275 tcond = TCG_COND_EQ;
1276 goto done;
1277 case 10: /* PL */
1278 case 11: /* MI */
1279 c->g1 = c->g2 = 0;
1280 c->v2 = tcg_const_i32(0);
1281 c->v1 = tmp = tcg_temp_new();
1282 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
1283 gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
1284 /* fallthru */
1285 case 12: /* GE */
1286 case 13: /* LT */
1287 tcond = TCG_COND_LT;
1288 goto done;
1289 case 14: /* GT */
1290 case 15: /* LE */
1291 tcond = TCG_COND_LE;
1292 goto done;
1293 }
1294 }
1295
1296 c->g1 = 1;
1297 c->g2 = 0;
1298 c->v2 = tcg_const_i32(0);
1299
1300 switch (cond) {
1301 case 0: /* T */
1302 case 1: /* F */
1303 c->v1 = c->v2;
1304 tcond = TCG_COND_NEVER;
1305 goto done;
1306 case 14: /* GT (!(Z || (N ^ V))) */
1307 case 15: /* LE (Z || (N ^ V)) */
1308 /* Logic operations clear V, which simplifies LE to (Z || N),
1309 and since Z and N are co-located, this becomes a normal
1310 comparison vs N. */
1311 if (op == CC_OP_LOGIC) {
1312 c->v1 = QREG_CC_N;
1313 tcond = TCG_COND_LE;
1314 goto done;
1315 }
1316 break;
1317 case 12: /* GE (!(N ^ V)) */
1318 case 13: /* LT (N ^ V) */
1319 /* Logic operations clear V, which simplifies this to N. */
1320 if (op != CC_OP_LOGIC) {
1321 break;
1322 }
1323 /* fallthru */
1324 case 10: /* PL (!N) */
1325 case 11: /* MI (N) */
1326 /* Several cases represent N normally. */
1327 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1328 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1329 op == CC_OP_LOGIC) {
1330 c->v1 = QREG_CC_N;
1331 tcond = TCG_COND_LT;
1332 goto done;
1333 }
1334 break;
1335 case 6: /* NE (!Z) */
1336 case 7: /* EQ (Z) */
1337 /* Some cases fold Z into N. */
1338 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1339 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1340 op == CC_OP_LOGIC) {
1341 tcond = TCG_COND_EQ;
1342 c->v1 = QREG_CC_N;
1343 goto done;
1344 }
1345 break;
1346 case 4: /* CC (!C) */
1347 case 5: /* CS (C) */
1348 /* Some cases fold C into X. */
1349 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1350 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL) {
1351 tcond = TCG_COND_NE;
1352 c->v1 = QREG_CC_X;
1353 goto done;
1354 }
1355 /* fallthru */
1356 case 8: /* VC (!V) */
1357 case 9: /* VS (V) */
1358 /* Logic operations clear V and C. */
1359 if (op == CC_OP_LOGIC) {
1360 tcond = TCG_COND_NEVER;
1361 c->v1 = c->v2;
1362 goto done;
1363 }
1364 break;
1365 }
1366
1367 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1368 gen_flush_flags(s);
1369
1370 switch (cond) {
1371 case 0: /* T */
1372 case 1: /* F */
1373 default:
1374 /* Invalid, or handled above. */
1375 abort();
1376 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1377 case 3: /* LS (C || Z) */
1378 c->v1 = tmp = tcg_temp_new();
1379 c->g1 = 0;
1380 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1381 tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
1382 tcond = TCG_COND_NE;
1383 break;
1384 case 4: /* CC (!C) */
1385 case 5: /* CS (C) */
1386 c->v1 = QREG_CC_C;
1387 tcond = TCG_COND_NE;
1388 break;
1389 case 6: /* NE (!Z) */
1390 case 7: /* EQ (Z) */
1391 c->v1 = QREG_CC_Z;
1392 tcond = TCG_COND_EQ;
1393 break;
1394 case 8: /* VC (!V) */
1395 case 9: /* VS (V) */
1396 c->v1 = QREG_CC_V;
1397 tcond = TCG_COND_LT;
1398 break;
1399 case 10: /* PL (!N) */
1400 case 11: /* MI (N) */
1401 c->v1 = QREG_CC_N;
1402 tcond = TCG_COND_LT;
1403 break;
1404 case 12: /* GE (!(N ^ V)) */
1405 case 13: /* LT (N ^ V) */
1406 c->v1 = tmp = tcg_temp_new();
1407 c->g1 = 0;
1408 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
1409 tcond = TCG_COND_LT;
1410 break;
1411 case 14: /* GT (!(Z || (N ^ V))) */
1412 case 15: /* LE (Z || (N ^ V)) */
1413 c->v1 = tmp = tcg_temp_new();
1414 c->g1 = 0;
1415 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1416 tcg_gen_neg_i32(tmp, tmp);
1417 tmp2 = tcg_temp_new();
1418 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
1419 tcg_gen_or_i32(tmp, tmp, tmp2);
1420 tcg_temp_free(tmp2);
1421 tcond = TCG_COND_LT;
1422 break;
1423 }
1424
1425 done:
1426 if ((cond & 1) == 0) {
1427 tcond = tcg_invert_cond(tcond);
1428 }
1429 c->tcond = tcond;
1430 }
1431
1432 static void free_cond(DisasCompare *c)
1433 {
1434 if (!c->g1) {
1435 tcg_temp_free(c->v1);
1436 }
1437 if (!c->g2) {
1438 tcg_temp_free(c->v2);
1439 }
1440 }
1441
1442 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
1443 {
1444 DisasCompare c;
1445
1446 gen_cc_cond(&c, s, cond);
1447 update_cc_op(s);
1448 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
1449 free_cond(&c);
1450 }
1451
1452 /* Force a TB lookup after an instruction that changes the CPU state. */
1453 static void gen_lookup_tb(DisasContext *s)
1454 {
1455 update_cc_op(s);
1456 tcg_gen_movi_i32(QREG_PC, s->pc);
1457 s->is_jmp = DISAS_UPDATE;
1458 }
1459
1460 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1461 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1462 op_sign ? EA_LOADS : EA_LOADU, IS_USER(s)); \
1463 if (IS_NULL_QREG(result)) { \
1464 gen_addr_fault(s); \
1465 return; \
1466 } \
1467 } while (0)
1468
1469 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1470 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, \
1471 EA_STORE, IS_USER(s)); \
1472 if (IS_NULL_QREG(ea_result)) { \
1473 gen_addr_fault(s); \
1474 return; \
1475 } \
1476 } while (0)
1477
1478 static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
1479 {
1480 #ifndef CONFIG_USER_ONLY
1481 return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
1482 (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
1483 #else
1484 return true;
1485 #endif
1486 }
1487
1488 /* Generate a jump to an immediate address. */
1489 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
1490 {
1491 if (unlikely(s->singlestep_enabled)) {
1492 gen_exception(s, dest, EXCP_DEBUG);
1493 } else if (use_goto_tb(s, dest)) {
1494 tcg_gen_goto_tb(n);
1495 tcg_gen_movi_i32(QREG_PC, dest);
1496 tcg_gen_exit_tb((uintptr_t)s->tb + n);
1497 } else {
1498 gen_jmp_im(s, dest);
1499 tcg_gen_exit_tb(0);
1500 }
1501 s->is_jmp = DISAS_TB_JUMP;
1502 }
1503
1504 DISAS_INSN(scc)
1505 {
1506 DisasCompare c;
1507 int cond;
1508 TCGv tmp;
1509
1510 cond = (insn >> 8) & 0xf;
1511 gen_cc_cond(&c, s, cond);
1512
1513 tmp = tcg_temp_new();
1514 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
1515 free_cond(&c);
1516
1517 tcg_gen_neg_i32(tmp, tmp);
1518 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
1519 tcg_temp_free(tmp);
1520 }
1521
1522 DISAS_INSN(dbcc)
1523 {
1524 TCGLabel *l1;
1525 TCGv reg;
1526 TCGv tmp;
1527 int16_t offset;
1528 uint32_t base;
1529
1530 reg = DREG(insn, 0);
1531 base = s->pc;
1532 offset = (int16_t)read_im16(env, s);
1533 l1 = gen_new_label();
1534 gen_jmpcc(s, (insn >> 8) & 0xf, l1);
1535
1536 tmp = tcg_temp_new();
1537 tcg_gen_ext16s_i32(tmp, reg);
1538 tcg_gen_addi_i32(tmp, tmp, -1);
1539 gen_partset_reg(OS_WORD, reg, tmp);
1540 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1);
1541 gen_jmp_tb(s, 1, base + offset);
1542 gen_set_label(l1);
1543 gen_jmp_tb(s, 0, s->pc);
1544 }
1545
1546 DISAS_INSN(undef_mac)
1547 {
1548 gen_exception(s, s->insn_pc, EXCP_LINEA);
1549 }
1550
1551 DISAS_INSN(undef_fpu)
1552 {
1553 gen_exception(s, s->insn_pc, EXCP_LINEF);
1554 }
1555
1556 DISAS_INSN(undef)
1557 {
1558 /* ??? This is both instructions that are as yet unimplemented
1559 for the 680x0 series, as well as those that are implemented
1560 but actually illegal for CPU32 or pre-68020. */
1561 qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x",
1562 insn, s->insn_pc);
1563 gen_exception(s, s->insn_pc, EXCP_UNSUPPORTED);
1564 }
1565
1566 DISAS_INSN(mulw)
1567 {
1568 TCGv reg;
1569 TCGv tmp;
1570 TCGv src;
1571 int sign;
1572
1573 sign = (insn & 0x100) != 0;
1574 reg = DREG(insn, 9);
1575 tmp = tcg_temp_new();
1576 if (sign)
1577 tcg_gen_ext16s_i32(tmp, reg);
1578 else
1579 tcg_gen_ext16u_i32(tmp, reg);
1580 SRC_EA(env, src, OS_WORD, sign, NULL);
1581 tcg_gen_mul_i32(tmp, tmp, src);
1582 tcg_gen_mov_i32(reg, tmp);
1583 gen_logic_cc(s, tmp, OS_LONG);
1584 tcg_temp_free(tmp);
1585 }
1586
1587 DISAS_INSN(divw)
1588 {
1589 int sign;
1590 TCGv src;
1591 TCGv destr;
1592
1593 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1594
1595 sign = (insn & 0x100) != 0;
1596
1597 /* dest.l / src.w */
1598
1599 SRC_EA(env, src, OS_WORD, sign, NULL);
1600 destr = tcg_const_i32(REG(insn, 9));
1601 if (sign) {
1602 gen_helper_divsw(cpu_env, destr, src);
1603 } else {
1604 gen_helper_divuw(cpu_env, destr, src);
1605 }
1606 tcg_temp_free(destr);
1607
1608 set_cc_op(s, CC_OP_FLAGS);
1609 }
1610
1611 DISAS_INSN(divl)
1612 {
1613 TCGv num, reg, den;
1614 int sign;
1615 uint16_t ext;
1616
1617 ext = read_im16(env, s);
1618
1619 sign = (ext & 0x0800) != 0;
1620
1621 if (ext & 0x400) {
1622 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
1623 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
1624 return;
1625 }
1626
1627 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1628
1629 SRC_EA(env, den, OS_LONG, 0, NULL);
1630 num = tcg_const_i32(REG(ext, 12));
1631 reg = tcg_const_i32(REG(ext, 0));
1632 if (sign) {
1633 gen_helper_divsll(cpu_env, num, reg, den);
1634 } else {
1635 gen_helper_divull(cpu_env, num, reg, den);
1636 }
1637 tcg_temp_free(reg);
1638 tcg_temp_free(num);
1639 set_cc_op(s, CC_OP_FLAGS);
1640 return;
1641 }
1642
1643 /* divX.l <EA>, Dq 32/32 -> 32q */
1644 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1645
1646 SRC_EA(env, den, OS_LONG, 0, NULL);
1647 num = tcg_const_i32(REG(ext, 12));
1648 reg = tcg_const_i32(REG(ext, 0));
1649 if (sign) {
1650 gen_helper_divsl(cpu_env, num, reg, den);
1651 } else {
1652 gen_helper_divul(cpu_env, num, reg, den);
1653 }
1654 tcg_temp_free(reg);
1655 tcg_temp_free(num);
1656
1657 set_cc_op(s, CC_OP_FLAGS);
1658 }
1659
1660 static void bcd_add(TCGv dest, TCGv src)
1661 {
1662 TCGv t0, t1;
1663
1664 /* dest10 = dest10 + src10 + X
1665 *
1666 * t1 = src
1667 * t2 = t1 + 0x066
1668 * t3 = t2 + dest + X
1669 * t4 = t2 ^ dest
1670 * t5 = t3 ^ t4
1671 * t6 = ~t5 & 0x110
1672 * t7 = (t6 >> 2) | (t6 >> 3)
1673 * return t3 - t7
1674 */
1675
1676 /* t1 = (src + 0x066) + dest + X
1677 * = result with some possible exceding 0x6
1678 */
1679
1680 t0 = tcg_const_i32(0x066);
1681 tcg_gen_add_i32(t0, t0, src);
1682
1683 t1 = tcg_temp_new();
1684 tcg_gen_add_i32(t1, t0, dest);
1685 tcg_gen_add_i32(t1, t1, QREG_CC_X);
1686
1687 /* we will remove exceding 0x6 where there is no carry */
1688
1689 /* t0 = (src + 0x0066) ^ dest
1690 * = t1 without carries
1691 */
1692
1693 tcg_gen_xor_i32(t0, t0, dest);
1694
1695 /* extract the carries
1696 * t0 = t0 ^ t1
1697 * = only the carries
1698 */
1699
1700 tcg_gen_xor_i32(t0, t0, t1);
1701
1702 /* generate 0x1 where there is no carry
1703 * and for each 0x10, generate a 0x6
1704 */
1705
1706 tcg_gen_shri_i32(t0, t0, 3);
1707 tcg_gen_not_i32(t0, t0);
1708 tcg_gen_andi_i32(t0, t0, 0x22);
1709 tcg_gen_add_i32(dest, t0, t0);
1710 tcg_gen_add_i32(dest, dest, t0);
1711 tcg_temp_free(t0);
1712
1713 /* remove the exceding 0x6
1714 * for digits that have not generated a carry
1715 */
1716
1717 tcg_gen_sub_i32(dest, t1, dest);
1718 tcg_temp_free(t1);
1719 }
1720
1721 static void bcd_sub(TCGv dest, TCGv src)
1722 {
1723 TCGv t0, t1, t2;
1724
1725 /* dest10 = dest10 - src10 - X
1726 * = bcd_add(dest + 1 - X, 0x199 - src)
1727 */
1728
1729 /* t0 = 0x066 + (0x199 - src) */
1730
1731 t0 = tcg_temp_new();
1732 tcg_gen_subfi_i32(t0, 0x1ff, src);
1733
1734 /* t1 = t0 + dest + 1 - X*/
1735
1736 t1 = tcg_temp_new();
1737 tcg_gen_add_i32(t1, t0, dest);
1738 tcg_gen_addi_i32(t1, t1, 1);
1739 tcg_gen_sub_i32(t1, t1, QREG_CC_X);
1740
1741 /* t2 = t0 ^ dest */
1742
1743 t2 = tcg_temp_new();
1744 tcg_gen_xor_i32(t2, t0, dest);
1745
1746 /* t0 = t1 ^ t2 */
1747
1748 tcg_gen_xor_i32(t0, t1, t2);
1749
1750 /* t2 = ~t0 & 0x110
1751 * t0 = (t2 >> 2) | (t2 >> 3)
1752 *
1753 * to fit on 8bit operands, changed in:
1754 *
1755 * t2 = ~(t0 >> 3) & 0x22
1756 * t0 = t2 + t2
1757 * t0 = t0 + t2
1758 */
1759
1760 tcg_gen_shri_i32(t2, t0, 3);
1761 tcg_gen_not_i32(t2, t2);
1762 tcg_gen_andi_i32(t2, t2, 0x22);
1763 tcg_gen_add_i32(t0, t2, t2);
1764 tcg_gen_add_i32(t0, t0, t2);
1765 tcg_temp_free(t2);
1766
1767 /* return t1 - t0 */
1768
1769 tcg_gen_sub_i32(dest, t1, t0);
1770 tcg_temp_free(t0);
1771 tcg_temp_free(t1);
1772 }
1773
1774 static void bcd_flags(TCGv val)
1775 {
1776 tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
1777 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
1778
1779 tcg_gen_extract_i32(QREG_CC_C, val, 8, 1);
1780
1781 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
1782 }
1783
1784 DISAS_INSN(abcd_reg)
1785 {
1786 TCGv src;
1787 TCGv dest;
1788
1789 gen_flush_flags(s); /* !Z is sticky */
1790
1791 src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
1792 dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
1793 bcd_add(dest, src);
1794 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1795
1796 bcd_flags(dest);
1797 }
1798
1799 DISAS_INSN(abcd_mem)
1800 {
1801 TCGv src, dest, addr;
1802
1803 gen_flush_flags(s); /* !Z is sticky */
1804
1805 /* Indirect pre-decrement load (mode 4) */
1806
1807 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1808 NULL_QREG, NULL, EA_LOADU, IS_USER(s));
1809 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1810 NULL_QREG, &addr, EA_LOADU, IS_USER(s));
1811
1812 bcd_add(dest, src);
1813
1814 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr,
1815 EA_STORE, IS_USER(s));
1816
1817 bcd_flags(dest);
1818 }
1819
1820 DISAS_INSN(sbcd_reg)
1821 {
1822 TCGv src, dest;
1823
1824 gen_flush_flags(s); /* !Z is sticky */
1825
1826 src = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
1827 dest = gen_extend(s, DREG(insn, 9), OS_BYTE, 0);
1828
1829 bcd_sub(dest, src);
1830
1831 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1832
1833 bcd_flags(dest);
1834 }
1835
1836 DISAS_INSN(sbcd_mem)
1837 {
1838 TCGv src, dest, addr;
1839
1840 gen_flush_flags(s); /* !Z is sticky */
1841
1842 /* Indirect pre-decrement load (mode 4) */
1843
1844 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1845 NULL_QREG, NULL, EA_LOADU, IS_USER(s));
1846 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1847 NULL_QREG, &addr, EA_LOADU, IS_USER(s));
1848
1849 bcd_sub(dest, src);
1850
1851 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr,
1852 EA_STORE, IS_USER(s));
1853
1854 bcd_flags(dest);
1855 }
1856
1857 DISAS_INSN(nbcd)
1858 {
1859 TCGv src, dest;
1860 TCGv addr;
1861
1862 gen_flush_flags(s); /* !Z is sticky */
1863
1864 SRC_EA(env, src, OS_BYTE, 0, &addr);
1865
1866 dest = tcg_const_i32(0);
1867 bcd_sub(dest, src);
1868
1869 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1870
1871 bcd_flags(dest);
1872
1873 tcg_temp_free(dest);
1874 }
1875
1876 DISAS_INSN(addsub)
1877 {
1878 TCGv reg;
1879 TCGv dest;
1880 TCGv src;
1881 TCGv tmp;
1882 TCGv addr;
1883 int add;
1884 int opsize;
1885
1886 add = (insn & 0x4000) != 0;
1887 opsize = insn_opsize(insn);
1888 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
1889 dest = tcg_temp_new();
1890 if (insn & 0x100) {
1891 SRC_EA(env, tmp, opsize, 1, &addr);
1892 src = reg;
1893 } else {
1894 tmp = reg;
1895 SRC_EA(env, src, opsize, 1, NULL);
1896 }
1897 if (add) {
1898 tcg_gen_add_i32(dest, tmp, src);
1899 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src);
1900 set_cc_op(s, CC_OP_ADDB + opsize);
1901 } else {
1902 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src);
1903 tcg_gen_sub_i32(dest, tmp, src);
1904 set_cc_op(s, CC_OP_SUBB + opsize);
1905 }
1906 gen_update_cc_add(dest, src, opsize);
1907 if (insn & 0x100) {
1908 DEST_EA(env, insn, opsize, dest, &addr);
1909 } else {
1910 gen_partset_reg(opsize, DREG(insn, 9), dest);
1911 }
1912 tcg_temp_free(dest);
1913 }
1914
1915 /* Reverse the order of the bits in REG. */
1916 DISAS_INSN(bitrev)
1917 {
1918 TCGv reg;
1919 reg = DREG(insn, 0);
1920 gen_helper_bitrev(reg, reg);
1921 }
1922
1923 DISAS_INSN(bitop_reg)
1924 {
1925 int opsize;
1926 int op;
1927 TCGv src1;
1928 TCGv src2;
1929 TCGv tmp;
1930 TCGv addr;
1931 TCGv dest;
1932
1933 if ((insn & 0x38) != 0)
1934 opsize = OS_BYTE;
1935 else
1936 opsize = OS_LONG;
1937 op = (insn >> 6) & 3;
1938 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1939
1940 gen_flush_flags(s);
1941 src2 = tcg_temp_new();
1942 if (opsize == OS_BYTE)
1943 tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
1944 else
1945 tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
1946
1947 tmp = tcg_const_i32(1);
1948 tcg_gen_shl_i32(tmp, tmp, src2);
1949 tcg_temp_free(src2);
1950
1951 tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
1952
1953 dest = tcg_temp_new();
1954 switch (op) {
1955 case 1: /* bchg */
1956 tcg_gen_xor_i32(dest, src1, tmp);
1957 break;
1958 case 2: /* bclr */
1959 tcg_gen_andc_i32(dest, src1, tmp);
1960 break;
1961 case 3: /* bset */
1962 tcg_gen_or_i32(dest, src1, tmp);
1963 break;
1964 default: /* btst */
1965 break;
1966 }
1967 tcg_temp_free(tmp);
1968 if (op) {
1969 DEST_EA(env, insn, opsize, dest, &addr);
1970 }
1971 tcg_temp_free(dest);
1972 }
1973
1974 DISAS_INSN(sats)
1975 {
1976 TCGv reg;
1977 reg = DREG(insn, 0);
1978 gen_flush_flags(s);
1979 gen_helper_sats(reg, reg, QREG_CC_V);
1980 gen_logic_cc(s, reg, OS_LONG);
1981 }
1982
1983 static void gen_push(DisasContext *s, TCGv val)
1984 {
1985 TCGv tmp;
1986
1987 tmp = tcg_temp_new();
1988 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1989 gen_store(s, OS_LONG, tmp, val, IS_USER(s));
1990 tcg_gen_mov_i32(QREG_SP, tmp);
1991 tcg_temp_free(tmp);
1992 }
1993
1994 static TCGv mreg(int reg)
1995 {
1996 if (reg < 8) {
1997 /* Dx */
1998 return cpu_dregs[reg];
1999 }
2000 /* Ax */
2001 return cpu_aregs[reg & 7];
2002 }
2003
2004 DISAS_INSN(movem)
2005 {
2006 TCGv addr, incr, tmp, r[16];
2007 int is_load = (insn & 0x0400) != 0;
2008 int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD;
2009 uint16_t mask = read_im16(env, s);
2010 int mode = extract32(insn, 3, 3);
2011 int reg0 = REG(insn, 0);
2012 int i;
2013
2014 tmp = cpu_aregs[reg0];
2015
2016 switch (mode) {
2017 case 0: /* data register direct */
2018 case 1: /* addr register direct */
2019 do_addr_fault:
2020 gen_addr_fault(s);
2021 return;
2022
2023 case 2: /* indirect */
2024 break;
2025
2026 case 3: /* indirect post-increment */
2027 if (!is_load) {
2028 /* post-increment is not allowed */
2029 goto do_addr_fault;
2030 }
2031 break;
2032
2033 case 4: /* indirect pre-decrement */
2034 if (is_load) {
2035 /* pre-decrement is not allowed */
2036 goto do_addr_fault;
2037 }
2038 /* We want a bare copy of the address reg, without any pre-decrement
2039 adjustment, as gen_lea would provide. */
2040 break;
2041
2042 default:
2043 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
2044 if (IS_NULL_QREG(tmp)) {
2045 goto do_addr_fault;
2046 }
2047 break;
2048 }
2049
2050 addr = tcg_temp_new();
2051 tcg_gen_mov_i32(addr, tmp);
2052 incr = tcg_const_i32(opsize_bytes(opsize));
2053
2054 if (is_load) {
2055 /* memory to register */
2056 for (i = 0; i < 16; i++) {
2057 if (mask & (1 << i)) {
2058 r[i] = gen_load(s, opsize, addr, 1, IS_USER(s));
2059 tcg_gen_add_i32(addr, addr, incr);
2060 }
2061 }
2062 for (i = 0; i < 16; i++) {
2063 if (mask & (1 << i)) {
2064 tcg_gen_mov_i32(mreg(i), r[i]);
2065 tcg_temp_free(r[i]);
2066 }
2067 }
2068 if (mode == 3) {
2069 /* post-increment: movem (An)+,X */
2070 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2071 }
2072 } else {
2073 /* register to memory */
2074 if (mode == 4) {
2075 /* pre-decrement: movem X,-(An) */
2076 for (i = 15; i >= 0; i--) {
2077 if ((mask << i) & 0x8000) {
2078 tcg_gen_sub_i32(addr, addr, incr);
2079 if (reg0 + 8 == i &&
2080 m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) {
2081 /* M68020+: if the addressing register is the
2082 * register moved to memory, the value written
2083 * is the initial value decremented by the size of
2084 * the operation, regardless of how many actual
2085 * stores have been performed until this point.
2086 * M68000/M68010: the value is the initial value.
2087 */
2088 tmp = tcg_temp_new();
2089 tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr);
2090 gen_store(s, opsize, addr, tmp, IS_USER(s));
2091 tcg_temp_free(tmp);
2092 } else {
2093 gen_store(s, opsize, addr, mreg(i), IS_USER(s));
2094 }
2095 }
2096 }
2097 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2098 } else {
2099 for (i = 0; i < 16; i++) {
2100 if (mask & (1 << i)) {
2101 gen_store(s, opsize, addr, mreg(i), IS_USER(s));
2102 tcg_gen_add_i32(addr, addr, incr);
2103 }
2104 }
2105 }
2106 }
2107
2108 tcg_temp_free(incr);
2109 tcg_temp_free(addr);
2110 }
2111
2112 DISAS_INSN(movep)
2113 {
2114 uint8_t i;
2115 int16_t displ;
2116 TCGv reg;
2117 TCGv addr;
2118 TCGv abuf;
2119 TCGv dbuf;
2120
2121 displ = read_im16(env, s);
2122
2123 addr = AREG(insn, 0);
2124 reg = DREG(insn, 9);
2125
2126 abuf = tcg_temp_new();
2127 tcg_gen_addi_i32(abuf, addr, displ);
2128 dbuf = tcg_temp_new();
2129
2130 if (insn & 0x40) {
2131 i = 4;
2132 } else {
2133 i = 2;
2134 }
2135
2136 if (insn & 0x80) {
2137 for ( ; i > 0 ; i--) {
2138 tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8);
2139 tcg_gen_qemu_st8(dbuf, abuf, IS_USER(s));
2140 if (i > 1) {
2141 tcg_gen_addi_i32(abuf, abuf, 2);
2142 }
2143 }
2144 } else {
2145 for ( ; i > 0 ; i--) {
2146 tcg_gen_qemu_ld8u(dbuf, abuf, IS_USER(s));
2147 tcg_gen_deposit_i32(reg, reg, dbuf, (i - 1) * 8, 8);
2148 if (i > 1) {
2149 tcg_gen_addi_i32(abuf, abuf, 2);
2150 }
2151 }
2152 }
2153 tcg_temp_free(abuf);
2154 tcg_temp_free(dbuf);
2155 }
2156
2157 DISAS_INSN(bitop_im)
2158 {
2159 int opsize;
2160 int op;
2161 TCGv src1;
2162 uint32_t mask;
2163 int bitnum;
2164 TCGv tmp;
2165 TCGv addr;
2166
2167 if ((insn & 0x38) != 0)
2168 opsize = OS_BYTE;
2169 else
2170 opsize = OS_LONG;
2171 op = (insn >> 6) & 3;
2172
2173 bitnum = read_im16(env, s);
2174 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2175 if (bitnum & 0xfe00) {
2176 disas_undef(env, s, insn);
2177 return;
2178 }
2179 } else {
2180 if (bitnum & 0xff00) {
2181 disas_undef(env, s, insn);
2182 return;
2183 }
2184 }
2185
2186 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
2187
2188 gen_flush_flags(s);
2189 if (opsize == OS_BYTE)
2190 bitnum &= 7;
2191 else
2192 bitnum &= 31;
2193 mask = 1 << bitnum;
2194
2195 tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
2196
2197 if (op) {
2198 tmp = tcg_temp_new();
2199 switch (op) {
2200 case 1: /* bchg */
2201 tcg_gen_xori_i32(tmp, src1, mask);
2202 break;
2203 case 2: /* bclr */
2204 tcg_gen_andi_i32(tmp, src1, ~mask);
2205 break;
2206 case 3: /* bset */
2207 tcg_gen_ori_i32(tmp, src1, mask);
2208 break;
2209 default: /* btst */
2210 break;
2211 }
2212 DEST_EA(env, insn, opsize, tmp, &addr);
2213 tcg_temp_free(tmp);
2214 }
2215 }
2216
2217 static TCGv gen_get_ccr(DisasContext *s)
2218 {
2219 TCGv dest;
2220
2221 update_cc_op(s);
2222 dest = tcg_temp_new();
2223 gen_helper_get_ccr(dest, cpu_env);
2224 return dest;
2225 }
2226
2227 static TCGv gen_get_sr(DisasContext *s)
2228 {
2229 TCGv ccr;
2230 TCGv sr;
2231
2232 ccr = gen_get_ccr(s);
2233 sr = tcg_temp_new();
2234 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
2235 tcg_gen_or_i32(sr, sr, ccr);
2236 return sr;
2237 }
2238
2239 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
2240 {
2241 if (ccr_only) {
2242 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
2243 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
2244 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
2245 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
2246 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
2247 } else {
2248 TCGv sr = tcg_const_i32(val);
2249 gen_helper_set_sr(cpu_env, sr);
2250 tcg_temp_free(sr);
2251 }
2252 set_cc_op(s, CC_OP_FLAGS);
2253 }
2254
2255 static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
2256 {
2257 if (ccr_only) {
2258 gen_helper_set_ccr(cpu_env, val);
2259 } else {
2260 gen_helper_set_sr(cpu_env, val);
2261 }
2262 set_cc_op(s, CC_OP_FLAGS);
2263 }
2264
2265 static void gen_move_to_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
2266 bool ccr_only)
2267 {
2268 if ((insn & 0x3f) == 0x3c) {
2269 uint16_t val;
2270 val = read_im16(env, s);
2271 gen_set_sr_im(s, val, ccr_only);
2272 } else {
2273 TCGv src;
2274 SRC_EA(env, src, OS_WORD, 0, NULL);
2275 gen_set_sr(s, src, ccr_only);
2276 }
2277 }
2278
2279 DISAS_INSN(arith_im)
2280 {
2281 int op;
2282 TCGv im;
2283 TCGv src1;
2284 TCGv dest;
2285 TCGv addr;
2286 int opsize;
2287 bool with_SR = ((insn & 0x3f) == 0x3c);
2288
2289 op = (insn >> 9) & 7;
2290 opsize = insn_opsize(insn);
2291 switch (opsize) {
2292 case OS_BYTE:
2293 im = tcg_const_i32((int8_t)read_im8(env, s));
2294 break;
2295 case OS_WORD:
2296 im = tcg_const_i32((int16_t)read_im16(env, s));
2297 break;
2298 case OS_LONG:
2299 im = tcg_const_i32(read_im32(env, s));
2300 break;
2301 default:
2302 abort();
2303 }
2304
2305 if (with_SR) {
2306 /* SR/CCR can only be used with andi/eori/ori */
2307 if (op == 2 || op == 3 || op == 6) {
2308 disas_undef(env, s, insn);
2309 return;
2310 }
2311 switch (opsize) {
2312 case OS_BYTE:
2313 src1 = gen_get_ccr(s);
2314 break;
2315 case OS_WORD:
2316 if (IS_USER(s)) {
2317 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
2318 return;
2319 }
2320 src1 = gen_get_sr(s);
2321 break;
2322 case OS_LONG:
2323 disas_undef(env, s, insn);
2324 return;
2325 }
2326 } else {
2327 SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr);
2328 }
2329 dest = tcg_temp_new();
2330 switch (op) {
2331 case 0: /* ori */
2332 tcg_gen_or_i32(dest, src1, im);
2333 if (with_SR) {
2334 gen_set_sr(s, dest, opsize == OS_BYTE);
2335 } else {
2336 DEST_EA(env, insn, opsize, dest, &addr);
2337 gen_logic_cc(s, dest, opsize);
2338 }
2339 break;
2340 case 1: /* andi */
2341 tcg_gen_and_i32(dest, src1, im);
2342 if (with_SR) {
2343 gen_set_sr(s, dest, opsize == OS_BYTE);
2344 } else {
2345 DEST_EA(env, insn, opsize, dest, &addr);
2346 gen_logic_cc(s, dest, opsize);
2347 }
2348 break;
2349 case 2: /* subi */
2350 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im);
2351 tcg_gen_sub_i32(dest, src1, im);
2352 gen_update_cc_add(dest, im, opsize);
2353 set_cc_op(s, CC_OP_SUBB + opsize);
2354 DEST_EA(env, insn, opsize, dest, &addr);
2355 break;
2356 case 3: /* addi */
2357 tcg_gen_add_i32(dest, src1, im);
2358 gen_update_cc_add(dest, im, opsize);
2359 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
2360 set_cc_op(s, CC_OP_ADDB + opsize);
2361 DEST_EA(env, insn, opsize, dest, &addr);
2362 break;
2363 case 5: /* eori */
2364 tcg_gen_xor_i32(dest, src1, im);
2365 if (with_SR) {
2366 gen_set_sr(s, dest, opsize == OS_BYTE);
2367 } else {
2368 DEST_EA(env, insn, opsize, dest, &addr);
2369 gen_logic_cc(s, dest, opsize);
2370 }
2371 break;
2372 case 6: /* cmpi */
2373 gen_update_cc_cmp(s, src1, im, opsize);
2374 break;
2375 default:
2376 abort();
2377 }
2378 tcg_temp_free(im);
2379 tcg_temp_free(dest);
2380 }
2381
2382 DISAS_INSN(cas)
2383 {
2384 int opsize;
2385 TCGv addr;
2386 uint16_t ext;
2387 TCGv load;
2388 TCGv cmp;
2389 TCGMemOp opc;
2390
2391 switch ((insn >> 9) & 3) {
2392 case 1:
2393 opsize = OS_BYTE;
2394 opc = MO_SB;
2395 break;
2396 case 2:
2397 opsize = OS_WORD;
2398 opc = MO_TESW;
2399 break;
2400 case 3:
2401 opsize = OS_LONG;
2402 opc = MO_TESL;
2403 break;
2404 default:
2405 g_assert_not_reached();
2406 }
2407
2408 ext = read_im16(env, s);
2409
2410 /* cas Dc,Du,<EA> */
2411
2412 addr = gen_lea(env, s, insn, opsize);
2413 if (IS_NULL_QREG(addr)) {
2414 gen_addr_fault(s);
2415 return;
2416 }
2417
2418 cmp = gen_extend(s, DREG(ext, 0), opsize, 1);
2419
2420 /* if <EA> == Dc then
2421 * <EA> = Du
2422 * Dc = <EA> (because <EA> == Dc)
2423 * else
2424 * Dc = <EA>
2425 */
2426
2427 load = tcg_temp_new();
2428 tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6),
2429 IS_USER(s), opc);
2430 /* update flags before setting cmp to load */
2431 gen_update_cc_cmp(s, load, cmp, opsize);
2432 gen_partset_reg(opsize, DREG(ext, 0), load);
2433
2434 tcg_temp_free(load);
2435
2436 switch (extract32(insn, 3, 3)) {
2437 case 3: /* Indirect postincrement. */
2438 tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize));
2439 break;
2440 case 4: /* Indirect predecrememnt. */
2441 tcg_gen_mov_i32(AREG(insn, 0), addr);
2442 break;
2443 }
2444 }
2445
2446 DISAS_INSN(cas2w)
2447 {
2448 uint16_t ext1, ext2;
2449 TCGv addr1, addr2;
2450 TCGv regs;
2451
2452 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2453
2454 ext1 = read_im16(env, s);
2455
2456 if (ext1 & 0x8000) {
2457 /* Address Register */
2458 addr1 = AREG(ext1, 12);
2459 } else {
2460 /* Data Register */
2461 addr1 = DREG(ext1, 12);
2462 }
2463
2464 ext2 = read_im16(env, s);
2465 if (ext2 & 0x8000) {
2466 /* Address Register */
2467 addr2 = AREG(ext2, 12);
2468 } else {
2469 /* Data Register */
2470 addr2 = DREG(ext2, 12);
2471 }
2472
2473 /* if (R1) == Dc1 && (R2) == Dc2 then
2474 * (R1) = Du1
2475 * (R2) = Du2
2476 * else
2477 * Dc1 = (R1)
2478 * Dc2 = (R2)
2479 */
2480
2481 regs = tcg_const_i32(REG(ext2, 6) |
2482 (REG(ext1, 6) << 3) |
2483 (REG(ext2, 0) << 6) |
2484 (REG(ext1, 0) << 9));
2485 if (tb_cflags(s->tb) & CF_PARALLEL) {
2486 gen_helper_exit_atomic(cpu_env);
2487 } else {
2488 gen_helper_cas2w(cpu_env, regs, addr1, addr2);
2489 }
2490 tcg_temp_free(regs);
2491
2492 /* Note that cas2w also assigned to env->cc_op. */
2493 s->cc_op = CC_OP_CMPW;
2494 s->cc_op_synced = 1;
2495 }
2496
2497 DISAS_INSN(cas2l)
2498 {
2499 uint16_t ext1, ext2;
2500 TCGv addr1, addr2, regs;
2501
2502 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2503
2504 ext1 = read_im16(env, s);
2505
2506 if (ext1 & 0x8000) {
2507 /* Address Register */
2508 addr1 = AREG(ext1, 12);
2509 } else {
2510 /* Data Register */
2511 addr1 = DREG(ext1, 12);
2512 }
2513
2514 ext2 = read_im16(env, s);
2515 if (ext2 & 0x8000) {
2516 /* Address Register */
2517 addr2 = AREG(ext2, 12);
2518 } else {
2519 /* Data Register */
2520 addr2 = DREG(ext2, 12);
2521 }
2522
2523 /* if (R1) == Dc1 && (R2) == Dc2 then
2524 * (R1) = Du1
2525 * (R2) = Du2
2526 * else
2527 * Dc1 = (R1)
2528 * Dc2 = (R2)
2529 */
2530
2531 regs = tcg_const_i32(REG(ext2, 6) |
2532 (REG(ext1, 6) << 3) |
2533 (REG(ext2, 0) << 6) |
2534 (REG(ext1, 0) << 9));
2535 if (tb_cflags(s->tb) & CF_PARALLEL) {
2536 gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
2537 } else {
2538 gen_helper_cas2l(cpu_env, regs, addr1, addr2);
2539 }
2540 tcg_temp_free(regs);
2541
2542 /* Note that cas2l also assigned to env->cc_op. */
2543 s->cc_op = CC_OP_CMPL;
2544 s->cc_op_synced = 1;
2545 }
2546
2547 DISAS_INSN(byterev)
2548 {
2549 TCGv reg;
2550
2551 reg = DREG(insn, 0);
2552 tcg_gen_bswap32_i32(reg, reg);
2553 }
2554
2555 DISAS_INSN(move)
2556 {
2557 TCGv src;
2558 TCGv dest;
2559 int op;
2560 int opsize;
2561
2562 switch (insn >> 12) {
2563 case 1: /* move.b */
2564 opsize = OS_BYTE;
2565 break;
2566 case 2: /* move.l */
2567 opsize = OS_LONG;
2568 break;
2569 case 3: /* move.w */
2570 opsize = OS_WORD;
2571 break;
2572 default:
2573 abort();
2574 }
2575 SRC_EA(env, src, opsize, 1, NULL);
2576 op = (insn >> 6) & 7;
2577 if (op == 1) {
2578 /* movea */
2579 /* The value will already have been sign extended. */
2580 dest = AREG(insn, 9);
2581 tcg_gen_mov_i32(dest, src);
2582 } else {
2583 /* normal move */
2584 uint16_t dest_ea;
2585 dest_ea = ((insn >> 9) & 7) | (op << 3);
2586 DEST_EA(env, dest_ea, opsize, src, NULL);
2587 /* This will be correct because loads sign extend. */
2588 gen_logic_cc(s, src, opsize);
2589 }
2590 }
2591
2592 DISAS_INSN(negx)
2593 {
2594 TCGv z;
2595 TCGv src;
2596 TCGv addr;
2597 int opsize;
2598
2599 opsize = insn_opsize(insn);
2600 SRC_EA(env, src, opsize, 1, &addr);
2601
2602 gen_flush_flags(s); /* compute old Z */
2603
2604 /* Perform substract with borrow.
2605 * (X, N) = -(src + X);
2606 */
2607
2608 z = tcg_const_i32(0);
2609 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
2610 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
2611 tcg_temp_free(z);
2612 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2613
2614 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2615
2616 /* Compute signed-overflow for negation. The normal formula for
2617 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2618 * this simplies to res & src.
2619 */
2620
2621 tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
2622
2623 /* Copy the rest of the results into place. */
2624 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2625 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2626
2627 set_cc_op(s, CC_OP_FLAGS);
2628
2629 /* result is in QREG_CC_N */
2630
2631 DEST_EA(env, insn, opsize, QREG_CC_N, &addr);
2632 }
2633
2634 DISAS_INSN(lea)
2635 {
2636 TCGv reg;
2637 TCGv tmp;
2638
2639 reg = AREG(insn, 9);
2640 tmp = gen_lea(env, s, insn, OS_LONG);
2641 if (IS_NULL_QREG(tmp)) {
2642 gen_addr_fault(s);
2643 return;
2644 }
2645 tcg_gen_mov_i32(reg, tmp);
2646 }
2647
2648 DISAS_INSN(clr)
2649 {
2650 int opsize;
2651 TCGv zero;
2652
2653 zero = tcg_const_i32(0);
2654
2655 opsize = insn_opsize(insn);
2656 DEST_EA(env, insn, opsize, zero, NULL);
2657 gen_logic_cc(s, zero, opsize);
2658 tcg_temp_free(zero);
2659 }
2660
2661 DISAS_INSN(move_from_ccr)
2662 {
2663 TCGv ccr;
2664
2665 ccr = gen_get_ccr(s);
2666 DEST_EA(env, insn, OS_WORD, ccr, NULL);
2667 }
2668
2669 DISAS_INSN(neg)
2670 {
2671 TCGv src1;
2672 TCGv dest;
2673 TCGv addr;
2674 int opsize;
2675
2676 opsize = insn_opsize(insn);
2677 SRC_EA(env, src1, opsize, 1, &addr);
2678 dest = tcg_temp_new();
2679 tcg_gen_neg_i32(dest, src1);
2680 set_cc_op(s, CC_OP_SUBB + opsize);
2681 gen_update_cc_add(dest, src1, opsize);
2682 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0);
2683 DEST_EA(env, insn, opsize, dest, &addr);
2684 tcg_temp_free(dest);
2685 }
2686
2687 DISAS_INSN(move_to_ccr)
2688 {
2689 gen_move_to_sr(env, s, insn, true);
2690 }
2691
2692 DISAS_INSN(not)
2693 {
2694 TCGv src1;
2695 TCGv dest;
2696 TCGv addr;
2697 int opsize;
2698
2699 opsize = insn_opsize(insn);
2700 SRC_EA(env, src1, opsize, 1, &addr);
2701 dest = tcg_temp_new();
2702 tcg_gen_not_i32(dest, src1);
2703 DEST_EA(env, insn, opsize, dest, &addr);
2704 gen_logic_cc(s, dest, opsize);
2705 }
2706
2707 DISAS_INSN(swap)
2708 {
2709 TCGv src1;
2710 TCGv src2;
2711 TCGv reg;
2712
2713 src1 = tcg_temp_new();
2714 src2 = tcg_temp_new();
2715 reg = DREG(insn, 0);
2716 tcg_gen_shli_i32(src1, reg, 16);
2717 tcg_gen_shri_i32(src2, reg, 16);
2718 tcg_gen_or_i32(reg, src1, src2);
2719 tcg_temp_free(src2);
2720 tcg_temp_free(src1);
2721 gen_logic_cc(s, reg, OS_LONG);
2722 }
2723
2724 DISAS_INSN(bkpt)
2725 {
2726 gen_exception(s, s->insn_pc, EXCP_DEBUG);
2727 }
2728
2729 DISAS_INSN(pea)
2730 {
2731 TCGv tmp;
2732
2733 tmp = gen_lea(env, s, insn, OS_LONG);
2734 if (IS_NULL_QREG(tmp)) {
2735 gen_addr_fault(s);
2736 return;
2737 }
2738 gen_push(s, tmp);
2739 }
2740
2741 DISAS_INSN(ext)
2742 {
2743 int op;
2744 TCGv reg;
2745 TCGv tmp;
2746
2747 reg = DREG(insn, 0);
2748 op = (insn >> 6) & 7;
2749 tmp = tcg_temp_new();
2750 if (op == 3)
2751 tcg_gen_ext16s_i32(tmp, reg);
2752 else
2753 tcg_gen_ext8s_i32(tmp, reg);
2754 if (op == 2)
2755 gen_partset_reg(OS_WORD, reg, tmp);
2756 else
2757 tcg_gen_mov_i32(reg, tmp);
2758 gen_logic_cc(s, tmp, OS_LONG);
2759 tcg_temp_free(tmp);
2760 }
2761
2762 DISAS_INSN(tst)
2763 {
2764 int opsize;
2765 TCGv tmp;
2766
2767 opsize = insn_opsize(insn);
2768 SRC_EA(env, tmp, opsize, 1, NULL);
2769 gen_logic_cc(s, tmp, opsize);
2770 }
2771
2772 DISAS_INSN(pulse)
2773 {
2774 /* Implemented as a NOP. */
2775 }
2776
2777 DISAS_INSN(illegal)
2778 {
2779 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
2780 }
2781
2782 /* ??? This should be atomic. */
2783 DISAS_INSN(tas)
2784 {
2785 TCGv dest;
2786 TCGv src1;
2787 TCGv addr;
2788
2789 dest = tcg_temp_new();
2790 SRC_EA(env, src1, OS_BYTE, 1, &addr);
2791 gen_logic_cc(s, src1, OS_BYTE);
2792 tcg_gen_ori_i32(dest, src1, 0x80);
2793 DEST_EA(env, insn, OS_BYTE, dest, &addr);
2794 tcg_temp_free(dest);
2795 }
2796
2797 DISAS_INSN(mull)
2798 {
2799 uint16_t ext;
2800 TCGv src1;
2801 int sign;
2802
2803 ext = read_im16(env, s);
2804
2805 sign = ext & 0x800;
2806
2807 if (ext & 0x400) {
2808 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
2809 gen_exception(s, s->insn_pc, EXCP_UNSUPPORTED);
2810 return;
2811 }
2812
2813 SRC_EA(env, src1, OS_LONG, 0, NULL);
2814
2815 if (sign) {
2816 tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2817 } else {
2818 tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2819 }
2820 /* if Dl == Dh, 68040 returns low word */
2821 tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N);
2822 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z);
2823 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N);
2824
2825 tcg_gen_movi_i32(QREG_CC_V, 0);
2826 tcg_gen_movi_i32(QREG_CC_C, 0);
2827
2828 set_cc_op(s, CC_OP_FLAGS);
2829 return;
2830 }
2831 SRC_EA(env, src1, OS_LONG, 0, NULL);
2832 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2833 tcg_gen_movi_i32(QREG_CC_C, 0);
2834 if (sign) {
2835 tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2836 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2837 tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
2838 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
2839 } else {
2840 tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2841 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2842 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
2843 }
2844 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
2845 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
2846
2847 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
2848
2849 set_cc_op(s, CC_OP_FLAGS);
2850 } else {
2851 /* The upper 32 bits of the product are discarded, so
2852 muls.l and mulu.l are functionally equivalent. */
2853 tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12));
2854 gen_logic_cc(s, DREG(ext, 12), OS_LONG);
2855 }
2856 }
2857
2858 static void gen_link(DisasContext *s, uint16_t insn, int32_t offset)
2859 {
2860 TCGv reg;
2861 TCGv tmp;
2862
2863 reg = AREG(insn, 0);
2864 tmp = tcg_temp_new();
2865 tcg_gen_subi_i32(tmp, QREG_SP, 4);
2866 gen_store(s, OS_LONG, tmp, reg, IS_USER(s));
2867 if ((insn & 7) != 7) {
2868 tcg_gen_mov_i32(reg, tmp);
2869 }
2870 tcg_gen_addi_i32(QREG_SP, tmp, offset);
2871 tcg_temp_free(tmp);
2872 }
2873
2874 DISAS_INSN(link)
2875 {
2876 int16_t offset;
2877
2878 offset = read_im16(env, s);
2879 gen_link(s, insn, offset);
2880 }
2881
2882 DISAS_INSN(linkl)
2883 {
2884 int32_t offset;
2885
2886 offset = read_im32(env, s);
2887 gen_link(s, insn, offset);
2888 }
2889
2890 DISAS_INSN(unlk)
2891 {
2892 TCGv src;
2893 TCGv reg;
2894 TCGv tmp;
2895
2896 src = tcg_temp_new();
2897 reg = AREG(insn, 0);
2898 tcg_gen_mov_i32(src, reg);
2899 tmp = gen_load(s, OS_LONG, src, 0, IS_USER(s));
2900 tcg_gen_mov_i32(reg, tmp);
2901 tcg_gen_addi_i32(QREG_SP, src, 4);
2902 tcg_temp_free(src);
2903 tcg_temp_free(tmp);
2904 }
2905
2906 #if defined(CONFIG_SOFTMMU)
2907 DISAS_INSN(reset)
2908 {
2909 if (IS_USER(s)) {
2910 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
2911 return;
2912 }
2913
2914 gen_helper_reset(cpu_env);
2915 }
2916 #endif
2917
2918 DISAS_INSN(nop)
2919 {
2920 }
2921
2922 DISAS_INSN(rtd)
2923 {
2924 TCGv tmp;
2925 int16_t offset = read_im16(env, s);
2926
2927 tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
2928 tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4);
2929 gen_jmp(s, tmp);
2930 }
2931
2932 DISAS_INSN(rts)
2933 {
2934 TCGv tmp;
2935
2936 tmp = gen_load(s, OS_LONG, QREG_SP, 0, IS_USER(s));
2937 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
2938 gen_jmp(s, tmp);
2939 }
2940
2941 DISAS_INSN(jump)
2942 {
2943 TCGv tmp;
2944
2945 /* Load the target address first to ensure correct exception
2946 behavior. */
2947 tmp = gen_lea(env, s, insn, OS_LONG);
2948 if (IS_NULL_QREG(tmp)) {
2949 gen_addr_fault(s);
2950 return;
2951 }
2952 if ((insn & 0x40) == 0) {
2953 /* jsr */
2954 gen_push(s, tcg_const_i32(s->pc));
2955 }
2956 gen_jmp(s, tmp);
2957 }
2958
2959 DISAS_INSN(addsubq)
2960 {
2961 TCGv src;
2962 TCGv dest;
2963 TCGv val;
2964 int imm;
2965 TCGv addr;
2966 int opsize;
2967
2968 if ((insn & 070) == 010) {
2969 /* Operation on address register is always long. */
2970 opsize = OS_LONG;
2971 } else {
2972 opsize = insn_opsize(insn);
2973 }
2974 SRC_EA(env, src, opsize, 1, &addr);
2975 imm = (insn >> 9) & 7;
2976 if (imm == 0) {
2977 imm = 8;
2978 }
2979 val = tcg_const_i32(imm);
2980 dest = tcg_temp_new();
2981 tcg_gen_mov_i32(dest, src);
2982 if ((insn & 0x38) == 0x08) {
2983 /* Don't update condition codes if the destination is an
2984 address register. */
2985 if (insn & 0x0100) {
2986 tcg_gen_sub_i32(dest, dest, val);
2987 } else {
2988 tcg_gen_add_i32(dest, dest, val);
2989 }
2990 } else {
2991 if (insn & 0x0100) {
2992 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
2993 tcg_gen_sub_i32(dest, dest, val);
2994 set_cc_op(s, CC_OP_SUBB + opsize);
2995 } else {
2996 tcg_gen_add_i32(dest, dest, val);
2997 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
2998 set_cc_op(s, CC_OP_ADDB + opsize);
2999 }
3000 gen_update_cc_add(dest, val, opsize);
3001 }
3002 tcg_temp_free(val);
3003 DEST_EA(env, insn, opsize, dest, &addr);
3004 tcg_temp_free(dest);
3005 }
3006
3007 DISAS_INSN(tpf)
3008 {
3009 switch (insn & 7) {
3010 case 2: /* One extension word. */
3011 s->pc += 2;
3012 break;
3013 case 3: /* Two extension words. */
3014 s->pc += 4;
3015 break;
3016 case 4: /* No extension words. */
3017 break;
3018 default:
3019 disas_undef(env, s, insn);
3020 }
3021 }
3022
3023 DISAS_INSN(branch)
3024 {
3025 int32_t offset;
3026 uint32_t base;
3027 int op;
3028 TCGLabel *l1;
3029
3030 base = s->pc;
3031 op = (insn >> 8) & 0xf;
3032 offset = (int8_t)insn;
3033 if (offset == 0) {
3034 offset = (int16_t)read_im16(env, s);
3035 } else if (offset == -1) {
3036 offset = read_im32(env, s);
3037 }
3038 if (op == 1) {
3039 /* bsr */
3040 gen_push(s, tcg_const_i32(s->pc));
3041 }
3042 if (op > 1) {
3043 /* Bcc */
3044 l1 = gen_new_label();
3045 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
3046 gen_jmp_tb(s, 1, base + offset);
3047 gen_set_label(l1);
3048 gen_jmp_tb(s, 0, s->pc);
3049 } else {
3050 /* Unconditional branch. */
3051 update_cc_op(s);
3052 gen_jmp_tb(s, 0, base + offset);
3053 }
3054 }
3055
3056 DISAS_INSN(moveq)
3057 {
3058 tcg_gen_movi_i32(DREG(insn, 9), (int8_t)insn);
3059 gen_logic_cc(s, DREG(insn, 9), OS_LONG);
3060 }
3061
3062 DISAS_INSN(mvzs)
3063 {
3064 int opsize;
3065 TCGv src;
3066 TCGv reg;
3067
3068 if (insn & 0x40)
3069 opsize = OS_WORD;
3070 else
3071 opsize = OS_BYTE;
3072 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
3073 reg = DREG(insn, 9);
3074 tcg_gen_mov_i32(reg, src);
3075 gen_logic_cc(s, src, opsize);
3076 }
3077
3078 DISAS_INSN(or)
3079 {
3080 TCGv reg;
3081 TCGv dest;
3082 TCGv src;
3083 TCGv addr;
3084 int opsize;
3085
3086 opsize = insn_opsize(insn);
3087 reg = gen_extend(s, DREG(insn, 9), opsize, 0);
3088 dest = tcg_temp_new();
3089 if (insn & 0x100) {
3090 SRC_EA(env, src, opsize, 0, &addr);
3091 tcg_gen_or_i32(dest, src, reg);
3092 DEST_EA(env, insn, opsize, dest, &addr);
3093 } else {
3094 SRC_EA(env, src, opsize, 0, NULL);
3095 tcg_gen_or_i32(dest, src, reg);
3096 gen_partset_reg(opsize, DREG(insn, 9), dest);
3097 }
3098 gen_logic_cc(s, dest, opsize);
3099 tcg_temp_free(dest);
3100 }
3101
3102 DISAS_INSN(suba)
3103 {
3104 TCGv src;
3105 TCGv reg;
3106
3107 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
3108 reg = AREG(insn, 9);
3109 tcg_gen_sub_i32(reg, reg, src);
3110 }
3111
3112 static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
3113 {
3114 TCGv tmp;
3115
3116 gen_flush_flags(s); /* compute old Z */
3117
3118 /* Perform substract with borrow.
3119 * (X, N) = dest - (src + X);
3120 */
3121
3122 tmp = tcg_const_i32(0);
3123 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
3124 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
3125 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3126 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
3127
3128 /* Compute signed-overflow for substract. */
3129
3130 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
3131 tcg_gen_xor_i32(tmp, dest, src);
3132 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
3133 tcg_temp_free(tmp);
3134
3135 /* Copy the rest of the results into place. */
3136 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3137 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3138
3139 set_cc_op(s, CC_OP_FLAGS);
3140
3141 /* result is in QREG_CC_N */
3142 }
3143
3144 DISAS_INSN(subx_reg)
3145 {
3146 TCGv dest;
3147 TCGv src;
3148 int opsize;
3149
3150 opsize = insn_opsize(insn);
3151
3152 src = gen_extend(s, DREG(insn, 0), opsize, 1);
3153 dest = gen_extend(s, DREG(insn, 9), opsize, 1);
3154
3155 gen_subx(s, src, dest, opsize);
3156
3157 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3158 }
3159
3160 DISAS_INSN(subx_mem)
3161 {
3162 TCGv src;
3163 TCGv addr_src;
3164 TCGv dest;
3165 TCGv addr_dest;
3166 int opsize;
3167
3168 opsize = insn_opsize(insn);
3169
3170 addr_src = AREG(insn, 0);
3171 tcg_gen_subi_i32(addr_src, addr_src, opsize);
3172 src = gen_load(s, opsize, addr_src, 1, IS_USER(s));
3173
3174 addr_dest = AREG(insn, 9);
3175 tcg_gen_subi_i32(addr_dest, addr_dest, opsize);
3176 dest = gen_load(s, opsize, addr_dest, 1, IS_USER(s));
3177
3178 gen_subx(s, src, dest, opsize);
3179
3180 gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s));
3181
3182 tcg_temp_free(dest);
3183 tcg_temp_free(src);
3184 }
3185
3186 DISAS_INSN(mov3q)
3187 {
3188 TCGv src;
3189 int val;
3190
3191 val = (insn >> 9) & 7;
3192 if (val == 0)
3193 val = -1;
3194 src = tcg_const_i32(val);
3195 gen_logic_cc(s, src, OS_LONG);
3196 DEST_EA(env, insn, OS_LONG, src, NULL);
3197 tcg_temp_free(src);
3198 }
3199
3200 DISAS_INSN(cmp)
3201 {
3202 TCGv src;
3203 TCGv reg;
3204 int opsize;
3205
3206 opsize = insn_opsize(insn);
3207 SRC_EA(env, src, opsize, 1, NULL);
3208 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
3209 gen_update_cc_cmp(s, reg, src, opsize);
3210 }
3211
3212 DISAS_INSN(cmpa)
3213 {
3214 int opsize;
3215 TCGv src;
3216 TCGv reg;
3217
3218 if (insn & 0x100) {
3219 opsize = OS_LONG;
3220 } else {
3221 opsize = OS_WORD;
3222 }
3223 SRC_EA(env, src, opsize, 1, NULL);
3224 reg = AREG(insn, 9);
3225 gen_update_cc_cmp(s, reg, src, OS_LONG);
3226 }
3227
3228 DISAS_INSN(cmpm)
3229 {
3230 int opsize = insn_opsize(insn);
3231 TCGv src, dst;
3232
3233 /* Post-increment load (mode 3) from Ay. */
3234 src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize,
3235 NULL_QREG, NULL, EA_LOADS, IS_USER(s));
3236 /* Post-increment load (mode 3) from Ax. */
3237 dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize,
3238 NULL_QREG, NULL, EA_LOADS, IS_USER(s));
3239
3240 gen_update_cc_cmp(s, dst, src, opsize);
3241 }
3242
3243 DISAS_INSN(eor)
3244 {
3245 TCGv src;
3246 TCGv dest;
3247 TCGv addr;
3248 int opsize;
3249
3250 opsize = insn_opsize(insn);
3251
3252 SRC_EA(env, src, opsize, 0, &addr);
3253 dest = tcg_temp_new();
3254 tcg_gen_xor_i32(dest, src, DREG(insn, 9));
3255 gen_logic_cc(s, dest, opsize);
3256 DEST_EA(env, insn, opsize, dest, &addr);
3257 tcg_temp_free(dest);
3258 }
3259
3260 static void do_exg(TCGv reg1, TCGv reg2)
3261 {
3262 TCGv temp = tcg_temp_new();
3263 tcg_gen_mov_i32(temp, reg1);
3264 tcg_gen_mov_i32(reg1, reg2);
3265 tcg_gen_mov_i32(reg2, temp);
3266 tcg_temp_free(temp);
3267 }
3268
3269 DISAS_INSN(exg_dd)
3270 {
3271 /* exchange Dx and Dy */
3272 do_exg(DREG(insn, 9), DREG(insn, 0));
3273 }
3274
3275 DISAS_INSN(exg_aa)
3276 {
3277 /* exchange Ax and Ay */
3278 do_exg(AREG(insn, 9), AREG(insn, 0));
3279 }
3280
3281 DISAS_INSN(exg_da)
3282 {
3283 /* exchange Dx and Ay */
3284 do_exg(DREG(insn, 9), AREG(insn, 0));
3285 }
3286
3287 DISAS_INSN(and)
3288 {
3289 TCGv src;
3290 TCGv reg;
3291 TCGv dest;
3292 TCGv addr;
3293 int opsize;
3294
3295 dest = tcg_temp_new();
3296
3297 opsize = insn_opsize(insn);
3298 reg = DREG(insn, 9);
3299 if (insn & 0x100) {
3300 SRC_EA(env, src, opsize, 0, &addr);
3301 tcg_gen_and_i32(dest, src, reg);
3302 DEST_EA(env, insn, opsize, dest, &addr);
3303 } else {
3304 SRC_EA(env, src, opsize, 0, NULL);
3305 tcg_gen_and_i32(dest, src, reg);
3306 gen_partset_reg(opsize, reg, dest);
3307 }
3308 gen_logic_cc(s, dest, opsize);
3309 tcg_temp_free(dest);
3310 }
3311
3312 DISAS_INSN(adda)
3313 {
3314 TCGv src;
3315 TCGv reg;
3316
3317 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
3318 reg = AREG(insn, 9);
3319 tcg_gen_add_i32(reg, reg, src);
3320 }
3321
3322 static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
3323 {
3324 TCGv tmp;
3325
3326 gen_flush_flags(s); /* compute old Z */
3327
3328 /* Perform addition with carry.
3329 * (X, N) = src + dest + X;
3330 */
3331
3332 tmp = tcg_const_i32(0);
3333 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
3334 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
3335 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3336
3337 /* Compute signed-overflow for addition. */
3338
3339 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3340 tcg_gen_xor_i32(tmp, dest, src);
3341 tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
3342 tcg_temp_free(tmp);
3343
3344 /* Copy the rest of the results into place. */
3345 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3346 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3347
3348 set_cc_op(s, CC_OP_FLAGS);
3349
3350 /* result is in QREG_CC_N */
3351 }
3352
3353 DISAS_INSN(addx_reg)
3354 {
3355 TCGv dest;
3356 TCGv src;
3357 int opsize;
3358
3359 opsize = insn_opsize(insn);
3360
3361 dest = gen_extend(s, DREG(insn, 9), opsize, 1);
3362 src = gen_extend(s, DREG(insn, 0), opsize, 1);
3363
3364 gen_addx(s, src, dest, opsize);
3365
3366 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3367 }
3368
3369 DISAS_INSN(addx_mem)
3370 {
3371 TCGv src;
3372 TCGv addr_src;
3373 TCGv dest;
3374 TCGv addr_dest;
3375 int opsize;
3376
3377 opsize = insn_opsize(insn);
3378
3379 addr_src = AREG(insn, 0);
3380 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3381 src = gen_load(s, opsize, addr_src, 1, IS_USER(s));
3382
3383 addr_dest = AREG(insn, 9);
3384 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3385 dest = gen_load(s, opsize, addr_dest, 1, IS_USER(s));
3386
3387 gen_addx(s, src, dest, opsize);
3388
3389 gen_store(s, opsize, addr_dest, QREG_CC_N, IS_USER(s));
3390
3391 tcg_temp_free(dest);
3392 tcg_temp_free(src);
3393 }
3394
3395 static inline void shift_im(DisasContext *s, uint16_t insn, int opsize)
3396 {
3397 int count = (insn >> 9) & 7;
3398 int logical = insn & 8;
3399 int left = insn & 0x100;
3400 int bits = opsize_bytes(opsize) * 8;
3401 TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
3402
3403 if (count == 0) {
3404 count = 8;
3405 }
3406
3407 tcg_gen_movi_i32(QREG_CC_V, 0);
3408 if (left) {
3409 tcg_gen_shri_i32(QREG_CC_C, reg, bits - count);
3410 tcg_gen_shli_i32(QREG_CC_N, reg, count);
3411
3412 /* Note that ColdFire always clears V (done above),
3413 while M68000 sets if the most significant bit is changed at
3414 any time during the shift operation */
3415 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3416 /* if shift count >= bits, V is (reg != 0) */
3417 if (count >= bits) {
3418 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
3419 } else {
3420 TCGv t0 = tcg_temp_new();
3421 tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1);
3422 tcg_gen_sari_i32(t0, reg, bits - count - 1);
3423 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0);
3424 tcg_temp_free(t0);
3425 }
3426 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3427 }
3428 } else {
3429 tcg_gen_shri_i32(QREG_CC_C, reg, count - 1);
3430 if (logical) {
3431 tcg_gen_shri_i32(QREG_CC_N, reg, count);
3432 } else {
3433 tcg_gen_sari_i32(QREG_CC_N, reg, count);
3434 }
3435 }
3436
3437 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3438 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3439 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3440 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3441
3442 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3443 set_cc_op(s, CC_OP_FLAGS);
3444 }
3445
3446 static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
3447 {
3448 int logical = insn & 8;
3449 int left = insn & 0x100;
3450 int bits = opsize_bytes(opsize) * 8;
3451 TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
3452 TCGv s32;
3453 TCGv_i64 t64, s64;
3454
3455 t64 = tcg_temp_new_i64();
3456 s64 = tcg_temp_new_i64();
3457 s32 = tcg_temp_new();
3458
3459 /* Note that m68k truncates the shift count modulo 64, not 32.
3460 In addition, a 64-bit shift makes it easy to find "the last
3461 bit shifted out", for the carry flag. */
3462 tcg_gen_andi_i32(s32, DREG(insn, 9), 63);
3463 tcg_gen_extu_i32_i64(s64, s32);
3464 tcg_gen_extu_i32_i64(t64, reg);
3465
3466 /* Optimistically set V=0. Also used as a zero source below. */
3467 tcg_gen_movi_i32(QREG_CC_V, 0);
3468 if (left) {
3469 tcg_gen_shl_i64(t64, t64, s64);
3470
3471 if (opsize == OS_LONG) {
3472 tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
3473 /* Note that C=0 if shift count is 0, and we get that for free. */
3474 } else {
3475 TCGv zero = tcg_const_i32(0);
3476 tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
3477 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
3478 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3479 s32, zero, zero, QREG_CC_C);
3480 tcg_temp_free(zero);
3481 }
3482 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3483
3484 /* X = C, but only if the shift count was non-zero. */
3485 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3486 QREG_CC_C, QREG_CC_X);
3487
3488 /* M68000 sets V if the most significant bit is changed at
3489 * any time during the shift operation. Do this via creating
3490 * an extension of the sign bit, comparing, and discarding
3491 * the bits below the sign bit. I.e.
3492 * int64_t s = (intN_t)reg;
3493 * int64_t t = (int64_t)(intN_t)reg << count;
3494 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3495 */
3496 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3497 TCGv_i64 tt = tcg_const_i64(32);
3498 /* if shift is greater than 32, use 32 */
3499 tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64);
3500 tcg_temp_free_i64(tt);
3501 /* Sign extend the input to 64 bits; re-do the shift. */
3502 tcg_gen_ext_i32_i64(t64, reg);
3503 tcg_gen_shl_i64(s64, t64, s64);
3504 /* Clear all bits that are unchanged. */
3505 tcg_gen_xor_i64(t64, t64, s64);
3506 /* Ignore the bits below the sign bit. */
3507 tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1));
3508 /* If any bits remain set, we have overflow. */
3509 tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0);
3510 tcg_gen_extrl_i64_i32(QREG_CC_V, t64);
3511 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3512 }
3513 } else {
3514 tcg_gen_shli_i64(t64, t64, 32);
3515 if (logical) {
3516 tcg_gen_shr_i64(t64, t64, s64);
3517 } else {
3518 tcg_gen_sar_i64(t64, t64, s64);
3519 }
3520 tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64);
3521
3522 /* Note that C=0 if shift count is 0, and we get that for free. */
3523 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31);
3524
3525 /* X = C, but only if the shift count was non-zero. */
3526 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3527 QREG_CC_C, QREG_CC_X);
3528 }
3529 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3530 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3531
3532 tcg_temp_free(s32);
3533 tcg_temp_free_i64(s64);
3534 tcg_temp_free_i64(t64);
3535
3536 /* Write back the result. */
3537 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3538 set_cc_op(s, CC_OP_FLAGS);
3539 }
3540
3541 DISAS_INSN(shift8_im)
3542 {
3543 shift_im(s, insn, OS_BYTE);
3544 }
3545
3546 DISAS_INSN(shift16_im)
3547 {
3548 shift_im(s, insn, OS_WORD);
3549 }
3550
3551 DISAS_INSN(shift_im)
3552 {
3553 shift_im(s, insn, OS_LONG);
3554 }
3555
3556 DISAS_INSN(shift8_reg)
3557 {
3558 shift_reg(s, insn, OS_BYTE);
3559 }
3560
3561 DISAS_INSN(shift16_reg)
3562 {
3563 shift_reg(s, insn, OS_WORD);
3564 }
3565
3566 DISAS_INSN(shift_reg)
3567 {
3568 shift_reg(s, insn, OS_LONG);
3569 }
3570
3571 DISAS_INSN(shift_mem)
3572 {
3573 int logical = insn & 8;
3574 int left = insn & 0x100;
3575 TCGv src;
3576 TCGv addr;
3577
3578 SRC_EA(env, src, OS_WORD, !logical, &addr);
3579 tcg_gen_movi_i32(QREG_CC_V, 0);
3580 if (left) {
3581 tcg_gen_shri_i32(QREG_CC_C, src, 15);
3582 tcg_gen_shli_i32(QREG_CC_N, src, 1);
3583
3584 /* Note that ColdFire always clears V,
3585 while M68000 sets if the most significant bit is changed at
3586 any time during the shift operation */
3587 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3588 src = gen_extend(s, src, OS_WORD, 1);
3589 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3590 }
3591 } else {
3592 tcg_gen_mov_i32(QREG_CC_C, src);
3593 if (logical) {
3594 tcg_gen_shri_i32(QREG_CC_N, src, 1);
3595 } else {
3596 tcg_gen_sari_i32(QREG_CC_N, src, 1);
3597 }
3598 }
3599
3600 gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1);
3601 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3602 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3603 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3604
3605 DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr);
3606 set_cc_op(s, CC_OP_FLAGS);
3607 }
3608
3609 static void rotate(TCGv reg, TCGv shift, int left, int size)
3610 {
3611 switch (size) {
3612 case 8:
3613 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3614 tcg_gen_ext8u_i32(reg, reg);
3615 tcg_gen_muli_i32(reg, reg, 0x01010101);
3616 goto do_long;
3617 case 16:
3618 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3619 tcg_gen_deposit_i32(reg, reg, reg, 16, 16);
3620 goto do_long;
3621 do_long:
3622 default:
3623 if (left) {
3624 tcg_gen_rotl_i32(reg, reg, shift);
3625 } else {
3626 tcg_gen_rotr_i32(reg, reg, shift);
3627 }
3628 }
3629
3630 /* compute flags */
3631
3632 switch (size) {
3633 case 8:
3634 tcg_gen_ext8s_i32(reg, reg);
3635 break;
3636 case 16:
3637 tcg_gen_ext16s_i32(reg, reg);
3638 break;
3639 default:
3640 break;
3641 }
3642
3643 /* QREG_CC_X is not affected */
3644
3645 tcg_gen_mov_i32(QREG_CC_N, reg);
3646 tcg_gen_mov_i32(QREG_CC_Z, reg);
3647
3648 if (left) {
3649 tcg_gen_andi_i32(QREG_CC_C, reg, 1);
3650 } else {
3651 tcg_gen_shri_i32(QREG_CC_C, reg, 31);
3652 }
3653
3654 tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */
3655 }
3656
3657 static void rotate_x_flags(TCGv reg, TCGv X, int size)
3658 {
3659 switch (size) {
3660 case 8:
3661 tcg_gen_ext8s_i32(reg, reg);
3662 break;
3663 case 16:
3664 tcg_gen_ext16s_i32(reg, reg);
3665 break;
3666 default:
3667 break;
3668 }
3669 tcg_gen_mov_i32(QREG_CC_N, reg);
3670 tcg_gen_mov_i32(QREG_CC_Z, reg);
3671 tcg_gen_mov_i32(QREG_CC_X, X);
3672 tcg_gen_mov_i32(QREG_CC_C, X);
3673 tcg_gen_movi_i32(QREG_CC_V, 0);
3674 }
3675
3676 /* Result of rotate_x() is valid if 0 <= shift <= size */
3677 static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
3678 {
3679 TCGv X, shl, shr, shx, sz, zero;
3680
3681 sz = tcg_const_i32(size);
3682
3683 shr = tcg_temp_new();
3684 shl = tcg_temp_new();
3685 shx = tcg_temp_new();
3686 if (left) {
3687 tcg_gen_mov_i32(shl, shift); /* shl = shift */
3688 tcg_gen_movi_i32(shr, size + 1);
3689 tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */
3690 tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */
3691 /* shx = shx < 0 ? size : shx; */
3692 zero = tcg_const_i32(0);
3693 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx);
3694 tcg_temp_free(zero);
3695 } else {
3696 tcg_gen_mov_i32(shr, shift); /* shr = shift */
3697 tcg_gen_movi_i32(shl, size + 1);
3698 tcg_gen_sub_i32(shl, shl, shift); /* shl = size + 1 - shift */
3699 tcg_gen_sub_i32(shx, sz, shift); /* shx = size - shift */
3700 }
3701
3702 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3703
3704 tcg_gen_shl_i32(shl, reg, shl);
3705 tcg_gen_shr_i32(shr, reg, shr);
3706 tcg_gen_or_i32(reg, shl, shr);
3707 tcg_temp_free(shl);
3708 tcg_temp_free(shr);
3709 tcg_gen_shl_i32(shx, QREG_CC_X, shx);
3710 tcg_gen_or_i32(reg, reg, shx);
3711 tcg_temp_free(shx);
3712
3713 /* X = (reg >> size) & 1 */
3714
3715 X = tcg_temp_new();
3716 tcg_gen_shr_i32(X, reg, sz);
3717 tcg_gen_andi_i32(X, X, 1);
3718 tcg_temp_free(sz);
3719
3720 return X;
3721 }
3722
3723 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3724 static TCGv rotate32_x(TCGv reg, TCGv shift, int left)
3725 {
3726 TCGv_i64 t0, shift64;
3727 TCGv X, lo, hi, zero;
3728
3729 shift64 = tcg_temp_new_i64();
3730 tcg_gen_extu_i32_i64(shift64, shift);
3731
3732 t0 = tcg_temp_new_i64();
3733
3734 X = tcg_temp_new();
3735 lo = tcg_temp_new();
3736 hi = tcg_temp_new();
3737
3738 if (left) {
3739 /* create [reg:X:..] */
3740
3741 tcg_gen_shli_i32(lo, QREG_CC_X, 31);
3742 tcg_gen_concat_i32_i64(t0, lo, reg);
3743
3744 /* rotate */
3745
3746 tcg_gen_rotl_i64(t0, t0, shift64);
3747 tcg_temp_free_i64(shift64);
3748
3749 /* result is [reg:..:reg:X] */
3750
3751 tcg_gen_extr_i64_i32(lo, hi, t0);
3752 tcg_gen_andi_i32(X, lo, 1);
3753
3754 tcg_gen_shri_i32(lo, lo, 1);
3755 } else {
3756 /* create [..:X:reg] */
3757
3758 tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X);
3759
3760 tcg_gen_rotr_i64(t0, t0, shift64);
3761 tcg_temp_free_i64(shift64);
3762
3763 /* result is value: [X:reg:..:reg] */
3764
3765 tcg_gen_extr_i64_i32(lo, hi, t0);
3766
3767 /* extract X */
3768
3769 tcg_gen_shri_i32(X, hi, 31);
3770
3771 /* extract result */
3772
3773 tcg_gen_shli_i32(hi, hi, 1);
3774 }
3775 tcg_temp_free_i64(t0);
3776 tcg_gen_or_i32(lo, lo, hi);
3777 tcg_temp_free(hi);
3778
3779 /* if shift == 0, register and X are not affected */
3780
3781 zero = tcg_const_i32(0);
3782 tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X);
3783 tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo);
3784 tcg_temp_free(zero);
3785 tcg_temp_free(lo);
3786
3787 return X;
3788 }
3789
3790 DISAS_INSN(rotate_im)
3791 {
3792 TCGv shift;
3793 int tmp;
3794 int left = (insn & 0x100);
3795
3796 tmp = (insn >> 9) & 7;
3797 if (tmp == 0) {
3798 tmp = 8;
3799 }
3800
3801 shift = tcg_const_i32(tmp);
3802 if (insn & 8) {
3803 rotate(DREG(insn, 0), shift, left, 32);
3804 } else {
3805 TCGv X = rotate32_x(DREG(insn, 0), shift, left);
3806 rotate_x_flags(DREG(insn, 0), X, 32);
3807 tcg_temp_free(X);
3808 }
3809 tcg_temp_free(shift);
3810
3811 set_cc_op(s, CC_OP_FLAGS);
3812 }
3813
3814 DISAS_INSN(rotate8_im)
3815 {
3816 int left = (insn & 0x100);
3817 TCGv reg;
3818 TCGv shift;
3819 int tmp;
3820
3821 reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
3822
3823 tmp = (insn >> 9) & 7;
3824 if (tmp == 0) {
3825 tmp = 8;
3826 }
3827
3828 shift = tcg_const_i32(tmp);
3829 if (insn & 8) {
3830 rotate(reg, shift, left, 8);
3831 } else {
3832 TCGv X = rotate_x(reg, shift, left, 8);
3833 rotate_x_flags(reg, X, 8);
3834 tcg_temp_free(X);
3835 }
3836 tcg_temp_free(shift);
3837 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3838 set_cc_op(s, CC_OP_FLAGS);
3839 }
3840
3841 DISAS_INSN(rotate16_im)
3842 {
3843 int left = (insn & 0x100);
3844 TCGv reg;
3845 TCGv shift;
3846 int tmp;
3847
3848 reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
3849 tmp = (insn >> 9) & 7;
3850 if (tmp == 0) {
3851 tmp = 8;
3852 }
3853
3854 shift = tcg_const_i32(tmp);
3855 if (insn & 8) {
3856 rotate(reg, shift, left, 16);
3857 } else {
3858 TCGv X = rotate_x(reg, shift, left, 16);
3859 rotate_x_flags(reg, X, 16);
3860 tcg_temp_free(X);
3861 }
3862 tcg_temp_free(shift);
3863 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3864 set_cc_op(s, CC_OP_FLAGS);
3865 }
3866
3867 DISAS_INSN(rotate_reg)
3868 {
3869 TCGv reg;
3870 TCGv src;
3871 TCGv t0, t1;
3872 int left = (insn & 0x100);
3873
3874 reg = DREG(insn, 0);
3875 src = DREG(insn, 9);
3876 /* shift in [0..63] */
3877 t0 = tcg_temp_new();
3878 tcg_gen_andi_i32(t0, src, 63);
3879 t1 = tcg_temp_new_i32();
3880 if (insn & 8) {
3881 tcg_gen_andi_i32(t1, src, 31);
3882 rotate(reg, t1, left, 32);
3883 /* if shift == 0, clear C */
3884 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3885 t0, QREG_CC_V /* 0 */,
3886 QREG_CC_V /* 0 */, QREG_CC_C);
3887 } else {
3888 TCGv X;
3889 /* modulo 33 */
3890 tcg_gen_movi_i32(t1, 33);
3891 tcg_gen_remu_i32(t1, t0, t1);
3892 X = rotate32_x(DREG(insn, 0), t1, left);
3893 rotate_x_flags(DREG(insn, 0), X, 32);
3894 tcg_temp_free(X);
3895 }
3896 tcg_temp_free(t1);
3897 tcg_temp_free(t0);
3898 set_cc_op(s, CC_OP_FLAGS);
3899 }
3900
3901 DISAS_INSN(rotate8_reg)
3902 {
3903 TCGv reg;
3904 TCGv src;
3905 TCGv t0, t1;
3906 int left = (insn & 0x100);
3907
3908 reg = gen_extend(s, DREG(insn, 0), OS_BYTE, 0);
3909 src = DREG(insn, 9);
3910 /* shift in [0..63] */
3911 t0 = tcg_temp_new_i32();
3912 tcg_gen_andi_i32(t0, src, 63);
3913 t1 = tcg_temp_new_i32();
3914 if (insn & 8) {
3915 tcg_gen_andi_i32(t1, src, 7);
3916 rotate(reg, t1, left, 8);
3917 /* if shift == 0, clear C */
3918 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3919 t0, QREG_CC_V /* 0 */,
3920 QREG_CC_V /* 0 */, QREG_CC_C);
3921 } else {
3922 TCGv X;
3923 /* modulo 9 */
3924 tcg_gen_movi_i32(t1, 9);
3925 tcg_gen_remu_i32(t1, t0, t1);
3926 X = rotate_x(reg, t1, left, 8);
3927 rotate_x_flags(reg, X, 8);
3928 tcg_temp_free(X);
3929 }
3930 tcg_temp_free(t1);
3931 tcg_temp_free(t0);
3932 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3933 set_cc_op(s, CC_OP_FLAGS);
3934 }
3935
3936 DISAS_INSN(rotate16_reg)
3937 {
3938 TCGv reg;
3939 TCGv src;
3940 TCGv t0, t1;
3941 int left = (insn & 0x100);
3942
3943 reg = gen_extend(s, DREG(insn, 0), OS_WORD, 0);
3944 src = DREG(insn, 9);
3945 /* shift in [0..63] */
3946 t0 = tcg_temp_new_i32();
3947 tcg_gen_andi_i32(t0, src, 63);
3948 t1 = tcg_temp_new_i32();
3949 if (insn & 8) {
3950 tcg_gen_andi_i32(t1, src, 15);
3951 rotate(reg, t1, left, 16);
3952 /* if shift == 0, clear C */
3953 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3954 t0, QREG_CC_V /* 0 */,
3955 QREG_CC_V /* 0 */, QREG_CC_C);
3956 } else {
3957 TCGv X;
3958 /* modulo 17 */
3959 tcg_gen_movi_i32(t1, 17);
3960 tcg_gen_remu_i32(t1, t0, t1);
3961 X = rotate_x(reg, t1, left, 16);
3962 rotate_x_flags(reg, X, 16);
3963 tcg_temp_free(X);
3964 }
3965 tcg_temp_free(t1);
3966 tcg_temp_free(t0);
3967 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3968 set_cc_op(s, CC_OP_FLAGS);
3969 }
3970
3971 DISAS_INSN(rotate_mem)
3972 {
3973 TCGv src;
3974 TCGv addr;
3975 TCGv shift;
3976 int left = (insn & 0x100);
3977
3978 SRC_EA(env, src, OS_WORD, 0, &addr);
3979
3980 shift = tcg_const_i32(1);
3981 if (insn & 0x0200) {
3982 rotate(src, shift, left, 16);
3983 } else {
3984 TCGv X = rotate_x(src, shift, left, 16);
3985 rotate_x_flags(src, X, 16);
3986 tcg_temp_free(X);
3987 }
3988 tcg_temp_free(shift);
3989 DEST_EA(env, insn, OS_WORD, src, &addr);
3990 set_cc_op(s, CC_OP_FLAGS);
3991 }
3992
3993 DISAS_INSN(bfext_reg)
3994 {
3995 int ext = read_im16(env, s);
3996 int is_sign = insn & 0x200;
3997 TCGv src = DREG(insn, 0);
3998 TCGv dst = DREG(ext, 12);
3999 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4000 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4001 int pos = 32 - ofs - len; /* little bit-endian */
4002 TCGv tmp = tcg_temp_new();
4003 TCGv shift;
4004
4005 /* In general, we're going to rotate the field so that it's at the
4006 top of the word and then right-shift by the compliment of the
4007 width to extend the field. */
4008 if (ext & 0x20) {
4009 /* Variable width. */
4010 if (ext & 0x800) {
4011 /* Variable offset. */
4012 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4013 tcg_gen_rotl_i32(tmp, src, tmp);
4014 } else {
4015 tcg_gen_rotli_i32(tmp, src, ofs);
4016 }
4017
4018 shift = tcg_temp_new();
4019 tcg_gen_neg_i32(shift, DREG(ext, 0));
4020 tcg_gen_andi_i32(shift, shift, 31);
4021 tcg_gen_sar_i32(QREG_CC_N, tmp, shift);
4022 if (is_sign) {
4023 tcg_gen_mov_i32(dst, QREG_CC_N);
4024 } else {
4025 tcg_gen_shr_i32(dst, tmp, shift);
4026 }
4027 tcg_temp_free(shift);
4028 } else {
4029 /* Immediate width. */
4030 if (ext & 0x800) {
4031 /* Variable offset */
4032 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4033 tcg_gen_rotl_i32(tmp, src, tmp);
4034 src = tmp;
4035 pos = 32 - len;
4036 } else {
4037 /* Immediate offset. If the field doesn't wrap around the
4038 end of the word, rely on (s)extract completely. */
4039 if (pos < 0) {
4040 tcg_gen_rotli_i32(tmp, src, ofs);
4041 src = tmp;
4042 pos = 32 - len;
4043 }
4044 }
4045
4046 tcg_gen_sextract_i32(QREG_CC_N, src, pos, len);
4047 if (is_sign) {
4048 tcg_gen_mov_i32(dst, QREG_CC_N);
4049 } else {
4050 tcg_gen_extract_i32(dst, src, pos, len);
4051 }
4052 }
4053
4054 tcg_temp_free(tmp);
4055 set_cc_op(s, CC_OP_LOGIC);
4056 }
4057
4058 DISAS_INSN(bfext_mem)
4059 {
4060 int ext = read_im16(env, s);
4061 int is_sign = insn & 0x200;
4062 TCGv dest = DREG(ext, 12);
4063 TCGv addr, len, ofs;
4064
4065 addr = gen_lea(env, s, insn, OS_UNSIZED);
4066 if (IS_NULL_QREG(addr)) {
4067 gen_addr_fault(s);
4068 return;
4069 }
4070
4071 if (ext & 0x20) {
4072 len = DREG(ext, 0);
4073 } else {
4074 len = tcg_const_i32(extract32(ext, 0, 5));
4075 }
4076 if (ext & 0x800) {
4077 ofs = DREG(ext, 6);
4078 } else {
4079 ofs = tcg_const_i32(extract32(ext, 6, 5));
4080 }
4081
4082 if (is_sign) {
4083 gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
4084 tcg_gen_mov_i32(QREG_CC_N, dest);
4085 } else {
4086 TCGv_i64 tmp = tcg_temp_new_i64();
4087 gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
4088 tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
4089 tcg_temp_free_i64(tmp);
4090 }
4091 set_cc_op(s, CC_OP_LOGIC);
4092
4093 if (!(ext & 0x20)) {
4094 tcg_temp_free(len);
4095 }
4096 if (!(ext & 0x800)) {
4097 tcg_temp_free(ofs);
4098 }
4099 }
4100
4101 DISAS_INSN(bfop_reg)
4102 {
4103 int ext = read_im16(env, s);
4104 TCGv src = DREG(insn, 0);
4105 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4106 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4107 TCGv mask, tofs, tlen;
4108
4109 tofs = NULL;
4110 tlen = NULL;
4111 if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
4112 tofs = tcg_temp_new();
4113 tlen = tcg_temp_new();
4114 }
4115
4116 if ((ext & 0x820) == 0) {
4117 /* Immediate width and offset. */
4118 uint32_t maski = 0x7fffffffu >> (len - 1);
4119 if (ofs + len <= 32) {
4120 tcg_gen_shli_i32(QREG_CC_N, src, ofs);
4121 } else {
4122 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4123 }
4124 tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
4125 mask = tcg_const_i32(ror32(maski, ofs));
4126 if (tofs) {
4127 tcg_gen_movi_i32(tofs, ofs);
4128 tcg_gen_movi_i32(tlen, len);
4129 }
4130 } else {
4131 TCGv tmp = tcg_temp_new();
4132 if (ext & 0x20) {
4133 /* Variable width */
4134 tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
4135 tcg_gen_andi_i32(tmp, tmp, 31);
4136 mask = tcg_const_i32(0x7fffffffu);
4137 tcg_gen_shr_i32(mask, mask, tmp);
4138 if (tlen) {
4139 tcg_gen_addi_i32(tlen, tmp, 1);
4140 }
4141 } else {
4142 /* Immediate width */
4143 mask = tcg_const_i32(0x7fffffffu >> (len - 1));
4144 if (tlen) {
4145 tcg_gen_movi_i32(tlen, len);
4146 }
4147 }
4148 if (ext & 0x800) {
4149 /* Variable offset */
4150 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
4151 tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
4152 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4153 tcg_gen_rotr_i32(mask, mask, tmp);
4154 if (tofs) {
4155 tcg_gen_mov_i32(tofs, tmp);
4156 }
4157 } else {
4158 /* Immediate offset (and variable width) */
4159 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4160 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4161 tcg_gen_rotri_i32(mask, mask, ofs);
4162 if (tofs) {
4163 tcg_gen_movi_i32(tofs, ofs);
4164 }
4165 }
4166 tcg_temp_free(tmp);
4167 }
4168 set_cc_op(s, CC_OP_LOGIC);
4169
4170 switch (insn & 0x0f00) {
4171 case 0x0a00: /* bfchg */
4172 tcg_gen_eqv_i32(src, src, mask);
4173 break;
4174 case 0x0c00: /* bfclr */
4175 tcg_gen_and_i32(src, src, mask);
4176 break;
4177 case 0x0d00: /* bfffo */
4178 gen_helper_bfffo_reg(DREG(ext, 12), QREG_CC_N, tofs, tlen);
4179 tcg_temp_free(tlen);
4180 tcg_temp_free(tofs);
4181 break;
4182 case 0x0e00: /* bfset */
4183 tcg_gen_orc_i32(src, src, mask);
4184 break;
4185 case 0x0800: /* bftst */
4186 /* flags already set; no other work to do. */
4187 break;
4188 default:
4189 g_assert_not_reached();
4190 }
4191 tcg_temp_free(mask);
4192 }
4193
4194 DISAS_INSN(bfop_mem)
4195 {
4196 int ext = read_im16(env, s);
4197 TCGv addr, len, ofs;
4198 TCGv_i64 t64;
4199
4200 addr = gen_lea(env, s, insn, OS_UNSIZED);
4201 if (IS_NULL_QREG(addr)) {
4202 gen_addr_fault(s);
4203 return;
4204 }
4205
4206 if (ext & 0x20) {
4207 len = DREG(ext, 0);
4208 } else {
4209 len = tcg_const_i32(extract32(ext, 0, 5));
4210 }
4211 if (ext & 0x800) {
4212 ofs = DREG(ext, 6);
4213 } else {
4214 ofs = tcg_const_i32(extract32(ext, 6, 5));
4215 }
4216
4217 switch (insn & 0x0f00) {
4218 case 0x0a00: /* bfchg */
4219 gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4220 break;
4221 case 0x0c00: /* bfclr */
4222 gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4223 break;
4224 case 0x0d00: /* bfffo */
4225 t64 = tcg_temp_new_i64();
4226 gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len);
4227 tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64);
4228 tcg_temp_free_i64(t64);
4229 break;
4230 case 0x0e00: /* bfset */
4231 gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4232 break;
4233 case 0x0800: /* bftst */
4234 gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4235 break;
4236 default:
4237 g_assert_not_reached();
4238 }
4239 set_cc_op(s, CC_OP_LOGIC);
4240
4241 if (!(ext & 0x20)) {
4242 tcg_temp_free(len);
4243 }
4244 if (!(ext & 0x800)) {
4245 tcg_temp_free(ofs);
4246 }
4247 }
4248
4249 DISAS_INSN(bfins_reg)
4250 {
4251 int ext = read_im16(env, s);
4252 TCGv dst = DREG(insn, 0);
4253 TCGv src = DREG(ext, 12);
4254 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4255 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4256 int pos = 32 - ofs - len; /* little bit-endian */
4257 TCGv tmp;
4258
4259 tmp = tcg_temp_new();
4260
4261 if (ext & 0x20) {
4262 /* Variable width */
4263 tcg_gen_neg_i32(tmp, DREG(ext, 0));
4264 tcg_gen_andi_i32(tmp, tmp, 31);
4265 tcg_gen_shl_i32(QREG_CC_N, src, tmp);
4266 } else {
4267 /* Immediate width */
4268 tcg_gen_shli_i32(QREG_CC_N, src, 32 - len);
4269 }
4270 set_cc_op(s, CC_OP_LOGIC);
4271
4272 /* Immediate width and offset */
4273 if ((ext & 0x820) == 0) {
4274 /* Check for suitability for deposit. */
4275 if (pos >= 0) {
4276 tcg_gen_deposit_i32(dst, dst, src, pos, len);
4277 } else {
4278 uint32_t maski = -2U << (len - 1);
4279 uint32_t roti = (ofs + len) & 31;
4280 tcg_gen_andi_i32(tmp, src, ~maski);
4281 tcg_gen_rotri_i32(tmp, tmp, roti);
4282 tcg_gen_andi_i32(dst, dst, ror32(maski, roti));
4283 tcg_gen_or_i32(dst, dst, tmp);
4284 }
4285 } else {
4286 TCGv mask = tcg_temp_new();
4287 TCGv rot = tcg_temp_new();
4288
4289 if (ext & 0x20) {
4290 /* Variable width */
4291 tcg_gen_subi_i32(rot, DREG(ext, 0), 1);
4292 tcg_gen_andi_i32(rot, rot, 31);
4293 tcg_gen_movi_i32(mask, -2);
4294 tcg_gen_shl_i32(mask, mask, rot);
4295 tcg_gen_mov_i32(rot, DREG(ext, 0));
4296 tcg_gen_andc_i32(tmp, src, mask);
4297 } else {
4298 /* Immediate width (variable offset) */
4299 uint32_t maski = -2U << (len - 1);
4300 tcg_gen_andi_i32(tmp, src, ~maski);
4301 tcg_gen_movi_i32(mask, maski);
4302 tcg_gen_movi_i32(rot, len & 31);
4303 }
4304 if (ext & 0x800) {
4305 /* Variable offset */
4306 tcg_gen_add_i32(rot, rot, DREG(ext, 6));
4307 } else {
4308 /* Immediate offset (variable width) */
4309 tcg_gen_addi_i32(rot, rot, ofs);
4310 }
4311 tcg_gen_andi_i32(rot, rot, 31);
4312 tcg_gen_rotr_i32(mask, mask, rot);
4313 tcg_gen_rotr_i32(tmp, tmp, rot);
4314 tcg_gen_and_i32(dst, dst, mask);
4315 tcg_gen_or_i32(dst, dst, tmp);
4316
4317 tcg_temp_free(rot);
4318 tcg_temp_free(mask);
4319 }
4320 tcg_temp_free(tmp);
4321 }
4322
4323 DISAS_INSN(bfins_mem)
4324 {
4325 int ext = read_im16(env, s);
4326 TCGv src = DREG(ext, 12);
4327 TCGv addr, len, ofs;
4328
4329 addr = gen_lea(env, s, insn, OS_UNSIZED);
4330 if (IS_NULL_QREG(addr)) {
4331 gen_addr_fault(s);
4332 return;
4333 }
4334
4335 if (ext & 0x20) {
4336 len = DREG(ext, 0);
4337 } else {
4338 len = tcg_const_i32(extract32(ext, 0, 5));
4339 }
4340 if (ext & 0x800) {
4341 ofs = DREG(ext, 6);
4342 } else {
4343 ofs = tcg_const_i32(extract32(ext, 6, 5));
4344 }
4345
4346 gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
4347 set_cc_op(s, CC_OP_LOGIC);
4348
4349 if (!(ext & 0x20)) {
4350 tcg_temp_free(len);
4351 }
4352 if (!(ext & 0x800)) {
4353 tcg_temp_free(ofs);
4354 }
4355 }
4356
4357 DISAS_INSN(ff1)
4358 {
4359 TCGv reg;
4360 reg = DREG(insn, 0);
4361 gen_logic_cc(s, reg, OS_LONG);
4362 gen_helper_ff1(reg, reg);
4363 }
4364
4365 DISAS_INSN(chk)
4366 {
4367 TCGv src, reg;
4368 int opsize;
4369
4370 switch ((insn >> 7) & 3) {
4371 case 3:
4372 opsize = OS_WORD;
4373 break;
4374 case 2:
4375 if (m68k_feature(env, M68K_FEATURE_CHK2)) {
4376 opsize = OS_LONG;
4377 break;
4378 }
4379 /* fallthru */
4380 default:
4381 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4382 return;
4383 }
4384 SRC_EA(env, src, opsize, 1, NULL);
4385 reg = gen_extend(s, DREG(insn, 9), opsize, 1);
4386
4387 gen_flush_flags(s);
4388 gen_helper_chk(cpu_env, reg, src);
4389 }
4390
4391 DISAS_INSN(chk2)
4392 {
4393 uint16_t ext;
4394 TCGv addr1, addr2, bound1, bound2, reg;
4395 int opsize;
4396
4397 switch ((insn >> 9) & 3) {
4398 case 0:
4399 opsize = OS_BYTE;
4400 break;
4401 case 1:
4402 opsize = OS_WORD;
4403 break;
4404 case 2:
4405 opsize = OS_LONG;
4406 break;
4407 default:
4408 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4409 return;
4410 }
4411
4412 ext = read_im16(env, s);
4413 if ((ext & 0x0800) == 0) {
4414 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4415 return;
4416 }
4417
4418 addr1 = gen_lea(env, s, insn, OS_UNSIZED);
4419 addr2 = tcg_temp_new();
4420 tcg_gen_addi_i32(addr2, addr1, opsize_bytes(opsize));
4421
4422 bound1 = gen_load(s, opsize, addr1, 1, IS_USER(s));
4423 tcg_temp_free(addr1);
4424 bound2 = gen_load(s, opsize, addr2, 1, IS_USER(s));
4425 tcg_temp_free(addr2);
4426
4427 reg = tcg_temp_new();
4428 if (ext & 0x8000) {
4429 tcg_gen_mov_i32(reg, AREG(ext, 12));
4430 } else {
4431 gen_ext(reg, DREG(ext, 12), opsize, 1);
4432 }
4433
4434 gen_flush_flags(s);
4435 gen_helper_chk2(cpu_env, reg, bound1, bound2);
4436 tcg_temp_free(reg);
4437 tcg_temp_free(bound1);
4438 tcg_temp_free(bound2);
4439 }
4440
4441 static void m68k_copy_line(TCGv dst, TCGv src, int index)
4442 {
4443 TCGv addr;
4444 TCGv_i64 t0, t1;
4445
4446 addr = tcg_temp_new();
4447
4448 t0 = tcg_temp_new_i64();
4449 t1 = tcg_temp_new_i64();
4450
4451 tcg_gen_andi_i32(addr, src, ~15);
4452 tcg_gen_qemu_ld64(t0, addr, index);
4453 tcg_gen_addi_i32(addr, addr, 8);
4454 tcg_gen_qemu_ld64(t1, addr, index);
4455
4456 tcg_gen_andi_i32(addr, dst, ~15);
4457 tcg_gen_qemu_st64(t0, addr, index);
4458 tcg_gen_addi_i32(addr, addr, 8);
4459 tcg_gen_qemu_st64(t1, addr, index);
4460
4461 tcg_temp_free_i64(t0);
4462 tcg_temp_free_i64(t1);
4463 tcg_temp_free(addr);
4464 }
4465
4466 DISAS_INSN(move16_reg)
4467 {
4468 int index = IS_USER(s);
4469 TCGv tmp;
4470 uint16_t ext;
4471
4472 ext = read_im16(env, s);
4473 if ((ext & (1 << 15)) == 0) {
4474 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4475 }
4476
4477 m68k_copy_line(AREG(ext, 12), AREG(insn, 0), index);
4478
4479 /* Ax can be Ay, so save Ay before incrementing Ax */
4480 tmp = tcg_temp_new();
4481 tcg_gen_mov_i32(tmp, AREG(ext, 12));
4482 tcg_gen_addi_i32(AREG(insn, 0), AREG(insn, 0), 16);
4483 tcg_gen_addi_i32(AREG(ext, 12), tmp, 16);
4484 tcg_temp_free(tmp);
4485 }
4486
4487 DISAS_INSN(move16_mem)
4488 {
4489 int index = IS_USER(s);
4490 TCGv reg, addr;
4491
4492 reg = AREG(insn, 0);
4493 addr = tcg_const_i32(read_im32(env, s));
4494
4495 if ((insn >> 3) & 1) {
4496 /* MOVE16 (xxx).L, (Ay) */
4497 m68k_copy_line(reg, addr, index);
4498 } else {
4499 /* MOVE16 (Ay), (xxx).L */
4500 m68k_copy_line(addr, reg, index);
4501 }
4502
4503 tcg_temp_free(addr);
4504
4505 if (((insn >> 3) & 2) == 0) {
4506 /* (Ay)+ */
4507 tcg_gen_addi_i32(reg, reg, 16);
4508 }
4509 }
4510
4511 DISAS_INSN(strldsr)
4512 {
4513 uint16_t ext;
4514 uint32_t addr;
4515
4516 addr = s->pc - 2;
4517 ext = read_im16(env, s);
4518 if (ext != 0x46FC) {
4519 gen_exception(s, addr, EXCP_UNSUPPORTED);
4520 return;
4521 }
4522 ext = read_im16(env, s);
4523 if (IS_USER(s) || (ext & SR_S) == 0) {
4524 gen_exception(s, addr, EXCP_PRIVILEGE);
4525 return;
4526 }
4527 gen_push(s, gen_get_sr(s));
4528 gen_set_sr_im(s, ext, 0);
4529 }
4530
4531 DISAS_INSN(move_from_sr)
4532 {
4533 TCGv sr;
4534
4535 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
4536 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4537 return;
4538 }
4539 sr = gen_get_sr(s);
4540 DEST_EA(env, insn, OS_WORD, sr, NULL);
4541 }
4542
4543 #if defined(CONFIG_SOFTMMU)
4544 DISAS_INSN(moves)
4545 {
4546 int opsize;
4547 uint16_t ext;
4548 TCGv reg;
4549 TCGv addr;
4550 int extend;
4551
4552 if (IS_USER(s)) {
4553 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4554 return;
4555 }
4556
4557 ext = read_im16(env, s);
4558
4559 opsize = insn_opsize(insn);
4560
4561 if (ext & 0x8000) {
4562 /* address register */
4563 reg = AREG(ext, 12);
4564 extend = 1;
4565 } else {
4566 /* data register */
4567 reg = DREG(ext, 12);
4568 extend = 0;
4569 }
4570
4571 addr = gen_lea(env, s, insn, opsize);
4572 if (IS_NULL_QREG(addr)) {
4573 gen_addr_fault(s);
4574 return;
4575 }
4576
4577 if (ext & 0x0800) {
4578 /* from reg to ea */
4579 gen_store(s, opsize, addr, reg, DFC_INDEX(s));
4580 } else {
4581 /* from ea to reg */
4582 TCGv tmp = gen_load(s, opsize, addr, 0, SFC_INDEX(s));
4583 if (extend) {
4584 gen_ext(reg, tmp, opsize, 1);
4585 } else {
4586 gen_partset_reg(opsize, reg, tmp);
4587 }
4588 tcg_temp_free(tmp);
4589 }
4590 switch (extract32(insn, 3, 3)) {
4591 case 3: /* Indirect postincrement. */
4592 tcg_gen_addi_i32(AREG(insn, 0), addr,
4593 REG(insn, 0) == 7 && opsize == OS_BYTE
4594 ? 2
4595 : opsize_bytes(opsize));
4596 break;
4597 case 4: /* Indirect predecrememnt. */
4598 tcg_gen_mov_i32(AREG(insn, 0), addr);
4599 break;
4600 }
4601 }
4602
4603 DISAS_INSN(move_to_sr)
4604 {
4605 if (IS_USER(s)) {
4606 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4607 return;
4608 }
4609 gen_move_to_sr(env, s, insn, false);
4610 gen_lookup_tb(s);
4611 }
4612
4613 DISAS_INSN(move_from_usp)
4614 {
4615 if (IS_USER(s)) {
4616 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4617 return;
4618 }
4619 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
4620 offsetof(CPUM68KState, sp[M68K_USP]));
4621 }
4622
4623 DISAS_INSN(move_to_usp)
4624 {
4625 if (IS_USER(s)) {
4626 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4627 return;
4628 }
4629 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
4630 offsetof(CPUM68KState, sp[M68K_USP]));
4631 }
4632
4633 DISAS_INSN(halt)
4634 {
4635 if (IS_USER(s)) {
4636 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4637 return;
4638 }
4639
4640 gen_exception(s, s->pc, EXCP_HALT_INSN);
4641 }
4642
4643 DISAS_INSN(stop)
4644 {
4645 uint16_t ext;
4646
4647 if (IS_USER(s)) {
4648 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4649 return;
4650 }
4651
4652 ext = read_im16(env, s);
4653
4654 gen_set_sr_im(s, ext, 0);
4655 tcg_gen_movi_i32(cpu_halted, 1);
4656 gen_exception(s, s->pc, EXCP_HLT);
4657 }
4658
4659 DISAS_INSN(rte)
4660 {
4661 if (IS_USER(s)) {
4662 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4663 return;
4664 }
4665 gen_exception(s, s->insn_pc, EXCP_RTE);
4666 }
4667
4668 DISAS_INSN(cf_movec)
4669 {
4670 uint16_t ext;
4671 TCGv reg;
4672
4673 if (IS_USER(s)) {
4674 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4675 return;
4676 }
4677
4678 ext = read_im16(env, s);
4679
4680 if (ext & 0x8000) {
4681 reg = AREG(ext, 12);
4682 } else {
4683 reg = DREG(ext, 12);
4684 }
4685 gen_helper_cf_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
4686 gen_lookup_tb(s);
4687 }
4688
4689 DISAS_INSN(m68k_movec)
4690 {
4691 uint16_t ext;
4692 TCGv reg;
4693
4694 if (IS_USER(s)) {
4695 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4696 return;
4697 }
4698
4699 ext = read_im16(env, s);
4700
4701 if (ext & 0x8000) {
4702 reg = AREG(ext, 12);
4703 } else {
4704 reg = DREG(ext, 12);
4705 }
4706 if (insn & 1) {
4707 gen_helper_m68k_movec_to(cpu_env, tcg_const_i32(ext & 0xfff), reg);
4708 } else {
4709 gen_helper_m68k_movec_from(reg, cpu_env, tcg_const_i32(ext & 0xfff));
4710 }
4711 gen_lookup_tb(s);
4712 }
4713
4714 DISAS_INSN(intouch)
4715 {
4716 if (IS_USER(s)) {
4717 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4718 return;
4719 }
4720 /* ICache fetch. Implement as no-op. */
4721 }
4722
4723 DISAS_INSN(cpushl)
4724 {
4725 if (IS_USER(s)) {
4726 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4727 return;
4728 }
4729 /* Cache push/invalidate. Implement as no-op. */
4730 }
4731
4732 DISAS_INSN(cpush)
4733 {
4734 if (IS_USER(s)) {
4735 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4736 return;
4737 }
4738 /* Cache push/invalidate. Implement as no-op. */
4739 }
4740
4741 DISAS_INSN(cinv)
4742 {
4743 if (IS_USER(s)) {
4744 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4745 return;
4746 }
4747 /* Invalidate cache line. Implement as no-op. */
4748 }
4749
4750 #if defined(CONFIG_SOFTMMU)
4751 DISAS_INSN(pflush)
4752 {
4753 TCGv opmode;
4754
4755 if (IS_USER(s)) {
4756 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4757 return;
4758 }
4759
4760 opmode = tcg_const_i32((insn >> 3) & 3);
4761 gen_helper_pflush(cpu_env, AREG(insn, 0), opmode);
4762 tcg_temp_free(opmode);
4763 }
4764
4765 DISAS_INSN(ptest)
4766 {
4767 TCGv is_read;
4768
4769 if (IS_USER(s)) {
4770 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4771 return;
4772 }
4773 is_read = tcg_const_i32((insn >> 5) & 1);
4774 gen_helper_ptest(cpu_env, AREG(insn, 0), is_read);
4775 tcg_temp_free(is_read);
4776 }
4777 #endif
4778
4779 DISAS_INSN(wddata)
4780 {
4781 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4782 }
4783
4784 DISAS_INSN(wdebug)
4785 {
4786 M68kCPU *cpu = m68k_env_get_cpu(env);
4787
4788 if (IS_USER(s)) {
4789 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
4790 return;
4791 }
4792 /* TODO: Implement wdebug. */
4793 cpu_abort(CPU(cpu), "WDEBUG not implemented");
4794 }
4795 #endif
4796
4797 DISAS_INSN(trap)
4798 {
4799 gen_exception(s, s->insn_pc, EXCP_TRAP0 + (insn & 0xf));
4800 }
4801
4802 static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
4803 {
4804 switch (reg) {
4805 case M68K_FPIAR:
4806 tcg_gen_movi_i32(res, 0);
4807 break;
4808 case M68K_FPSR:
4809 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr));
4810 break;
4811 case M68K_FPCR:
4812 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr));
4813 break;
4814 }
4815 }
4816
4817 static void gen_store_fcr(DisasContext *s, TCGv val, int reg)
4818 {
4819 switch (reg) {
4820 case M68K_FPIAR:
4821 break;
4822 case M68K_FPSR:
4823 tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr));
4824 break;
4825 case M68K_FPCR:
4826 gen_helper_set_fpcr(cpu_env, val);
4827 break;
4828 }
4829 }
4830
4831 static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
4832 {
4833 int index = IS_USER(s);
4834 TCGv tmp;
4835
4836 tmp = tcg_temp_new();
4837 gen_load_fcr(s, tmp, reg);
4838 tcg_gen_qemu_st32(tmp, addr, index);
4839 tcg_temp_free(tmp);
4840 }
4841
4842 static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
4843 {
4844 int index = IS_USER(s);
4845 TCGv tmp;
4846
4847 tmp = tcg_temp_new();
4848 tcg_gen_qemu_ld32u(tmp, addr, index);
4849 gen_store_fcr(s, tmp, reg);
4850 tcg_temp_free(tmp);
4851 }
4852
4853
4854 static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
4855 uint32_t insn, uint32_t ext)
4856 {
4857 int mask = (ext >> 10) & 7;
4858 int is_write = (ext >> 13) & 1;
4859 int mode = extract32(insn, 3, 3);
4860 int i;
4861 TCGv addr, tmp;
4862
4863 switch (mode) {
4864 case 0: /* Dn */
4865 if (mask != M68K_FPIAR && mask != M68K_FPSR && mask != M68K_FPCR) {
4866 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4867 return;
4868 }
4869 if (is_write) {
4870 gen_load_fcr(s, DREG(insn, 0), mask);
4871 } else {
4872 gen_store_fcr(s, DREG(insn, 0), mask);
4873 }
4874 return;
4875 case 1: /* An, only with FPIAR */
4876 if (mask != M68K_FPIAR) {
4877 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4878 return;
4879 }
4880 if (is_write) {
4881 gen_load_fcr(s, AREG(insn, 0), mask);
4882 } else {
4883 gen_store_fcr(s, AREG(insn, 0), mask);
4884 }
4885 return;
4886 default:
4887 break;
4888 }
4889
4890 tmp = gen_lea(env, s, insn, OS_LONG);
4891 if (IS_NULL_QREG(tmp)) {
4892 gen_addr_fault(s);
4893 return;
4894 }
4895
4896 addr = tcg_temp_new();
4897 tcg_gen_mov_i32(addr, tmp);
4898
4899 /* mask:
4900 *
4901 * 0b100 Floating-Point Control Register
4902 * 0b010 Floating-Point Status Register
4903 * 0b001 Floating-Point Instruction Address Register
4904 *
4905 */
4906
4907 if (is_write && mode == 4) {
4908 for (i = 2; i >= 0; i--, mask >>= 1) {
4909 if (mask & 1) {
4910 gen_qemu_store_fcr(s, addr, 1 << i);
4911 if (mask != 1) {
4912 tcg_gen_subi_i32(addr, addr, opsize_bytes(OS_LONG));
4913 }
4914 }
4915 }
4916 tcg_gen_mov_i32(AREG(insn, 0), addr);
4917 } else {
4918 for (i = 0; i < 3; i++, mask >>= 1) {
4919 if (mask & 1) {
4920 if (is_write) {
4921 gen_qemu_store_fcr(s, addr, 1 << i);
4922 } else {
4923 gen_qemu_load_fcr(s, addr, 1 << i);
4924 }
4925 if (mask != 1 || mode == 3) {
4926 tcg_gen_addi_i32(addr, addr, opsize_bytes(OS_LONG));
4927 }
4928 }
4929 }
4930 if (mode == 3) {
4931 tcg_gen_mov_i32(AREG(insn, 0), addr);
4932 }
4933 }
4934 tcg_temp_free_i32(addr);
4935 }
4936
4937 static void gen_op_fmovem(CPUM68KState *env, DisasContext *s,
4938 uint32_t insn, uint32_t ext)
4939 {
4940 int opsize;
4941 TCGv addr, tmp;
4942 int mode = (ext >> 11) & 0x3;
4943 int is_load = ((ext & 0x2000) == 0);
4944
4945 if (m68k_feature(s->env, M68K_FEATURE_FPU)) {
4946 opsize = OS_EXTENDED;
4947 } else {
4948 opsize = OS_DOUBLE; /* FIXME */
4949 }
4950
4951 addr = gen_lea(env, s, insn, opsize);
4952 if (IS_NULL_QREG(addr)) {
4953 gen_addr_fault(s);
4954 return;
4955 }
4956
4957 tmp = tcg_temp_new();
4958 if (mode & 0x1) {
4959 /* Dynamic register list */
4960 tcg_gen_ext8u_i32(tmp, DREG(ext, 4));
4961 } else {
4962 /* Static register list */
4963 tcg_gen_movi_i32(tmp, ext & 0xff);
4964 }
4965
4966 if (!is_load && (mode & 2) == 0) {
4967 /* predecrement addressing mode
4968 * only available to store register to memory
4969 */
4970 if (opsize == OS_EXTENDED) {
4971 gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp);
4972 } else {
4973 gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp);
4974 }
4975 } else {
4976 /* postincrement addressing mode */
4977 if (opsize == OS_EXTENDED) {
4978 if (is_load) {
4979 gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp);
4980 } else {
4981 gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp);
4982 }
4983 } else {
4984 if (is_load) {
4985 gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp);
4986 } else {
4987 gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp);
4988 }
4989 }
4990 }
4991 if ((insn & 070) == 030 || (insn & 070) == 040) {
4992 tcg_gen_mov_i32(AREG(insn, 0), tmp);
4993 }
4994 tcg_temp_free(tmp);
4995 }
4996
4997 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
4998 immediately before the next FP instruction is executed. */
4999 DISAS_INSN(fpu)
5000 {
5001 uint16_t ext;
5002 int opmode;
5003 int opsize;
5004 TCGv_ptr cpu_src, cpu_dest;
5005
5006 ext = read_im16(env, s);
5007 opmode = ext & 0x7f;
5008 switch ((ext >> 13) & 7) {
5009 case 0:
5010 break;
5011 case 1:
5012 goto undef;
5013 case 2:
5014 if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) {
5015 /* fmovecr */
5016 TCGv rom_offset = tcg_const_i32(opmode);
5017 cpu_dest = gen_fp_ptr(REG(ext, 7));
5018 gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
5019 tcg_temp_free_ptr(cpu_dest);
5020 tcg_temp_free(rom_offset);
5021 return;
5022 }
5023 break;
5024 case 3: /* fmove out */
5025 cpu_src = gen_fp_ptr(REG(ext, 7));
5026 opsize = ext_opsize(ext, 10);
5027 if (gen_ea_fp(env, s, insn, opsize, cpu_src,
5028 EA_STORE, IS_USER(s)) == -1) {
5029 gen_addr_fault(s);
5030 }
5031 gen_helper_ftst(cpu_env, cpu_src);
5032 tcg_temp_free_ptr(cpu_src);
5033 return;
5034 case 4: /* fmove to control register. */
5035 case 5: /* fmove from control register. */
5036 gen_op_fmove_fcr(env, s, insn, ext);
5037 return;
5038 case 6: /* fmovem */
5039 case 7:
5040 if ((ext & 0x1000) == 0 && !m68k_feature(s->env, M68K_FEATURE_FPU)) {
5041 goto undef;
5042 }
5043 gen_op_fmovem(env, s, insn, ext);
5044 return;
5045 }
5046 if (ext & (1 << 14)) {
5047 /* Source effective address. */
5048 opsize = ext_opsize(ext, 10);
5049 cpu_src = gen_fp_result_ptr();
5050 if (gen_ea_fp(env, s, insn, opsize, cpu_src,
5051 EA_LOADS, IS_USER(s)) == -1) {
5052 gen_addr_fault(s);
5053 return;
5054 }
5055 } else {
5056 /* Source register. */
5057 opsize = OS_EXTENDED;
5058 cpu_src = gen_fp_ptr(REG(ext, 10));
5059 }
5060 cpu_dest = gen_fp_ptr(REG(ext, 7));
5061 switch (opmode) {
5062 case 0: /* fmove */
5063 gen_fp_move(cpu_dest, cpu_src);
5064 break;
5065 case 0x40: /* fsmove */
5066 gen_helper_fsround(cpu_env, cpu_dest, cpu_src);
5067 break;
5068 case 0x44: /* fdmove */
5069 gen_helper_fdround(cpu_env, cpu_dest, cpu_src);
5070 break;
5071 case 1: /* fint */
5072 gen_helper_firound(cpu_env, cpu_dest, cpu_src);
5073 break;
5074 case 2: /* fsinh */
5075 gen_helper_fsinh(cpu_env, cpu_dest, cpu_src);
5076 break;
5077 case 3: /* fintrz */
5078 gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
5079 break;
5080 case 4: /* fsqrt */
5081 gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
5082 break;
5083 case 0x41: /* fssqrt */
5084 gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src);
5085 break;
5086 case 0x45: /* fdsqrt */
5087 gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src);
5088 break;
5089 case 0x06: /* flognp1 */
5090 gen_helper_flognp1(cpu_env, cpu_dest, cpu_src);
5091 break;
5092 case 0x09: /* ftanh */
5093 gen_helper_ftanh(cpu_env, cpu_dest, cpu_src);
5094 break;
5095 case 0x0a: /* fatan */
5096 gen_helper_fatan(cpu_env, cpu_dest, cpu_src);
5097 break;
5098 case 0x0c: /* fasin */
5099 gen_helper_fasin(cpu_env, cpu_dest, cpu_src);
5100 break;
5101 case 0x0d: /* fatanh */
5102 gen_helper_fatanh(cpu_env, cpu_dest, cpu_src);
5103 break;
5104 case 0x0e: /* fsin */
5105 gen_helper_fsin(cpu_env, cpu_dest, cpu_src);
5106 break;
5107 case 0x0f: /* ftan */
5108 gen_helper_ftan(cpu_env, cpu_dest, cpu_src);
5109 break;
5110 case 0x10: /* fetox */
5111 gen_helper_fetox(cpu_env, cpu_dest, cpu_src);
5112 break;
5113 case 0x11: /* ftwotox */
5114 gen_helper_ftwotox(cpu_env, cpu_dest, cpu_src);
5115 break;
5116 case 0x12: /* ftentox */
5117 gen_helper_ftentox(cpu_env, cpu_dest, cpu_src);
5118 break;
5119 case 0x14: /* flogn */
5120 gen_helper_flogn(cpu_env, cpu_dest, cpu_src);
5121 break;
5122 case 0x15: /* flog10 */
5123 gen_helper_flog10(cpu_env, cpu_dest, cpu_src);
5124 break;
5125 case 0x16: /* flog2 */
5126 gen_helper_flog2(cpu_env, cpu_dest, cpu_src);
5127 break;
5128 case 0x18: /* fabs */
5129 gen_helper_fabs(cpu_env, cpu_dest, cpu_src);
5130 break;
5131 case 0x58: /* fsabs */
5132 gen_helper_fsabs(cpu_env, cpu_dest, cpu_src);
5133 break;
5134 case 0x5c: /* fdabs */
5135 gen_helper_fdabs(cpu_env, cpu_dest, cpu_src);
5136 break;
5137 case 0x19: /* fcosh */
5138 gen_helper_fcosh(cpu_env, cpu_dest, cpu_src);
5139 break;
5140 case 0x1a: /* fneg */
5141 gen_helper_fneg(cpu_env, cpu_dest, cpu_src);
5142 break;
5143 case 0x5a: /* fsneg */
5144 gen_helper_fsneg(cpu_env, cpu_dest, cpu_src);
5145 break;
5146 case 0x5e: /* fdneg */
5147 gen_helper_fdneg(cpu_env, cpu_dest, cpu_src);
5148 break;
5149 case 0x1c: /* facos */
5150 gen_helper_facos(cpu_env, cpu_dest, cpu_src);
5151 break;
5152 case 0x1d: /* fcos */
5153 gen_helper_fcos(cpu_env, cpu_dest, cpu_src);
5154 break;
5155 case 0x1e: /* fgetexp */
5156 gen_helper_fgetexp(cpu_env, cpu_dest, cpu_src);
5157 break;
5158 case 0x1f: /* fgetman */
5159 gen_helper_fgetman(cpu_env, cpu_dest, cpu_src);
5160 break;
5161 case 0x20: /* fdiv */
5162 gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5163 break;
5164 case 0x60: /* fsdiv */
5165 gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5166 break;
5167 case 0x64: /* fddiv */
5168 gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5169 break;
5170 case 0x21: /* fmod */
5171 gen_helper_fmod(cpu_env, cpu_dest, cpu_src, cpu_dest);
5172 break;
5173 case 0x22: /* fadd */
5174 gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5175 break;
5176 case 0x62: /* fsadd */
5177 gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5178 break;
5179 case 0x66: /* fdadd */
5180 gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
5181 break;
5182 case 0x23: /* fmul */
5183 gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5184 break;
5185 case 0x63: /* fsmul */
5186 gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5187 break;
5188 case 0x67: /* fdmul */
5189 gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5190 break;
5191 case 0x24: /* fsgldiv */
5192 gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
5193 break;
5194 case 0x25: /* frem */
5195 gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest);
5196 break;
5197 case 0x26: /* fscale */
5198 gen_helper_fscale(cpu_env, cpu_dest, cpu_src, cpu_dest);
5199 break;
5200 case 0x27: /* fsglmul */
5201 gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
5202 break;
5203 case 0x28: /* fsub */
5204 gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5205 break;
5206 case 0x68: /* fssub */
5207 gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5208 break;
5209 case 0x6c: /* fdsub */
5210 gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
5211 break;
5212 case 0x30: case 0x31: case 0x32:
5213 case 0x33: case 0x34: case 0x35:
5214 case 0x36: case 0x37: {
5215 TCGv_ptr cpu_dest2 = gen_fp_ptr(REG(ext, 0));
5216 gen_helper_fsincos(cpu_env, cpu_dest, cpu_dest2, cpu_src);
5217 tcg_temp_free_ptr(cpu_dest2);
5218 }
5219 break;
5220 case 0x38: /* fcmp */
5221 gen_helper_fcmp(cpu_env, cpu_src, cpu_dest);
5222 return;
5223 case 0x3a: /* ftst */
5224 gen_helper_ftst(cpu_env, cpu_src);
5225 return;
5226 default:
5227 goto undef;
5228 }
5229 tcg_temp_free_ptr(cpu_src);
5230 gen_helper_ftst(cpu_env, cpu_dest);
5231 tcg_temp_free_ptr(cpu_dest);
5232 return;
5233 undef:
5234 /* FIXME: Is this right for offset addressing modes? */
5235 s->pc -= 2;
5236 disas_undef_fpu(env, s, insn);
5237 }
5238
5239 static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
5240 {
5241 TCGv fpsr;
5242
5243 c->g1 = 1;
5244 c->v2 = tcg_const_i32(0);
5245 c->g2 = 0;
5246 /* TODO: Raise BSUN exception. */
5247 fpsr = tcg_temp_new();
5248 gen_load_fcr(s, fpsr, M68K_FPSR);
5249 switch (cond) {
5250 case 0: /* False */
5251 case 16: /* Signaling False */
5252 c->v1 = c->v2;
5253 c->tcond = TCG_COND_NEVER;
5254 break;
5255 case 1: /* EQual Z */
5256 case 17: /* Signaling EQual Z */
5257 c->v1 = tcg_temp_new();
5258 c->g1 = 0;
5259 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5260 c->tcond = TCG_COND_NE;
5261 break;
5262 case 2: /* Ordered Greater Than !(A || Z || N) */
5263 case 18: /* Greater Than !(A || Z || N) */
5264 c->v1 = tcg_temp_new();
5265 c->g1 = 0;
5266 tcg_gen_andi_i32(c->v1, fpsr,
5267 FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5268 c->tcond = TCG_COND_EQ;
5269 break;
5270 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
5271 case 19: /* Greater than or Equal Z || !(A || N) */
5272 c->v1 = tcg_temp_new();
5273 c->g1 = 0;
5274 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5275 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
5276 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N);
5277 tcg_gen_or_i32(c->v1, c->v1, fpsr);
5278 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5279 c->tcond = TCG_COND_NE;
5280 break;
5281 case 4: /* Ordered Less Than !(!N || A || Z); */
5282 case 20: /* Less Than !(!N || A || Z); */
5283 c->v1 = tcg_temp_new();
5284 c->g1 = 0;
5285 tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
5286 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
5287 c->tcond = TCG_COND_EQ;
5288 break;
5289 case 5: /* Ordered Less than or Equal Z || (N && !A) */
5290 case 21: /* Less than or Equal Z || (N && !A) */
5291 c->v1 = tcg_temp_new();
5292 c->g1 = 0;
5293 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5294 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
5295 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
5296 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_Z | FPSR_CC_N);
5297 c->tcond = TCG_COND_NE;
5298 break;
5299 case 6: /* Ordered Greater or Less than !(A || Z) */
5300 case 22: /* Greater or Less than !(A || Z) */
5301 c->v1 = tcg_temp_new();
5302 c->g1 = 0;
5303 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
5304 c->tcond = TCG_COND_EQ;
5305 break;
5306 case 7: /* Ordered !A */
5307 case 23: /* Greater, Less or Equal !A */
5308 c->v1 = tcg_temp_new();
5309 c->g1 = 0;
5310 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5311 c->tcond = TCG_COND_EQ;
5312 break;
5313 case 8: /* Unordered A */
5314 case 24: /* Not Greater, Less or Equal A */
5315 c->v1 = tcg_temp_new();
5316 c->g1 = 0;
5317 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
5318 c->tcond = TCG_COND_NE;
5319 break;
5320 case 9: /* Unordered or Equal A || Z */
5321 case 25: /* Not Greater or Less then A || Z */
5322 c->v1 = tcg_temp_new();
5323 c->g1 = 0;
5324 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
5325 c->tcond = TCG_COND_NE;
5326 break;
5327 case 10: /* Unordered or Greater Than A || !(N || Z)) */
5328 case 26: /* Not Less or Equal A || !(N || Z)) */
5329 c->v1 = tcg_temp_new();
5330 c->g1 = 0;
5331 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5332 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
5333 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N);
5334 tcg_gen_or_i32(c->v1, c->v1, fpsr);
5335 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5336 c->tcond = TCG_COND_NE;
5337 break;
5338 case 11: /* Unordered or Greater or Equal A || Z || !N */
5339 case 27: /* Not Less Than A || Z || !N */
5340 c->v1 = tcg_temp_new();
5341 c->g1 = 0;
5342 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5343 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
5344 c->tcond = TCG_COND_NE;
5345 break;
5346 case 12: /* Unordered or Less Than A || (N && !Z) */
5347 case 28: /* Not Greater than or Equal A || (N && !Z) */
5348 c->v1 = tcg_temp_new();
5349 c->g1 = 0;
5350 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5351 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
5352 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
5353 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N);
5354 c->tcond = TCG_COND_NE;
5355 break;
5356 case 13: /* Unordered or Less or Equal A || Z || N */
5357 case 29: /* Not Greater Than A || Z || N */
5358 c->v1 = tcg_temp_new();
5359 c->g1 = 0;
5360 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
5361 c->tcond = TCG_COND_NE;
5362 break;
5363 case 14: /* Not Equal !Z */
5364 case 30: /* Signaling Not Equal !Z */
5365 c->v1 = tcg_temp_new();
5366 c->g1 = 0;
5367 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
5368 c->tcond = TCG_COND_EQ;
5369 break;
5370 case 15: /* True */
5371 case 31: /* Signaling True */
5372 c->v1 = c->v2;
5373 c->tcond = TCG_COND_ALWAYS;
5374 break;
5375 }
5376 tcg_temp_free(fpsr);
5377 }
5378
5379 static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1)
5380 {
5381 DisasCompare c;
5382
5383 gen_fcc_cond(&c, s, cond);
5384 update_cc_op(s);
5385 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
5386 free_cond(&c);
5387 }
5388
5389 DISAS_INSN(fbcc)
5390 {
5391 uint32_t offset;
5392 uint32_t base;
5393 TCGLabel *l1;
5394
5395 base = s->pc;
5396 offset = (int16_t)read_im16(env, s);
5397 if (insn & (1 << 6)) {
5398 offset = (offset << 16) | read_im16(env, s);
5399 }
5400
5401 l1 = gen_new_label();
5402 update_cc_op(s);
5403 gen_fjmpcc(s, insn & 0x3f, l1);
5404 gen_jmp_tb(s, 0, s->pc);
5405 gen_set_label(l1);
5406 gen_jmp_tb(s, 1, base + offset);
5407 }
5408
5409 DISAS_INSN(fscc)
5410 {
5411 DisasCompare c;
5412 int cond;
5413 TCGv tmp;
5414 uint16_t ext;
5415
5416 ext = read_im16(env, s);
5417 cond = ext & 0x3f;
5418 gen_fcc_cond(&c, s, cond);
5419
5420 tmp = tcg_temp_new();
5421 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
5422 free_cond(&c);
5423
5424 tcg_gen_neg_i32(tmp, tmp);
5425 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
5426 tcg_temp_free(tmp);
5427 }
5428
5429 #if defined(CONFIG_SOFTMMU)
5430 DISAS_INSN(frestore)
5431 {
5432 TCGv addr;
5433
5434 if (IS_USER(s)) {
5435 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
5436 return;
5437 }
5438 if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
5439 SRC_EA(env, addr, OS_LONG, 0, NULL);
5440 /* FIXME: check the state frame */
5441 } else {
5442 disas_undef(env, s, insn);
5443 }
5444 }
5445
5446 DISAS_INSN(fsave)
5447 {
5448 if (IS_USER(s)) {
5449 gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
5450 return;
5451 }
5452
5453 if (m68k_feature(s->env, M68K_FEATURE_M68040)) {
5454 /* always write IDLE */
5455 TCGv idle = tcg_const_i32(0x41000000);
5456 DEST_EA(env, insn, OS_LONG, idle, NULL);
5457 tcg_temp_free(idle);
5458 } else {
5459 disas_undef(env, s, insn);
5460 }
5461 }
5462 #endif
5463
5464 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
5465 {
5466 TCGv tmp = tcg_temp_new();
5467 if (s->env->macsr & MACSR_FI) {
5468 if (upper)
5469 tcg_gen_andi_i32(tmp, val, 0xffff0000);
5470 else
5471 tcg_gen_shli_i32(tmp, val, 16);
5472 } else if (s->env->macsr & MACSR_SU) {
5473 if (upper)
5474 tcg_gen_sari_i32(tmp, val, 16);
5475 else
5476 tcg_gen_ext16s_i32(tmp, val);
5477 } else {
5478 if (upper)
5479 tcg_gen_shri_i32(tmp, val, 16);
5480 else
5481 tcg_gen_ext16u_i32(tmp, val);
5482 }
5483 return tmp;
5484 }
5485
5486 static void gen_mac_clear_flags(void)
5487 {
5488 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
5489 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
5490 }
5491
5492 DISAS_INSN(mac)
5493 {
5494 TCGv rx;
5495 TCGv ry;
5496 uint16_t ext;
5497 int acc;
5498 TCGv tmp;
5499 TCGv addr;
5500 TCGv loadval;
5501 int dual;
5502 TCGv saved_flags;
5503
5504 if (!s->done_mac) {
5505 s->mactmp = tcg_temp_new_i64();
5506 s->done_mac = 1;
5507 }
5508
5509 ext = read_im16(env, s);
5510
5511 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
5512 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
5513 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
5514 disas_undef(env, s, insn);
5515 return;
5516 }
5517 if (insn & 0x30) {
5518 /* MAC with load. */
5519 tmp = gen_lea(env, s, insn, OS_LONG);
5520 addr = tcg_temp_new();
5521 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
5522 /* Load the value now to ensure correct exception behavior.
5523 Perform writeback after reading the MAC inputs. */
5524 loadval = gen_load(s, OS_LONG, addr, 0, IS_USER(s));
5525
5526 acc ^= 1;
5527 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
5528 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
5529 } else {
5530 loadval = addr = NULL_QREG;
5531 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5532 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5533 }
5534
5535 gen_mac_clear_flags();
5536 #if 0
5537 l1 = -1;
5538 /* Disabled because conditional branches clobber temporary vars. */
5539 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
5540 /* Skip the multiply if we know we will ignore it. */
5541 l1 = gen_new_label();
5542 tmp = tcg_temp_new();
5543 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
5544 gen_op_jmp_nz32(tmp, l1);
5545 }
5546 #endif
5547
5548 if ((ext & 0x0800) == 0) {
5549 /* Word. */
5550 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
5551 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
5552 }
5553 if (s->env->macsr & MACSR_FI) {
5554 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
5555 } else {
5556 if (s->env->macsr & MACSR_SU)
5557 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
5558 else
5559 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
5560 switch ((ext >> 9) & 3) {
5561 case 1:
5562 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
5563 break;
5564 case 3:
5565 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
5566 break;
5567 }
5568 }
5569
5570 if (dual) {
5571 /* Save the overflow flag from the multiply. */
5572 saved_flags = tcg_temp_new();
5573 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
5574 } else {
5575 saved_flags = NULL_QREG;
5576 }
5577
5578 #if 0
5579 /* Disabled because conditional branches clobber temporary vars. */
5580 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
5581 /* Skip the accumulate if the value is already saturated. */
5582 l1 = gen_new_label();
5583 tmp = tcg_temp_new();
5584 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5585 gen_op_jmp_nz32(tmp, l1);
5586 }
5587 #endif
5588
5589 if (insn & 0x100)
5590 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5591 else
5592 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5593
5594 if (s->env->macsr & MACSR_FI)
5595 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5596 else if (s->env->macsr & MACSR_SU)
5597 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5598 else
5599 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5600
5601 #if 0
5602 /* Disabled because conditional branches clobber temporary vars. */
5603 if (l1 != -1)
5604 gen_set_label(l1);
5605 #endif
5606
5607 if (dual) {
5608 /* Dual accumulate variant. */
5609 acc = (ext >> 2) & 3;
5610 /* Restore the overflow flag from the multiplier. */
5611 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
5612 #if 0
5613 /* Disabled because conditional branches clobber temporary vars. */
5614 if ((s->env->macsr & MACSR_OMC) != 0) {
5615 /* Skip the accumulate if the value is already saturated. */
5616 l1 = gen_new_label();
5617 tmp = tcg_temp_new();
5618 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5619 gen_op_jmp_nz32(tmp, l1);
5620 }
5621 #endif
5622 if (ext & 2)
5623 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5624 else
5625 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5626 if (s->env->macsr & MACSR_FI)
5627 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5628 else if (s->env->macsr & MACSR_SU)
5629 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5630 else
5631 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5632 #if 0
5633 /* Disabled because conditional branches clobber temporary vars. */
5634 if (l1 != -1)
5635 gen_set_label(l1);
5636 #endif
5637 }
5638 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
5639
5640 if (insn & 0x30) {
5641 TCGv rw;
5642 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5643 tcg_gen_mov_i32(rw, loadval);
5644 /* FIXME: Should address writeback happen with the masked or
5645 unmasked value? */
5646 switch ((insn >> 3) & 7) {
5647 case 3: /* Post-increment. */
5648 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
5649 break;
5650 case 4: /* Pre-decrement. */
5651 tcg_gen_mov_i32(AREG(insn, 0), addr);
5652 }
5653 tcg_temp_free(loadval);
5654 }
5655 }
5656
5657 DISAS_INSN(from_mac)
5658 {
5659 TCGv rx;
5660 TCGv_i64 acc;
5661 int accnum;
5662
5663 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5664 accnum = (insn >> 9) & 3;
5665 acc = MACREG(accnum);
5666 if (s->env->macsr & MACSR_FI) {
5667 gen_helper_get_macf(rx, cpu_env, acc);
5668 } else if ((s->env->macsr & MACSR_OMC) == 0) {
5669 tcg_gen_extrl_i64_i32(rx, acc);
5670 } else if (s->env->macsr & MACSR_SU) {
5671 gen_helper_get_macs(rx, acc);
5672 } else {
5673 gen_helper_get_macu(rx, acc);
5674 }
5675 if (insn & 0x40) {
5676 tcg_gen_movi_i64(acc, 0);
5677 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5678 }
5679 }
5680
5681 DISAS_INSN(move_mac)
5682 {
5683 /* FIXME: This can be done without a helper. */
5684 int src;
5685 TCGv dest;
5686 src = insn & 3;
5687 dest = tcg_const_i32((insn >> 9) & 3);
5688 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
5689 gen_mac_clear_flags();
5690 gen_helper_mac_set_flags(cpu_env, dest);
5691 }
5692
5693 DISAS_INSN(from_macsr)
5694 {
5695 TCGv reg;
5696
5697 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5698 tcg_gen_mov_i32(reg, QREG_MACSR);
5699 }
5700
5701 DISAS_INSN(from_mask)
5702 {
5703 TCGv reg;
5704 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5705 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
5706 }
5707
5708 DISAS_INSN(from_mext)
5709 {
5710 TCGv reg;
5711 TCGv acc;
5712 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5713 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5714 if (s->env->macsr & MACSR_FI)
5715 gen_helper_get_mac_extf(reg, cpu_env, acc);
5716 else
5717 gen_helper_get_mac_exti(reg, cpu_env, acc);
5718 }
5719
5720 DISAS_INSN(macsr_to_ccr)
5721 {
5722 TCGv tmp = tcg_temp_new();
5723 tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
5724 gen_helper_set_sr(cpu_env, tmp);
5725 tcg_temp_free(tmp);
5726 set_cc_op(s, CC_OP_FLAGS);
5727 }
5728
5729 DISAS_INSN(to_mac)
5730 {
5731 TCGv_i64 acc;
5732 TCGv val;
5733 int accnum;
5734 accnum = (insn >> 9) & 3;
5735 acc = MACREG(accnum);
5736 SRC_EA(env, val, OS_LONG, 0, NULL);
5737 if (s->env->macsr & MACSR_FI) {
5738 tcg_gen_ext_i32_i64(acc, val);
5739 tcg_gen_shli_i64(acc, acc, 8);
5740 } else if (s->env->macsr & MACSR_SU) {
5741 tcg_gen_ext_i32_i64(acc, val);
5742 } else {
5743 tcg_gen_extu_i32_i64(acc, val);
5744 }
5745 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5746 gen_mac_clear_flags();
5747 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
5748 }
5749
5750 DISAS_INSN(to_macsr)
5751 {
5752 TCGv val;
5753 SRC_EA(env, val, OS_LONG, 0, NULL);
5754 gen_helper_set_macsr(cpu_env, val);
5755 gen_lookup_tb(s);
5756 }
5757
5758 DISAS_INSN(to_mask)
5759 {
5760 TCGv val;
5761 SRC_EA(env, val, OS_LONG, 0, NULL);
5762 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
5763 }
5764
5765 DISAS_INSN(to_mext)
5766 {
5767 TCGv val;
5768 TCGv acc;
5769 SRC_EA(env, val, OS_LONG, 0, NULL);
5770 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5771 if (s->env->macsr & MACSR_FI)
5772 gen_helper_set_mac_extf(cpu_env, val, acc);
5773 else if (s->env->macsr & MACSR_SU)
5774 gen_helper_set_mac_exts(cpu_env, val, acc);
5775 else
5776 gen_helper_set_mac_extu(cpu_env, val, acc);
5777 }
5778
5779 static disas_proc opcode_table[65536];
5780
5781 static void
5782 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
5783 {
5784 int i;
5785 int from;
5786 int to;
5787
5788 /* Sanity check. All set bits must be included in the mask. */
5789 if (opcode & ~mask) {
5790 fprintf(stderr,
5791 "qemu internal error: bogus opcode definition %04x/%04x\n",
5792 opcode, mask);
5793 abort();
5794 }
5795 /* This could probably be cleverer. For now just optimize the case where
5796 the top bits are known. */
5797 /* Find the first zero bit in the mask. */
5798 i = 0x8000;
5799 while ((i & mask) != 0)
5800 i >>= 1;
5801 /* Iterate over all combinations of this and lower bits. */
5802 if (i == 0)
5803 i = 1;
5804 else
5805 i <<= 1;
5806 from = opcode & ~(i - 1);
5807 to = from + i;
5808 for (i = from; i < to; i++) {
5809 if ((i & mask) == opcode)
5810 opcode_table[i] = proc;
5811 }
5812 }
5813
5814 /* Register m68k opcode handlers. Order is important.
5815 Later insn override earlier ones. */
5816 void register_m68k_insns (CPUM68KState *env)
5817 {
5818 /* Build the opcode table only once to avoid
5819 multithreading issues. */
5820 if (opcode_table[0] != NULL) {
5821 return;
5822 }
5823
5824 /* use BASE() for instruction available
5825 * for CF_ISA_A and M68000.
5826 */
5827 #define BASE(name, opcode, mask) \
5828 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5829 #define INSN(name, opcode, mask, feature) do { \
5830 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5831 BASE(name, opcode, mask); \
5832 } while(0)
5833 BASE(undef, 0000, 0000);
5834 INSN(arith_im, 0080, fff8, CF_ISA_A);
5835 INSN(arith_im, 0000, ff00, M68000);
5836 INSN(chk2, 00c0, f9c0, CHK2);
5837 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
5838 BASE(bitop_reg, 0100, f1c0);
5839 BASE(bitop_reg, 0140, f1c0);
5840 BASE(bitop_reg, 0180, f1c0);
5841 BASE(bitop_reg, 01c0, f1c0);
5842 INSN(movep, 0108, f138, MOVEP);
5843 INSN(arith_im, 0280, fff8, CF_ISA_A);
5844 INSN(arith_im, 0200, ff00, M68000);
5845 INSN(undef, 02c0, ffc0, M68000);
5846 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
5847 INSN(arith_im, 0480, fff8, CF_ISA_A);
5848 INSN(arith_im, 0400, ff00, M68000);
5849 INSN(undef, 04c0, ffc0, M68000);
5850 INSN(arith_im, 0600, ff00, M68000);
5851 INSN(undef, 06c0, ffc0, M68000);
5852 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
5853 INSN(arith_im, 0680, fff8, CF_ISA_A);
5854 INSN(arith_im, 0c00, ff38, CF_ISA_A);
5855 INSN(arith_im, 0c00, ff00, M68000);
5856 BASE(bitop_im, 0800, ffc0);
5857 BASE(bitop_im, 0840, ffc0);
5858 BASE(bitop_im, 0880, ffc0);
5859 BASE(bitop_im, 08c0, ffc0);
5860 INSN(arith_im, 0a80, fff8, CF_ISA_A);
5861 INSN(arith_im, 0a00, ff00, M68000);
5862 #if defined(CONFIG_SOFTMMU)
5863 INSN(moves, 0e00, ff00, M68000);
5864 #endif
5865 INSN(cas, 0ac0, ffc0, CAS);
5866 INSN(cas, 0cc0, ffc0, CAS);
5867 INSN(cas, 0ec0, ffc0, CAS);
5868 INSN(cas2w, 0cfc, ffff, CAS);
5869 INSN(cas2l, 0efc, ffff, CAS);
5870 BASE(move, 1000, f000);
5871 BASE(move, 2000, f000);
5872 BASE(move, 3000, f000);
5873 INSN(chk, 4000, f040, M68000);
5874 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
5875 INSN(negx, 4080, fff8, CF_ISA_A);
5876 INSN(negx, 4000, ff00, M68000);
5877 INSN(undef, 40c0, ffc0, M68000);
5878 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
5879 INSN(move_from_sr, 40c0, ffc0, M68000);
5880 BASE(lea, 41c0, f1c0);
5881 BASE(clr, 4200, ff00);
5882 BASE(undef, 42c0, ffc0);
5883 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
5884 INSN(move_from_ccr, 42c0, ffc0, M68000);
5885 INSN(neg, 4480, fff8, CF_ISA_A);
5886 INSN(neg, 4400, ff00, M68000);
5887 INSN(undef, 44c0, ffc0, M68000);
5888 BASE(move_to_ccr, 44c0, ffc0);
5889 INSN(not, 4680, fff8, CF_ISA_A);
5890 INSN(not, 4600, ff00, M68000);
5891 #if defined(CONFIG_SOFTMMU)
5892 BASE(move_to_sr, 46c0, ffc0);
5893 #endif
5894 INSN(nbcd, 4800, ffc0, M68000);
5895 INSN(linkl, 4808, fff8, M68000);
5896 BASE(pea, 4840, ffc0);
5897 BASE(swap, 4840, fff8);
5898 INSN(bkpt, 4848, fff8, BKPT);
5899 INSN(movem, 48d0, fbf8, CF_ISA_A);
5900 INSN(movem, 48e8, fbf8, CF_ISA_A);
5901 INSN(movem, 4880, fb80, M68000);
5902 BASE(ext, 4880, fff8);
5903 BASE(ext, 48c0, fff8);
5904 BASE(ext, 49c0, fff8);
5905 BASE(tst, 4a00, ff00);
5906 INSN(tas, 4ac0, ffc0, CF_ISA_B);
5907 INSN(tas, 4ac0, ffc0, M68000);
5908 #if defined(CONFIG_SOFTMMU)
5909 INSN(halt, 4ac8, ffff, CF_ISA_A);
5910 #endif
5911 INSN(pulse, 4acc, ffff, CF_ISA_A);
5912 BASE(illegal, 4afc, ffff);
5913 INSN(mull, 4c00, ffc0, CF_ISA_A);
5914 INSN(mull, 4c00, ffc0, LONG_MULDIV);
5915 INSN(divl, 4c40, ffc0, CF_ISA_A);
5916 INSN(divl, 4c40, ffc0, LONG_MULDIV);
5917 INSN(sats, 4c80, fff8, CF_ISA_B);
5918 BASE(trap, 4e40, fff0);
5919 BASE(link, 4e50, fff8);
5920 BASE(unlk, 4e58, fff8);
5921 #if defined(CONFIG_SOFTMMU)
5922 INSN(move_to_usp, 4e60, fff8, USP);
5923 INSN(move_from_usp, 4e68, fff8, USP);
5924 INSN(reset, 4e70, ffff, M68000);
5925 BASE(stop, 4e72, ffff);
5926 BASE(rte, 4e73, ffff);
5927 INSN(cf_movec, 4e7b, ffff, CF_ISA_A);
5928 INSN(m68k_movec, 4e7a, fffe, M68000);
5929 #endif
5930 BASE(nop, 4e71, ffff);
5931 INSN(rtd, 4e74, ffff, RTD);
5932 BASE(rts, 4e75, ffff);
5933 BASE(jump, 4e80, ffc0);
5934 BASE(jump, 4ec0, ffc0);
5935 INSN(addsubq, 5000, f080, M68000);
5936 BASE(addsubq, 5080, f0c0);
5937 INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
5938 INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */
5939 INSN(dbcc, 50c8, f0f8, M68000);
5940 INSN(tpf, 51f8, fff8, CF_ISA_A);
5941
5942 /* Branch instructions. */
5943 BASE(branch, 6000, f000);
5944 /* Disable long branch instructions, then add back the ones we want. */
5945 BASE(undef, 60ff, f0ff); /* All long branches. */
5946 INSN(branch, 60ff, f0ff, CF_ISA_B);
5947 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
5948 INSN(branch, 60ff, ffff, BRAL);
5949 INSN(branch, 60ff, f0ff, BCCL);
5950
5951 BASE(moveq, 7000, f100);
5952 INSN(mvzs, 7100, f100, CF_ISA_B);
5953 BASE(or, 8000, f000);
5954 BASE(divw, 80c0, f0c0);
5955 INSN(sbcd_reg, 8100, f1f8, M68000);
5956 INSN(sbcd_mem, 8108, f1f8, M68000);
5957 BASE(addsub, 9000, f000);
5958 INSN(undef, 90c0, f0c0, CF_ISA_A);
5959 INSN(subx_reg, 9180, f1f8, CF_ISA_A);
5960 INSN(subx_reg, 9100, f138, M68000);
5961 INSN(subx_mem, 9108, f138, M68000);
5962 INSN(suba, 91c0, f1c0, CF_ISA_A);
5963 INSN(suba, 90c0, f0c0, M68000);
5964
5965 BASE(undef_mac, a000, f000);
5966 INSN(mac, a000, f100, CF_EMAC);
5967 INSN(from_mac, a180, f9b0, CF_EMAC);
5968 INSN(move_mac, a110, f9fc, CF_EMAC);
5969 INSN(from_macsr,a980, f9f0, CF_EMAC);
5970 INSN(from_mask, ad80, fff0, CF_EMAC);
5971 INSN(from_mext, ab80, fbf0, CF_EMAC);
5972 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
5973 INSN(to_mac, a100, f9c0, CF_EMAC);
5974 INSN(to_macsr, a900, ffc0, CF_EMAC);
5975 INSN(to_mext, ab00, fbc0, CF_EMAC);
5976 INSN(to_mask, ad00, ffc0, CF_EMAC);
5977
5978 INSN(mov3q, a140, f1c0, CF_ISA_B);
5979 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
5980 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
5981 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
5982 INSN(cmp, b080, f1c0, CF_ISA_A);
5983 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
5984 INSN(cmp, b000, f100, M68000);
5985 INSN(eor, b100, f100, M68000);
5986 INSN(cmpm, b108, f138, M68000);
5987 INSN(cmpa, b0c0, f0c0, M68000);
5988 INSN(eor, b180, f1c0, CF_ISA_A);
5989 BASE(and, c000, f000);
5990 INSN(exg_dd, c140, f1f8, M68000);
5991 INSN(exg_aa, c148, f1f8, M68000);
5992 INSN(exg_da, c188, f1f8, M68000);
5993 BASE(mulw, c0c0, f0c0);
5994 INSN(abcd_reg, c100, f1f8, M68000);
5995 INSN(abcd_mem, c108, f1f8, M68000);
5996 BASE(addsub, d000, f000);
5997 INSN(undef, d0c0, f0c0, CF_ISA_A);
5998 INSN(addx_reg, d180, f1f8, CF_ISA_A);
5999 INSN(addx_reg, d100, f138, M68000);
6000 INSN(addx_mem, d108, f138, M68000);
6001 INSN(adda, d1c0, f1c0, CF_ISA_A);
6002 INSN(adda, d0c0, f0c0, M68000);
6003 INSN(shift_im, e080, f0f0, CF_ISA_A);
6004 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
6005 INSN(shift8_im, e000, f0f0, M68000);
6006 INSN(shift16_im, e040, f0f0, M68000);
6007 INSN(shift_im, e080, f0f0, M68000);
6008 INSN(shift8_reg, e020, f0f0, M68000);
6009 INSN(shift16_reg, e060, f0f0, M68000);
6010 INSN(shift_reg, e0a0, f0f0, M68000);
6011 INSN(shift_mem, e0c0, fcc0, M68000);
6012 INSN(rotate_im, e090, f0f0, M68000);
6013 INSN(rotate8_im, e010, f0f0, M68000);
6014 INSN(rotate16_im, e050, f0f0, M68000);
6015 INSN(rotate_reg, e0b0, f0f0, M68000);
6016 INSN(rotate8_reg, e030, f0f0, M68000);
6017 INSN(rotate16_reg, e070, f0f0, M68000);
6018 INSN(rotate_mem, e4c0, fcc0, M68000);
6019 INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */
6020 INSN(bfext_reg, e9c0, fdf8, BITFIELD);
6021 INSN(bfins_mem, efc0, ffc0, BITFIELD);
6022 INSN(bfins_reg, efc0, fff8, BITFIELD);
6023 INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */
6024 INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
6025 INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
6026 INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
6027 INSN(bfop_mem, edc0, ffc0, BITFIELD); /* bfffo */
6028 INSN(bfop_reg, edc0, fff8, BITFIELD); /* bfffo */
6029 INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
6030 INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
6031 INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
6032 INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
6033 BASE(undef_fpu, f000, f000);
6034 INSN(fpu, f200, ffc0, CF_FPU);
6035 INSN(fbcc, f280, ffc0, CF_FPU);
6036 INSN(fpu, f200, ffc0, FPU);
6037 INSN(fscc, f240, ffc0, FPU);
6038 INSN(fbcc, f280, ff80, FPU);
6039 #if defined(CONFIG_SOFTMMU)
6040 INSN(frestore, f340, ffc0, CF_FPU);
6041 INSN(fsave, f300, ffc0, CF_FPU);
6042 INSN(frestore, f340, ffc0, FPU);
6043 INSN(fsave, f300, ffc0, FPU);
6044 INSN(intouch, f340, ffc0, CF_ISA_A);
6045 INSN(cpushl, f428, ff38, CF_ISA_A);
6046 INSN(cpush, f420, ff20, M68040);
6047 INSN(cinv, f400, ff20, M68040);
6048 INSN(pflush, f500, ffe0, M68040);
6049 INSN(ptest, f548, ffd8, M68040);
6050 INSN(wddata, fb00, ff00, CF_ISA_A);
6051 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
6052 #endif
6053 INSN(move16_mem, f600, ffe0, M68040);
6054 INSN(move16_reg, f620, fff8, M68040);
6055 #undef INSN
6056 }
6057
6058 /* ??? Some of this implementation is not exception safe. We should always
6059 write back the result to memory before setting the condition codes. */
6060 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
6061 {
6062 uint16_t insn = read_im16(env, s);
6063 opcode_table[insn](env, s, insn);
6064 do_writebacks(s);
6065 do_release(s);
6066 }
6067
6068 /* generate intermediate code for basic block 'tb'. */
6069 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
6070 {
6071 CPUM68KState *env = cs->env_ptr;
6072 DisasContext dc1, *dc = &dc1;
6073 target_ulong pc_start;
6074 int pc_offset;
6075 int num_insns;
6076 int max_insns;
6077
6078 /* generate intermediate code */
6079 pc_start = tb->pc;
6080
6081 dc->tb = tb;
6082
6083 dc->env = env;
6084 dc->is_jmp = DISAS_NEXT;
6085 dc->pc = pc_start;
6086 dc->cc_op = CC_OP_DYNAMIC;
6087 dc->cc_op_synced = 1;
6088 dc->singlestep_enabled = cs->singlestep_enabled;
6089 dc->done_mac = 0;
6090 dc->writeback_mask = 0;
6091 num_insns = 0;
6092 max_insns = tb_cflags(tb) & CF_COUNT_MASK;
6093 if (max_insns == 0) {
6094 max_insns = CF_COUNT_MASK;
6095 }
6096 if (max_insns > TCG_MAX_INSNS) {
6097 max_insns = TCG_MAX_INSNS;
6098 }
6099
6100 init_release_array(dc);
6101
6102 gen_tb_start(tb);
6103 do {
6104 pc_offset = dc->pc - pc_start;
6105 tcg_gen_insn_start(dc->pc, dc->cc_op);
6106 num_insns++;
6107
6108 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
6109 gen_exception(dc, dc->pc, EXCP_DEBUG);
6110 dc->is_jmp = DISAS_JUMP;
6111 /* The address covered by the breakpoint must be included in
6112 [tb->pc, tb->pc + tb->size) in order to for it to be
6113 properly cleared -- thus we increment the PC here so that
6114 the logic setting tb->size below does the right thing. */
6115 dc->pc += 2;
6116 break;
6117 }
6118
6119 if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
6120 gen_io_start();
6121 }
6122
6123 dc->insn_pc = dc->pc;
6124 disas_m68k_insn(env, dc);
6125 } while (!dc->is_jmp && !tcg_op_buf_full() &&
6126 !cs->singlestep_enabled &&
6127 !singlestep &&
6128 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
6129 num_insns < max_insns);
6130
6131 if (tb_cflags(tb) & CF_LAST_IO)
6132 gen_io_end();
6133 if (unlikely(cs->singlestep_enabled)) {
6134 /* Make sure the pc is updated, and raise a debug exception. */
6135 if (!dc->is_jmp) {
6136 update_cc_op(dc);
6137 tcg_gen_movi_i32(QREG_PC, dc->pc);
6138 }
6139 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
6140 } else {
6141 switch(dc->is_jmp) {
6142 case DISAS_NEXT:
6143 update_cc_op(dc);
6144 gen_jmp_tb(dc, 0, dc->pc);
6145 break;
6146 default:
6147 case DISAS_JUMP:
6148 case DISAS_UPDATE:
6149 update_cc_op(dc);
6150 /* indicate that the hash table must be used to find the next TB */
6151 tcg_gen_exit_tb(0);
6152 break;
6153 case DISAS_TB_JUMP:
6154 /* nothing more to generate */
6155 break;
6156 }
6157 }
6158 gen_tb_end(tb, num_insns);
6159
6160 #ifdef DEBUG_DISAS
6161 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
6162 && qemu_log_in_addr_range(pc_start)) {
6163 qemu_log_lock();
6164 qemu_log("----------------\n");
6165 qemu_log("IN: %s\n", lookup_symbol(pc_start));
6166 log_target_disas(cs, pc_start, dc->pc - pc_start);
6167 qemu_log("\n");
6168 qemu_log_unlock();
6169 }
6170 #endif
6171 tb->size = dc->pc - pc_start;
6172 tb->icount = num_insns;
6173 }
6174
6175 static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
6176 {
6177 floatx80 a = { .high = high, .low = low };
6178 union {
6179 float64 f64;
6180 double d;
6181 } u;
6182
6183 u.f64 = floatx80_to_float64(a, &env->fp_status);
6184 return u.d;
6185 }
6186
6187 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6188 int flags)
6189 {
6190 M68kCPU *cpu = M68K_CPU(cs);
6191 CPUM68KState *env = &cpu->env;
6192 int i;
6193 uint16_t sr;
6194 for (i = 0; i < 8; i++) {
6195 cpu_fprintf(f, "D%d = %08x A%d = %08x "
6196 "F%d = %04x %016"PRIx64" (%12g)\n",
6197 i, env->dregs[i], i, env->aregs[i],
6198 i, env->fregs[i].l.upper, env->fregs[i].l.lower,
6199 floatx80_to_double(env, env->fregs[i].l.upper,
6200 env->fregs[i].l.lower));
6201 }
6202 cpu_fprintf (f, "PC = %08x ", env->pc);
6203 sr = env->sr | cpu_m68k_get_ccr(env);
6204 cpu_fprintf(f, "SR = %04x T:%x I:%x %c%c %c%c%c%c%c\n",
6205 sr, (sr & SR_T) >> SR_T_SHIFT, (sr & SR_I) >> SR_I_SHIFT,
6206 (sr & SR_S) ? 'S' : 'U', (sr & SR_M) ? '%' : 'I',
6207 (sr & CCF_X) ? 'X' : '-', (sr & CCF_N) ? 'N' : '-',
6208 (sr & CCF_Z) ? 'Z' : '-', (sr & CCF_V) ? 'V' : '-',
6209 (sr & CCF_C) ? 'C' : '-');
6210 cpu_fprintf(f, "FPSR = %08x %c%c%c%c ", env->fpsr,
6211 (env->fpsr & FPSR_CC_A) ? 'A' : '-',
6212 (env->fpsr & FPSR_CC_I) ? 'I' : '-',
6213 (env->fpsr & FPSR_CC_Z) ? 'Z' : '-',
6214 (env->fpsr & FPSR_CC_N) ? 'N' : '-');
6215 cpu_fprintf(f, "\n "
6216 "FPCR = %04x ", env->fpcr);
6217 switch (env->fpcr & FPCR_PREC_MASK) {
6218 case FPCR_PREC_X:
6219 cpu_fprintf(f, "X ");
6220 break;
6221 case FPCR_PREC_S:
6222 cpu_fprintf(f, "S ");
6223 break;
6224 case FPCR_PREC_D:
6225 cpu_fprintf(f, "D ");
6226 break;
6227 }
6228 switch (env->fpcr & FPCR_RND_MASK) {
6229 case FPCR_RND_N:
6230 cpu_fprintf(f, "RN ");
6231 break;
6232 case FPCR_RND_Z:
6233 cpu_fprintf(f, "RZ ");
6234 break;
6235 case FPCR_RND_M:
6236 cpu_fprintf(f, "RM ");
6237 break;
6238 case FPCR_RND_P:
6239 cpu_fprintf(f, "RP ");
6240 break;
6241 }
6242 cpu_fprintf(f, "\n");
6243 #ifdef CONFIG_SOFTMMU
6244 cpu_fprintf(f, "%sA7(MSP) = %08x %sA7(USP) = %08x %sA7(ISP) = %08x\n",
6245 env->current_sp == M68K_SSP ? "->" : " ", env->sp[M68K_SSP],
6246 env->current_sp == M68K_USP ? "->" : " ", env->sp[M68K_USP],
6247 env->current_sp == M68K_ISP ? "->" : " ", env->sp[M68K_ISP]);
6248 cpu_fprintf(f, "VBR = 0x%08x\n", env->vbr);
6249 cpu_fprintf(f, "SFC = %x DFC %x\n", env->sfc, env->dfc);
6250 cpu_fprintf(f, "SSW %08x TCR %08x URP %08x SRP %08x\n",
6251 env->mmu.ssw, env->mmu.tcr, env->mmu.urp, env->mmu.srp);
6252 cpu_fprintf(f, "DTTR0/1: %08x/%08x ITTR0/1: %08x/%08x\n",
6253 env->mmu.ttr[M68K_DTTR0], env->mmu.ttr[M68K_DTTR1],
6254 env->mmu.ttr[M68K_ITTR0], env->mmu.ttr[M68K_ITTR1]);
6255 cpu_fprintf(f, "MMUSR %08x, fault at %08x\n",
6256 env->mmu.mmusr, env->mmu.ar);
6257 #endif
6258 }
6259
6260 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
6261 target_ulong *data)
6262 {
6263 int cc_op = data[1];
6264 env->pc = data[0];
6265 if (cc_op != CC_OP_DYNAMIC) {
6266 env->cc_op = cc_op;
6267 }
6268 }
AR7 emulation for QEMU