softmmu/qtest.c

   1 /*
   2  * Test Server
   3  *
   4  * Copyright IBM, Corp. 2011
   5  *
   6  * Authors:
   7  *  Anthony Liguori   <aliguori@us.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  *
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qapi/error.h"
  16 #include "cpu.h"
  17 #include "sysemu/qtest.h"
  18 #include "sysemu/runstate.h"
  19 #include "chardev/char-fe.h"
  20 #include "exec/ioport.h"
  21 #include "exec/memory.h"
  22 #include "hw/irq.h"
  23 #include "sysemu/accel.h"
  24 #include "sysemu/cpu-timers.h"
  25 #include "qemu/config-file.h"
  26 #include "qemu/option.h"
  27 #include "qemu/error-report.h"
  28 #include "qemu/module.h"
  29 #include "qemu/cutils.h"
  30 #include CONFIG_DEVICES
  31 #ifdef CONFIG_PSERIES
  32 #include "hw/ppc/spapr_rtas.h"
  33 #endif
  34
  35 #define MAX_IRQ 256
  36
  37 bool qtest_allowed;
  38
  39 static DeviceState *irq_intercept_dev;
  40 static FILE *qtest_log_fp;
  41 static CharBackend qtest_chr;
  42 static GString *inbuf;
  43 static int irq_levels[MAX_IRQ];
  44 static qemu_timeval start_time;
  45 static bool qtest_opened;
  46 static void (*qtest_server_send)(void*, const char*);
  47 static void *qtest_server_send_opaque;
  48
  49 #define FMT_timeval "%ld.%06ld"
  50
  51 /**
  52  * QTest Protocol
  53  *
  54  * Line based protocol, request/response based.  Server can send async messages
  55  * so clients should always handle many async messages before the response
  56  * comes in.
  57  *
  58  * Valid requests
  59  *
  60  * Clock management:
  61  *
  62  * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL.  qtest commands
  63  * let you adjust the value of the clock (monotonically).  All the commands
  64  * return the current value of the clock in nanoseconds.
  65  *
  66  *  > clock_step
  67  *  < OK VALUE
  68  *
  69  *     Advance the clock to the next deadline.  Useful when waiting for
  70  *     asynchronous events.
  71  *
  72  *  > clock_step NS
  73  *  < OK VALUE
  74  *
  75  *     Advance the clock by NS nanoseconds.
  76  *
  77  *  > clock_set NS
  78  *  < OK VALUE
  79  *
  80  *     Advance the clock to NS nanoseconds (do nothing if it's already past).
  81  *
  82  * PIO and memory access:
  83  *
  84  *  > outb ADDR VALUE
  85  *  < OK
  86  *
  87  *  > outw ADDR VALUE
  88  *  < OK
  89  *
  90  *  > outl ADDR VALUE
  91  *  < OK
  92  *
  93  *  > inb ADDR
  94  *  < OK VALUE
  95  *
  96  *  > inw ADDR
  97  *  < OK VALUE
  98  *
  99  *  > inl ADDR
 100  *  < OK VALUE
 101  *
 102  *  > writeb ADDR VALUE
 103  *  < OK
 104  *
 105  *  > writew ADDR VALUE
 106  *  < OK
 107  *
 108  *  > writel ADDR VALUE
 109  *  < OK
 110  *
 111  *  > writeq ADDR VALUE
 112  *  < OK
 113  *
 114  *  > readb ADDR
 115  *  < OK VALUE
 116  *
 117  *  > readw ADDR
 118  *  < OK VALUE
 119  *
 120  *  > readl ADDR
 121  *  < OK VALUE
 122  *
 123  *  > readq ADDR
 124  *  < OK VALUE
 125  *
 126  *  > read ADDR SIZE
 127  *  < OK DATA
 128  *
 129  *  > write ADDR SIZE DATA
 130  *  < OK
 131  *
 132  *  > b64read ADDR SIZE
 133  *  < OK B64_DATA
 134  *
 135  *  > b64write ADDR SIZE B64_DATA
 136  *  < OK
 137  *
 138  *  > memset ADDR SIZE VALUE
 139  *  < OK
 140  *
 141  * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
 142  * For 'memset' a zero size is permitted and does nothing.
 143  *
 144  * DATA is an arbitrarily long hex number prefixed with '0x'.  If it's smaller
 145  * than the expected size, the value will be zero filled at the end of the data
 146  * sequence.
 147  *
 148  * B64_DATA is an arbitrarily long base64 encoded string.
 149  * If the sizes do not match, the data will be truncated.
 150  *
 151  * IRQ management:
 152  *
 153  *  > irq_intercept_in QOM-PATH
 154  *  < OK
 155  *
 156  *  > irq_intercept_out QOM-PATH
 157  *  < OK
 158  *
 159  * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
 160  * QOM-PATH.  When the pin is triggered, one of the following async messages
 161  * will be printed to the qtest stream:
 162  *
 163  *  IRQ raise NUM
 164  *  IRQ lower NUM
 165  *
 166  * where NUM is an IRQ number.  For the PC, interrupts can be intercepted
 167  * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
 168  * NUM=0 even though it is remapped to GSI 2).
 169  *
 170  * Setting interrupt level:
 171  *
 172  *  > set_irq_in QOM-PATH NAME NUM LEVEL
 173  *  < OK
 174  *
 175  *  where NAME is the name of the irq/gpio list, NUM is an IRQ number and
 176  *  LEVEL is an signed integer IRQ level.
 177  *
 178  * Forcibly set the given interrupt pin to the given level.
 179  *
 180  */
 181
 182 static int hex2nib(char ch)
 183 {
 184     if (ch >= '0' && ch <= '9') {
 185         return ch - '0';
 186     } else if (ch >= 'a' && ch <= 'f') {
 187         return 10 + (ch - 'a');
 188     } else if (ch >= 'A' && ch <= 'F') {
 189         return 10 + (ch - 'A');
 190     } else {
 191         return -1;
 192     }
 193 }
 194
 195 static void qtest_get_time(qemu_timeval *tv)
 196 {
 197     qemu_gettimeofday(tv);
 198     tv->tv_sec -= start_time.tv_sec;
 199     tv->tv_usec -= start_time.tv_usec;
 200     if (tv->tv_usec < 0) {
 201         tv->tv_usec += 1000000;
 202         tv->tv_sec -= 1;
 203     }
 204 }
 205
 206 static void qtest_send_prefix(CharBackend *chr)
 207 {
 208     qemu_timeval tv;
 209
 210     if (!qtest_log_fp || !qtest_opened) {
 211         return;
 212     }
 213
 214     qtest_get_time(&tv);
 215     fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
 216             (long) tv.tv_sec, (long) tv.tv_usec);
 217 }
 218
 219 static void GCC_FMT_ATTR(1, 2) qtest_log_send(const char *fmt, ...)
 220 {
 221     va_list ap;
 222
 223     if (!qtest_log_fp || !qtest_opened) {
 224         return;
 225     }
 226
 227     qtest_send_prefix(NULL);
 228
 229     va_start(ap, fmt);
 230     vfprintf(qtest_log_fp, fmt, ap);
 231     va_end(ap);
 232 }
 233
 234 static void qtest_server_char_be_send(void *opaque, const char *str)
 235 {
 236     size_t len = strlen(str);
 237     CharBackend* chr = (CharBackend *)opaque;
 238     qemu_chr_fe_write_all(chr, (uint8_t *)str, len);
 239     if (qtest_log_fp && qtest_opened) {
 240         fprintf(qtest_log_fp, "%s", str);
 241     }
 242 }
 243
 244 static void qtest_send(CharBackend *chr, const char *str)
 245 {
 246     qtest_server_send(qtest_server_send_opaque, str);
 247 }
 248
 249 static void GCC_FMT_ATTR(2, 3) qtest_sendf(CharBackend *chr,
 250                                            const char *fmt, ...)
 251 {
 252     va_list ap;
 253     gchar *buffer;
 254
 255     va_start(ap, fmt);
 256     buffer = g_strdup_vprintf(fmt, ap);
 257     qtest_send(chr, buffer);
 258     g_free(buffer);
 259     va_end(ap);
 260 }
 261
 262 static void qtest_irq_handler(void *opaque, int n, int level)
 263 {
 264     qemu_irq old_irq = *(qemu_irq *)opaque;
 265     qemu_set_irq(old_irq, level);
 266
 267     if (irq_levels[n] != level) {
 268         CharBackend *chr = &qtest_chr;
 269         irq_levels[n] = level;
 270         qtest_send_prefix(chr);
 271         qtest_sendf(chr, "IRQ %s %d\n",
 272                     level ? "raise" : "lower", n);
 273     }
 274 }
 275
 276 static int64_t qtest_clock_counter;
 277
 278 int64_t qtest_get_virtual_clock(void)
 279 {
 280     return qatomic_read_i64(&qtest_clock_counter);
 281 }
 282
 283 static void qtest_set_virtual_clock(int64_t count)
 284 {
 285     qatomic_set_i64(&qtest_clock_counter, count);
 286 }
 287
 288 static void qtest_clock_warp(int64_t dest)
 289 {
 290     int64_t clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 291     AioContext *aio_context;
 292     assert(qtest_enabled());
 293     aio_context = qemu_get_aio_context();
 294     while (clock < dest) {
 295         int64_t deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
 296                                                       QEMU_TIMER_ATTR_ALL);
 297         int64_t warp = qemu_soonest_timeout(dest - clock, deadline);
 298
 299         qtest_set_virtual_clock(qtest_get_virtual_clock() + warp);
 300
 301         qemu_clock_run_timers(QEMU_CLOCK_VIRTUAL);
 302         timerlist_run_timers(aio_context->tlg.tl[QEMU_CLOCK_VIRTUAL]);
 303         clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 304     }
 305     qemu_clock_notify(QEMU_CLOCK_VIRTUAL);
 306 }
 307
 308 static void qtest_process_command(CharBackend *chr, gchar **words)
 309 {
 310     const gchar *command;
 311
 312     g_assert(words);
 313
 314     command = words[0];
 315
 316     if (qtest_log_fp) {
 317         qemu_timeval tv;
 318         int i;
 319
 320         qtest_get_time(&tv);
 321         fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
 322                 (long) tv.tv_sec, (long) tv.tv_usec);
 323         for (i = 0; words[i]; i++) {
 324             fprintf(qtest_log_fp, " %s", words[i]);
 325         }
 326         fprintf(qtest_log_fp, "\n");
 327     }
 328
 329     g_assert(command);
 330     if (strcmp(words[0], "irq_intercept_out") == 0
 331         || strcmp(words[0], "irq_intercept_in") == 0) {
 332         DeviceState *dev;
 333         NamedGPIOList *ngl;
 334
 335         g_assert(words[1]);
 336         dev = DEVICE(object_resolve_path(words[1], NULL));
 337         if (!dev) {
 338             qtest_send_prefix(chr);
 339             qtest_send(chr, "FAIL Unknown device\n");
 340             return;
 341         }
 342
 343         if (irq_intercept_dev) {
 344             qtest_send_prefix(chr);
 345             if (irq_intercept_dev != dev) {
 346                 qtest_send(chr, "FAIL IRQ intercept already enabled\n");
 347             } else {
 348                 qtest_send(chr, "OK\n");
 349             }
 350             return;
 351         }
 352
 353         QLIST_FOREACH(ngl, &dev->gpios, node) {
 354             /* We don't support intercept of named GPIOs yet */
 355             if (ngl->name) {
 356                 continue;
 357             }
 358             if (words[0][14] == 'o') {
 359                 int i;
 360                 for (i = 0; i < ngl->num_out; ++i) {
 361                     qemu_irq *disconnected = g_new0(qemu_irq, 1);
 362                     qemu_irq icpt = qemu_allocate_irq(qtest_irq_handler,
 363                                                       disconnected, i);
 364
 365                     *disconnected = qdev_intercept_gpio_out(dev, icpt,
 366                                                             ngl->name, i);
 367                 }
 368             } else {
 369                 qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
 370                                       ngl->num_in);
 371             }
 372         }
 373         irq_intercept_dev = dev;
 374         qtest_send_prefix(chr);
 375         qtest_send(chr, "OK\n");
 376     } else if (strcmp(words[0], "set_irq_in") == 0) {
 377         DeviceState *dev;
 378         qemu_irq irq;
 379         char *name;
 380         int ret;
 381         int num;
 382         int level;
 383
 384         g_assert(words[1] && words[2] && words[3] && words[4]);
 385
 386         dev = DEVICE(object_resolve_path(words[1], NULL));
 387         if (!dev) {
 388             qtest_send_prefix(chr);
 389             qtest_send(chr, "FAIL Unknown device\n");
 390             return;
 391         }
 392
 393         if (strcmp(words[2], "unnamed-gpio-in") == 0) {
 394             name = NULL;
 395         } else {
 396             name = words[2];
 397         }
 398
 399         ret = qemu_strtoi(words[3], NULL, 0, &num);
 400         g_assert(!ret);
 401         ret = qemu_strtoi(words[4], NULL, 0, &level);
 402         g_assert(!ret);
 403
 404         irq = qdev_get_gpio_in_named(dev, name, num);
 405
 406         qemu_set_irq(irq, level);
 407         qtest_send_prefix(chr);
 408         qtest_send(chr, "OK\n");
 409     } else if (strcmp(words[0], "outb") == 0 ||
 410                strcmp(words[0], "outw") == 0 ||
 411                strcmp(words[0], "outl") == 0) {
 412         unsigned long addr;
 413         unsigned long value;
 414         int ret;
 415
 416         g_assert(words[1] && words[2]);
 417         ret = qemu_strtoul(words[1], NULL, 0, &addr);
 418         g_assert(ret == 0);
 419         ret = qemu_strtoul(words[2], NULL, 0, &value);
 420         g_assert(ret == 0);
 421         g_assert(addr <= 0xffff);
 422
 423         if (words[0][3] == 'b') {
 424             cpu_outb(addr, value);
 425         } else if (words[0][3] == 'w') {
 426             cpu_outw(addr, value);
 427         } else if (words[0][3] == 'l') {
 428             cpu_outl(addr, value);
 429         }
 430         qtest_send_prefix(chr);
 431         qtest_send(chr, "OK\n");
 432     } else if (strcmp(words[0], "inb") == 0 ||
 433         strcmp(words[0], "inw") == 0 ||
 434         strcmp(words[0], "inl") == 0) {
 435         unsigned long addr;
 436         uint32_t value = -1U;
 437         int ret;
 438
 439         g_assert(words[1]);
 440         ret = qemu_strtoul(words[1], NULL, 0, &addr);
 441         g_assert(ret == 0);
 442         g_assert(addr <= 0xffff);
 443
 444         if (words[0][2] == 'b') {
 445             value = cpu_inb(addr);
 446         } else if (words[0][2] == 'w') {
 447             value = cpu_inw(addr);
 448         } else if (words[0][2] == 'l') {
 449             value = cpu_inl(addr);
 450         }
 451         qtest_send_prefix(chr);
 452         qtest_sendf(chr, "OK 0x%04x\n", value);
 453     } else if (strcmp(words[0], "writeb") == 0 ||
 454                strcmp(words[0], "writew") == 0 ||
 455                strcmp(words[0], "writel") == 0 ||
 456                strcmp(words[0], "writeq") == 0) {
 457         uint64_t addr;
 458         uint64_t value;
 459         int ret;
 460
 461         g_assert(words[1] && words[2]);
 462         ret = qemu_strtou64(words[1], NULL, 0, &addr);
 463         g_assert(ret == 0);
 464         ret = qemu_strtou64(words[2], NULL, 0, &value);
 465         g_assert(ret == 0);
 466
 467         if (words[0][5] == 'b') {
 468             uint8_t data = value;
 469             address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
 470                                 &data, 1);
 471         } else if (words[0][5] == 'w') {
 472             uint16_t data = value;
 473             tswap16s(&data);
 474             address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
 475                                 &data, 2);
 476         } else if (words[0][5] == 'l') {
 477             uint32_t data = value;
 478             tswap32s(&data);
 479             address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
 480                                 &data, 4);
 481         } else if (words[0][5] == 'q') {
 482             uint64_t data = value;
 483             tswap64s(&data);
 484             address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
 485                                 &data, 8);
 486         }
 487         qtest_send_prefix(chr);
 488         qtest_send(chr, "OK\n");
 489     } else if (strcmp(words[0], "readb") == 0 ||
 490                strcmp(words[0], "readw") == 0 ||
 491                strcmp(words[0], "readl") == 0 ||
 492                strcmp(words[0], "readq") == 0) {
 493         uint64_t addr;
 494         uint64_t value = UINT64_C(-1);
 495         int ret;
 496
 497         g_assert(words[1]);
 498         ret = qemu_strtou64(words[1], NULL, 0, &addr);
 499         g_assert(ret == 0);
 500
 501         if (words[0][4] == 'b') {
 502             uint8_t data;
 503             address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
 504                                &data, 1);
 505             value = data;
 506         } else if (words[0][4] == 'w') {
 507             uint16_t data;
 508             address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
 509                                &data, 2);
 510             value = tswap16(data);
 511         } else if (words[0][4] == 'l') {
 512             uint32_t data;
 513             address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
 514                                &data, 4);
 515             value = tswap32(data);
 516         } else if (words[0][4] == 'q') {
 517             address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
 518                                &value, 8);
 519             tswap64s(&value);
 520         }
 521         qtest_send_prefix(chr);
 522         qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value);
 523     } else if (strcmp(words[0], "read") == 0) {
 524         uint64_t addr, len, i;
 525         uint8_t *data;
 526         char *enc;
 527         int ret;
 528
 529         g_assert(words[1] && words[2]);
 530         ret = qemu_strtou64(words[1], NULL, 0, &addr);
 531         g_assert(ret == 0);
 532         ret = qemu_strtou64(words[2], NULL, 0, &len);
 533         g_assert(ret == 0);
 534         /* We'd send garbage to libqtest if len is 0 */
 535         g_assert(len);
 536
 537         data = g_malloc(len);
 538         address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
 539                            len);
 540
 541         enc = g_malloc(2 * len + 1);
 542         for (i = 0; i < len; i++) {
 543             sprintf(&enc[i * 2], "%02x", data[i]);
 544         }
 545
 546         qtest_send_prefix(chr);
 547         qtest_sendf(chr, "OK 0x%s\n", enc);
 548
 549         g_free(data);
 550         g_free(enc);
 551     } else if (strcmp(words[0], "b64read") == 0) {
 552         uint64_t addr, len;
 553         uint8_t *data;
 554         gchar *b64_data;
 555         int ret;
 556
 557         g_assert(words[1] && words[2]);
 558         ret = qemu_strtou64(words[1], NULL, 0, &addr);
 559         g_assert(ret == 0);
 560         ret = qemu_strtou64(words[2], NULL, 0, &len);
 561         g_assert(ret == 0);
 562
 563         data = g_malloc(len);
 564         address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
 565                            len);
 566         b64_data = g_base64_encode(data, len);
 567         qtest_send_prefix(chr);
 568         qtest_sendf(chr, "OK %s\n", b64_data);
 569
 570         g_free(data);
 571         g_free(b64_data);
 572     } else if (strcmp(words[0], "write") == 0) {
 573         uint64_t addr, len, i;
 574         uint8_t *data;
 575         size_t data_len;
 576         int ret;
 577
 578         g_assert(words[1] && words[2] && words[3]);
 579         ret = qemu_strtou64(words[1], NULL, 0, &addr);
 580         g_assert(ret == 0);
 581         ret = qemu_strtou64(words[2], NULL, 0, &len);
 582         g_assert(ret == 0);
 583
 584         data_len = strlen(words[3]);
 585         if (data_len < 3) {
 586             qtest_send(chr, "ERR invalid argument size\n");
 587             return;
 588         }
 589
 590         data = g_malloc(len);
 591         for (i = 0; i < len; i++) {
 592             if ((i * 2 + 4) <= data_len) {
 593                 data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
 594                 data[i] |= hex2nib(words[3][i * 2 + 3]);
 595             } else {
 596                 data[i] = 0;
 597             }
 598         }
 599         address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
 600                             len);
 601         g_free(data);
 602
 603         qtest_send_prefix(chr);
 604         qtest_send(chr, "OK\n");
 605     } else if (strcmp(words[0], "memset") == 0) {
 606         uint64_t addr, len;
 607         uint8_t *data;
 608         unsigned long pattern;
 609         int ret;
 610
 611         g_assert(words[1] && words[2] && words[3]);
 612         ret = qemu_strtou64(words[1], NULL, 0, &addr);
 613         g_assert(ret == 0);
 614         ret = qemu_strtou64(words[2], NULL, 0, &len);
 615         g_assert(ret == 0);
 616         ret = qemu_strtoul(words[3], NULL, 0, &pattern);
 617         g_assert(ret == 0);
 618
 619         if (len) {
 620             data = g_malloc(len);
 621             memset(data, pattern, len);
 622             address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED,
 623                                 data, len);
 624             g_free(data);
 625         }
 626
 627         qtest_send_prefix(chr);
 628         qtest_send(chr, "OK\n");
 629     }  else if (strcmp(words[0], "b64write") == 0) {
 630         uint64_t addr, len;
 631         uint8_t *data;
 632         size_t data_len;
 633         gsize out_len;
 634         int ret;
 635
 636         g_assert(words[1] && words[2] && words[3]);
 637         ret = qemu_strtou64(words[1], NULL, 0, &addr);
 638         g_assert(ret == 0);
 639         ret = qemu_strtou64(words[2], NULL, 0, &len);
 640         g_assert(ret == 0);
 641
 642         data_len = strlen(words[3]);
 643         if (data_len < 3) {
 644             qtest_send(chr, "ERR invalid argument size\n");
 645             return;
 646         }
 647
 648         data = g_base64_decode_inplace(words[3], &out_len);
 649         if (out_len != len) {
 650             qtest_log_send("b64write: data length mismatch (told %"PRIu64", "
 651                            "found %zu)\n",
 652                            len, out_len);
 653             out_len = MIN(out_len, len);
 654         }
 655
 656         address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data,
 657                             len);
 658
 659         qtest_send_prefix(chr);
 660         qtest_send(chr, "OK\n");
 661     } else if (strcmp(words[0], "endianness") == 0) {
 662         qtest_send_prefix(chr);
 663 #if defined(TARGET_WORDS_BIGENDIAN)
 664         qtest_sendf(chr, "OK big\n");
 665 #else
 666         qtest_sendf(chr, "OK little\n");
 667 #endif
 668 #ifdef CONFIG_PSERIES
 669     } else if (strcmp(words[0], "rtas") == 0) {
 670         uint64_t res, args, ret;
 671         unsigned long nargs, nret;
 672         int rc;
 673
 674         rc = qemu_strtoul(words[2], NULL, 0, &nargs);
 675         g_assert(rc == 0);
 676         rc = qemu_strtou64(words[3], NULL, 0, &args);
 677         g_assert(rc == 0);
 678         rc = qemu_strtoul(words[4], NULL, 0, &nret);
 679         g_assert(rc == 0);
 680         rc = qemu_strtou64(words[5], NULL, 0, &ret);
 681         g_assert(rc == 0);
 682         res = qtest_rtas_call(words[1], nargs, args, nret, ret);
 683
 684         qtest_send_prefix(chr);
 685         qtest_sendf(chr, "OK %"PRIu64"\n", res);
 686 #endif
 687     } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
 688         int64_t ns;
 689
 690         if (words[1]) {
 691             int ret = qemu_strtoi64(words[1], NULL, 0, &ns);
 692             g_assert(ret == 0);
 693         } else {
 694             ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL,
 695                                             QEMU_TIMER_ATTR_ALL);
 696         }
 697         qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
 698         qtest_send_prefix(chr);
 699         qtest_sendf(chr, "OK %"PRIi64"\n",
 700                     (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 701     } else if (strcmp(words[0], "module_load") == 0) {
 702         g_assert(words[1] && words[2]);
 703
 704         qtest_send_prefix(chr);
 705         if (module_load_one(words[1], words[2])) {
 706             qtest_sendf(chr, "OK\n");
 707         } else {
 708             qtest_sendf(chr, "FAIL\n");
 709         }
 710     } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
 711         int64_t ns;
 712         int ret;
 713
 714         g_assert(words[1]);
 715         ret = qemu_strtoi64(words[1], NULL, 0, &ns);
 716         g_assert(ret == 0);
 717         qtest_clock_warp(ns);
 718         qtest_send_prefix(chr);
 719         qtest_sendf(chr, "OK %"PRIi64"\n",
 720                     (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 721     } else {
 722         qtest_send_prefix(chr);
 723         qtest_sendf(chr, "FAIL Unknown command '%s'\n", words[0]);
 724     }
 725 }
 726
 727 static void qtest_process_inbuf(CharBackend *chr, GString *inbuf)
 728 {
 729     char *end;
 730
 731     while ((end = strchr(inbuf->str, '\n')) != NULL) {
 732         size_t offset;
 733         GString *cmd;
 734         gchar **words;
 735
 736         offset = end - inbuf->str;
 737
 738         cmd = g_string_new_len(inbuf->str, offset);
 739         g_string_erase(inbuf, 0, offset + 1);
 740
 741         words = g_strsplit(cmd->str, " ", 0);
 742         qtest_process_command(chr, words);
 743         g_strfreev(words);
 744
 745         g_string_free(cmd, TRUE);
 746     }
 747 }
 748
 749 static void qtest_read(void *opaque, const uint8_t *buf, int size)
 750 {
 751     CharBackend *chr = opaque;
 752
 753     g_string_append_len(inbuf, (const gchar *)buf, size);
 754     qtest_process_inbuf(chr, inbuf);
 755 }
 756
 757 static int qtest_can_read(void *opaque)
 758 {
 759     return 1024;
 760 }
 761
 762 static void qtest_event(void *opaque, QEMUChrEvent event)
 763 {
 764     int i;
 765
 766     switch (event) {
 767     case CHR_EVENT_OPENED:
 768         /*
 769          * We used to call qemu_system_reset() here, hoping we could
 770          * use the same process for multiple tests that way.  Never
 771          * used.  Injects an extra reset even when it's not used, and
 772          * that can mess up tests, e.g. -boot once.
 773          */
 774         for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
 775             irq_levels[i] = 0;
 776         }
 777         qemu_gettimeofday(&start_time);
 778         qtest_opened = true;
 779         if (qtest_log_fp) {
 780             fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
 781                     (long) start_time.tv_sec, (long) start_time.tv_usec);
 782         }
 783         break;
 784     case CHR_EVENT_CLOSED:
 785         qtest_opened = false;
 786         if (qtest_log_fp) {
 787             qemu_timeval tv;
 788             qtest_get_time(&tv);
 789             fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
 790                     (long) tv.tv_sec, (long) tv.tv_usec);
 791         }
 792         break;
 793     default:
 794         break;
 795     }
 796 }
 797 void qtest_server_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
 798 {
 799     Chardev *chr;
 800
 801     chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
 802
 803     if (chr == NULL) {
 804         error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
 805                    qtest_chrdev);
 806         return;
 807     }
 808
 809     if (qtest_log) {
 810         if (strcmp(qtest_log, "none") != 0) {
 811             qtest_log_fp = fopen(qtest_log, "w+");
 812         }
 813     } else {
 814         qtest_log_fp = stderr;
 815     }
 816
 817     qemu_chr_fe_init(&qtest_chr, chr, errp);
 818     qemu_chr_fe_set_handlers(&qtest_chr, qtest_can_read, qtest_read,
 819                              qtest_event, NULL, &qtest_chr, NULL, true);
 820     qemu_chr_fe_set_echo(&qtest_chr, true);
 821
 822     inbuf = g_string_new("");
 823
 824     if (!qtest_server_send) {
 825         qtest_server_set_send_handler(qtest_server_char_be_send, &qtest_chr);
 826     }
 827 }
 828
 829 void qtest_server_set_send_handler(void (*send)(void*, const char*),
 830                                    void *opaque)
 831 {
 832     qtest_server_send = send;
 833     qtest_server_send_opaque = opaque;
 834 }
 835
 836 bool qtest_driver(void)
 837 {
 838     return qtest_chr.chr != NULL;
 839 }
 840
 841 void qtest_server_inproc_recv(void *dummy, const char *buf)
 842 {
 843     static GString *gstr;
 844     if (!gstr) {
 845         gstr = g_string_new(NULL);
 846     }
 847     g_string_append(gstr, buf);
 848     if (gstr->str[gstr->len - 1] == '\n') {
 849         qtest_process_inbuf(NULL, gstr);
 850         g_string_truncate(gstr, 0);
 851     }
 852 }