include/hw/char/imx_serial.h

   1 /*
   2  * Device model for i.MX UART
   3  *
   4  * Copyright (c) 2008 OKL
   5  * Originally Written by Hans Jiang
   6  * Copyright (c) 2011 NICTA Pty Ltd.
   7  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef IMX_SERIAL_H
  19 #define IMX_SERIAL_H
  20
  21 #include "hw/sysbus.h"
  22 #include "chardev/char-fe.h"
  23 #include "qom/object.h"
  24
  25 #define TYPE_IMX_SERIAL "imx.serial"
  26 OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
  27
  28 #define URXD_CHARRDY    (1<<15)   /* character read is valid */
  29 #define URXD_ERR        (1<<14)   /* Character has error */
  30 #define URXD_FRMERR     (1<<12)   /* Character has frame error */
  31 #define URXD_BRK        (1<<11)   /* Break received */
  32
  33 #define USR1_PARTYER    (1<<15)   /* Parity Error */
  34 #define USR1_RTSS       (1<<14)   /* RTS pin status */
  35 #define USR1_TRDY       (1<<13)   /* Tx ready */
  36 #define USR1_RTSD       (1<<12)   /* RTS delta: pin changed state */
  37 #define USR1_ESCF       (1<<11)   /* Escape sequence interrupt */
  38 #define USR1_FRAMERR    (1<<10)   /* Framing error  */
  39 #define USR1_RRDY       (1<<9)    /* receiver ready */
  40 #define USR1_AGTIM      (1<<8)    /* Aging timer interrupt */
  41 #define USR1_DTRD       (1<<7)    /* DTR changed */
  42 #define USR1_RXDS       (1<<6)    /* Receiver is idle */
  43 #define USR1_AIRINT     (1<<5)    /* Aysnch IR interrupt */
  44 #define USR1_AWAKE      (1<<4)    /* Falling edge detected on RXd pin */
  45
  46 #define USR2_ADET       (1<<15)   /* Autobaud complete */
  47 #define USR2_TXFE       (1<<14)   /* Transmit FIFO empty */
  48 #define USR2_DTRF       (1<<13)   /* DTR/DSR transition */
  49 #define USR2_IDLE       (1<<12)   /* UART has been idle for too long */
  50 #define USR2_ACST       (1<<11)   /* Autobaud counter stopped */
  51 #define USR2_RIDELT     (1<<10)   /* Ring Indicator delta */
  52 #define USR2_RIIN       (1<<9)    /* Ring Indicator Input */
  53 #define USR2_IRINT      (1<<8)    /* Serial Infrared Interrupt */
  54 #define USR2_WAKE       (1<<7)    /* Start bit detected */
  55 #define USR2_DCDDELT    (1<<6)    /* Data Carrier Detect delta */
  56 #define USR2_DCDIN      (1<<5)    /* Data Carrier Detect Input */
  57 #define USR2_RTSF       (1<<4)    /* RTS transition */
  58 #define USR2_TXDC       (1<<3)    /* Transmission complete */
  59 #define USR2_BRCD       (1<<2)    /* Break condition detected */
  60 #define USR2_ORE        (1<<1)    /* Overrun error */
  61 #define USR2_RDR        (1<<0)    /* Receive data ready */
  62
  63 #define UCR1_TRDYEN     (1<<13)   /* Tx Ready Interrupt Enable */
  64 #define UCR1_RRDYEN     (1<<9)    /* Rx Ready Interrupt Enable */
  65 #define UCR1_TXMPTYEN   (1<<6)    /* Tx Empty Interrupt Enable */
  66 #define UCR1_UARTEN     (1<<0)    /* UART Enable */
  67
  68 #define UCR2_TXEN       (1<<2)    /* Transmitter enable */
  69 #define UCR2_RXEN       (1<<1)    /* Receiver enable */
  70 #define UCR2_SRST       (1<<0)    /* Reset complete */
  71
  72 #define UCR4_DREN       BIT(0)    /* Receive Data Ready interrupt enable */
  73 #define UCR4_TCEN       BIT(3)    /* TX complete interrupt enable */
  74
  75 #define UTS1_TXEMPTY    (1<<6)
  76 #define UTS1_RXEMPTY    (1<<5)
  77 #define UTS1_TXFULL     (1<<4)
  78 #define UTS1_RXFULL     (1<<3)
  79
  80 struct IMXSerialState {
  81     /*< private >*/
  82     SysBusDevice parent_obj;
  83
  84     /*< public >*/
  85     MemoryRegion iomem;
  86     int32_t readbuff;
  87
  88     uint32_t usr1;
  89     uint32_t usr2;
  90     uint32_t ucr1;
  91     uint32_t ucr2;
  92     uint32_t uts1;
  93
  94     /*
  95      * The registers below are implemented just so that the
  96      * guest OS sees what it has written
  97      */
  98     uint32_t onems;
  99     uint32_t ufcr;
 100     uint32_t ubmr;
 101     uint32_t ubrc;
 102     uint32_t ucr3;
 103     uint32_t ucr4;
 104
 105     qemu_irq irq;
 106     CharBackend chr;
 107 };
 108
 109 #endif