hw/arm/xlnx-versal-virt.c

   1 /*
   2  * Xilinx Versal Virtual board.
   3  *
   4  * Copyright (c) 2018 Xilinx Inc.
   5  * Written by Edgar E. Iglesias
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 or
   9  * (at your option) any later version.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qemu/log.h"
  14 #include "qemu/error-report.h"
  15 #include "qapi/error.h"
  16 #include "sysemu/device_tree.h"
  17 #include "exec/address-spaces.h"
  18 #include "hw/boards.h"
  19 #include "hw/sysbus.h"
  20 #include "hw/arm/sysbus-fdt.h"
  21 #include "hw/arm/fdt.h"
  22 #include "cpu.h"
  23 #include "hw/arm/xlnx-versal.h"
  24
  25 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
  26 #define XLNX_VERSAL_VIRT_MACHINE(obj) \
  27     OBJECT_CHECK(VersalVirt, (obj), TYPE_XLNX_VERSAL_VIRT_MACHINE)
  28
  29 typedef struct VersalVirt {
  30     MachineState parent_obj;
  31
  32     Versal soc;
  33
  34     void *fdt;
  35     int fdt_size;
  36     struct {
  37         uint32_t gic;
  38         uint32_t ethernet_phy[2];
  39         uint32_t clk_125Mhz;
  40         uint32_t clk_25Mhz;
  41     } phandle;
  42     struct arm_boot_info binfo;
  43
  44     struct {
  45         bool secure;
  46     } cfg;
  47 } VersalVirt;
  48
  49 static void fdt_create(VersalVirt *s)
  50 {
  51     MachineClass *mc = MACHINE_GET_CLASS(s);
  52     int i;
  53
  54     s->fdt = create_device_tree(&s->fdt_size);
  55     if (!s->fdt) {
  56         error_report("create_device_tree() failed");
  57         exit(1);
  58     }
  59
  60     /* Allocate all phandles.  */
  61     s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt);
  62     for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) {
  63         s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt);
  64     }
  65     s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
  66     s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
  67
  68     /* Create /chosen node for load_dtb.  */
  69     qemu_fdt_add_subnode(s->fdt, "/chosen");
  70
  71     /* Header */
  72     qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic);
  73     qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2);
  74     qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2);
  75     qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc);
  76     qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt");
  77 }
  78
  79 static void fdt_add_clk_node(VersalVirt *s, const char *name,
  80                              unsigned int freq_hz, uint32_t phandle)
  81 {
  82     qemu_fdt_add_subnode(s->fdt, name);
  83     qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
  84     qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz);
  85     qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0);
  86     qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock");
  87     qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
  88 }
  89
  90 static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
  91 {
  92     int i;
  93
  94     qemu_fdt_add_subnode(s->fdt, "/cpus");
  95     qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0);
  96     qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1);
  97
  98     for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) {
  99         char *name = g_strdup_printf("/cpus/cpu@%d", i);
 100         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
 101
 102         qemu_fdt_add_subnode(s->fdt, name);
 103         qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
 104         if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
 105             qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci");
 106         }
 107         qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu");
 108         qemu_fdt_setprop_string(s->fdt, name, "compatible",
 109                                 armcpu->dtb_compatible);
 110         g_free(name);
 111     }
 112 }
 113
 114 static void fdt_add_gic_nodes(VersalVirt *s)
 115 {
 116     char *nodename;
 117
 118     nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN);
 119     qemu_fdt_add_subnode(s->fdt, nodename);
 120     qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic);
 121     qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts",
 122                            GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ,
 123                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 124     qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0);
 125     qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
 126                                  2, MM_GIC_APU_DIST_MAIN,
 127                                  2, MM_GIC_APU_DIST_MAIN_SIZE,
 128                                  2, MM_GIC_APU_REDIST_0,
 129                                  2, MM_GIC_APU_REDIST_0_SIZE);
 130     qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3);
 131     qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3");
 132     g_free(nodename);
 133 }
 134
 135 static void fdt_add_timer_nodes(VersalVirt *s)
 136 {
 137     const char compat[] = "arm,armv8-timer";
 138     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
 139
 140     qemu_fdt_add_subnode(s->fdt, "/timer");
 141     qemu_fdt_setprop_cells(s->fdt, "/timer", "interrupts",
 142             GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_S_EL1_IRQ, irqflags,
 143             GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL1_IRQ, irqflags,
 144             GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_VIRT_IRQ, irqflags,
 145             GIC_FDT_IRQ_TYPE_PPI, VERSAL_TIMER_NS_EL2_IRQ, irqflags);
 146     qemu_fdt_setprop(s->fdt, "/timer", "compatible",
 147                      compat, sizeof(compat));
 148 }
 149
 150 static void fdt_add_uart_nodes(VersalVirt *s)
 151 {
 152     uint64_t addrs[] = { MM_UART1, MM_UART0 };
 153     unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 };
 154     const char compat[] = "arm,pl011\0arm,sbsa-uart";
 155     const char clocknames[] = "uartclk\0apb_pclk";
 156     int i;
 157
 158     for (i = 0; i < ARRAY_SIZE(addrs); i++) {
 159         char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]);
 160         qemu_fdt_add_subnode(s->fdt, name);
 161         qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200);
 162         qemu_fdt_setprop_cells(s->fdt, name, "clocks",
 163                                s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
 164         qemu_fdt_setprop(s->fdt, name, "clock-names",
 165                          clocknames, sizeof(clocknames));
 166
 167         qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 168                                GIC_FDT_IRQ_TYPE_SPI, irqs[i],
 169                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 170         qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 171                                      2, addrs[i], 2, 0x1000);
 172         qemu_fdt_setprop(s->fdt, name, "compatible",
 173                          compat, sizeof(compat));
 174         qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
 175
 176         if (addrs[i] == MM_UART0) {
 177             /* Select UART0.  */
 178             qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name);
 179         }
 180         g_free(name);
 181     }
 182 }
 183
 184 static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname,
 185                                      uint32_t phandle)
 186 {
 187     char *name = g_strdup_printf("%s/fixed-link", gemname);
 188
 189     qemu_fdt_add_subnode(s->fdt, name);
 190     qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
 191     qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0);
 192     qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000);
 193     g_free(name);
 194 }
 195
 196 static void fdt_add_gem_nodes(VersalVirt *s)
 197 {
 198     uint64_t addrs[] = { MM_GEM1, MM_GEM0 };
 199     unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 };
 200     const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk";
 201     const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem";
 202     int i;
 203
 204     for (i = 0; i < ARRAY_SIZE(addrs); i++) {
 205         char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]);
 206         qemu_fdt_add_subnode(s->fdt, name);
 207
 208         fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]);
 209         qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id");
 210         qemu_fdt_setprop_cell(s->fdt, name, "phy-handle",
 211                               s->phandle.ethernet_phy[i]);
 212         qemu_fdt_setprop_cells(s->fdt, name, "clocks",
 213                                s->phandle.clk_25Mhz, s->phandle.clk_25Mhz,
 214                                s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
 215         qemu_fdt_setprop(s->fdt, name, "clock-names",
 216                          clocknames, sizeof(clocknames));
 217         qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 218                                GIC_FDT_IRQ_TYPE_SPI, irqs[i],
 219                                GIC_FDT_IRQ_FLAGS_LEVEL_HI,
 220                                GIC_FDT_IRQ_TYPE_SPI, irqs[i],
 221                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 222         qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 223                                      2, addrs[i], 2, 0x1000);
 224         qemu_fdt_setprop(s->fdt, name, "compatible",
 225                          compat_gem, sizeof(compat_gem));
 226         qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1);
 227         qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0);
 228         g_free(name);
 229     }
 230 }
 231
 232 static void fdt_add_zdma_nodes(VersalVirt *s)
 233 {
 234     const char clocknames[] = "clk_main\0clk_apb";
 235     const char compat[] = "xlnx,zynqmp-dma-1.0";
 236     int i;
 237
 238     for (i = XLNX_VERSAL_NR_ADMAS - 1; i >= 0; i--) {
 239         uint64_t addr = MM_ADMA_CH0 + MM_ADMA_CH0_SIZE * i;
 240         char *name = g_strdup_printf("/dma@%" PRIx64, addr);
 241
 242         qemu_fdt_add_subnode(s->fdt, name);
 243
 244         qemu_fdt_setprop_cell(s->fdt, name, "xlnx,bus-width", 64);
 245         qemu_fdt_setprop_cells(s->fdt, name, "clocks",
 246                                s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
 247         qemu_fdt_setprop(s->fdt, name, "clock-names",
 248                          clocknames, sizeof(clocknames));
 249         qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 250                                GIC_FDT_IRQ_TYPE_SPI, VERSAL_ADMA_IRQ_0 + i,
 251                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 252         qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 253                                      2, addr, 2, 0x1000);
 254         qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
 255         g_free(name);
 256     }
 257 }
 258
 259 static void fdt_nop_memory_nodes(void *fdt, Error **errp)
 260 {
 261     Error *err = NULL;
 262     char **node_path;
 263     int n = 0;
 264
 265     node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
 266     if (err) {
 267         error_propagate(errp, err);
 268         return;
 269     }
 270     while (node_path[n]) {
 271         if (g_str_has_prefix(node_path[n], "/memory")) {
 272             qemu_fdt_nop_node(fdt, node_path[n]);
 273         }
 274         n++;
 275     }
 276     g_strfreev(node_path);
 277 }
 278
 279 static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_size)
 280 {
 281     /* Describes the various split DDR access regions.  */
 282     static const struct {
 283         uint64_t base;
 284         uint64_t size;
 285     } addr_ranges[] = {
 286         { MM_TOP_DDR, MM_TOP_DDR_SIZE },
 287         { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE },
 288         { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE },
 289         { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE }
 290     };
 291     uint64_t mem_reg_prop[8] = {0};
 292     uint64_t size = ram_size;
 293     Error *err = NULL;
 294     char *name;
 295     int i;
 296
 297     fdt_nop_memory_nodes(fdt, &err);
 298     if (err) {
 299         error_report_err(err);
 300         return;
 301     }
 302
 303     name = g_strdup_printf("/memory@%x", MM_TOP_DDR);
 304     for (i = 0; i < ARRAY_SIZE(addr_ranges) && size; i++) {
 305         uint64_t mapsize;
 306
 307         mapsize = size < addr_ranges[i].size ? size : addr_ranges[i].size;
 308
 309         mem_reg_prop[i * 2] = addr_ranges[i].base;
 310         mem_reg_prop[i * 2 + 1] = mapsize;
 311         size -= mapsize;
 312     }
 313     qemu_fdt_add_subnode(fdt, name);
 314     qemu_fdt_setprop_string(fdt, name, "device_type", "memory");
 315
 316     switch (i) {
 317     case 1:
 318         qemu_fdt_setprop_sized_cells(fdt, name, "reg",
 319                                      2, mem_reg_prop[0],
 320                                      2, mem_reg_prop[1]);
 321         break;
 322     case 2:
 323         qemu_fdt_setprop_sized_cells(fdt, name, "reg",
 324                                      2, mem_reg_prop[0],
 325                                      2, mem_reg_prop[1],
 326                                      2, mem_reg_prop[2],
 327                                      2, mem_reg_prop[3]);
 328         break;
 329     case 3:
 330         qemu_fdt_setprop_sized_cells(fdt, name, "reg",
 331                                      2, mem_reg_prop[0],
 332                                      2, mem_reg_prop[1],
 333                                      2, mem_reg_prop[2],
 334                                      2, mem_reg_prop[3],
 335                                      2, mem_reg_prop[4],
 336                                      2, mem_reg_prop[5]);
 337         break;
 338     case 4:
 339         qemu_fdt_setprop_sized_cells(fdt, name, "reg",
 340                                      2, mem_reg_prop[0],
 341                                      2, mem_reg_prop[1],
 342                                      2, mem_reg_prop[2],
 343                                      2, mem_reg_prop[3],
 344                                      2, mem_reg_prop[4],
 345                                      2, mem_reg_prop[5],
 346                                      2, mem_reg_prop[6],
 347                                      2, mem_reg_prop[7]);
 348         break;
 349     default:
 350         g_assert_not_reached();
 351     }
 352     g_free(name);
 353 }
 354
 355 static void versal_virt_modify_dtb(const struct arm_boot_info *binfo,
 356                                     void *fdt)
 357 {
 358     VersalVirt *s = container_of(binfo, VersalVirt, binfo);
 359
 360     fdt_add_memory_nodes(s, fdt, binfo->ram_size);
 361 }
 362
 363 static void *versal_virt_get_dtb(const struct arm_boot_info *binfo,
 364                                   int *fdt_size)
 365 {
 366     const VersalVirt *board = container_of(binfo, VersalVirt, binfo);
 367
 368     *fdt_size = board->fdt_size;
 369     return board->fdt;
 370 }
 371
 372 #define NUM_VIRTIO_TRANSPORT 8
 373 static void create_virtio_regions(VersalVirt *s)
 374 {
 375     int virtio_mmio_size = 0x200;
 376     int i;
 377
 378     for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
 379         char *name = g_strdup_printf("virtio%d", i);
 380         hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
 381         int irq = VERSAL_RSVD_IRQ_FIRST + i;
 382         MemoryRegion *mr;
 383         DeviceState *dev;
 384         qemu_irq pic_irq;
 385
 386         pic_irq = qdev_get_gpio_in(DEVICE(&s->soc.fpd.apu.gic), irq);
 387         dev = qdev_create(NULL, "virtio-mmio");
 388         object_property_add_child(OBJECT(&s->soc), name, OBJECT(dev),
 389                                   &error_fatal);
 390         qdev_init_nofail(dev);
 391         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
 392         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 393         memory_region_add_subregion(&s->soc.mr_ps, base, mr);
 394         g_free(name);
 395     }
 396
 397     for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
 398         hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
 399         int irq = VERSAL_RSVD_IRQ_FIRST + i;
 400         char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
 401
 402         qemu_fdt_add_subnode(s->fdt, name);
 403         qemu_fdt_setprop(s->fdt, name, "dma-coherent", NULL, 0);
 404         qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
 405                                GIC_FDT_IRQ_TYPE_SPI, irq,
 406                                GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
 407         qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 408                                      2, base, 2, virtio_mmio_size);
 409         qemu_fdt_setprop_string(s->fdt, name, "compatible", "virtio,mmio");
 410         g_free(name);
 411     }
 412 }
 413
 414 static void versal_virt_init(MachineState *machine)
 415 {
 416     VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
 417     int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
 418
 419     /*
 420      * If the user provides an Operating System to be loaded, we expect them
 421      * to use the -kernel command line option.
 422      *
 423      * Users can load firmware or boot-loaders with the -device loader options.
 424      *
 425      * When loading an OS, we generate a dtb and let arm_load_kernel() select
 426      * where it gets loaded. This dtb will be passed to the kernel in x0.
 427      *
 428      * If there's no -kernel option, we generate a DTB and place it at 0x1000
 429      * for the bootloaders or firmware to pick up.
 430      *
 431      * If users want to provide their own DTB, they can use the -dtb option.
 432      * These dtb's will have their memory nodes modified to match QEMU's
 433      * selected ram_size option before they get passed to the kernel or fw.
 434      *
 435      * When loading an OS, we turn on QEMU's PSCI implementation with SMC
 436      * as the PSCI conduit. When there's no -kernel, we assume the user
 437      * provides EL3 firmware to handle PSCI.
 438      */
 439     if (machine->kernel_filename) {
 440         psci_conduit = QEMU_PSCI_CONDUIT_SMC;
 441     }
 442
 443     sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc,
 444                           sizeof(s->soc), TYPE_XLNX_VERSAL);
 445     object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
 446                              "ddr", &error_abort);
 447     object_property_set_int(OBJECT(&s->soc), psci_conduit,
 448                             "psci-conduit", &error_abort);
 449     object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
 450
 451     fdt_create(s);
 452     create_virtio_regions(s);
 453     fdt_add_gem_nodes(s);
 454     fdt_add_uart_nodes(s);
 455     fdt_add_gic_nodes(s);
 456     fdt_add_timer_nodes(s);
 457     fdt_add_zdma_nodes(s);
 458     fdt_add_cpu_nodes(s, psci_conduit);
 459     fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
 460     fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
 461
 462     /* Make the APU cpu address space visible to virtio and other
 463      * modules unaware of muliple address-spaces.  */
 464     memory_region_add_subregion_overlap(get_system_memory(),
 465                                         0, &s->soc.fpd.apu.mr, 0);
 466
 467     s->binfo.ram_size = machine->ram_size;
 468     s->binfo.loader_start = 0x0;
 469     s->binfo.get_dtb = versal_virt_get_dtb;
 470     s->binfo.modify_dtb = versal_virt_modify_dtb;
 471     if (machine->kernel_filename) {
 472         arm_load_kernel(s->soc.fpd.apu.cpu[0], machine, &s->binfo);
 473     } else {
 474         AddressSpace *as = arm_boot_address_space(s->soc.fpd.apu.cpu[0],
 475                                                   &s->binfo);
 476         /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
 477          * Offset things by 4K.  */
 478         s->binfo.loader_start = 0x1000;
 479         s->binfo.dtb_limit = 0x1000000;
 480         if (arm_load_dtb(s->binfo.loader_start,
 481                          &s->binfo, s->binfo.dtb_limit, as, machine) < 0) {
 482             exit(EXIT_FAILURE);
 483         }
 484     }
 485 }
 486
 487 static void versal_virt_machine_instance_init(Object *obj)
 488 {
 489 }
 490
 491 static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
 492 {
 493     MachineClass *mc = MACHINE_CLASS(oc);
 494
 495     mc->desc = "Xilinx Versal Virtual development board";
 496     mc->init = versal_virt_init;
 497     mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
 498     mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
 499     mc->no_cdrom = true;
 500     mc->default_ram_id = "ddr";
 501 }
 502
 503 static const TypeInfo versal_virt_machine_init_typeinfo = {
 504     .name       = TYPE_XLNX_VERSAL_VIRT_MACHINE,
 505     .parent     = TYPE_MACHINE,
 506     .class_init = versal_virt_machine_class_init,
 507     .instance_init = versal_virt_machine_instance_init,
 508     .instance_size = sizeof(VersalVirt),
 509 };
 510
 511 static void versal_virt_machine_init_register_types(void)
 512 {
 513     type_register_static(&versal_virt_machine_init_typeinfo);
 514 }
 515
 516 type_init(versal_virt_machine_init_register_types)
 517