2 * SD Association Host Standard Specification v2.0 controller emulation
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/error-report.h"
28 #include "qapi/error.h"
30 #include "sysemu/dma.h"
31 #include "qemu/timer.h"
32 #include "qemu/bitops.h"
33 #include "hw/sd/sdhci.h"
34 #include "sdhci-internal.h"
36 #include "qemu/module.h"
39 #define TYPE_SDHCI_BUS "sdhci-bus"
40 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
42 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
44 static inline unsigned int sdhci_get_fifolen(SDHCIState
*s
)
46 return 1 << (9 + FIELD_EX32(s
->capareg
, SDHC_CAPAB
, MAXBLOCKLENGTH
));
49 /* return true on error */
50 static bool sdhci_check_capab_freq_range(SDHCIState
*s
, const char *desc
,
51 uint8_t freq
, Error
**errp
)
53 if (s
->sd_spec_version
>= 3) {
61 error_setg(errp
, "SD %s clock frequency can have value"
62 "in range 0-63 only", desc
);
68 static void sdhci_check_capareg(SDHCIState
*s
, Error
**errp
)
70 uint64_t msk
= s
->capareg
;
74 switch (s
->sd_spec_version
) {
76 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BUS64BIT_V4
);
77 trace_sdhci_capareg("64-bit system bus (v4)", val
);
78 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BUS64BIT_V4
, 0);
80 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, UHS_II
);
81 trace_sdhci_capareg("UHS-II", val
);
82 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, UHS_II
, 0);
84 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ADMA3
);
85 trace_sdhci_capareg("ADMA3", val
);
86 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ADMA3
, 0);
90 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ASYNC_INT
);
91 trace_sdhci_capareg("async interrupt", val
);
92 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ASYNC_INT
, 0);
94 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SLOT_TYPE
);
96 error_setg(errp
, "slot-type not supported");
99 trace_sdhci_capareg("slot type", val
);
100 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SLOT_TYPE
, 0);
103 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, EMBEDDED_8BIT
);
104 trace_sdhci_capareg("8-bit bus", val
);
106 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, EMBEDDED_8BIT
, 0);
108 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BUS_SPEED
);
109 trace_sdhci_capareg("bus speed mask", val
);
110 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BUS_SPEED
, 0);
112 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, DRIVER_STRENGTH
);
113 trace_sdhci_capareg("driver strength mask", val
);
114 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, DRIVER_STRENGTH
, 0);
116 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, TIMER_RETUNING
);
117 trace_sdhci_capareg("timer re-tuning", val
);
118 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, TIMER_RETUNING
, 0);
120 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SDR50_TUNING
);
121 trace_sdhci_capareg("use SDR50 tuning", val
);
122 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SDR50_TUNING
, 0);
124 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, RETUNING_MODE
);
125 trace_sdhci_capareg("re-tuning mode", val
);
126 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, RETUNING_MODE
, 0);
128 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, CLOCK_MULT
);
129 trace_sdhci_capareg("clock multiplier", val
);
130 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, CLOCK_MULT
, 0);
133 case 2: /* default version */
134 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ADMA2
);
135 trace_sdhci_capareg("ADMA2", val
);
136 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ADMA2
, 0);
138 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ADMA1
);
139 trace_sdhci_capareg("ADMA1", val
);
140 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ADMA1
, 0);
142 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BUS64BIT
);
143 trace_sdhci_capareg("64-bit system bus (v3)", val
);
144 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BUS64BIT
, 0);
148 y
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, TOUNIT
);
149 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, TOUNIT
, 0);
151 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, TOCLKFREQ
);
152 trace_sdhci_capareg(y
? "timeout (MHz)" : "Timeout (KHz)", val
);
153 if (sdhci_check_capab_freq_range(s
, "timeout", val
, errp
)) {
156 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, TOCLKFREQ
, 0);
158 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BASECLKFREQ
);
159 trace_sdhci_capareg(y
? "base (MHz)" : "Base (KHz)", val
);
160 if (sdhci_check_capab_freq_range(s
, "base", val
, errp
)) {
163 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BASECLKFREQ
, 0);
165 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, MAXBLOCKLENGTH
);
167 error_setg(errp
, "block size can be 512, 1024 or 2048 only");
170 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s
));
171 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, MAXBLOCKLENGTH
, 0);
173 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, HIGHSPEED
);
174 trace_sdhci_capareg("high speed", val
);
175 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, HIGHSPEED
, 0);
177 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SDMA
);
178 trace_sdhci_capareg("SDMA", val
);
179 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SDMA
, 0);
181 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SUSPRESUME
);
182 trace_sdhci_capareg("suspend/resume", val
);
183 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SUSPRESUME
, 0);
185 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, V33
);
186 trace_sdhci_capareg("3.3v", val
);
187 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, V33
, 0);
189 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, V30
);
190 trace_sdhci_capareg("3.0v", val
);
191 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, V30
, 0);
193 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, V18
);
194 trace_sdhci_capareg("1.8v", val
);
195 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, V18
, 0);
199 error_setg(errp
, "Unsupported spec version: %u", s
->sd_spec_version
);
202 qemu_log_mask(LOG_UNIMP
,
203 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64
"\n", msk
);
207 static uint8_t sdhci_slotint(SDHCIState
*s
)
209 return (s
->norintsts
& s
->norintsigen
) || (s
->errintsts
& s
->errintsigen
) ||
210 ((s
->norintsts
& SDHC_NIS_INSERT
) && (s
->wakcon
& SDHC_WKUP_ON_INS
)) ||
211 ((s
->norintsts
& SDHC_NIS_REMOVE
) && (s
->wakcon
& SDHC_WKUP_ON_RMV
));
214 static inline void sdhci_update_irq(SDHCIState
*s
)
216 qemu_set_irq(s
->irq
, sdhci_slotint(s
));
219 static void sdhci_raise_insertion_irq(void *opaque
)
221 SDHCIState
*s
= (SDHCIState
*)opaque
;
223 if (s
->norintsts
& SDHC_NIS_REMOVE
) {
224 timer_mod(s
->insert_timer
,
225 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
227 s
->prnsts
= 0x1ff0000;
228 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
229 s
->norintsts
|= SDHC_NIS_INSERT
;
235 static void sdhci_set_inserted(DeviceState
*dev
, bool level
)
237 SDHCIState
*s
= (SDHCIState
*)dev
;
239 trace_sdhci_set_inserted(level
? "insert" : "eject");
240 if ((s
->norintsts
& SDHC_NIS_REMOVE
) && level
) {
241 /* Give target some time to notice card ejection */
242 timer_mod(s
->insert_timer
,
243 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
246 s
->prnsts
= 0x1ff0000;
247 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
248 s
->norintsts
|= SDHC_NIS_INSERT
;
251 s
->prnsts
= 0x1fa0000;
252 s
->pwrcon
&= ~SDHC_POWER_ON
;
253 s
->clkcon
&= ~SDHC_CLOCK_SDCLK_EN
;
254 if (s
->norintstsen
& SDHC_NISEN_REMOVE
) {
255 s
->norintsts
|= SDHC_NIS_REMOVE
;
262 static void sdhci_set_readonly(DeviceState
*dev
, bool level
)
264 SDHCIState
*s
= (SDHCIState
*)dev
;
267 s
->prnsts
&= ~SDHC_WRITE_PROTECT
;
270 s
->prnsts
|= SDHC_WRITE_PROTECT
;
274 static void sdhci_reset(SDHCIState
*s
)
276 DeviceState
*dev
= DEVICE(s
);
278 timer_del(s
->insert_timer
);
279 timer_del(s
->transfer_timer
);
281 /* Set all registers to 0. Capabilities/Version registers are not cleared
282 * and assumed to always preserve their value, given to them during
284 memset(&s
->sdmasysad
, 0, (uintptr_t)&s
->capareg
- (uintptr_t)&s
->sdmasysad
);
286 /* Reset other state based on current card insertion/readonly status */
287 sdhci_set_inserted(dev
, sdbus_get_inserted(&s
->sdbus
));
288 sdhci_set_readonly(dev
, sdbus_get_readonly(&s
->sdbus
));
291 s
->stopped_state
= sdhc_not_stopped
;
292 s
->pending_insert_state
= false;
295 static void sdhci_poweron_reset(DeviceState
*dev
)
297 /* QOM (ie power-on) reset. This is identical to reset
298 * commanded via device register apart from handling of the
299 * 'pending insert on powerup' quirk.
301 SDHCIState
*s
= (SDHCIState
*)dev
;
305 if (s
->pending_insert_quirk
) {
306 s
->pending_insert_state
= true;
310 static void sdhci_data_transfer(void *opaque
);
312 static void sdhci_send_command(SDHCIState
*s
)
315 uint8_t response
[16];
320 request
.cmd
= s
->cmdreg
>> 8;
321 request
.arg
= s
->argument
;
323 trace_sdhci_send_command(request
.cmd
, request
.arg
);
324 rlen
= sdbus_do_command(&s
->sdbus
, &request
, response
);
326 if (s
->cmdreg
& SDHC_CMD_RESPONSE
) {
328 s
->rspreg
[0] = ldl_be_p(response
);
329 s
->rspreg
[1] = s
->rspreg
[2] = s
->rspreg
[3] = 0;
330 trace_sdhci_response4(s
->rspreg
[0]);
331 } else if (rlen
== 16) {
332 s
->rspreg
[0] = ldl_be_p(&response
[11]);
333 s
->rspreg
[1] = ldl_be_p(&response
[7]);
334 s
->rspreg
[2] = ldl_be_p(&response
[3]);
335 s
->rspreg
[3] = (response
[0] << 16) | (response
[1] << 8) |
337 trace_sdhci_response16(s
->rspreg
[3], s
->rspreg
[2],
338 s
->rspreg
[1], s
->rspreg
[0]);
340 trace_sdhci_error("timeout waiting for command response");
341 if (s
->errintstsen
& SDHC_EISEN_CMDTIMEOUT
) {
342 s
->errintsts
|= SDHC_EIS_CMDTIMEOUT
;
343 s
->norintsts
|= SDHC_NIS_ERR
;
347 if (!(s
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
) &&
348 (s
->norintstsen
& SDHC_NISEN_TRSCMP
) &&
349 (s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
) {
350 s
->norintsts
|= SDHC_NIS_TRSCMP
;
354 if (s
->norintstsen
& SDHC_NISEN_CMDCMP
) {
355 s
->norintsts
|= SDHC_NIS_CMDCMP
;
360 if (s
->blksize
&& (s
->cmdreg
& SDHC_CMD_DATA_PRESENT
)) {
362 sdhci_data_transfer(s
);
366 static void sdhci_end_transfer(SDHCIState
*s
)
368 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
369 if ((s
->trnmod
& SDHC_TRNS_ACMD12
) != 0) {
371 uint8_t response
[16];
375 trace_sdhci_end_transfer(request
.cmd
, request
.arg
);
376 sdbus_do_command(&s
->sdbus
, &request
, response
);
377 /* Auto CMD12 response goes to the upper Response register */
378 s
->rspreg
[3] = ldl_be_p(response
);
381 s
->prnsts
&= ~(SDHC_DOING_READ
| SDHC_DOING_WRITE
|
382 SDHC_DAT_LINE_ACTIVE
| SDHC_DATA_INHIBIT
|
383 SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
);
385 if (s
->norintstsen
& SDHC_NISEN_TRSCMP
) {
386 s
->norintsts
|= SDHC_NIS_TRSCMP
;
393 * Programmed i/o data transfer
395 #define BLOCK_SIZE_MASK (4 * KiB - 1)
397 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */
398 static void sdhci_read_block_from_card(SDHCIState
*s
)
402 const uint16_t blk_size
= s
->blksize
& BLOCK_SIZE_MASK
;
404 if ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
405 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) {
409 for (index
= 0; index
< blk_size
; index
++) {
410 data
= sdbus_read_data(&s
->sdbus
);
411 if (!FIELD_EX32(s
->hostctl2
, SDHC_HOSTCTL2
, EXECUTE_TUNING
)) {
412 /* Device is not in tuning */
413 s
->fifo_buffer
[index
] = data
;
417 if (FIELD_EX32(s
->hostctl2
, SDHC_HOSTCTL2
, EXECUTE_TUNING
)) {
418 /* Device is in tuning */
419 s
->hostctl2
&= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK
;
420 s
->hostctl2
|= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK
;
421 s
->prnsts
&= ~(SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_READ
|
426 /* New data now available for READ through Buffer Port Register */
427 s
->prnsts
|= SDHC_DATA_AVAILABLE
;
428 if (s
->norintstsen
& SDHC_NISEN_RBUFRDY
) {
429 s
->norintsts
|= SDHC_NIS_RBUFRDY
;
432 /* Clear DAT line active status if that was the last block */
433 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
434 ((s
->trnmod
& SDHC_TRNS_MULTI
) && s
->blkcnt
== 1)) {
435 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
438 /* If stop at block gap request was set and it's not the last block of
439 * data - generate Block Event interrupt */
440 if (s
->stopped_state
== sdhc_gap_read
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
442 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
443 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
444 s
->norintsts
|= SDHC_EIS_BLKGAP
;
452 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */
453 static uint32_t sdhci_read_dataport(SDHCIState
*s
, unsigned size
)
458 /* first check that a valid data exists in host controller input buffer */
459 if ((s
->prnsts
& SDHC_DATA_AVAILABLE
) == 0) {
460 trace_sdhci_error("read from empty buffer");
464 for (i
= 0; i
< size
; i
++) {
465 value
|= s
->fifo_buffer
[s
->data_count
] << i
* 8;
467 /* check if we've read all valid data (blksize bytes) from buffer */
468 if ((s
->data_count
) >= (s
->blksize
& BLOCK_SIZE_MASK
)) {
469 trace_sdhci_read_dataport(s
->data_count
);
470 s
->prnsts
&= ~SDHC_DATA_AVAILABLE
; /* no more data in a buffer */
471 s
->data_count
= 0; /* next buff read must start at position [0] */
473 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
477 /* if that was the last block of data */
478 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
479 ((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) ||
480 /* stop at gap request */
481 (s
->stopped_state
== sdhc_gap_read
&&
482 !(s
->prnsts
& SDHC_DAT_LINE_ACTIVE
))) {
483 sdhci_end_transfer(s
);
484 } else { /* if there are more data, read next block from card */
485 sdhci_read_block_from_card(s
);
494 /* Write data from host controller FIFO to card */
495 static void sdhci_write_block_to_card(SDHCIState
*s
)
499 if (s
->prnsts
& SDHC_SPACE_AVAILABLE
) {
500 if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
501 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
507 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
508 if (s
->blkcnt
== 0) {
515 for (index
= 0; index
< (s
->blksize
& BLOCK_SIZE_MASK
); index
++) {
516 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[index
]);
519 /* Next data can be written through BUFFER DATORT register */
520 s
->prnsts
|= SDHC_SPACE_AVAILABLE
;
522 /* Finish transfer if that was the last block of data */
523 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
524 ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
525 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0))) {
526 sdhci_end_transfer(s
);
527 } else if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
528 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
531 /* Generate Block Gap Event if requested and if not the last block */
532 if (s
->stopped_state
== sdhc_gap_write
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
534 s
->prnsts
&= ~SDHC_DOING_WRITE
;
535 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
536 s
->norintsts
|= SDHC_EIS_BLKGAP
;
538 sdhci_end_transfer(s
);
544 /* Write @size bytes of @value data to host controller @s Buffer Data Port
546 static void sdhci_write_dataport(SDHCIState
*s
, uint32_t value
, unsigned size
)
550 /* Check that there is free space left in a buffer */
551 if (!(s
->prnsts
& SDHC_SPACE_AVAILABLE
)) {
552 trace_sdhci_error("Can't write to data buffer: buffer full");
556 for (i
= 0; i
< size
; i
++) {
557 s
->fifo_buffer
[s
->data_count
] = value
& 0xFF;
560 if (s
->data_count
>= (s
->blksize
& BLOCK_SIZE_MASK
)) {
561 trace_sdhci_write_dataport(s
->data_count
);
563 s
->prnsts
&= ~SDHC_SPACE_AVAILABLE
;
564 if (s
->prnsts
& SDHC_DOING_WRITE
) {
565 sdhci_write_block_to_card(s
);
572 * Single DMA data transfer
575 /* Multi block SDMA transfer */
576 static void sdhci_sdma_transfer_multi_blocks(SDHCIState
*s
)
578 bool page_aligned
= false;
579 unsigned int n
, begin
;
580 const uint16_t block_size
= s
->blksize
& BLOCK_SIZE_MASK
;
581 uint32_t boundary_chk
= 1 << (((s
->blksize
& ~BLOCK_SIZE_MASK
) >> 12) + 12);
582 uint32_t boundary_count
= boundary_chk
- (s
->sdmasysad
% boundary_chk
);
584 if (!(s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) || !s
->blkcnt
) {
585 qemu_log_mask(LOG_UNIMP
, "infinite transfer is not supported\n");
589 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
590 * possible stop at page boundary if initial address is not page aligned,
591 * allow them to work properly */
592 if ((s
->sdmasysad
% boundary_chk
) == 0) {
596 if (s
->trnmod
& SDHC_TRNS_READ
) {
597 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
598 SDHC_DAT_LINE_ACTIVE
;
600 if (s
->data_count
== 0) {
601 for (n
= 0; n
< block_size
; n
++) {
602 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
605 begin
= s
->data_count
;
606 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
607 s
->data_count
= boundary_count
+ begin
;
610 s
->data_count
= block_size
;
611 boundary_count
-= block_size
- begin
;
612 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
616 dma_memory_write(s
->dma_as
, s
->sdmasysad
,
617 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
618 s
->sdmasysad
+= s
->data_count
- begin
;
619 if (s
->data_count
== block_size
) {
622 if (page_aligned
&& boundary_count
== 0) {
627 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DATA_INHIBIT
|
628 SDHC_DAT_LINE_ACTIVE
;
630 begin
= s
->data_count
;
631 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
632 s
->data_count
= boundary_count
+ begin
;
635 s
->data_count
= block_size
;
636 boundary_count
-= block_size
- begin
;
638 dma_memory_read(s
->dma_as
, s
->sdmasysad
,
639 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
640 s
->sdmasysad
+= s
->data_count
- begin
;
641 if (s
->data_count
== block_size
) {
642 for (n
= 0; n
< block_size
; n
++) {
643 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
646 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
650 if (page_aligned
&& boundary_count
== 0) {
656 if (s
->blkcnt
== 0) {
657 sdhci_end_transfer(s
);
659 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
660 s
->norintsts
|= SDHC_NIS_DMA
;
666 /* single block SDMA transfer */
667 static void sdhci_sdma_transfer_single_block(SDHCIState
*s
)
670 uint32_t datacnt
= s
->blksize
& BLOCK_SIZE_MASK
;
672 if (s
->trnmod
& SDHC_TRNS_READ
) {
673 for (n
= 0; n
< datacnt
; n
++) {
674 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
676 dma_memory_write(s
->dma_as
, s
->sdmasysad
, s
->fifo_buffer
, datacnt
);
678 dma_memory_read(s
->dma_as
, s
->sdmasysad
, s
->fifo_buffer
, datacnt
);
679 for (n
= 0; n
< datacnt
; n
++) {
680 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
685 sdhci_end_transfer(s
);
688 typedef struct ADMADescr
{
695 static void get_adma_description(SDHCIState
*s
, ADMADescr
*dscr
)
699 hwaddr entry_addr
= (hwaddr
)s
->admasysaddr
;
700 switch (SDHC_DMA_TYPE(s
->hostctl1
)) {
701 case SDHC_CTRL_ADMA2_32
:
702 dma_memory_read(s
->dma_as
, entry_addr
, (uint8_t *)&adma2
,
704 adma2
= le64_to_cpu(adma2
);
705 /* The spec does not specify endianness of descriptor table.
706 * We currently assume that it is LE.
708 dscr
->addr
= (hwaddr
)extract64(adma2
, 32, 32) & ~0x3ull
;
709 dscr
->length
= (uint16_t)extract64(adma2
, 16, 16);
710 dscr
->attr
= (uint8_t)extract64(adma2
, 0, 7);
713 case SDHC_CTRL_ADMA1_32
:
714 dma_memory_read(s
->dma_as
, entry_addr
, (uint8_t *)&adma1
,
716 adma1
= le32_to_cpu(adma1
);
717 dscr
->addr
= (hwaddr
)(adma1
& 0xFFFFF000);
718 dscr
->attr
= (uint8_t)extract32(adma1
, 0, 7);
720 if ((dscr
->attr
& SDHC_ADMA_ATTR_ACT_MASK
) == SDHC_ADMA_ATTR_SET_LEN
) {
721 dscr
->length
= (uint16_t)extract32(adma1
, 12, 16);
723 dscr
->length
= 4 * KiB
;
726 case SDHC_CTRL_ADMA2_64
:
727 dma_memory_read(s
->dma_as
, entry_addr
,
728 (uint8_t *)(&dscr
->attr
), 1);
729 dma_memory_read(s
->dma_as
, entry_addr
+ 2,
730 (uint8_t *)(&dscr
->length
), 2);
731 dscr
->length
= le16_to_cpu(dscr
->length
);
732 dma_memory_read(s
->dma_as
, entry_addr
+ 4,
733 (uint8_t *)(&dscr
->addr
), 8);
734 dscr
->addr
= le64_to_cpu(dscr
->addr
);
735 dscr
->attr
&= (uint8_t) ~0xC0;
741 /* Advanced DMA data transfer */
743 static void sdhci_do_adma(SDHCIState
*s
)
745 unsigned int n
, begin
, length
;
746 const uint16_t block_size
= s
->blksize
& BLOCK_SIZE_MASK
;
750 for (i
= 0; i
< SDHC_ADMA_DESCS_PER_DELAY
; ++i
) {
751 s
->admaerr
&= ~SDHC_ADMAERR_LENGTH_MISMATCH
;
753 get_adma_description(s
, &dscr
);
754 trace_sdhci_adma_loop(dscr
.addr
, dscr
.length
, dscr
.attr
);
756 if ((dscr
.attr
& SDHC_ADMA_ATTR_VALID
) == 0) {
757 /* Indicate that error occurred in ST_FDS state */
758 s
->admaerr
&= ~SDHC_ADMAERR_STATE_MASK
;
759 s
->admaerr
|= SDHC_ADMAERR_STATE_ST_FDS
;
761 /* Generate ADMA error interrupt */
762 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
763 s
->errintsts
|= SDHC_EIS_ADMAERR
;
764 s
->norintsts
|= SDHC_NIS_ERR
;
771 length
= dscr
.length
? dscr
.length
: 64 * KiB
;
773 switch (dscr
.attr
& SDHC_ADMA_ATTR_ACT_MASK
) {
774 case SDHC_ADMA_ATTR_ACT_TRAN
: /* data transfer */
776 if (s
->trnmod
& SDHC_TRNS_READ
) {
778 if (s
->data_count
== 0) {
779 for (n
= 0; n
< block_size
; n
++) {
780 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
783 begin
= s
->data_count
;
784 if ((length
+ begin
) < block_size
) {
785 s
->data_count
= length
+ begin
;
788 s
->data_count
= block_size
;
789 length
-= block_size
- begin
;
791 dma_memory_write(s
->dma_as
, dscr
.addr
,
792 &s
->fifo_buffer
[begin
],
793 s
->data_count
- begin
);
794 dscr
.addr
+= s
->data_count
- begin
;
795 if (s
->data_count
== block_size
) {
797 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
799 if (s
->blkcnt
== 0) {
807 begin
= s
->data_count
;
808 if ((length
+ begin
) < block_size
) {
809 s
->data_count
= length
+ begin
;
812 s
->data_count
= block_size
;
813 length
-= block_size
- begin
;
815 dma_memory_read(s
->dma_as
, dscr
.addr
,
816 &s
->fifo_buffer
[begin
],
817 s
->data_count
- begin
);
818 dscr
.addr
+= s
->data_count
- begin
;
819 if (s
->data_count
== block_size
) {
820 for (n
= 0; n
< block_size
; n
++) {
821 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
824 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
826 if (s
->blkcnt
== 0) {
833 s
->admasysaddr
+= dscr
.incr
;
835 case SDHC_ADMA_ATTR_ACT_LINK
: /* link to next descriptor table */
836 s
->admasysaddr
= dscr
.addr
;
837 trace_sdhci_adma("link", s
->admasysaddr
);
840 s
->admasysaddr
+= dscr
.incr
;
844 if (dscr
.attr
& SDHC_ADMA_ATTR_INT
) {
845 trace_sdhci_adma("interrupt", s
->admasysaddr
);
846 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
847 s
->norintsts
|= SDHC_NIS_DMA
;
853 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
854 if (((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
855 (s
->blkcnt
== 0)) || (dscr
.attr
& SDHC_ADMA_ATTR_END
)) {
856 trace_sdhci_adma_transfer_completed();
857 if (length
|| ((dscr
.attr
& SDHC_ADMA_ATTR_END
) &&
858 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
860 trace_sdhci_error("SD/MMC host ADMA length mismatch");
861 s
->admaerr
|= SDHC_ADMAERR_LENGTH_MISMATCH
|
862 SDHC_ADMAERR_STATE_ST_TFR
;
863 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
864 trace_sdhci_error("Set ADMA error flag");
865 s
->errintsts
|= SDHC_EIS_ADMAERR
;
866 s
->norintsts
|= SDHC_NIS_ERR
;
871 sdhci_end_transfer(s
);
877 /* we have unfinished business - reschedule to continue ADMA */
878 timer_mod(s
->transfer_timer
,
879 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_TRANSFER_DELAY
);
882 /* Perform data transfer according to controller configuration */
884 static void sdhci_data_transfer(void *opaque
)
886 SDHCIState
*s
= (SDHCIState
*)opaque
;
888 if (s
->trnmod
& SDHC_TRNS_DMA
) {
889 switch (SDHC_DMA_TYPE(s
->hostctl1
)) {
891 if ((s
->blkcnt
== 1) || !(s
->trnmod
& SDHC_TRNS_MULTI
)) {
892 sdhci_sdma_transfer_single_block(s
);
894 sdhci_sdma_transfer_multi_blocks(s
);
898 case SDHC_CTRL_ADMA1_32
:
899 if (!(s
->capareg
& R_SDHC_CAPAB_ADMA1_MASK
)) {
900 trace_sdhci_error("ADMA1 not supported");
906 case SDHC_CTRL_ADMA2_32
:
907 if (!(s
->capareg
& R_SDHC_CAPAB_ADMA2_MASK
)) {
908 trace_sdhci_error("ADMA2 not supported");
914 case SDHC_CTRL_ADMA2_64
:
915 if (!(s
->capareg
& R_SDHC_CAPAB_ADMA2_MASK
) ||
916 !(s
->capareg
& R_SDHC_CAPAB_BUS64BIT_MASK
)) {
917 trace_sdhci_error("64 bit ADMA not supported");
924 trace_sdhci_error("Unsupported DMA type");
928 if ((s
->trnmod
& SDHC_TRNS_READ
) && sdbus_data_ready(&s
->sdbus
)) {
929 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
930 SDHC_DAT_LINE_ACTIVE
;
931 sdhci_read_block_from_card(s
);
933 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DAT_LINE_ACTIVE
|
934 SDHC_SPACE_AVAILABLE
| SDHC_DATA_INHIBIT
;
935 sdhci_write_block_to_card(s
);
940 static bool sdhci_can_issue_command(SDHCIState
*s
)
942 if (!SDHC_CLOCK_IS_ON(s
->clkcon
) ||
943 (((s
->prnsts
& SDHC_DATA_INHIBIT
) || s
->stopped_state
) &&
944 ((s
->cmdreg
& SDHC_CMD_DATA_PRESENT
) ||
945 ((s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
&&
946 !(SDHC_COMMAND_TYPE(s
->cmdreg
) == SDHC_CMD_ABORT
))))) {
953 /* The Buffer Data Port register must be accessed in sequential and
954 * continuous manner */
956 sdhci_buff_access_is_sequential(SDHCIState
*s
, unsigned byte_num
)
958 if ((s
->data_count
& 0x3) != byte_num
) {
959 trace_sdhci_error("Non-sequential access to Buffer Data Port register"
966 static uint64_t sdhci_read(void *opaque
, hwaddr offset
, unsigned size
)
968 SDHCIState
*s
= (SDHCIState
*)opaque
;
971 switch (offset
& ~0x3) {
976 ret
= s
->blksize
| (s
->blkcnt
<< 16);
982 ret
= s
->trnmod
| (s
->cmdreg
<< 16);
984 case SDHC_RSPREG0
... SDHC_RSPREG3
:
985 ret
= s
->rspreg
[((offset
& ~0x3) - SDHC_RSPREG0
) >> 2];
988 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
989 ret
= sdhci_read_dataport(s
, size
);
990 trace_sdhci_access("rd", size
<< 3, offset
, "->", ret
, ret
);
996 ret
= FIELD_DP32(ret
, SDHC_PRNSTS
, DAT_LVL
,
997 sdbus_get_dat_lines(&s
->sdbus
));
998 ret
= FIELD_DP32(ret
, SDHC_PRNSTS
, CMD_LVL
,
999 sdbus_get_cmd_line(&s
->sdbus
));
1002 ret
= s
->hostctl1
| (s
->pwrcon
<< 8) | (s
->blkgap
<< 16) |
1006 ret
= s
->clkcon
| (s
->timeoutcon
<< 16);
1008 case SDHC_NORINTSTS
:
1009 ret
= s
->norintsts
| (s
->errintsts
<< 16);
1011 case SDHC_NORINTSTSEN
:
1012 ret
= s
->norintstsen
| (s
->errintstsen
<< 16);
1014 case SDHC_NORINTSIGEN
:
1015 ret
= s
->norintsigen
| (s
->errintsigen
<< 16);
1017 case SDHC_ACMD12ERRSTS
:
1018 ret
= s
->acmd12errsts
| (s
->hostctl2
<< 16);
1021 ret
= (uint32_t)s
->capareg
;
1023 case SDHC_CAPAB
+ 4:
1024 ret
= (uint32_t)(s
->capareg
>> 32);
1027 ret
= (uint32_t)s
->maxcurr
;
1029 case SDHC_MAXCURR
+ 4:
1030 ret
= (uint32_t)(s
->maxcurr
>> 32);
1035 case SDHC_ADMASYSADDR
:
1036 ret
= (uint32_t)s
->admasysaddr
;
1038 case SDHC_ADMASYSADDR
+ 4:
1039 ret
= (uint32_t)(s
->admasysaddr
>> 32);
1041 case SDHC_SLOT_INT_STATUS
:
1042 ret
= (s
->version
<< 16) | sdhci_slotint(s
);
1045 qemu_log_mask(LOG_UNIMP
, "SDHC rd_%ub @0x%02" HWADDR_PRIx
" "
1046 "not implemented\n", size
, offset
);
1050 ret
>>= (offset
& 0x3) * 8;
1051 ret
&= (1ULL << (size
* 8)) - 1;
1052 trace_sdhci_access("rd", size
<< 3, offset
, "->", ret
, ret
);
1056 static inline void sdhci_blkgap_write(SDHCIState
*s
, uint8_t value
)
1058 if ((value
& SDHC_STOP_AT_GAP_REQ
) && (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
)) {
1061 s
->blkgap
= value
& SDHC_STOP_AT_GAP_REQ
;
1063 if ((value
& SDHC_CONTINUE_REQ
) && s
->stopped_state
&&
1064 (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
) == 0) {
1065 if (s
->stopped_state
== sdhc_gap_read
) {
1066 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_READ
;
1067 sdhci_read_block_from_card(s
);
1069 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_WRITE
;
1070 sdhci_write_block_to_card(s
);
1072 s
->stopped_state
= sdhc_not_stopped
;
1073 } else if (!s
->stopped_state
&& (value
& SDHC_STOP_AT_GAP_REQ
)) {
1074 if (s
->prnsts
& SDHC_DOING_READ
) {
1075 s
->stopped_state
= sdhc_gap_read
;
1076 } else if (s
->prnsts
& SDHC_DOING_WRITE
) {
1077 s
->stopped_state
= sdhc_gap_write
;
1082 static inline void sdhci_reset_write(SDHCIState
*s
, uint8_t value
)
1085 case SDHC_RESET_ALL
:
1088 case SDHC_RESET_CMD
:
1089 s
->prnsts
&= ~SDHC_CMD_INHIBIT
;
1090 s
->norintsts
&= ~SDHC_NIS_CMDCMP
;
1092 case SDHC_RESET_DATA
:
1094 s
->prnsts
&= ~(SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
|
1095 SDHC_DOING_READ
| SDHC_DOING_WRITE
|
1096 SDHC_DATA_INHIBIT
| SDHC_DAT_LINE_ACTIVE
);
1097 s
->blkgap
&= ~(SDHC_STOP_AT_GAP_REQ
| SDHC_CONTINUE_REQ
);
1098 s
->stopped_state
= sdhc_not_stopped
;
1099 s
->norintsts
&= ~(SDHC_NIS_WBUFRDY
| SDHC_NIS_RBUFRDY
|
1100 SDHC_NIS_DMA
| SDHC_NIS_TRSCMP
| SDHC_NIS_BLKGAP
);
1106 sdhci_write(void *opaque
, hwaddr offset
, uint64_t val
, unsigned size
)
1108 SDHCIState
*s
= (SDHCIState
*)opaque
;
1109 unsigned shift
= 8 * (offset
& 0x3);
1110 uint32_t mask
= ~(((1ULL << (size
* 8)) - 1) << shift
);
1111 uint32_t value
= val
;
1114 switch (offset
& ~0x3) {
1116 s
->sdmasysad
= (s
->sdmasysad
& mask
) | value
;
1117 MASKED_WRITE(s
->sdmasysad
, mask
, value
);
1118 /* Writing to last byte of sdmasysad might trigger transfer */
1119 if (!(mask
& 0xFF000000) && TRANSFERRING_DATA(s
->prnsts
) && s
->blkcnt
&&
1120 s
->blksize
&& SDHC_DMA_TYPE(s
->hostctl1
) == SDHC_CTRL_SDMA
) {
1121 if (s
->trnmod
& SDHC_TRNS_MULTI
) {
1122 sdhci_sdma_transfer_multi_blocks(s
);
1124 sdhci_sdma_transfer_single_block(s
);
1129 if (!TRANSFERRING_DATA(s
->prnsts
)) {
1130 MASKED_WRITE(s
->blksize
, mask
, value
);
1131 MASKED_WRITE(s
->blkcnt
, mask
>> 16, value
>> 16);
1134 /* Limit block size to the maximum buffer size */
1135 if (extract32(s
->blksize
, 0, 12) > s
->buf_maxsz
) {
1136 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Size 0x%x is larger than " \
1137 "the maximum buffer 0x%x", __func__
, s
->blksize
,
1140 s
->blksize
= deposit32(s
->blksize
, 0, 12, s
->buf_maxsz
);
1145 MASKED_WRITE(s
->argument
, mask
, value
);
1148 /* DMA can be enabled only if it is supported as indicated by
1149 * capabilities register */
1150 if (!(s
->capareg
& R_SDHC_CAPAB_SDMA_MASK
)) {
1151 value
&= ~SDHC_TRNS_DMA
;
1153 MASKED_WRITE(s
->trnmod
, mask
, value
& SDHC_TRNMOD_MASK
);
1154 MASKED_WRITE(s
->cmdreg
, mask
>> 16, value
>> 16);
1156 /* Writing to the upper byte of CMDREG triggers SD command generation */
1157 if ((mask
& 0xFF000000) || !sdhci_can_issue_command(s
)) {
1161 sdhci_send_command(s
);
1164 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
1165 sdhci_write_dataport(s
, value
>> shift
, size
);
1169 if (!(mask
& 0xFF0000)) {
1170 sdhci_blkgap_write(s
, value
>> 16);
1172 MASKED_WRITE(s
->hostctl1
, mask
, value
);
1173 MASKED_WRITE(s
->pwrcon
, mask
>> 8, value
>> 8);
1174 MASKED_WRITE(s
->wakcon
, mask
>> 24, value
>> 24);
1175 if (!(s
->prnsts
& SDHC_CARD_PRESENT
) || ((s
->pwrcon
>> 1) & 0x7) < 5 ||
1176 !(s
->capareg
& (1 << (31 - ((s
->pwrcon
>> 1) & 0x7))))) {
1177 s
->pwrcon
&= ~SDHC_POWER_ON
;
1181 if (!(mask
& 0xFF000000)) {
1182 sdhci_reset_write(s
, value
>> 24);
1184 MASKED_WRITE(s
->clkcon
, mask
, value
);
1185 MASKED_WRITE(s
->timeoutcon
, mask
>> 16, value
>> 16);
1186 if (s
->clkcon
& SDHC_CLOCK_INT_EN
) {
1187 s
->clkcon
|= SDHC_CLOCK_INT_STABLE
;
1189 s
->clkcon
&= ~SDHC_CLOCK_INT_STABLE
;
1192 case SDHC_NORINTSTS
:
1193 if (s
->norintstsen
& SDHC_NISEN_CARDINT
) {
1194 value
&= ~SDHC_NIS_CARDINT
;
1196 s
->norintsts
&= mask
| ~value
;
1197 s
->errintsts
&= (mask
>> 16) | ~(value
>> 16);
1199 s
->norintsts
|= SDHC_NIS_ERR
;
1201 s
->norintsts
&= ~SDHC_NIS_ERR
;
1203 sdhci_update_irq(s
);
1205 case SDHC_NORINTSTSEN
:
1206 MASKED_WRITE(s
->norintstsen
, mask
, value
);
1207 MASKED_WRITE(s
->errintstsen
, mask
>> 16, value
>> 16);
1208 s
->norintsts
&= s
->norintstsen
;
1209 s
->errintsts
&= s
->errintstsen
;
1211 s
->norintsts
|= SDHC_NIS_ERR
;
1213 s
->norintsts
&= ~SDHC_NIS_ERR
;
1215 /* Quirk for Raspberry Pi: pending card insert interrupt
1216 * appears when first enabled after power on */
1217 if ((s
->norintstsen
& SDHC_NISEN_INSERT
) && s
->pending_insert_state
) {
1218 assert(s
->pending_insert_quirk
);
1219 s
->norintsts
|= SDHC_NIS_INSERT
;
1220 s
->pending_insert_state
= false;
1222 sdhci_update_irq(s
);
1224 case SDHC_NORINTSIGEN
:
1225 MASKED_WRITE(s
->norintsigen
, mask
, value
);
1226 MASKED_WRITE(s
->errintsigen
, mask
>> 16, value
>> 16);
1227 sdhci_update_irq(s
);
1230 MASKED_WRITE(s
->admaerr
, mask
, value
);
1232 case SDHC_ADMASYSADDR
:
1233 s
->admasysaddr
= (s
->admasysaddr
& (0xFFFFFFFF00000000ULL
|
1234 (uint64_t)mask
)) | (uint64_t)value
;
1236 case SDHC_ADMASYSADDR
+ 4:
1237 s
->admasysaddr
= (s
->admasysaddr
& (0x00000000FFFFFFFFULL
|
1238 ((uint64_t)mask
<< 32))) | ((uint64_t)value
<< 32);
1241 s
->acmd12errsts
|= value
;
1242 s
->errintsts
|= (value
>> 16) & s
->errintstsen
;
1243 if (s
->acmd12errsts
) {
1244 s
->errintsts
|= SDHC_EIS_CMD12ERR
;
1247 s
->norintsts
|= SDHC_NIS_ERR
;
1249 sdhci_update_irq(s
);
1251 case SDHC_ACMD12ERRSTS
:
1252 MASKED_WRITE(s
->acmd12errsts
, mask
, value
& UINT16_MAX
);
1253 if (s
->uhs_mode
>= UHS_I
) {
1254 MASKED_WRITE(s
->hostctl2
, mask
>> 16, value
>> 16);
1256 if (FIELD_EX32(s
->hostctl2
, SDHC_HOSTCTL2
, V18_ENA
)) {
1257 sdbus_set_voltage(&s
->sdbus
, SD_VOLTAGE_1_8V
);
1259 sdbus_set_voltage(&s
->sdbus
, SD_VOLTAGE_3_3V
);
1265 case SDHC_CAPAB
+ 4:
1267 case SDHC_MAXCURR
+ 4:
1268 qemu_log_mask(LOG_GUEST_ERROR
, "SDHC wr_%ub @0x%02" HWADDR_PRIx
1269 " <- 0x%08x read-only\n", size
, offset
, value
>> shift
);
1273 qemu_log_mask(LOG_UNIMP
, "SDHC wr_%ub @0x%02" HWADDR_PRIx
" <- 0x%08x "
1274 "not implemented\n", size
, offset
, value
>> shift
);
1277 trace_sdhci_access("wr", size
<< 3, offset
, "<-",
1278 value
>> shift
, value
>> shift
);
1281 static const MemoryRegionOps sdhci_mmio_ops
= {
1283 .write
= sdhci_write
,
1285 .min_access_size
= 1,
1286 .max_access_size
= 4,
1289 .endianness
= DEVICE_LITTLE_ENDIAN
,
1292 static void sdhci_init_readonly_registers(SDHCIState
*s
, Error
**errp
)
1294 Error
*local_err
= NULL
;
1296 switch (s
->sd_spec_version
) {
1300 error_setg(errp
, "Only Spec v2/v3 are supported");
1303 s
->version
= (SDHC_HCVER_VENDOR
<< 8) | (s
->sd_spec_version
- 1);
1305 sdhci_check_capareg(s
, &local_err
);
1307 error_propagate(errp
, local_err
);
1312 /* --- qdev common --- */
1314 void sdhci_initfn(SDHCIState
*s
)
1316 qbus_create_inplace(&s
->sdbus
, sizeof(s
->sdbus
),
1317 TYPE_SDHCI_BUS
, DEVICE(s
), "sd-bus");
1319 s
->insert_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_raise_insertion_irq
, s
);
1320 s
->transfer_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_data_transfer
, s
);
1322 s
->io_ops
= &sdhci_mmio_ops
;
1325 void sdhci_uninitfn(SDHCIState
*s
)
1327 timer_del(s
->insert_timer
);
1328 timer_free(s
->insert_timer
);
1329 timer_del(s
->transfer_timer
);
1330 timer_free(s
->transfer_timer
);
1332 g_free(s
->fifo_buffer
);
1333 s
->fifo_buffer
= NULL
;
1336 void sdhci_common_realize(SDHCIState
*s
, Error
**errp
)
1338 Error
*local_err
= NULL
;
1340 sdhci_init_readonly_registers(s
, &local_err
);
1342 error_propagate(errp
, local_err
);
1345 s
->buf_maxsz
= sdhci_get_fifolen(s
);
1346 s
->fifo_buffer
= g_malloc0(s
->buf_maxsz
);
1348 memory_region_init_io(&s
->iomem
, OBJECT(s
), s
->io_ops
, s
, "sdhci",
1349 SDHC_REGISTERS_MAP_SIZE
);
1352 void sdhci_common_unrealize(SDHCIState
*s
, Error
**errp
)
1354 /* This function is expected to be called only once for each class:
1355 * - SysBus: via DeviceClass->unrealize(),
1356 * - PCI: via PCIDeviceClass->exit().
1357 * However to avoid double-free and/or use-after-free we still nullify
1358 * this variable (better safe than sorry!). */
1359 g_free(s
->fifo_buffer
);
1360 s
->fifo_buffer
= NULL
;
1363 static bool sdhci_pending_insert_vmstate_needed(void *opaque
)
1365 SDHCIState
*s
= opaque
;
1367 return s
->pending_insert_state
;
1370 static const VMStateDescription sdhci_pending_insert_vmstate
= {
1371 .name
= "sdhci/pending-insert",
1373 .minimum_version_id
= 1,
1374 .needed
= sdhci_pending_insert_vmstate_needed
,
1375 .fields
= (VMStateField
[]) {
1376 VMSTATE_BOOL(pending_insert_state
, SDHCIState
),
1377 VMSTATE_END_OF_LIST()
1381 const VMStateDescription sdhci_vmstate
= {
1384 .minimum_version_id
= 1,
1385 .fields
= (VMStateField
[]) {
1386 VMSTATE_UINT32(sdmasysad
, SDHCIState
),
1387 VMSTATE_UINT16(blksize
, SDHCIState
),
1388 VMSTATE_UINT16(blkcnt
, SDHCIState
),
1389 VMSTATE_UINT32(argument
, SDHCIState
),
1390 VMSTATE_UINT16(trnmod
, SDHCIState
),
1391 VMSTATE_UINT16(cmdreg
, SDHCIState
),
1392 VMSTATE_UINT32_ARRAY(rspreg
, SDHCIState
, 4),
1393 VMSTATE_UINT32(prnsts
, SDHCIState
),
1394 VMSTATE_UINT8(hostctl1
, SDHCIState
),
1395 VMSTATE_UINT8(pwrcon
, SDHCIState
),
1396 VMSTATE_UINT8(blkgap
, SDHCIState
),
1397 VMSTATE_UINT8(wakcon
, SDHCIState
),
1398 VMSTATE_UINT16(clkcon
, SDHCIState
),
1399 VMSTATE_UINT8(timeoutcon
, SDHCIState
),
1400 VMSTATE_UINT8(admaerr
, SDHCIState
),
1401 VMSTATE_UINT16(norintsts
, SDHCIState
),
1402 VMSTATE_UINT16(errintsts
, SDHCIState
),
1403 VMSTATE_UINT16(norintstsen
, SDHCIState
),
1404 VMSTATE_UINT16(errintstsen
, SDHCIState
),
1405 VMSTATE_UINT16(norintsigen
, SDHCIState
),
1406 VMSTATE_UINT16(errintsigen
, SDHCIState
),
1407 VMSTATE_UINT16(acmd12errsts
, SDHCIState
),
1408 VMSTATE_UINT16(data_count
, SDHCIState
),
1409 VMSTATE_UINT64(admasysaddr
, SDHCIState
),
1410 VMSTATE_UINT8(stopped_state
, SDHCIState
),
1411 VMSTATE_VBUFFER_UINT32(fifo_buffer
, SDHCIState
, 1, NULL
, buf_maxsz
),
1412 VMSTATE_TIMER_PTR(insert_timer
, SDHCIState
),
1413 VMSTATE_TIMER_PTR(transfer_timer
, SDHCIState
),
1414 VMSTATE_END_OF_LIST()
1416 .subsections
= (const VMStateDescription
*[]) {
1417 &sdhci_pending_insert_vmstate
,
1422 void sdhci_common_class_init(ObjectClass
*klass
, void *data
)
1424 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1426 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1427 dc
->vmsd
= &sdhci_vmstate
;
1428 dc
->reset
= sdhci_poweron_reset
;
1431 /* --- qdev SysBus --- */
1433 static Property sdhci_sysbus_properties
[] = {
1434 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState
),
1435 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState
, pending_insert_quirk
,
1437 DEFINE_PROP_LINK("dma", SDHCIState
,
1438 dma_mr
, TYPE_MEMORY_REGION
, MemoryRegion
*),
1439 DEFINE_PROP_END_OF_LIST(),
1442 static void sdhci_sysbus_init(Object
*obj
)
1444 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1449 static void sdhci_sysbus_finalize(Object
*obj
)
1451 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1454 object_unparent(OBJECT(s
->dma_mr
));
1460 static void sdhci_sysbus_realize(DeviceState
*dev
, Error
** errp
)
1462 SDHCIState
*s
= SYSBUS_SDHCI(dev
);
1463 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1464 Error
*local_err
= NULL
;
1466 sdhci_common_realize(s
, &local_err
);
1468 error_propagate(errp
, local_err
);
1473 s
->dma_as
= &s
->sysbus_dma_as
;
1474 address_space_init(s
->dma_as
, s
->dma_mr
, "sdhci-dma");
1476 /* use system_memory() if property "dma" not set */
1477 s
->dma_as
= &address_space_memory
;
1480 sysbus_init_irq(sbd
, &s
->irq
);
1482 sysbus_init_mmio(sbd
, &s
->iomem
);
1485 static void sdhci_sysbus_unrealize(DeviceState
*dev
, Error
**errp
)
1487 SDHCIState
*s
= SYSBUS_SDHCI(dev
);
1489 sdhci_common_unrealize(s
, &error_abort
);
1492 address_space_destroy(s
->dma_as
);
1496 static void sdhci_sysbus_class_init(ObjectClass
*klass
, void *data
)
1498 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1500 dc
->props
= sdhci_sysbus_properties
;
1501 dc
->realize
= sdhci_sysbus_realize
;
1502 dc
->unrealize
= sdhci_sysbus_unrealize
;
1504 sdhci_common_class_init(klass
, data
);
1507 static const TypeInfo sdhci_sysbus_info
= {
1508 .name
= TYPE_SYSBUS_SDHCI
,
1509 .parent
= TYPE_SYS_BUS_DEVICE
,
1510 .instance_size
= sizeof(SDHCIState
),
1511 .instance_init
= sdhci_sysbus_init
,
1512 .instance_finalize
= sdhci_sysbus_finalize
,
1513 .class_init
= sdhci_sysbus_class_init
,
1516 /* --- qdev bus master --- */
1518 static void sdhci_bus_class_init(ObjectClass
*klass
, void *data
)
1520 SDBusClass
*sbc
= SD_BUS_CLASS(klass
);
1522 sbc
->set_inserted
= sdhci_set_inserted
;
1523 sbc
->set_readonly
= sdhci_set_readonly
;
1526 static const TypeInfo sdhci_bus_info
= {
1527 .name
= TYPE_SDHCI_BUS
,
1528 .parent
= TYPE_SD_BUS
,
1529 .instance_size
= sizeof(SDBus
),
1530 .class_init
= sdhci_bus_class_init
,
1533 static uint64_t usdhc_read(void *opaque
, hwaddr offset
, unsigned size
)
1535 SDHCIState
*s
= SYSBUS_SDHCI(opaque
);
1541 return sdhci_read(opaque
, offset
, size
);
1545 * For a detailed explanation on the following bit
1546 * manipulation code see comments in a similar part of
1549 hostctl1
= SDHC_DMA_TYPE(s
->hostctl1
) << (8 - 3);
1551 if (s
->hostctl1
& SDHC_CTRL_8BITBUS
) {
1552 hostctl1
|= ESDHC_CTRL_8BITBUS
;
1555 if (s
->hostctl1
& SDHC_CTRL_4BITBUS
) {
1556 hostctl1
|= ESDHC_CTRL_4BITBUS
;
1560 ret
|= (uint32_t)s
->blkgap
<< 16;
1561 ret
|= (uint32_t)s
->wakcon
<< 24;
1566 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
1567 ret
= sdhci_read(opaque
, offset
, size
) & ~ESDHC_PRNSTS_SDSTB
;
1568 if (s
->clkcon
& SDHC_CLOCK_INT_STABLE
) {
1569 ret
|= ESDHC_PRNSTS_SDSTB
;
1573 case ESDHC_DLL_CTRL
:
1574 case ESDHC_TUNE_CTRL_STATUS
:
1575 case ESDHC_UNDOCUMENTED_REG27
:
1576 case ESDHC_TUNING_CTRL
:
1577 case ESDHC_VENDOR_SPEC
:
1578 case ESDHC_MIX_CTRL
:
1579 case ESDHC_WTMK_LVL
:
1588 usdhc_write(void *opaque
, hwaddr offset
, uint64_t val
, unsigned size
)
1590 SDHCIState
*s
= SYSBUS_SDHCI(opaque
);
1592 uint32_t value
= (uint32_t)val
;
1595 case ESDHC_DLL_CTRL
:
1596 case ESDHC_TUNE_CTRL_STATUS
:
1597 case ESDHC_UNDOCUMENTED_REG27
:
1598 case ESDHC_TUNING_CTRL
:
1599 case ESDHC_WTMK_LVL
:
1600 case ESDHC_VENDOR_SPEC
:
1605 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL)
1608 * |-----------+--------+--------+-----------+----------+---------|
1609 * | Card | Card | Endian | DATA3 | Data | Led |
1610 * | Detect | Detect | Mode | as Card | Transfer | Control |
1611 * | Signal | Test | | Detection | Width | |
1612 * | Selection | Level | | Pin | | |
1613 * |-----------+--------+--------+-----------+----------+---------|
1618 * |----------+------|
1619 * | Reserved | DMA |
1622 * |----------+------|
1624 * and here's what SDCHI spec expects those offsets to be:
1626 * 0x28 (Host Control Register)
1629 * |--------+--------+----------+------+--------+----------+---------|
1630 * | Card | Card | Extended | DMA | High | Data | LED |
1631 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control |
1632 * | Signal | Test | Transfer | | Enable | Width | |
1633 * | Sel. | Level | Width | | | | |
1634 * |--------+--------+----------+------+--------+----------+---------|
1636 * and 0x29 (Power Control Register)
1638 * |----------------------------------|
1639 * | Power Control Register |
1641 * | Description omitted, |
1642 * | since it has no analog in ESDHCI |
1644 * |----------------------------------|
1646 * Since offsets 0x2A and 0x2B should be compatible between
1647 * both IP specs we only need to reconcile least 16-bit of the
1648 * word we've been given.
1652 * First, save bits 7 6 and 0 since they are identical
1654 hostctl1
= value
& (SDHC_CTRL_LED
|
1655 SDHC_CTRL_CDTEST_INS
|
1656 SDHC_CTRL_CDTEST_EN
);
1658 * Second, split "Data Transfer Width" from bits 2 and 1 in to
1661 if (value
& ESDHC_CTRL_8BITBUS
) {
1662 hostctl1
|= SDHC_CTRL_8BITBUS
;
1665 if (value
& ESDHC_CTRL_4BITBUS
) {
1666 hostctl1
|= ESDHC_CTRL_4BITBUS
;
1670 * Third, move DMA select from bits 9 and 8 to bits 4 and 3
1672 hostctl1
|= SDHC_DMA_TYPE(value
>> (8 - 3));
1675 * Now place the corrected value into low 16-bit of the value
1676 * we are going to give standard SDHCI write function
1678 * NOTE: This transformation should be the inverse of what can
1679 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux
1682 value
&= ~UINT16_MAX
;
1684 value
|= (uint16_t)s
->pwrcon
<< 8;
1686 sdhci_write(opaque
, offset
, value
, size
);
1689 case ESDHC_MIX_CTRL
:
1691 * So, when SD/MMC stack in Linux tries to write to "Transfer
1692 * Mode Register", ESDHC i.MX quirk code will translate it
1693 * into a write to ESDHC_MIX_CTRL, so we do the opposite in
1694 * order to get where we started
1696 * Note that Auto CMD23 Enable bit is located in a wrong place
1697 * on i.MX, but since it is not used by QEMU we do not care.
1699 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
1700 * here becuase it will result in a call to
1701 * sdhci_send_command(s) which we don't want.
1704 s
->trnmod
= value
& UINT16_MAX
;
1708 * Similar to above, but this time a write to "Command
1709 * Register" will be translated into a 4-byte write to
1710 * "Transfer Mode register" where lower 16-bit of value would
1711 * be set to zero. So what we do is fill those bits with
1712 * cached value from s->trnmod and let the SDHCI
1713 * infrastructure handle the rest
1715 sdhci_write(opaque
, offset
, val
| s
->trnmod
, size
);
1719 * ESDHCI does not implement "Host SDMA Buffer Boundary", and
1720 * Linux driver will try to zero this field out which will
1721 * break the rest of SDHCI emulation.
1723 * Linux defaults to maximum possible setting (512K boundary)
1724 * and it seems to be the only option that i.MX IP implements,
1725 * so we artificially set it to that value.
1730 sdhci_write(opaque
, offset
, val
, size
);
1736 static const MemoryRegionOps usdhc_mmio_ops
= {
1738 .write
= usdhc_write
,
1740 .min_access_size
= 1,
1741 .max_access_size
= 4,
1744 .endianness
= DEVICE_LITTLE_ENDIAN
,
1747 static void imx_usdhc_init(Object
*obj
)
1749 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1751 s
->io_ops
= &usdhc_mmio_ops
;
1752 s
->quirks
= SDHCI_QUIRK_NO_BUSY_IRQ
;
1755 static const TypeInfo imx_usdhc_info
= {
1756 .name
= TYPE_IMX_USDHC
,
1757 .parent
= TYPE_SYSBUS_SDHCI
,
1758 .instance_init
= imx_usdhc_init
,
1761 static void sdhci_register_types(void)
1763 type_register_static(&sdhci_sysbus_info
);
1764 type_register_static(&sdhci_bus_info
);
1765 type_register_static(&imx_usdhc_info
);
1768 type_init(sdhci_register_types
)