?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
hw/timer/armv7m_systick: Forbid non-privileged accesses
[qemu/ar7.git] / hw / arm / aspeed_soc.c
blobc6fb3700f27ea871097846af29896ce219b4dd21
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "cpu.h"
16 #include "exec/address-spaces.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
20 #include "qemu/log.h"
21 #include "qemu/module.h"
22 #include "qemu/error-report.h"
23 #include "hw/i2c/aspeed_i2c.h"
24 #include "net/net.h"
25
26 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
27
28 static const hwaddr aspeed_soc_ast2400_memmap[] = {
29 [ASPEED_IOMEM] = 0x1E600000,
30 [ASPEED_FMC] = 0x1E620000,
31 [ASPEED_SPI1] = 0x1E630000,
32 [ASPEED_VIC] = 0x1E6C0000,
33 [ASPEED_SDMC] = 0x1E6E0000,
34 [ASPEED_SCU] = 0x1E6E2000,
35 [ASPEED_XDMA] = 0x1E6E7000,
36 [ASPEED_ADC] = 0x1E6E9000,
37 [ASPEED_SRAM] = 0x1E720000,
38 [ASPEED_GPIO] = 0x1E780000,
39 [ASPEED_RTC] = 0x1E781000,
40 [ASPEED_TIMER1] = 0x1E782000,
41 [ASPEED_WDT] = 0x1E785000,
42 [ASPEED_PWM] = 0x1E786000,
43 [ASPEED_LPC] = 0x1E789000,
44 [ASPEED_IBT] = 0x1E789140,
45 [ASPEED_I2C] = 0x1E78A000,
46 [ASPEED_ETH1] = 0x1E660000,
47 [ASPEED_ETH2] = 0x1E680000,
48 [ASPEED_UART1] = 0x1E783000,
49 [ASPEED_UART5] = 0x1E784000,
50 [ASPEED_VUART] = 0x1E787000,
51 [ASPEED_SDRAM] = 0x40000000,
52 };
53
54 static const hwaddr aspeed_soc_ast2500_memmap[] = {
55 [ASPEED_IOMEM] = 0x1E600000,
56 [ASPEED_FMC] = 0x1E620000,
57 [ASPEED_SPI1] = 0x1E630000,
58 [ASPEED_SPI2] = 0x1E631000,
59 [ASPEED_VIC] = 0x1E6C0000,
60 [ASPEED_SDMC] = 0x1E6E0000,
61 [ASPEED_SCU] = 0x1E6E2000,
62 [ASPEED_XDMA] = 0x1E6E7000,
63 [ASPEED_ADC] = 0x1E6E9000,
64 [ASPEED_SRAM] = 0x1E720000,
65 [ASPEED_GPIO] = 0x1E780000,
66 [ASPEED_RTC] = 0x1E781000,
67 [ASPEED_TIMER1] = 0x1E782000,
68 [ASPEED_WDT] = 0x1E785000,
69 [ASPEED_PWM] = 0x1E786000,
70 [ASPEED_LPC] = 0x1E789000,
71 [ASPEED_IBT] = 0x1E789140,
72 [ASPEED_I2C] = 0x1E78A000,
73 [ASPEED_ETH1] = 0x1E660000,
74 [ASPEED_ETH2] = 0x1E680000,
75 [ASPEED_UART1] = 0x1E783000,
76 [ASPEED_UART5] = 0x1E784000,
77 [ASPEED_VUART] = 0x1E787000,
78 [ASPEED_SDRAM] = 0x80000000,
79 };
80
81 static const int aspeed_soc_ast2400_irqmap[] = {
82 [ASPEED_UART1] = 9,
83 [ASPEED_UART2] = 32,
84 [ASPEED_UART3] = 33,
85 [ASPEED_UART4] = 34,
86 [ASPEED_UART5] = 10,
87 [ASPEED_VUART] = 8,
88 [ASPEED_FMC] = 19,
89 [ASPEED_SDMC] = 0,
90 [ASPEED_SCU] = 21,
91 [ASPEED_ADC] = 31,
92 [ASPEED_GPIO] = 20,
93 [ASPEED_RTC] = 22,
94 [ASPEED_TIMER1] = 16,
95 [ASPEED_TIMER2] = 17,
96 [ASPEED_TIMER3] = 18,
97 [ASPEED_TIMER4] = 35,
98 [ASPEED_TIMER5] = 36,
99 [ASPEED_TIMER6] = 37,
100 [ASPEED_TIMER7] = 38,
101 [ASPEED_TIMER8] = 39,
102 [ASPEED_WDT] = 27,
103 [ASPEED_PWM] = 28,
104 [ASPEED_LPC] = 8,
105 [ASPEED_IBT] = 8, /* LPC */
106 [ASPEED_I2C] = 12,
107 [ASPEED_ETH1] = 2,
108 [ASPEED_ETH2] = 3,
109 [ASPEED_XDMA] = 6,
110 };
111
112 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
113
114 static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
115 static const char *aspeed_soc_ast2500_typenames[] = {
116 "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
117
118 static const AspeedSoCInfo aspeed_socs[] = {
119 {
120 .name = "ast2400-a0",
121 .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
122 .silicon_rev = AST2400_A0_SILICON_REV,
123 .sram_size = 0x8000,
124 .spis_num = 1,
125 .fmc_typename = "aspeed.smc.fmc",
126 .spi_typename = aspeed_soc_ast2400_typenames,
127 .wdts_num = 2,
128 .irqmap = aspeed_soc_ast2400_irqmap,
129 .memmap = aspeed_soc_ast2400_memmap,
130 .num_cpus = 1,
131 }, {
132 .name = "ast2400-a1",
133 .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
134 .silicon_rev = AST2400_A1_SILICON_REV,
135 .sram_size = 0x8000,
136 .spis_num = 1,
137 .fmc_typename = "aspeed.smc.fmc",
138 .spi_typename = aspeed_soc_ast2400_typenames,
139 .wdts_num = 2,
140 .irqmap = aspeed_soc_ast2400_irqmap,
141 .memmap = aspeed_soc_ast2400_memmap,
142 .num_cpus = 1,
143 }, {
144 .name = "ast2400",
145 .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
146 .silicon_rev = AST2400_A0_SILICON_REV,
147 .sram_size = 0x8000,
148 .spis_num = 1,
149 .fmc_typename = "aspeed.smc.fmc",
150 .spi_typename = aspeed_soc_ast2400_typenames,
151 .wdts_num = 2,
152 .irqmap = aspeed_soc_ast2400_irqmap,
153 .memmap = aspeed_soc_ast2400_memmap,
154 .num_cpus = 1,
155 }, {
156 .name = "ast2500-a1",
157 .cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
158 .silicon_rev = AST2500_A1_SILICON_REV,
159 .sram_size = 0x9000,
160 .spis_num = 2,
161 .fmc_typename = "aspeed.smc.ast2500-fmc",
162 .spi_typename = aspeed_soc_ast2500_typenames,
163 .wdts_num = 3,
164 .irqmap = aspeed_soc_ast2500_irqmap,
165 .memmap = aspeed_soc_ast2500_memmap,
166 .num_cpus = 1,
167 },
168 };
169
170 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
171 {
172 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
173
174 return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]);
175 }
176
177 static void aspeed_soc_init(Object *obj)
178 {
179 AspeedSoCState *s = ASPEED_SOC(obj);
180 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
181 int i;
182
183 for (i = 0; i < sc->info->num_cpus; i++) {
184 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
185 sizeof(s->cpu[i]), sc->info->cpu_type,
186 &error_abort, NULL);
187 }
188
189 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
190 TYPE_ASPEED_SCU);
191 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
192 sc->info->silicon_rev);
193 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
194 "hw-strap1", &error_abort);
195 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
196 "hw-strap2", &error_abort);
197 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
198 "hw-prot-key", &error_abort);
199
200 sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
201 TYPE_ASPEED_VIC);
202
203 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
204 TYPE_ASPEED_RTC);
205
206 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
207 sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
208 object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
209 OBJECT(&s->scu), &error_abort);
210
211 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
212 TYPE_ASPEED_I2C);
213
214 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
215 sc->info->fmc_typename);
216 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
217 &error_abort);
218
219 for (i = 0; i < sc->info->spis_num; i++) {
220 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
221 sizeof(s->spi[i]), sc->info->spi_typename[i]);
222 }
223
224 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
225 TYPE_ASPEED_SDMC);
226 qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
227 sc->info->silicon_rev);
228 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
229 "ram-size", &error_abort);
230 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
231 "max-ram-size", &error_abort);
232
233 for (i = 0; i < sc->info->wdts_num; i++) {
234 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
235 sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
236 qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
237 sc->info->silicon_rev);
238 object_property_add_const_link(OBJECT(&s->wdt[i]), "scu",
239 OBJECT(&s->scu), &error_abort);
240 }
241
242 for (i = 0; i < ASPEED_MACS_NUM; i++) {
243 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
244 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
245 }
246
247 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
248 TYPE_ASPEED_XDMA);
249 }
250
251 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
252 {
253 int i;
254 AspeedSoCState *s = ASPEED_SOC(dev);
255 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
256 Error *err = NULL, *local_err = NULL;
257
258 /* IO space */
259 create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
260 ASPEED_SOC_IOMEM_SIZE);
261
262 if (s->num_cpus > sc->info->num_cpus) {
263 warn_report("%s: invalid number of CPUs %d, using default %d",
264 sc->info->name, s->num_cpus, sc->info->num_cpus);
265 s->num_cpus = sc->info->num_cpus;
266 }
267
268 /* CPU */
269 for (i = 0; i < s->num_cpus; i++) {
270 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
271 if (err) {
272 error_propagate(errp, err);
273 return;
274 }
275 }
276
277 /* SRAM */
278 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
279 sc->info->sram_size, &err);
280 if (err) {
281 error_propagate(errp, err);
282 return;
283 }
284 memory_region_add_subregion(get_system_memory(),
285 sc->info->memmap[ASPEED_SRAM], &s->sram);
286
287 /* SCU */
288 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
289 if (err) {
290 error_propagate(errp, err);
291 return;
292 }
293 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]);
294
295 /* VIC */
296 object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
297 if (err) {
298 error_propagate(errp, err);
299 return;
300 }
301 sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]);
302 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
303 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
304 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
305 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
306
307 /* RTC */
308 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
309 if (err) {
310 error_propagate(errp, err);
311 return;
312 }
313 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]);
314 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
315 aspeed_soc_get_irq(s, ASPEED_RTC));
316
317 /* Timer */
318 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
319 if (err) {
320 error_propagate(errp, err);
321 return;
322 }
323 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
324 sc->info->memmap[ASPEED_TIMER1]);
325 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
326 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
327 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
328 }
329
330 /* UART - attach an 8250 to the IO space as our UART5 */
331 if (serial_hd(0)) {
332 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
333 serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2,
334 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
335 }
336
337 /* I2C */
338 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
339 if (err) {
340 error_propagate(errp, err);
341 return;
342 }
343 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]);
344 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
345 aspeed_soc_get_irq(s, ASPEED_I2C));
346
347 /* FMC, The number of CS is set at the board level */
348 object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM],
349 "sdram-base", &err);
350 if (err) {
351 error_propagate(errp, err);
352 return;
353 }
354 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
355 if (err) {
356 error_propagate(errp, err);
357 return;
358 }
359 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]);
360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
361 s->fmc.ctrl->flash_window_base);
362 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
363 aspeed_soc_get_irq(s, ASPEED_FMC));
364
365 /* SPI */
366 for (i = 0; i < sc->info->spis_num; i++) {
367 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
368 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
369 &local_err);
370 error_propagate(&err, local_err);
371 if (err) {
372 error_propagate(errp, err);
373 return;
374 }
375 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
376 sc->info->memmap[ASPEED_SPI1 + i]);
377 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
378 s->spi[i].ctrl->flash_window_base);
379 }
380
381 /* SDMC - SDRAM Memory Controller */
382 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
383 if (err) {
384 error_propagate(errp, err);
385 return;
386 }
387 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]);
388
389 /* Watch dog */
390 for (i = 0; i < sc->info->wdts_num; i++) {
391 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
392 if (err) {
393 error_propagate(errp, err);
394 return;
395 }
396 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
397 sc->info->memmap[ASPEED_WDT] + i * 0x20);
398 }
399
400 /* Net */
401 for (i = 0; i < nb_nics; i++) {
402 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
403 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
404 &err);
405 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
406 &local_err);
407 error_propagate(&err, local_err);
408 if (err) {
409 error_propagate(errp, err);
410 return;
411 }
412 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
413 sc->info->memmap[ASPEED_ETH1 + i]);
414 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
415 aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
416 }
417
418 /* XDMA */
419 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
420 if (err) {
421 error_propagate(errp, err);
422 return;
423 }
424 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
425 sc->info->memmap[ASPEED_XDMA]);
426 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
427 aspeed_soc_get_irq(s, ASPEED_XDMA));
428 }
429 static Property aspeed_soc_properties[] = {
430 DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
431 DEFINE_PROP_END_OF_LIST(),
432 };
433
434 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
435 {
436 DeviceClass *dc = DEVICE_CLASS(oc);
437 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
438
439 sc->info = (AspeedSoCInfo *) data;
440 dc->realize = aspeed_soc_realize;
441 /* Reason: Uses serial_hds and nd_table in realize() directly */
442 dc->user_creatable = false;
443 dc->props = aspeed_soc_properties;
444 }
445
446 static const TypeInfo aspeed_soc_type_info = {
447 .name = TYPE_ASPEED_SOC,
448 .parent = TYPE_DEVICE,
449 .instance_init = aspeed_soc_init,
450 .instance_size = sizeof(AspeedSoCState),
451 .class_size = sizeof(AspeedSoCClass),
452 .abstract = true,
453 };
454
455 static void aspeed_soc_register_types(void)
456 {
457 int i;
458
459 type_register_static(&aspeed_soc_type_info);
460 for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
461 TypeInfo ti = {
462 .name = aspeed_socs[i].name,
463 .parent = TYPE_ASPEED_SOC,
464 .class_init = aspeed_soc_class_init,
465 .class_data = (void *) &aspeed_socs[i],
466 };
467 type_register(&ti);
468 }
469 }
470
471 type_init(aspeed_soc_register_types)
AR7 emulation for QEMU