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sysbus: Drop useless OBJECT() in sysbus_init_child_obj() calls
[qemu/ar7.git] / hw / arm / aspeed_soc.c
blob5806e5c9b42e74c88b9f49452f18aa1cba49069a
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "cpu.h"
16 #include "exec/address-spaces.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
20 #include "qemu/log.h"
21 #include "qemu/module.h"
22 #include "qemu/error-report.h"
23 #include "hw/i2c/aspeed_i2c.h"
24 #include "net/net.h"
25 #include "sysemu/sysemu.h"
26
27 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
28
29 static const hwaddr aspeed_soc_ast2400_memmap[] = {
30 [ASPEED_IOMEM] = 0x1E600000,
31 [ASPEED_FMC] = 0x1E620000,
32 [ASPEED_SPI1] = 0x1E630000,
33 [ASPEED_EHCI1] = 0x1E6A1000,
34 [ASPEED_VIC] = 0x1E6C0000,
35 [ASPEED_SDMC] = 0x1E6E0000,
36 [ASPEED_SCU] = 0x1E6E2000,
37 [ASPEED_XDMA] = 0x1E6E7000,
38 [ASPEED_VIDEO] = 0x1E700000,
39 [ASPEED_ADC] = 0x1E6E9000,
40 [ASPEED_SRAM] = 0x1E720000,
41 [ASPEED_SDHCI] = 0x1E740000,
42 [ASPEED_GPIO] = 0x1E780000,
43 [ASPEED_RTC] = 0x1E781000,
44 [ASPEED_TIMER1] = 0x1E782000,
45 [ASPEED_WDT] = 0x1E785000,
46 [ASPEED_PWM] = 0x1E786000,
47 [ASPEED_LPC] = 0x1E789000,
48 [ASPEED_IBT] = 0x1E789140,
49 [ASPEED_I2C] = 0x1E78A000,
50 [ASPEED_ETH1] = 0x1E660000,
51 [ASPEED_ETH2] = 0x1E680000,
52 [ASPEED_UART1] = 0x1E783000,
53 [ASPEED_UART5] = 0x1E784000,
54 [ASPEED_VUART] = 0x1E787000,
55 [ASPEED_SDRAM] = 0x40000000,
56 };
57
58 static const hwaddr aspeed_soc_ast2500_memmap[] = {
59 [ASPEED_IOMEM] = 0x1E600000,
60 [ASPEED_FMC] = 0x1E620000,
61 [ASPEED_SPI1] = 0x1E630000,
62 [ASPEED_SPI2] = 0x1E631000,
63 [ASPEED_EHCI1] = 0x1E6A1000,
64 [ASPEED_EHCI2] = 0x1E6A3000,
65 [ASPEED_VIC] = 0x1E6C0000,
66 [ASPEED_SDMC] = 0x1E6E0000,
67 [ASPEED_SCU] = 0x1E6E2000,
68 [ASPEED_XDMA] = 0x1E6E7000,
69 [ASPEED_ADC] = 0x1E6E9000,
70 [ASPEED_VIDEO] = 0x1E700000,
71 [ASPEED_SRAM] = 0x1E720000,
72 [ASPEED_SDHCI] = 0x1E740000,
73 [ASPEED_GPIO] = 0x1E780000,
74 [ASPEED_RTC] = 0x1E781000,
75 [ASPEED_TIMER1] = 0x1E782000,
76 [ASPEED_WDT] = 0x1E785000,
77 [ASPEED_PWM] = 0x1E786000,
78 [ASPEED_LPC] = 0x1E789000,
79 [ASPEED_IBT] = 0x1E789140,
80 [ASPEED_I2C] = 0x1E78A000,
81 [ASPEED_ETH1] = 0x1E660000,
82 [ASPEED_ETH2] = 0x1E680000,
83 [ASPEED_UART1] = 0x1E783000,
84 [ASPEED_UART5] = 0x1E784000,
85 [ASPEED_VUART] = 0x1E787000,
86 [ASPEED_SDRAM] = 0x80000000,
87 };
88
89 static const int aspeed_soc_ast2400_irqmap[] = {
90 [ASPEED_UART1] = 9,
91 [ASPEED_UART2] = 32,
92 [ASPEED_UART3] = 33,
93 [ASPEED_UART4] = 34,
94 [ASPEED_UART5] = 10,
95 [ASPEED_VUART] = 8,
96 [ASPEED_FMC] = 19,
97 [ASPEED_EHCI1] = 5,
98 [ASPEED_EHCI2] = 13,
99 [ASPEED_SDMC] = 0,
100 [ASPEED_SCU] = 21,
101 [ASPEED_ADC] = 31,
102 [ASPEED_GPIO] = 20,
103 [ASPEED_RTC] = 22,
104 [ASPEED_TIMER1] = 16,
105 [ASPEED_TIMER2] = 17,
106 [ASPEED_TIMER3] = 18,
107 [ASPEED_TIMER4] = 35,
108 [ASPEED_TIMER5] = 36,
109 [ASPEED_TIMER6] = 37,
110 [ASPEED_TIMER7] = 38,
111 [ASPEED_TIMER8] = 39,
112 [ASPEED_WDT] = 27,
113 [ASPEED_PWM] = 28,
114 [ASPEED_LPC] = 8,
115 [ASPEED_IBT] = 8, /* LPC */
116 [ASPEED_I2C] = 12,
117 [ASPEED_ETH1] = 2,
118 [ASPEED_ETH2] = 3,
119 [ASPEED_XDMA] = 6,
120 [ASPEED_SDHCI] = 26,
121 };
122
123 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
124
125 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
126 {
127 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
128
129 return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]);
130 }
131
132 static void aspeed_soc_init(Object *obj)
133 {
134 AspeedSoCState *s = ASPEED_SOC(obj);
135 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
136 int i;
137 char socname[8];
138 char typename[64];
139
140 if (sscanf(sc->name, "%7s", socname) != 1) {
141 g_assert_not_reached();
142 }
143
144 for (i = 0; i < sc->num_cpus; i++) {
145 object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
146 }
147
148 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
149 sysbus_init_child_obj(obj, "scu", &s->scu, sizeof(s->scu), typename);
150 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
151 sc->silicon_rev);
152 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
153 "hw-strap1");
154 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
155 "hw-strap2");
156 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
157 "hw-prot-key");
158
159 sysbus_init_child_obj(obj, "vic", &s->vic, sizeof(s->vic),
160 TYPE_ASPEED_VIC);
161
162 sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
163 TYPE_ASPEED_RTC);
164
165 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
166 sysbus_init_child_obj(obj, "timerctrl", &s->timerctrl,
167 sizeof(s->timerctrl), typename);
168
169 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
170 sysbus_init_child_obj(obj, "i2c", &s->i2c, sizeof(s->i2c), typename);
171
172 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
173 sysbus_init_child_obj(obj, "fmc", &s->fmc, sizeof(s->fmc), typename);
174 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
175
176 for (i = 0; i < sc->spis_num; i++) {
177 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
178 sysbus_init_child_obj(obj, "spi[*]", &s->spi[i],
179 sizeof(s->spi[i]), typename);
180 }
181
182 for (i = 0; i < sc->ehcis_num; i++) {
183 sysbus_init_child_obj(obj, "ehci[*]", &s->ehci[i],
184 sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
185 }
186
187 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
188 sysbus_init_child_obj(obj, "sdmc", &s->sdmc, sizeof(s->sdmc), typename);
189 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
190 "ram-size");
191 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
192 "max-ram-size");
193
194 for (i = 0; i < sc->wdts_num; i++) {
195 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
196 sysbus_init_child_obj(obj, "wdt[*]", &s->wdt[i],
197 sizeof(s->wdt[i]), typename);
198 }
199
200 for (i = 0; i < sc->macs_num; i++) {
201 sysbus_init_child_obj(obj, "ftgmac100[*]", &s->ftgmac100[i],
202 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
203 }
204
205 sysbus_init_child_obj(obj, "xdma", &s->xdma, sizeof(s->xdma),
206 TYPE_ASPEED_XDMA);
207
208 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
209 sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), typename);
210
211 sysbus_init_child_obj(obj, "sdc", &s->sdhci, sizeof(s->sdhci),
212 TYPE_ASPEED_SDHCI);
213
214 object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
215
216 /* Init sd card slot class here so that they're under the correct parent */
217 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
218 sysbus_init_child_obj(obj, "sdhci[*]", &s->sdhci.slots[i],
219 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
220 }
221 }
222
223 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
224 {
225 int i;
226 AspeedSoCState *s = ASPEED_SOC(dev);
227 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
228 Error *err = NULL, *local_err = NULL;
229
230 /* IO space */
231 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
232 ASPEED_SOC_IOMEM_SIZE);
233
234 /* Video engine stub */
235 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
236 0x1000);
237
238 /* CPU */
239 for (i = 0; i < sc->num_cpus; i++) {
240 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
241 if (err) {
242 error_propagate(errp, err);
243 return;
244 }
245 }
246
247 /* SRAM */
248 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
249 sc->sram_size, &err);
250 if (err) {
251 error_propagate(errp, err);
252 return;
253 }
254 memory_region_add_subregion(get_system_memory(),
255 sc->memmap[ASPEED_SRAM], &s->sram);
256
257 /* SCU */
258 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
259 if (err) {
260 error_propagate(errp, err);
261 return;
262 }
263 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
264
265 /* VIC */
266 object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
267 if (err) {
268 error_propagate(errp, err);
269 return;
270 }
271 sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]);
272 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
273 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
274 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
275 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
276
277 /* RTC */
278 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
279 if (err) {
280 error_propagate(errp, err);
281 return;
282 }
283 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
284 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
285 aspeed_soc_get_irq(s, ASPEED_RTC));
286
287 /* Timer */
288 object_property_set_link(OBJECT(&s->timerctrl),
289 OBJECT(&s->scu), "scu", &error_abort);
290 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
291 if (err) {
292 error_propagate(errp, err);
293 return;
294 }
295 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
296 sc->memmap[ASPEED_TIMER1]);
297 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
298 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
299 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
300 }
301
302 /* UART - attach an 8250 to the IO space as our UART5 */
303 if (serial_hd(0)) {
304 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
305 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
306 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
307 }
308
309 /* I2C */
310 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
311 if (err) {
312 error_propagate(errp, err);
313 return;
314 }
315 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
316 if (err) {
317 error_propagate(errp, err);
318 return;
319 }
320 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
321 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
322 aspeed_soc_get_irq(s, ASPEED_I2C));
323
324 /* FMC, The number of CS is set at the board level */
325 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
326 if (err) {
327 error_propagate(errp, err);
328 return;
329 }
330 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
331 "sdram-base", &err);
332 if (err) {
333 error_propagate(errp, err);
334 return;
335 }
336 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
337 if (err) {
338 error_propagate(errp, err);
339 return;
340 }
341 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
342 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
343 s->fmc.ctrl->flash_window_base);
344 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
345 aspeed_soc_get_irq(s, ASPEED_FMC));
346
347 /* SPI */
348 for (i = 0; i < sc->spis_num; i++) {
349 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
350 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
351 &local_err);
352 error_propagate(&err, local_err);
353 if (err) {
354 error_propagate(errp, err);
355 return;
356 }
357 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
358 sc->memmap[ASPEED_SPI1 + i]);
359 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
360 s->spi[i].ctrl->flash_window_base);
361 }
362
363 /* EHCI */
364 for (i = 0; i < sc->ehcis_num; i++) {
365 object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
366 if (err) {
367 error_propagate(errp, err);
368 return;
369 }
370 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
371 sc->memmap[ASPEED_EHCI1 + i]);
372 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
373 aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
374 }
375
376 /* SDMC - SDRAM Memory Controller */
377 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
378 if (err) {
379 error_propagate(errp, err);
380 return;
381 }
382 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
383
384 /* Watch dog */
385 for (i = 0; i < sc->wdts_num; i++) {
386 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
387
388 object_property_set_link(OBJECT(&s->wdt[i]),
389 OBJECT(&s->scu), "scu", &error_abort);
390 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
391 if (err) {
392 error_propagate(errp, err);
393 return;
394 }
395 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
396 sc->memmap[ASPEED_WDT] + i * awc->offset);
397 }
398
399 /* Net */
400 for (i = 0; i < sc->macs_num; i++) {
401 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
402 &err);
403 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
404 &local_err);
405 error_propagate(&err, local_err);
406 if (err) {
407 error_propagate(errp, err);
408 return;
409 }
410 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
411 sc->memmap[ASPEED_ETH1 + i]);
412 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
413 aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
414 }
415
416 /* XDMA */
417 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
418 if (err) {
419 error_propagate(errp, err);
420 return;
421 }
422 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
423 sc->memmap[ASPEED_XDMA]);
424 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
425 aspeed_soc_get_irq(s, ASPEED_XDMA));
426
427 /* GPIO */
428 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
429 if (err) {
430 error_propagate(errp, err);
431 return;
432 }
433 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
434 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
435 aspeed_soc_get_irq(s, ASPEED_GPIO));
436
437 /* SDHCI */
438 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
439 if (err) {
440 error_propagate(errp, err);
441 return;
442 }
443 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
444 sc->memmap[ASPEED_SDHCI]);
445 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
446 aspeed_soc_get_irq(s, ASPEED_SDHCI));
447 }
448 static Property aspeed_soc_properties[] = {
449 DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
450 MemoryRegion *),
451 DEFINE_PROP_END_OF_LIST(),
452 };
453
454 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
455 {
456 DeviceClass *dc = DEVICE_CLASS(oc);
457
458 dc->realize = aspeed_soc_realize;
459 /* Reason: Uses serial_hds and nd_table in realize() directly */
460 dc->user_creatable = false;
461 device_class_set_props(dc, aspeed_soc_properties);
462 }
463
464 static const TypeInfo aspeed_soc_type_info = {
465 .name = TYPE_ASPEED_SOC,
466 .parent = TYPE_DEVICE,
467 .instance_size = sizeof(AspeedSoCState),
468 .class_size = sizeof(AspeedSoCClass),
469 .class_init = aspeed_soc_class_init,
470 .abstract = true,
471 };
472
473 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
474 {
475 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
476
477 sc->name = "ast2400-a1";
478 sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
479 sc->silicon_rev = AST2400_A1_SILICON_REV;
480 sc->sram_size = 0x8000;
481 sc->spis_num = 1;
482 sc->ehcis_num = 1;
483 sc->wdts_num = 2;
484 sc->macs_num = 2;
485 sc->irqmap = aspeed_soc_ast2400_irqmap;
486 sc->memmap = aspeed_soc_ast2400_memmap;
487 sc->num_cpus = 1;
488 }
489
490 static const TypeInfo aspeed_soc_ast2400_type_info = {
491 .name = "ast2400-a1",
492 .parent = TYPE_ASPEED_SOC,
493 .instance_init = aspeed_soc_init,
494 .instance_size = sizeof(AspeedSoCState),
495 .class_init = aspeed_soc_ast2400_class_init,
496 };
497
498 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
499 {
500 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
501
502 sc->name = "ast2500-a1";
503 sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
504 sc->silicon_rev = AST2500_A1_SILICON_REV;
505 sc->sram_size = 0x9000;
506 sc->spis_num = 2;
507 sc->ehcis_num = 2;
508 sc->wdts_num = 3;
509 sc->macs_num = 2;
510 sc->irqmap = aspeed_soc_ast2500_irqmap;
511 sc->memmap = aspeed_soc_ast2500_memmap;
512 sc->num_cpus = 1;
513 }
514
515 static const TypeInfo aspeed_soc_ast2500_type_info = {
516 .name = "ast2500-a1",
517 .parent = TYPE_ASPEED_SOC,
518 .instance_init = aspeed_soc_init,
519 .instance_size = sizeof(AspeedSoCState),
520 .class_init = aspeed_soc_ast2500_class_init,
521 };
522 static void aspeed_soc_register_types(void)
523 {
524 type_register_static(&aspeed_soc_type_info);
525 type_register_static(&aspeed_soc_ast2400_type_info);
526 type_register_static(&aspeed_soc_ast2500_type_info);
527 };
528
529 type_init(aspeed_soc_register_types)
AR7 emulation for QEMU