target/mips/cpu.c

   1 /*
   2  * QEMU MIPS CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/cutils.h"
  23 #include "qemu/qemu-print.h"
  24 #include "qapi/error.h"
  25 #include "cpu.h"
  26 #include "internal.h"
  27 #include "kvm_mips.h"
  28 #include "qemu/module.h"
  29 #include "sysemu/kvm.h"
  30 #include "sysemu/qtest.h"
  31 #include "exec/exec-all.h"
  32 #include "hw/qdev-properties.h"
  33 #include "hw/qdev-clock.h"
  34 #include "hw/semihosting/semihost.h"
  35 #include "qapi/qapi-commands-machine-target.h"
  36
  37 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
  38 {
  39     MIPSCPU *cpu = MIPS_CPU(cs);
  40     CPUMIPSState *env = &cpu->env;
  41
  42     env->active_tc.PC = value & ~(target_ulong)1;
  43     if (value & 1) {
  44         env->hflags |= MIPS_HFLAG_M16;
  45     } else {
  46         env->hflags &= ~(MIPS_HFLAG_M16);
  47     }
  48 }
  49
  50 static void mips_cpu_synchronize_from_tb(CPUState *cs,
  51                                          const TranslationBlock *tb)
  52 {
  53     MIPSCPU *cpu = MIPS_CPU(cs);
  54     CPUMIPSState *env = &cpu->env;
  55
  56     env->active_tc.PC = tb->pc;
  57     env->hflags &= ~MIPS_HFLAG_BMASK;
  58     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
  59 }
  60
  61 static bool mips_cpu_has_work(CPUState *cs)
  62 {
  63     MIPSCPU *cpu = MIPS_CPU(cs);
  64     CPUMIPSState *env = &cpu->env;
  65     bool has_work = false;
  66
  67     /*
  68      * Prior to MIPS Release 6 it is implementation dependent if non-enabled
  69      * interrupts wake-up the CPU, however most of the implementations only
  70      * check for interrupts that can be taken.
  71      */
  72     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
  73         cpu_mips_hw_interrupts_pending(env)) {
  74         if (cpu_mips_hw_interrupts_enabled(env) ||
  75             (env->insn_flags & ISA_MIPS_R6)) {
  76             has_work = true;
  77         }
  78     }
  79
  80     /* MIPS-MT has the ability to halt the CPU.  */
  81     if (ase_mt_available(env)) {
  82         /*
  83          * The QEMU model will issue an _WAKE request whenever the CPUs
  84          * should be woken up.
  85          */
  86         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  87             has_work = true;
  88         }
  89
  90         if (!mips_vpe_active(env)) {
  91             has_work = false;
  92         }
  93     }
  94     /* MIPS Release 6 has the ability to halt the CPU.  */
  95     if (env->CP0_Config5 & (1 << CP0C5_VP)) {
  96         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  97             has_work = true;
  98         }
  99         if (!mips_vp_active(env)) {
 100             has_work = false;
 101         }
 102     }
 103     return has_work;
 104 }
 105
 106 #include "translate_init.c.inc"
 107
 108 static void mips_cpu_reset(DeviceState *dev)
 109 {
 110     CPUState *cs = CPU(dev);
 111     MIPSCPU *cpu = MIPS_CPU(cs);
 112     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
 113     CPUMIPSState *env = &cpu->env;
 114
 115     mcc->parent_reset(dev);
 116
 117     memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
 118
 119     /* Reset registers to their default values */
 120     env->CP0_PRid = env->cpu_model->CP0_PRid;
 121     env->CP0_Config0 = env->cpu_model->CP0_Config0;
 122 #ifdef TARGET_WORDS_BIGENDIAN
 123     env->CP0_Config0 |= (1 << CP0C0_BE);
 124 #endif
 125     env->CP0_Config1 = env->cpu_model->CP0_Config1;
 126     env->CP0_Config2 = env->cpu_model->CP0_Config2;
 127     env->CP0_Config3 = env->cpu_model->CP0_Config3;
 128     env->CP0_Config4 = env->cpu_model->CP0_Config4;
 129     env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
 130     env->CP0_Config5 = env->cpu_model->CP0_Config5;
 131     env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
 132     env->CP0_Config6 = env->cpu_model->CP0_Config6;
 133     env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
 134     env->CP0_Config7 = env->cpu_model->CP0_Config7;
 135     env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
 136     env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
 137                                  << env->cpu_model->CP0_LLAddr_shift;
 138     env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
 139     env->SYNCI_Step = env->cpu_model->SYNCI_Step;
 140     env->CCRes = env->cpu_model->CCRes;
 141     env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
 142     env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
 143     env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
 144     env->current_tc = 0;
 145     env->SEGBITS = env->cpu_model->SEGBITS;
 146     env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
 147 #if defined(TARGET_MIPS64)
 148     if (env->cpu_model->insn_flags & ISA_MIPS3) {
 149         env->SEGMask |= 3ULL << 62;
 150     }
 151 #endif
 152     env->PABITS = env->cpu_model->PABITS;
 153     env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
 154     env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
 155     env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
 156     env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
 157     env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
 158     env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
 159     env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
 160     env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
 161     env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
 162     env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
 163     env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
 164     env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
 165     env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask;
 166     env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
 167     env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
 168     env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
 169     env->msair = env->cpu_model->MSAIR;
 170     env->insn_flags = env->cpu_model->insn_flags;
 171
 172 #if defined(CONFIG_USER_ONLY)
 173     env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
 174 # ifdef TARGET_MIPS64
 175     /* Enable 64-bit register mode.  */
 176     env->CP0_Status |= (1 << CP0St_PX);
 177 # endif
 178 # ifdef TARGET_ABI_MIPSN64
 179     /* Enable 64-bit address mode.  */
 180     env->CP0_Status |= (1 << CP0St_UX);
 181 # endif
 182     /*
 183      * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
 184      * hardware registers.
 185      */
 186     env->CP0_HWREna |= 0x0000000F;
 187     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
 188         env->CP0_Status |= (1 << CP0St_CU1);
 189     }
 190     if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
 191         env->CP0_Status |= (1 << CP0St_MX);
 192     }
 193 # if defined(TARGET_MIPS64)
 194     /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
 195     if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
 196         (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
 197         env->CP0_Status |= (1 << CP0St_FR);
 198     }
 199 # endif
 200 #else /* !CONFIG_USER_ONLY */
 201     if (env->hflags & MIPS_HFLAG_BMASK) {
 202         /*
 203          * If the exception was raised from a delay slot,
 204          * come back to the jump.
 205          */
 206         env->CP0_ErrorEPC = (env->active_tc.PC
 207                              - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
 208     } else {
 209         env->CP0_ErrorEPC = env->active_tc.PC;
 210     }
 211     env->active_tc.PC = env->exception_base;
 212     env->CP0_Random = env->tlb->nb_tlb - 1;
 213     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 214     env->CP0_Wired = 0;
 215     env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
 216     env->CP0_EBase = (cs->cpu_index & 0x3FF);
 217     if (mips_um_ksegs_enabled()) {
 218         env->CP0_EBase |= 0x40000000;
 219     } else {
 220         env->CP0_EBase |= (int32_t)0x80000000;
 221     }
 222     if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
 223         env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
 224     }
 225     env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
 226             0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
 227     env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
 228     /*
 229      * Vectored interrupts not implemented, timer on int 7,
 230      * no performance counters.
 231      */
 232     env->CP0_IntCtl = 0xe0000000;
 233     {
 234         int i;
 235
 236         for (i = 0; i < 7; i++) {
 237             env->CP0_WatchLo[i] = 0;
 238             env->CP0_WatchHi[i] = 0x80000000;
 239         }
 240         env->CP0_WatchLo[7] = 0;
 241         env->CP0_WatchHi[7] = 0;
 242     }
 243     /* Count register increments in debug mode, EJTAG version 1 */
 244     env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
 245
 246     cpu_mips_store_count(env, 1);
 247
 248     if (ase_mt_available(env)) {
 249         int i;
 250
 251         /* Only TC0 on VPE 0 starts as active.  */
 252         for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
 253             env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
 254             env->tcs[i].CP0_TCHalt = 1;
 255         }
 256         env->active_tc.CP0_TCHalt = 1;
 257         cs->halted = 1;
 258
 259         if (cs->cpu_index == 0) {
 260             /* VPE0 starts up enabled.  */
 261             env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
 262             env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
 263
 264             /* TC0 starts up unhalted.  */
 265             cs->halted = 0;
 266             env->active_tc.CP0_TCHalt = 0;
 267             env->tcs[0].CP0_TCHalt = 0;
 268             /* With thread 0 active.  */
 269             env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
 270             env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
 271         }
 272     }
 273
 274     /*
 275      * Configure default legacy segmentation control. We use this regardless of
 276      * whether segmentation control is presented to the guest.
 277      */
 278     /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
 279     env->CP0_SegCtl0 =   (CP0SC_AM_MK << CP0SC_AM);
 280     /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
 281     env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16;
 282     /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
 283     env->CP0_SegCtl1 =   (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
 284                          (2 << CP0SC_C);
 285     /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
 286     env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
 287                          (3 << CP0SC_C)) << 16;
 288     /* USeg (seg4 0x40000000..0x7FFFFFFF) */
 289     env->CP0_SegCtl2 =   (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
 290                          (1 << CP0SC_EU) | (2 << CP0SC_C);
 291     /* USeg (seg5 0x00000000..0x3FFFFFFF) */
 292     env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
 293                          (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16;
 294     /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
 295     env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
 296 #endif /* !CONFIG_USER_ONLY */
 297     if ((env->insn_flags & ISA_MIPS_R6) &&
 298         (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
 299         /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
 300         env->CP0_Status |= (1 << CP0St_FR);
 301     }
 302
 303     if (env->insn_flags & ISA_MIPS_R6) {
 304         /* PTW  =  1 */
 305         env->CP0_PWSize = 0x40;
 306         /* GDI  = 12 */
 307         /* UDI  = 12 */
 308         /* MDI  = 12 */
 309         /* PRI  = 12 */
 310         /* PTEI =  2 */
 311         env->CP0_PWField = 0x0C30C302;
 312     } else {
 313         /* GDI  =  0 */
 314         /* UDI  =  0 */
 315         /* MDI  =  0 */
 316         /* PRI  =  0 */
 317         /* PTEI =  2 */
 318         env->CP0_PWField = 0x02;
 319     }
 320
 321     if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
 322         /*  microMIPS on reset when Config3.ISA is 3 */
 323         env->hflags |= MIPS_HFLAG_M16;
 324     }
 325
 326     /* MSA */
 327     if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
 328         msa_reset(env);
 329     }
 330
 331     compute_hflags(env);
 332     restore_fp_status(env);
 333     restore_pamask(env);
 334     cs->exception_index = EXCP_NONE;
 335
 336     if (semihosting_get_argc()) {
 337         /* UHI interface can be used to obtain argc and argv */
 338         env->active_tc.gpr[4] = -1;
 339     }
 340
 341 #ifndef CONFIG_USER_ONLY
 342     if (kvm_enabled()) {
 343         kvm_mips_reset_vcpu(cpu);
 344     }
 345 #endif
 346 }
 347
 348 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 349 {
 350     MIPSCPU *cpu = MIPS_CPU(s);
 351     CPUMIPSState *env = &cpu->env;
 352
 353     if (!(env->insn_flags & ISA_NANOMIPS32)) {
 354 #ifdef TARGET_WORDS_BIGENDIAN
 355         info->print_insn = print_insn_big_mips;
 356 #else
 357         info->print_insn = print_insn_little_mips;
 358 #endif
 359     } else {
 360 #if defined(CONFIG_NANOMIPS_DIS)
 361         info->print_insn = print_insn_nanomips;
 362 #endif
 363     }
 364 }
 365
 366 /*
 367  * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
 368  */
 369 #define CPU_FREQ_HZ_DEFAULT     200000000
 370 #define CP0_COUNT_RATE_DEFAULT  2
 371
 372 static void mips_cp0_period_set(MIPSCPU *cpu)
 373 {
 374     CPUMIPSState *env = &cpu->env;
 375
 376     env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
 377                                           cpu->cp0_count_rate);
 378     assert(env->cp0_count_ns);
 379 }
 380
 381 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
 382 {
 383     CPUState *cs = CPU(dev);
 384     MIPSCPU *cpu = MIPS_CPU(dev);
 385     CPUMIPSState *env = &cpu->env;
 386     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
 387     Error *local_err = NULL;
 388
 389     if (!clock_get(cpu->clock)) {
 390 #ifndef CONFIG_USER_ONLY
 391         if (!qtest_enabled()) {
 392             g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT);
 393
 394             warn_report("CPU input clock is not connected to any output clock, "
 395                         "using default frequency of %s.", cpu_freq_str);
 396         }
 397 #endif
 398         /* Initialize the frequency in case the clock remains unconnected. */
 399         clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT);
 400     }
 401     mips_cp0_period_set(cpu);
 402
 403     cpu_exec_realizefn(cs, &local_err);
 404     if (local_err != NULL) {
 405         error_propagate(errp, local_err);
 406         return;
 407     }
 408
 409     env->exception_base = (int32_t)0xBFC00000;
 410
 411 #ifndef CONFIG_USER_ONLY
 412     mmu_init(env, env->cpu_model);
 413 #endif
 414     fpu_init(env, env->cpu_model);
 415     mvp_init(env);
 416
 417     cpu_reset(cs);
 418     qemu_init_vcpu(cs);
 419
 420     mcc->parent_realize(dev, errp);
 421 }
 422
 423 static void mips_cpu_initfn(Object *obj)
 424 {
 425     MIPSCPU *cpu = MIPS_CPU(obj);
 426     CPUMIPSState *env = &cpu->env;
 427     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
 428
 429     cpu_set_cpustate_pointers(cpu);
 430     cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu);
 431     env->cpu_model = mcc->cpu_def;
 432 }
 433
 434 static char *mips_cpu_type_name(const char *cpu_model)
 435 {
 436     return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
 437 }
 438
 439 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
 440 {
 441     ObjectClass *oc;
 442     char *typename;
 443
 444     typename = mips_cpu_type_name(cpu_model);
 445     oc = object_class_by_name(typename);
 446     g_free(typename);
 447     return oc;
 448 }
 449
 450 static Property mips_cpu_properties[] = {
 451     /* CP0 timer running at half the clock of the CPU */
 452     DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate,
 453                        CP0_COUNT_RATE_DEFAULT),
 454     DEFINE_PROP_END_OF_LIST()
 455 };
 456
 457 static void mips_cpu_class_init(ObjectClass *c, void *data)
 458 {
 459     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
 460     CPUClass *cc = CPU_CLASS(c);
 461     DeviceClass *dc = DEVICE_CLASS(c);
 462
 463     device_class_set_parent_realize(dc, mips_cpu_realizefn,
 464                                     &mcc->parent_realize);
 465     device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
 466     device_class_set_props(dc, mips_cpu_properties);
 467
 468     cc->class_by_name = mips_cpu_class_by_name;
 469     cc->has_work = mips_cpu_has_work;
 470     cc->do_interrupt = mips_cpu_do_interrupt;
 471     cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
 472     cc->dump_state = mips_cpu_dump_state;
 473     cc->set_pc = mips_cpu_set_pc;
 474     cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
 475     cc->gdb_read_register = mips_cpu_gdb_read_register;
 476     cc->gdb_write_register = mips_cpu_gdb_write_register;
 477 #ifndef CONFIG_USER_ONLY
 478     cc->do_transaction_failed = mips_cpu_do_transaction_failed;
 479     cc->do_unaligned_access = mips_cpu_do_unaligned_access;
 480     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 481     cc->vmsd = &vmstate_mips_cpu;
 482 #endif
 483     cc->disas_set_info = mips_cpu_disas_set_info;
 484 #ifdef CONFIG_TCG
 485     cc->tcg_initialize = mips_tcg_init;
 486     cc->tlb_fill = mips_cpu_tlb_fill;
 487 #endif
 488
 489     cc->gdb_num_core_regs = 73;
 490     cc->gdb_stop_before_watchpoint = true;
 491 }
 492
 493 static const TypeInfo mips_cpu_type_info = {
 494     .name = TYPE_MIPS_CPU,
 495     .parent = TYPE_CPU,
 496     .instance_size = sizeof(MIPSCPU),
 497     .instance_init = mips_cpu_initfn,
 498     .abstract = true,
 499     .class_size = sizeof(MIPSCPUClass),
 500     .class_init = mips_cpu_class_init,
 501 };
 502
 503 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
 504 {
 505     MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
 506     mcc->cpu_def = data;
 507 }
 508
 509 static void mips_register_cpudef_type(const struct mips_def_t *def)
 510 {
 511     char *typename = mips_cpu_type_name(def->name);
 512     TypeInfo ti = {
 513         .name = typename,
 514         .parent = TYPE_MIPS_CPU,
 515         .class_init = mips_cpu_cpudef_class_init,
 516         .class_data = (void *)def,
 517     };
 518
 519     type_register(&ti);
 520     g_free(typename);
 521 }
 522
 523 static void mips_cpu_register_types(void)
 524 {
 525     int i;
 526
 527     type_register_static(&mips_cpu_type_info);
 528     for (i = 0; i < mips_defs_number; i++) {
 529         mips_register_cpudef_type(&mips_defs[i]);
 530     }
 531 }
 532
 533 type_init(mips_cpu_register_types)
 534
 535 static void mips_cpu_add_definition(gpointer data, gpointer user_data)
 536 {
 537     ObjectClass *oc = data;
 538     CpuDefinitionInfoList **cpu_list = user_data;
 539     CpuDefinitionInfo *info;
 540     const char *typename;
 541
 542     typename = object_class_get_name(oc);
 543     info = g_malloc0(sizeof(*info));
 544     info->name = g_strndup(typename,
 545                            strlen(typename) - strlen("-" TYPE_MIPS_CPU));
 546     info->q_typename = g_strdup(typename);
 547
 548     QAPI_LIST_PREPEND(*cpu_list, info);
 549 }
 550
 551 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 552 {
 553     CpuDefinitionInfoList *cpu_list = NULL;
 554     GSList *list;
 555
 556     list = object_class_get_list(TYPE_MIPS_CPU, false);
 557     g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
 558     g_slist_free(list);
 559
 560     return cpu_list;
 561 }
 562
 563 /* Could be used by generic CPU object */
 564 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
 565 {
 566     DeviceState *cpu;
 567
 568     cpu = DEVICE(object_new(cpu_type));
 569     qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
 570     qdev_realize(cpu, NULL, &error_abort);
 571
 572     return MIPS_CPU(cpu);
 573 }
 574
 575 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
 576 {
 577     return (env->cpu_model->insn_flags & isa_mask) != 0;
 578 }
 579
 580 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa)
 581 {
 582     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
 583     return (mcc->cpu_def->insn_flags & isa) != 0;
 584 }
 585
 586 bool cpu_type_supports_cps_smp(const char *cpu_type)
 587 {
 588     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
 589     return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
 590 }
 591
 592 void cpu_set_exception_base(int vp_index, target_ulong address)
 593 {
 594     MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
 595     vp->env.exception_base = address;
 596 }