target/mips/cpu.c

   1 /*
   2  * QEMU MIPS CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/cutils.h"
  23 #include "qemu/qemu-print.h"
  24 #include "qapi/error.h"
  25 #include "cpu.h"
  26 #include "internal.h"
  27 #include "kvm_mips.h"
  28 #include "qemu/module.h"
  29 #include "sysemu/kvm.h"
  30 #include "sysemu/qtest.h"
  31 #include "exec/exec-all.h"
  32 #include "hw/qdev-properties.h"
  33 #include "hw/qdev-clock.h"
  34 #include "hw/semihosting/semihost.h"
  35 #include "qapi/qapi-commands-machine-target.h"
  36 #include "fpu_helper.h"
  37
  38 #if !defined(CONFIG_USER_ONLY)
  39
  40 /* Called for updates to CP0_Status.  */
  41 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
  42 {
  43     int32_t tcstatus, *tcst;
  44     uint32_t v = cpu->CP0_Status;
  45     uint32_t cu, mx, asid, ksu;
  46     uint32_t mask = ((1 << CP0TCSt_TCU3)
  47                        | (1 << CP0TCSt_TCU2)
  48                        | (1 << CP0TCSt_TCU1)
  49                        | (1 << CP0TCSt_TCU0)
  50                        | (1 << CP0TCSt_TMX)
  51                        | (3 << CP0TCSt_TKSU)
  52                        | (0xff << CP0TCSt_TASID));
  53
  54     cu = (v >> CP0St_CU0) & 0xf;
  55     mx = (v >> CP0St_MX) & 0x1;
  56     ksu = (v >> CP0St_KSU) & 0x3;
  57     asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
  58
  59     tcstatus = cu << CP0TCSt_TCU0;
  60     tcstatus |= mx << CP0TCSt_TMX;
  61     tcstatus |= ksu << CP0TCSt_TKSU;
  62     tcstatus |= asid;
  63
  64     if (tc == cpu->current_tc) {
  65         tcst = &cpu->active_tc.CP0_TCStatus;
  66     } else {
  67         tcst = &cpu->tcs[tc].CP0_TCStatus;
  68     }
  69
  70     *tcst &= ~mask;
  71     *tcst |= tcstatus;
  72     compute_hflags(cpu);
  73 }
  74
  75 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
  76 {
  77     uint32_t mask = env->CP0_Status_rw_bitmask;
  78     target_ulong old = env->CP0_Status;
  79
  80     if (env->insn_flags & ISA_MIPS_R6) {
  81         bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
  82 #if defined(TARGET_MIPS64)
  83         uint32_t ksux = (1 << CP0St_KX) & val;
  84         ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
  85         ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
  86         val = (val & ~(7 << CP0St_UX)) | ksux;
  87 #endif
  88         if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
  89             mask &= ~(3 << CP0St_KSU);
  90         }
  91         mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
  92     }
  93
  94     env->CP0_Status = (old & ~mask) | (val & mask);
  95 #if defined(TARGET_MIPS64)
  96     if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
  97         /* Access to at least one of the 64-bit segments has been disabled */
  98         tlb_flush(env_cpu(env));
  99     }
 100 #endif
 101     if (ase_mt_available(env)) {
 102         sync_c0_status(env, env, env->current_tc);
 103     } else {
 104         compute_hflags(env);
 105     }
 106 }
 107
 108 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
 109 {
 110     uint32_t mask = 0x00C00300;
 111     uint32_t old = env->CP0_Cause;
 112     int i;
 113
 114     if (env->insn_flags & ISA_MIPS_R2) {
 115         mask |= 1 << CP0Ca_DC;
 116     }
 117     if (env->insn_flags & ISA_MIPS_R6) {
 118         mask &= ~((1 << CP0Ca_WP) & val);
 119     }
 120
 121     env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
 122
 123     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
 124         if (env->CP0_Cause & (1 << CP0Ca_DC)) {
 125             cpu_mips_stop_count(env);
 126         } else {
 127             cpu_mips_start_count(env);
 128         }
 129     }
 130
 131     /* Set/reset software interrupts */
 132     for (i = 0 ; i < 2 ; i++) {
 133         if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
 134             cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
 135         }
 136     }
 137 }
 138
 139 #endif /* !CONFIG_USER_ONLY */
 140
 141 static const char * const excp_names[EXCP_LAST + 1] = {
 142     [EXCP_RESET] = "reset",
 143     [EXCP_SRESET] = "soft reset",
 144     [EXCP_DSS] = "debug single step",
 145     [EXCP_DINT] = "debug interrupt",
 146     [EXCP_NMI] = "non-maskable interrupt",
 147     [EXCP_MCHECK] = "machine check",
 148     [EXCP_EXT_INTERRUPT] = "interrupt",
 149     [EXCP_DFWATCH] = "deferred watchpoint",
 150     [EXCP_DIB] = "debug instruction breakpoint",
 151     [EXCP_IWATCH] = "instruction fetch watchpoint",
 152     [EXCP_AdEL] = "address error load",
 153     [EXCP_AdES] = "address error store",
 154     [EXCP_TLBF] = "TLB refill",
 155     [EXCP_IBE] = "instruction bus error",
 156     [EXCP_DBp] = "debug breakpoint",
 157     [EXCP_SYSCALL] = "syscall",
 158     [EXCP_BREAK] = "break",
 159     [EXCP_CpU] = "coprocessor unusable",
 160     [EXCP_RI] = "reserved instruction",
 161     [EXCP_OVERFLOW] = "arithmetic overflow",
 162     [EXCP_TRAP] = "trap",
 163     [EXCP_FPE] = "floating point",
 164     [EXCP_DDBS] = "debug data break store",
 165     [EXCP_DWATCH] = "data watchpoint",
 166     [EXCP_LTLBL] = "TLB modify",
 167     [EXCP_TLBL] = "TLB load",
 168     [EXCP_TLBS] = "TLB store",
 169     [EXCP_DBE] = "data bus error",
 170     [EXCP_DDBL] = "debug data break load",
 171     [EXCP_THREAD] = "thread",
 172     [EXCP_MDMX] = "MDMX",
 173     [EXCP_C2E] = "precise coprocessor 2",
 174     [EXCP_CACHE] = "cache error",
 175     [EXCP_TLBXI] = "TLB execute-inhibit",
 176     [EXCP_TLBRI] = "TLB read-inhibit",
 177     [EXCP_MSADIS] = "MSA disabled",
 178     [EXCP_MSAFPE] = "MSA floating point",
 179 };
 180
 181 const char *mips_exception_name(int32_t exception)
 182 {
 183     if (exception < 0 || exception > EXCP_LAST) {
 184         return "unknown";
 185     }
 186     return excp_names[exception];
 187 }
 188
 189 void cpu_set_exception_base(int vp_index, target_ulong address)
 190 {
 191     MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
 192     vp->env.exception_base = address;
 193 }
 194
 195 target_ulong exception_resume_pc(CPUMIPSState *env)
 196 {
 197     target_ulong bad_pc;
 198     target_ulong isa_mode;
 199
 200     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 201     bad_pc = env->active_tc.PC | isa_mode;
 202     if (env->hflags & MIPS_HFLAG_BMASK) {
 203         /*
 204          * If the exception was raised from a delay slot, come back to
 205          * the jump.
 206          */
 207         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 208     }
 209
 210     return bad_pc;
 211 }
 212
 213 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 214 {
 215     if (interrupt_request & CPU_INTERRUPT_HARD) {
 216         MIPSCPU *cpu = MIPS_CPU(cs);
 217         CPUMIPSState *env = &cpu->env;
 218
 219         if (cpu_mips_hw_interrupts_enabled(env) &&
 220             cpu_mips_hw_interrupts_pending(env)) {
 221             /* Raise it */
 222             cs->exception_index = EXCP_EXT_INTERRUPT;
 223             env->error_code = 0;
 224             mips_cpu_do_interrupt(cs);
 225             return true;
 226         }
 227     }
 228     return false;
 229 }
 230
 231 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
 232                                           uint32_t exception,
 233                                           int error_code,
 234                                           uintptr_t pc)
 235 {
 236     CPUState *cs = env_cpu(env);
 237
 238     qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n",
 239                   __func__, exception, mips_exception_name(exception),
 240                   error_code);
 241     cs->exception_index = exception;
 242     env->error_code = error_code;
 243
 244     cpu_loop_exit_restore(cs, pc);
 245 }
 246
 247 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
 248 {
 249     MIPSCPU *cpu = MIPS_CPU(cs);
 250     CPUMIPSState *env = &cpu->env;
 251
 252     env->active_tc.PC = value & ~(target_ulong)1;
 253     if (value & 1) {
 254         env->hflags |= MIPS_HFLAG_M16;
 255     } else {
 256         env->hflags &= ~(MIPS_HFLAG_M16);
 257     }
 258 }
 259
 260 static void mips_cpu_synchronize_from_tb(CPUState *cs,
 261                                          const TranslationBlock *tb)
 262 {
 263     MIPSCPU *cpu = MIPS_CPU(cs);
 264     CPUMIPSState *env = &cpu->env;
 265
 266     env->active_tc.PC = tb->pc;
 267     env->hflags &= ~MIPS_HFLAG_BMASK;
 268     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
 269 }
 270
 271 static bool mips_cpu_has_work(CPUState *cs)
 272 {
 273     MIPSCPU *cpu = MIPS_CPU(cs);
 274     CPUMIPSState *env = &cpu->env;
 275     bool has_work = false;
 276
 277     /*
 278      * Prior to MIPS Release 6 it is implementation dependent if non-enabled
 279      * interrupts wake-up the CPU, however most of the implementations only
 280      * check for interrupts that can be taken.
 281      */
 282     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
 283         cpu_mips_hw_interrupts_pending(env)) {
 284         if (cpu_mips_hw_interrupts_enabled(env) ||
 285             (env->insn_flags & ISA_MIPS_R6)) {
 286             has_work = true;
 287         }
 288     }
 289
 290     /* MIPS-MT has the ability to halt the CPU.  */
 291     if (ase_mt_available(env)) {
 292         /*
 293          * The QEMU model will issue an _WAKE request whenever the CPUs
 294          * should be woken up.
 295          */
 296         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
 297             has_work = true;
 298         }
 299
 300         if (!mips_vpe_active(env)) {
 301             has_work = false;
 302         }
 303     }
 304     /* MIPS Release 6 has the ability to halt the CPU.  */
 305     if (env->CP0_Config5 & (1 << CP0C5_VP)) {
 306         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
 307             has_work = true;
 308         }
 309         if (!mips_vp_active(env)) {
 310             has_work = false;
 311         }
 312     }
 313     return has_work;
 314 }
 315
 316 #include "cpu-defs.c.inc"
 317
 318 static void mips_cpu_reset(DeviceState *dev)
 319 {
 320     CPUState *cs = CPU(dev);
 321     MIPSCPU *cpu = MIPS_CPU(cs);
 322     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
 323     CPUMIPSState *env = &cpu->env;
 324
 325     mcc->parent_reset(dev);
 326
 327     memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
 328
 329     /* Reset registers to their default values */
 330     env->CP0_PRid = env->cpu_model->CP0_PRid;
 331     env->CP0_Config0 = env->cpu_model->CP0_Config0;
 332 #ifdef TARGET_WORDS_BIGENDIAN
 333     env->CP0_Config0 |= (1 << CP0C0_BE);
 334 #endif
 335     env->CP0_Config1 = env->cpu_model->CP0_Config1;
 336     env->CP0_Config2 = env->cpu_model->CP0_Config2;
 337     env->CP0_Config3 = env->cpu_model->CP0_Config3;
 338     env->CP0_Config4 = env->cpu_model->CP0_Config4;
 339     env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask;
 340     env->CP0_Config5 = env->cpu_model->CP0_Config5;
 341     env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
 342     env->CP0_Config6 = env->cpu_model->CP0_Config6;
 343     env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
 344     env->CP0_Config7 = env->cpu_model->CP0_Config7;
 345     env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
 346     env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
 347                                  << env->cpu_model->CP0_LLAddr_shift;
 348     env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
 349     env->SYNCI_Step = env->cpu_model->SYNCI_Step;
 350     env->CCRes = env->cpu_model->CCRes;
 351     env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask;
 352     env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask;
 353     env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl;
 354     env->current_tc = 0;
 355     env->SEGBITS = env->cpu_model->SEGBITS;
 356     env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1);
 357 #if defined(TARGET_MIPS64)
 358     if (env->cpu_model->insn_flags & ISA_MIPS3) {
 359         env->SEGMask |= 3ULL << 62;
 360     }
 361 #endif
 362     env->PABITS = env->cpu_model->PABITS;
 363     env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask;
 364     env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0;
 365     env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask;
 366     env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1;
 367     env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask;
 368     env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2;
 369     env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask;
 370     env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
 371     env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
 372     env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
 373     env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
 374     env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
 375     env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask;
 376     env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
 377     env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask;
 378     env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
 379     env->msair = env->cpu_model->MSAIR;
 380     env->insn_flags = env->cpu_model->insn_flags;
 381
 382 #if defined(CONFIG_USER_ONLY)
 383     env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
 384 # ifdef TARGET_MIPS64
 385     /* Enable 64-bit register mode.  */
 386     env->CP0_Status |= (1 << CP0St_PX);
 387 # endif
 388 # ifdef TARGET_ABI_MIPSN64
 389     /* Enable 64-bit address mode.  */
 390     env->CP0_Status |= (1 << CP0St_UX);
 391 # endif
 392     /*
 393      * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
 394      * hardware registers.
 395      */
 396     env->CP0_HWREna |= 0x0000000F;
 397     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
 398         env->CP0_Status |= (1 << CP0St_CU1);
 399     }
 400     if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
 401         env->CP0_Status |= (1 << CP0St_MX);
 402     }
 403 # if defined(TARGET_MIPS64)
 404     /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */
 405     if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
 406         (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
 407         env->CP0_Status |= (1 << CP0St_FR);
 408     }
 409 # endif
 410 #else /* !CONFIG_USER_ONLY */
 411     if (env->hflags & MIPS_HFLAG_BMASK) {
 412         /*
 413          * If the exception was raised from a delay slot,
 414          * come back to the jump.
 415          */
 416         env->CP0_ErrorEPC = (env->active_tc.PC
 417                              - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4));
 418     } else {
 419         env->CP0_ErrorEPC = env->active_tc.PC;
 420     }
 421     env->active_tc.PC = env->exception_base;
 422     env->CP0_Random = env->tlb->nb_tlb - 1;
 423     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 424     env->CP0_Wired = 0;
 425     env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId;
 426     env->CP0_EBase = (cs->cpu_index & 0x3FF);
 427     if (mips_um_ksegs_enabled()) {
 428         env->CP0_EBase |= 0x40000000;
 429     } else {
 430         env->CP0_EBase |= (int32_t)0x80000000;
 431     }
 432     if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {
 433         env->CP0_CMGCRBase = 0x1fbf8000 >> 4;
 434     }
 435     env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ?
 436             0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff;
 437     env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
 438     /*
 439      * Vectored interrupts not implemented, timer on int 7,
 440      * no performance counters.
 441      */
 442     env->CP0_IntCtl = 0xe0000000;
 443     {
 444         int i;
 445
 446         for (i = 0; i < 7; i++) {
 447             env->CP0_WatchLo[i] = 0;
 448             env->CP0_WatchHi[i] = 0x80000000;
 449         }
 450         env->CP0_WatchLo[7] = 0;
 451         env->CP0_WatchHi[7] = 0;
 452     }
 453     /* Count register increments in debug mode, EJTAG version 1 */
 454     env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
 455
 456     cpu_mips_store_count(env, 1);
 457
 458     if (ase_mt_available(env)) {
 459         int i;
 460
 461         /* Only TC0 on VPE 0 starts as active.  */
 462         for (i = 0; i < ARRAY_SIZE(env->tcs); i++) {
 463             env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE;
 464             env->tcs[i].CP0_TCHalt = 1;
 465         }
 466         env->active_tc.CP0_TCHalt = 1;
 467         cs->halted = 1;
 468
 469         if (cs->cpu_index == 0) {
 470             /* VPE0 starts up enabled.  */
 471             env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
 472             env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
 473
 474             /* TC0 starts up unhalted.  */
 475             cs->halted = 0;
 476             env->active_tc.CP0_TCHalt = 0;
 477             env->tcs[0].CP0_TCHalt = 0;
 478             /* With thread 0 active.  */
 479             env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A);
 480             env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
 481         }
 482     }
 483
 484     /*
 485      * Configure default legacy segmentation control. We use this regardless of
 486      * whether segmentation control is presented to the guest.
 487      */
 488     /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */
 489     env->CP0_SegCtl0 =   (CP0SC_AM_MK << CP0SC_AM);
 490     /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */
 491     env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16;
 492     /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */
 493     env->CP0_SegCtl1 =   (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
 494                          (2 << CP0SC_C);
 495     /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */
 496     env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) |
 497                          (3 << CP0SC_C)) << 16;
 498     /* USeg (seg4 0x40000000..0x7FFFFFFF) */
 499     env->CP0_SegCtl2 =   (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
 500                          (1 << CP0SC_EU) | (2 << CP0SC_C);
 501     /* USeg (seg5 0x00000000..0x3FFFFFFF) */
 502     env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) |
 503                          (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16;
 504     /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */
 505     env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM);
 506 #endif /* !CONFIG_USER_ONLY */
 507     if ((env->insn_flags & ISA_MIPS_R6) &&
 508         (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
 509         /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
 510         env->CP0_Status |= (1 << CP0St_FR);
 511     }
 512
 513     if (env->insn_flags & ISA_MIPS_R6) {
 514         /* PTW  =  1 */
 515         env->CP0_PWSize = 0x40;
 516         /* GDI  = 12 */
 517         /* UDI  = 12 */
 518         /* MDI  = 12 */
 519         /* PRI  = 12 */
 520         /* PTEI =  2 */
 521         env->CP0_PWField = 0x0C30C302;
 522     } else {
 523         /* GDI  =  0 */
 524         /* UDI  =  0 */
 525         /* MDI  =  0 */
 526         /* PRI  =  0 */
 527         /* PTEI =  2 */
 528         env->CP0_PWField = 0x02;
 529     }
 530
 531     if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
 532         /*  microMIPS on reset when Config3.ISA is 3 */
 533         env->hflags |= MIPS_HFLAG_M16;
 534     }
 535
 536     msa_reset(env);
 537
 538     compute_hflags(env);
 539     restore_fp_status(env);
 540     restore_pamask(env);
 541     cs->exception_index = EXCP_NONE;
 542
 543     if (semihosting_get_argc()) {
 544         /* UHI interface can be used to obtain argc and argv */
 545         env->active_tc.gpr[4] = -1;
 546     }
 547
 548 #ifndef CONFIG_USER_ONLY
 549     if (kvm_enabled()) {
 550         kvm_mips_reset_vcpu(cpu);
 551     }
 552 #endif
 553 }
 554
 555 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 556 {
 557     MIPSCPU *cpu = MIPS_CPU(s);
 558     CPUMIPSState *env = &cpu->env;
 559
 560     if (!(env->insn_flags & ISA_NANOMIPS32)) {
 561 #ifdef TARGET_WORDS_BIGENDIAN
 562         info->print_insn = print_insn_big_mips;
 563 #else
 564         info->print_insn = print_insn_little_mips;
 565 #endif
 566     } else {
 567 #if defined(CONFIG_NANOMIPS_DIS)
 568         info->print_insn = print_insn_nanomips;
 569 #endif
 570     }
 571 }
 572
 573 /*
 574  * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
 575  */
 576 #define CPU_FREQ_HZ_DEFAULT     200000000
 577 #define CP0_COUNT_RATE_DEFAULT  2
 578
 579 static void mips_cp0_period_set(MIPSCPU *cpu)
 580 {
 581     CPUMIPSState *env = &cpu->env;
 582
 583     env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
 584                                           cpu->cp0_count_rate);
 585     assert(env->cp0_count_ns);
 586 }
 587
 588 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
 589 {
 590     CPUState *cs = CPU(dev);
 591     MIPSCPU *cpu = MIPS_CPU(dev);
 592     CPUMIPSState *env = &cpu->env;
 593     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
 594     Error *local_err = NULL;
 595
 596     if (!clock_get(cpu->clock)) {
 597 #ifndef CONFIG_USER_ONLY
 598         if (!qtest_enabled()) {
 599             g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT);
 600
 601             warn_report("CPU input clock is not connected to any output clock, "
 602                         "using default frequency of %s.", cpu_freq_str);
 603         }
 604 #endif
 605         /* Initialize the frequency in case the clock remains unconnected. */
 606         clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT);
 607     }
 608     mips_cp0_period_set(cpu);
 609
 610     cpu_exec_realizefn(cs, &local_err);
 611     if (local_err != NULL) {
 612         error_propagate(errp, local_err);
 613         return;
 614     }
 615
 616     env->exception_base = (int32_t)0xBFC00000;
 617
 618 #ifndef CONFIG_USER_ONLY
 619     mmu_init(env, env->cpu_model);
 620 #endif
 621     fpu_init(env, env->cpu_model);
 622     mvp_init(env);
 623
 624     cpu_reset(cs);
 625     qemu_init_vcpu(cs);
 626
 627     mcc->parent_realize(dev, errp);
 628 }
 629
 630 static void mips_cpu_initfn(Object *obj)
 631 {
 632     MIPSCPU *cpu = MIPS_CPU(obj);
 633     CPUMIPSState *env = &cpu->env;
 634     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
 635
 636     cpu_set_cpustate_pointers(cpu);
 637     cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu);
 638     env->cpu_model = mcc->cpu_def;
 639 }
 640
 641 static char *mips_cpu_type_name(const char *cpu_model)
 642 {
 643     return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model);
 644 }
 645
 646 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
 647 {
 648     ObjectClass *oc;
 649     char *typename;
 650
 651     typename = mips_cpu_type_name(cpu_model);
 652     oc = object_class_by_name(typename);
 653     g_free(typename);
 654     return oc;
 655 }
 656
 657 static Property mips_cpu_properties[] = {
 658     /* CP0 timer running at half the clock of the CPU */
 659     DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate,
 660                        CP0_COUNT_RATE_DEFAULT),
 661     DEFINE_PROP_END_OF_LIST()
 662 };
 663
 664 static void mips_cpu_class_init(ObjectClass *c, void *data)
 665 {
 666     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
 667     CPUClass *cc = CPU_CLASS(c);
 668     DeviceClass *dc = DEVICE_CLASS(c);
 669
 670     device_class_set_parent_realize(dc, mips_cpu_realizefn,
 671                                     &mcc->parent_realize);
 672     device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
 673     device_class_set_props(dc, mips_cpu_properties);
 674
 675     cc->class_by_name = mips_cpu_class_by_name;
 676     cc->has_work = mips_cpu_has_work;
 677     cc->do_interrupt = mips_cpu_do_interrupt;
 678     cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
 679     cc->dump_state = mips_cpu_dump_state;
 680     cc->set_pc = mips_cpu_set_pc;
 681     cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
 682     cc->gdb_read_register = mips_cpu_gdb_read_register;
 683     cc->gdb_write_register = mips_cpu_gdb_write_register;
 684 #ifndef CONFIG_USER_ONLY
 685     cc->do_transaction_failed = mips_cpu_do_transaction_failed;
 686     cc->do_unaligned_access = mips_cpu_do_unaligned_access;
 687     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 688     cc->vmsd = &vmstate_mips_cpu;
 689 #endif
 690     cc->disas_set_info = mips_cpu_disas_set_info;
 691 #ifdef CONFIG_TCG
 692     cc->tcg_initialize = mips_tcg_init;
 693     cc->tlb_fill = mips_cpu_tlb_fill;
 694 #endif
 695
 696     cc->gdb_num_core_regs = 73;
 697     cc->gdb_stop_before_watchpoint = true;
 698 }
 699
 700 static const TypeInfo mips_cpu_type_info = {
 701     .name = TYPE_MIPS_CPU,
 702     .parent = TYPE_CPU,
 703     .instance_size = sizeof(MIPSCPU),
 704     .instance_init = mips_cpu_initfn,
 705     .abstract = true,
 706     .class_size = sizeof(MIPSCPUClass),
 707     .class_init = mips_cpu_class_init,
 708 };
 709
 710 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
 711 {
 712     MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
 713     mcc->cpu_def = data;
 714 }
 715
 716 static void mips_register_cpudef_type(const struct mips_def_t *def)
 717 {
 718     char *typename = mips_cpu_type_name(def->name);
 719     TypeInfo ti = {
 720         .name = typename,
 721         .parent = TYPE_MIPS_CPU,
 722         .class_init = mips_cpu_cpudef_class_init,
 723         .class_data = (void *)def,
 724     };
 725
 726     type_register(&ti);
 727     g_free(typename);
 728 }
 729
 730 static void mips_cpu_register_types(void)
 731 {
 732     int i;
 733
 734     type_register_static(&mips_cpu_type_info);
 735     for (i = 0; i < mips_defs_number; i++) {
 736         mips_register_cpudef_type(&mips_defs[i]);
 737     }
 738 }
 739
 740 type_init(mips_cpu_register_types)
 741
 742 static void mips_cpu_add_definition(gpointer data, gpointer user_data)
 743 {
 744     ObjectClass *oc = data;
 745     CpuDefinitionInfoList **cpu_list = user_data;
 746     CpuDefinitionInfo *info;
 747     const char *typename;
 748
 749     typename = object_class_get_name(oc);
 750     info = g_malloc0(sizeof(*info));
 751     info->name = g_strndup(typename,
 752                            strlen(typename) - strlen("-" TYPE_MIPS_CPU));
 753     info->q_typename = g_strdup(typename);
 754
 755     QAPI_LIST_PREPEND(*cpu_list, info);
 756 }
 757
 758 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
 759 {
 760     CpuDefinitionInfoList *cpu_list = NULL;
 761     GSList *list;
 762
 763     list = object_class_get_list(TYPE_MIPS_CPU, false);
 764     g_slist_foreach(list, mips_cpu_add_definition, &cpu_list);
 765     g_slist_free(list);
 766
 767     return cpu_list;
 768 }
 769
 770 /* Could be used by generic CPU object */
 771 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
 772 {
 773     DeviceState *cpu;
 774
 775     cpu = DEVICE(object_new(cpu_type));
 776     qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
 777     qdev_realize(cpu, NULL, &error_abort);
 778
 779     return MIPS_CPU(cpu);
 780 }
 781
 782 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
 783 {
 784     return (env->cpu_model->insn_flags & isa_mask) != 0;
 785 }
 786
 787 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa)
 788 {
 789     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
 790     return (mcc->cpu_def->insn_flags & isa) != 0;
 791 }
 792
 793 bool cpu_type_supports_cps_smp(const char *cpu_type)
 794 {
 795     const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
 796     return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
 797 }