2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
4 * Copyright (c) 2020 Western Digital
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef HW_OPENTITAN_H
20 #define HW_OPENTITAN_H
22 #include "hw/riscv/riscv_hart.h"
23 #include "hw/intc/ibex_plic.h"
24 #include "hw/char/ibex_uart.h"
26 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
27 #define RISCV_IBEX_SOC(obj) \
28 OBJECT_CHECK(LowRISCIbexSoCState, (obj), TYPE_RISCV_IBEX_SOC)
30 typedef struct LowRISCIbexSoCState
{
32 SysBusDevice parent_obj
;
35 RISCVHartArrayState cpus
;
39 MemoryRegion flash_mem
;
41 } LowRISCIbexSoCState
;
43 typedef struct OpenTitanState
{
45 SysBusDevice parent_obj
;
48 LowRISCIbexSoCState soc
;
67 IBEX_DEV_ALERT_HANDLER
,
74 IBEX_UART_RX_PARITY_ERR_IRQ
= 0x28,
75 IBEX_UART_RX_TIMEOUT_IRQ
= 0x27,
76 IBEX_UART_RX_BREAK_ERR_IRQ
= 0x26,
77 IBEX_UART_RX_FRAME_ERR_IRQ
= 0x25,
78 IBEX_UART_RX_OVERFLOW_IRQ
= 0x24,
79 IBEX_UART_TX_EMPTY_IRQ
= 0x23,
80 IBEX_UART_RX_WATERMARK_IRQ
= 0x22,
81 IBEX_UART_TX_WATERMARK_IRQ
= 0x21,