hw/riscv/sifive_u.c

   1 /*
   2  * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017 SiFive, Inc.
   6  * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
   7  *
   8  * Provides a board compatible with the SiFive Freedom U SDK:
   9  *
  10  * 0) UART
  11  * 1) CLINT (Core Level Interruptor)
  12  * 2) PLIC (Platform Level Interrupt Controller)
  13  * 3) PRCI (Power, Reset, Clock, Interrupt)
  14  * 4) OTP (One-Time Programmable) memory with stored serial number
  15  * 5) GEM (Gigabit Ethernet Controller) and management block
  16  *
  17  * This board currently generates devicetree dynamically that indicates at least
  18  * two harts and up to five harts.
  19  *
  20  * This program is free software; you can redistribute it and/or modify it
  21  * under the terms and conditions of the GNU General Public License,
  22  * version 2 or later, as published by the Free Software Foundation.
  23  *
  24  * This program is distributed in the hope it will be useful, but WITHOUT
  25  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  26  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  27  * more details.
  28  *
  29  * You should have received a copy of the GNU General Public License along with
  30  * this program.  If not, see <http://www.gnu.org/licenses/>.
  31  */
  32
  33 #include "qemu/osdep.h"
  34 #include "qemu/log.h"
  35 #include "qemu/error-report.h"
  36 #include "qapi/error.h"
  37 #include "hw/boards.h"
  38 #include "hw/loader.h"
  39 #include "hw/sysbus.h"
  40 #include "hw/char/serial.h"
  41 #include "hw/cpu/cluster.h"
  42 #include "hw/misc/unimp.h"
  43 #include "target/riscv/cpu.h"
  44 #include "hw/riscv/riscv_hart.h"
  45 #include "hw/riscv/sifive_plic.h"
  46 #include "hw/riscv/sifive_clint.h"
  47 #include "hw/riscv/sifive_uart.h"
  48 #include "hw/riscv/sifive_u.h"
  49 #include "hw/riscv/boot.h"
  50 #include "chardev/char.h"
  51 #include "net/eth.h"
  52 #include "sysemu/arch_init.h"
  53 #include "sysemu/device_tree.h"
  54 #include "sysemu/sysemu.h"
  55 #include "exec/address-spaces.h"
  56
  57 #include <libfdt.h>
  58
  59 #if defined(TARGET_RISCV32)
  60 # define BIOS_FILENAME "opensbi-riscv32-sifive_u-fw_jump.bin"
  61 #else
  62 # define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin"
  63 #endif
  64
  65 static const struct MemmapEntry {
  66     hwaddr base;
  67     hwaddr size;
  68 } sifive_u_memmap[] = {
  69     [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
  70     [SIFIVE_U_MROM] =     {     0x1000,    0x11000 },
  71     [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
  72     [SIFIVE_U_L2LIM] =    {  0x8000000,  0x2000000 },
  73     [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
  74     [SIFIVE_U_PRCI] =     { 0x10000000,     0x1000 },
  75     [SIFIVE_U_UART0] =    { 0x10010000,     0x1000 },
  76     [SIFIVE_U_UART1] =    { 0x10011000,     0x1000 },
  77     [SIFIVE_U_OTP] =      { 0x10070000,     0x1000 },
  78     [SIFIVE_U_FLASH0] =   { 0x20000000, 0x10000000 },
  79     [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
  80     [SIFIVE_U_GEM] =      { 0x10090000,     0x2000 },
  81     [SIFIVE_U_GEM_MGMT] = { 0x100a0000,     0x1000 },
  82 };
  83
  84 #define OTP_SERIAL          1
  85 #define GEM_REVISION        0x10070109
  86
  87 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
  88     uint64_t mem_size, const char *cmdline)
  89 {
  90     MachineState *ms = MACHINE(qdev_get_machine());
  91     void *fdt;
  92     int cpu;
  93     uint32_t *cells;
  94     char *nodename;
  95     char ethclk_names[] = "pclk\0hclk";
  96     uint32_t plic_phandle, prci_phandle, phandle = 1;
  97     uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
  98
  99     fdt = s->fdt = create_device_tree(&s->fdt_size);
 100     if (!fdt) {
 101         error_report("create_device_tree() failed");
 102         exit(1);
 103     }
 104
 105     qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
 106     qemu_fdt_setprop_string(fdt, "/", "compatible",
 107                             "sifive,hifive-unleashed-a00");
 108     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 109     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 110
 111     qemu_fdt_add_subnode(fdt, "/soc");
 112     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 113     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
 114     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 115     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 116
 117     hfclk_phandle = phandle++;
 118     nodename = g_strdup_printf("/hfclk");
 119     qemu_fdt_add_subnode(fdt, nodename);
 120     qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
 121     qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
 122     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 123         SIFIVE_U_HFCLK_FREQ);
 124     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
 125     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 126     g_free(nodename);
 127
 128     rtcclk_phandle = phandle++;
 129     nodename = g_strdup_printf("/rtcclk");
 130     qemu_fdt_add_subnode(fdt, nodename);
 131     qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
 132     qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
 133     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 134         SIFIVE_U_RTCCLK_FREQ);
 135     qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
 136     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
 137     g_free(nodename);
 138
 139     nodename = g_strdup_printf("/memory@%lx",
 140         (long)memmap[SIFIVE_U_DRAM].base);
 141     qemu_fdt_add_subnode(fdt, nodename);
 142     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 143         memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
 144         mem_size >> 32, mem_size);
 145     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 146     g_free(nodename);
 147
 148     qemu_fdt_add_subnode(fdt, "/cpus");
 149     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 150         SIFIVE_CLINT_TIMEBASE_FREQ);
 151     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 152     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 153
 154     for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
 155         int cpu_phandle = phandle++;
 156         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 157         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 158         char *isa;
 159         qemu_fdt_add_subnode(fdt, nodename);
 160         /* cpu 0 is the management hart that does not have mmu */
 161         if (cpu != 0) {
 162             qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 163             isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
 164         } else {
 165             isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
 166         }
 167         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 168         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 169         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 170         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 171         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 172         qemu_fdt_add_subnode(fdt, intc);
 173         qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
 174         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 175         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 176         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 177         g_free(isa);
 178         g_free(intc);
 179         g_free(nodename);
 180     }
 181
 182     cells =  g_new0(uint32_t, ms->smp.cpus * 4);
 183     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 184         nodename =
 185             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 186         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 187         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 188         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 189         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 190         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 191         g_free(nodename);
 192     }
 193     nodename = g_strdup_printf("/soc/clint@%lx",
 194         (long)memmap[SIFIVE_U_CLINT].base);
 195     qemu_fdt_add_subnode(fdt, nodename);
 196     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 197     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 198         0x0, memmap[SIFIVE_U_CLINT].base,
 199         0x0, memmap[SIFIVE_U_CLINT].size);
 200     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 201         cells, ms->smp.cpus * sizeof(uint32_t) * 4);
 202     g_free(cells);
 203     g_free(nodename);
 204
 205     prci_phandle = phandle++;
 206     nodename = g_strdup_printf("/soc/clock-controller@%lx",
 207         (long)memmap[SIFIVE_U_PRCI].base);
 208     qemu_fdt_add_subnode(fdt, nodename);
 209     qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
 210     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
 211     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 212         hfclk_phandle, rtcclk_phandle);
 213     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 214         0x0, memmap[SIFIVE_U_PRCI].base,
 215         0x0, memmap[SIFIVE_U_PRCI].size);
 216     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 217         "sifive,fu540-c000-prci");
 218     g_free(nodename);
 219
 220     plic_phandle = phandle++;
 221     cells =  g_new0(uint32_t, ms->smp.cpus * 4 - 2);
 222     for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
 223         nodename =
 224             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 225         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 226         /* cpu 0 is the management hart that does not have S-mode */
 227         if (cpu == 0) {
 228             cells[0] = cpu_to_be32(intc_phandle);
 229             cells[1] = cpu_to_be32(IRQ_M_EXT);
 230         } else {
 231             cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
 232             cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
 233             cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 234             cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
 235         }
 236         g_free(nodename);
 237     }
 238     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 239         (long)memmap[SIFIVE_U_PLIC].base);
 240     qemu_fdt_add_subnode(fdt, nodename);
 241     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 242     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 243     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 244     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 245         cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
 246     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 247         0x0, memmap[SIFIVE_U_PLIC].base,
 248         0x0, memmap[SIFIVE_U_PLIC].size);
 249     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
 250     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 251     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 252     g_free(cells);
 253     g_free(nodename);
 254
 255     phy_phandle = phandle++;
 256     nodename = g_strdup_printf("/soc/ethernet@%lx",
 257         (long)memmap[SIFIVE_U_GEM].base);
 258     qemu_fdt_add_subnode(fdt, nodename);
 259     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 260         "sifive,fu540-c000-gem");
 261     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 262         0x0, memmap[SIFIVE_U_GEM].base,
 263         0x0, memmap[SIFIVE_U_GEM].size,
 264         0x0, memmap[SIFIVE_U_GEM_MGMT].base,
 265         0x0, memmap[SIFIVE_U_GEM_MGMT].size);
 266     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 267     qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
 268     qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
 269     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 270     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 271     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 272         prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
 273     qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
 274         sizeof(ethclk_names));
 275     qemu_fdt_setprop(fdt, nodename, "local-mac-address",
 276         s->soc.gem.conf.macaddr.a, ETH_ALEN);
 277     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
 278     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
 279
 280     qemu_fdt_add_subnode(fdt, "/aliases");
 281     qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
 282
 283     g_free(nodename);
 284
 285     nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
 286         (long)memmap[SIFIVE_U_GEM].base);
 287     qemu_fdt_add_subnode(fdt, nodename);
 288     qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
 289     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
 290     g_free(nodename);
 291
 292     nodename = g_strdup_printf("/soc/serial@%lx",
 293         (long)memmap[SIFIVE_U_UART0].base);
 294     qemu_fdt_add_subnode(fdt, nodename);
 295     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
 296     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 297         0x0, memmap[SIFIVE_U_UART0].base,
 298         0x0, memmap[SIFIVE_U_UART0].size);
 299     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
 300         prci_phandle, PRCI_CLK_TLCLK);
 301     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 302     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
 303
 304     qemu_fdt_add_subnode(fdt, "/chosen");
 305     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 306     if (cmdline) {
 307         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 308     }
 309
 310     qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
 311
 312     g_free(nodename);
 313 }
 314
 315 static void riscv_sifive_u_init(MachineState *machine)
 316 {
 317     const struct MemmapEntry *memmap = sifive_u_memmap;
 318     SiFiveUState *s = RISCV_U_MACHINE(machine);
 319     MemoryRegion *system_memory = get_system_memory();
 320     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 321     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
 322     target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
 323     int i;
 324
 325     /* Initialize SoC */
 326     object_initialize_child(OBJECT(machine), "soc", &s->soc,
 327                             sizeof(s->soc), TYPE_RISCV_U_SOC,
 328                             &error_abort, NULL);
 329     object_property_set_bool(OBJECT(&s->soc), true, "realized",
 330                             &error_abort);
 331
 332     /* register RAM */
 333     memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
 334                            machine->ram_size, &error_fatal);
 335     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
 336                                 main_mem);
 337
 338     /* register QSPI0 Flash */
 339     memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
 340                            memmap[SIFIVE_U_FLASH0].size, &error_fatal);
 341     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
 342                                 flash0);
 343
 344     /* create device tree */
 345     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 346
 347     riscv_find_and_load_firmware(machine, BIOS_FILENAME,
 348                                  memmap[SIFIVE_U_DRAM].base);
 349
 350     if (machine->kernel_filename) {
 351         uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
 352                                                   NULL);
 353
 354         if (machine->initrd_filename) {
 355             hwaddr start;
 356             hwaddr end = riscv_load_initrd(machine->initrd_filename,
 357                                            machine->ram_size, kernel_entry,
 358                                            &start);
 359             qemu_fdt_setprop_cell(s->fdt, "/chosen",
 360                                   "linux,initrd-start", start);
 361             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 362                                   end);
 363         }
 364     }
 365
 366     if (s->start_in_flash) {
 367         start_addr = memmap[SIFIVE_U_FLASH0].base;
 368     }
 369
 370     /* reset vector */
 371     uint32_t reset_vec[8] = {
 372         0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
 373         0x02028593,                    /*     addi   a1, t0, %pcrel_lo(1b) */
 374         0xf1402573,                    /*     csrr   a0, mhartid  */
 375 #if defined(TARGET_RISCV32)
 376         0x0182a283,                    /*     lw     t0, 24(t0) */
 377 #elif defined(TARGET_RISCV64)
 378         0x0182b283,                    /*     ld     t0, 24(t0) */
 379 #endif
 380         0x00028067,                    /*     jr     t0 */
 381         0x00000000,
 382         start_addr,                    /* start: .dword */
 383         0x00000000,
 384                                        /* dtb: */
 385     };
 386
 387     /* copy in the reset vector in little_endian byte order */
 388     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 389         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 390     }
 391     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 392                           memmap[SIFIVE_U_MROM].base, &address_space_memory);
 393
 394     /* copy in the device tree */
 395     if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
 396             memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
 397         error_report("not enough space to store device-tree");
 398         exit(1);
 399     }
 400     qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
 401     rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
 402                           memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
 403                           &address_space_memory);
 404 }
 405
 406 static void riscv_sifive_u_soc_init(Object *obj)
 407 {
 408     MachineState *ms = MACHINE(qdev_get_machine());
 409     SiFiveUSoCState *s = RISCV_U_SOC(obj);
 410
 411     object_initialize_child(obj, "e-cluster", &s->e_cluster,
 412                             sizeof(s->e_cluster), TYPE_CPU_CLUSTER,
 413                             &error_abort, NULL);
 414     qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
 415
 416     object_initialize_child(OBJECT(&s->e_cluster), "e-cpus",
 417                             &s->e_cpus, sizeof(s->e_cpus),
 418                             TYPE_RISCV_HART_ARRAY, &error_abort,
 419                             NULL);
 420     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
 421     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
 422     qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
 423
 424     object_initialize_child(obj, "u-cluster", &s->u_cluster,
 425                             sizeof(s->u_cluster), TYPE_CPU_CLUSTER,
 426                             &error_abort, NULL);
 427     qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
 428
 429     object_initialize_child(OBJECT(&s->u_cluster), "u-cpus",
 430                             &s->u_cpus, sizeof(s->u_cpus),
 431                             TYPE_RISCV_HART_ARRAY, &error_abort,
 432                             NULL);
 433     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
 434     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
 435     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
 436
 437     sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
 438                           TYPE_SIFIVE_U_PRCI);
 439     sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
 440                           TYPE_SIFIVE_U_OTP);
 441     qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
 442     sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
 443                           TYPE_CADENCE_GEM);
 444 }
 445
 446 static bool sifive_u_get_start_in_flash(Object *obj, Error **errp)
 447 {
 448     SiFiveUState *s = RISCV_U_MACHINE(obj);
 449
 450     return s->start_in_flash;
 451 }
 452
 453 static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp)
 454 {
 455     SiFiveUState *s = RISCV_U_MACHINE(obj);
 456
 457     s->start_in_flash = value;
 458 }
 459
 460 static void riscv_sifive_u_machine_instance_init(Object *obj)
 461 {
 462     SiFiveUState *s = RISCV_U_MACHINE(obj);
 463
 464     s->start_in_flash = false;
 465     object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_flash,
 466                              sifive_u_set_start_in_flash, NULL);
 467     object_property_set_description(obj, "start-in-flash",
 468                                     "Set on to tell QEMU's ROM to jump to " \
 469                                     "flash. Otherwise QEMU will jump to DRAM",
 470                                     NULL);
 471 }
 472
 473 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
 474 {
 475     MachineState *ms = MACHINE(qdev_get_machine());
 476     SiFiveUSoCState *s = RISCV_U_SOC(dev);
 477     const struct MemmapEntry *memmap = sifive_u_memmap;
 478     MemoryRegion *system_memory = get_system_memory();
 479     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 480     MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
 481     qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
 482     char *plic_hart_config;
 483     size_t plic_hart_config_len;
 484     int i;
 485     Error *err = NULL;
 486     NICInfo *nd = &nd_table[0];
 487
 488     object_property_set_bool(OBJECT(&s->e_cpus), true, "realized",
 489                              &error_abort);
 490     object_property_set_bool(OBJECT(&s->u_cpus), true, "realized",
 491                              &error_abort);
 492     /*
 493      * The cluster must be realized after the RISC-V hart array container,
 494      * as the container's CPU object is only created on realize, and the
 495      * CPU must exist and have been parented into the cluster before the
 496      * cluster is realized.
 497      */
 498     object_property_set_bool(OBJECT(&s->e_cluster), true, "realized",
 499                              &error_abort);
 500     object_property_set_bool(OBJECT(&s->u_cluster), true, "realized",
 501                              &error_abort);
 502
 503     /* boot rom */
 504     memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
 505                            memmap[SIFIVE_U_MROM].size, &error_fatal);
 506     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
 507                                 mask_rom);
 508
 509     /*
 510      * Add L2-LIM at reset size.
 511      * This should be reduced in size as the L2 Cache Controller WayEnable
 512      * register is incremented. Unfortunately I don't see a nice (or any) way
 513      * to handle reducing or blocking out the L2 LIM while still allowing it
 514      * be re returned to all enabled after a reset. For the time being, just
 515      * leave it enabled all the time. This won't break anything, but will be
 516      * too generous to misbehaving guests.
 517      */
 518     memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
 519                            memmap[SIFIVE_U_L2LIM].size, &error_fatal);
 520     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
 521                                 l2lim_mem);
 522
 523     /* create PLIC hart topology configuration string */
 524     plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
 525                            ms->smp.cpus;
 526     plic_hart_config = g_malloc0(plic_hart_config_len);
 527     for (i = 0; i < ms->smp.cpus; i++) {
 528         if (i != 0) {
 529             strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
 530                     plic_hart_config_len);
 531         } else {
 532             strncat(plic_hart_config, "M", plic_hart_config_len);
 533         }
 534         plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
 535     }
 536
 537     /* MMIO */
 538     s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
 539         plic_hart_config,
 540         SIFIVE_U_PLIC_NUM_SOURCES,
 541         SIFIVE_U_PLIC_NUM_PRIORITIES,
 542         SIFIVE_U_PLIC_PRIORITY_BASE,
 543         SIFIVE_U_PLIC_PENDING_BASE,
 544         SIFIVE_U_PLIC_ENABLE_BASE,
 545         SIFIVE_U_PLIC_ENABLE_STRIDE,
 546         SIFIVE_U_PLIC_CONTEXT_BASE,
 547         SIFIVE_U_PLIC_CONTEXT_STRIDE,
 548         memmap[SIFIVE_U_PLIC].size);
 549     g_free(plic_hart_config);
 550     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
 551         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
 552     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
 553         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
 554     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
 555         memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
 556         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
 557
 558     object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
 559     sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
 560
 561     object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
 562     sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
 563
 564     for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
 565         plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
 566     }
 567
 568     if (nd->used) {
 569         qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 570         qdev_set_nic_properties(DEVICE(&s->gem), nd);
 571     }
 572     object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
 573                             &error_abort);
 574     object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
 575     if (err) {
 576         error_propagate(errp, err);
 577         return;
 578     }
 579     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
 580     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
 581                        plic_gpios[SIFIVE_U_GEM_IRQ]);
 582
 583     create_unimplemented_device("riscv.sifive.u.gem-mgmt",
 584         memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
 585 }
 586
 587 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
 588 {
 589     DeviceClass *dc = DEVICE_CLASS(oc);
 590
 591     dc->realize = riscv_sifive_u_soc_realize;
 592     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 593     dc->user_creatable = false;
 594 }
 595
 596 static const TypeInfo riscv_sifive_u_soc_type_info = {
 597     .name = TYPE_RISCV_U_SOC,
 598     .parent = TYPE_DEVICE,
 599     .instance_size = sizeof(SiFiveUSoCState),
 600     .instance_init = riscv_sifive_u_soc_init,
 601     .class_init = riscv_sifive_u_soc_class_init,
 602 };
 603
 604 static void riscv_sifive_u_soc_register_types(void)
 605 {
 606     type_register_static(&riscv_sifive_u_soc_type_info);
 607 }
 608
 609 type_init(riscv_sifive_u_soc_register_types)
 610
 611 static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data)
 612 {
 613     MachineClass *mc = MACHINE_CLASS(oc);
 614
 615     mc->desc = "RISC-V Board compatible with SiFive U SDK";
 616     mc->init = riscv_sifive_u_init;
 617     mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
 618     mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
 619     mc->default_cpus = mc->min_cpus;
 620 }
 621
 622 static const TypeInfo riscv_sifive_u_machine_typeinfo = {
 623     .name       = MACHINE_TYPE_NAME("sifive_u"),
 624     .parent     = TYPE_MACHINE,
 625     .class_init = riscv_sifive_u_machine_class_init,
 626     .instance_init = riscv_sifive_u_machine_instance_init,
 627     .instance_size = sizeof(SiFiveUState),
 628 };
 629
 630 static void riscv_sifive_u_machine_init_register_types(void)
 631 {
 632     type_register_static(&riscv_sifive_u_machine_typeinfo);
 633 }
 634
 635 type_init(riscv_sifive_u_machine_init_register_types)