2 * Exynos4210 UART Emulation
4 * Copyright (C) 2011 Samsung Electronics Co Ltd.
5 * Maksim Kozlov, <m.kozlov@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "hw/sysbus.h"
24 #include "migration/vmstate.h"
25 #include "qemu/error-report.h"
26 #include "qemu/module.h"
27 #include "qemu/timer.h"
28 #include "chardev/char-fe.h"
29 #include "chardev/char-serial.h"
31 #include "hw/arm/exynos4210.h"
33 #include "hw/qdev-properties.h"
38 * Offsets for UART registers relative to SFR base address
42 #define ULCON 0x0000 /* Line Control */
43 #define UCON 0x0004 /* Control */
44 #define UFCON 0x0008 /* FIFO Control */
45 #define UMCON 0x000C /* Modem Control */
46 #define UTRSTAT 0x0010 /* Tx/Rx Status */
47 #define UERSTAT 0x0014 /* UART Error Status */
48 #define UFSTAT 0x0018 /* FIFO Status */
49 #define UMSTAT 0x001C /* Modem Status */
50 #define UTXH 0x0020 /* Transmit Buffer */
51 #define URXH 0x0024 /* Receive Buffer */
52 #define UBRDIV 0x0028 /* Baud Rate Divisor */
53 #define UFRACVAL 0x002C /* Divisor Fractional Value */
54 #define UINTP 0x0030 /* Interrupt Pending */
55 #define UINTSP 0x0034 /* Interrupt Source Pending */
56 #define UINTM 0x0038 /* Interrupt Mask */
59 * for indexing register in the uint32_t array
61 * 'reg' - register offset (see offsets definitions above)
64 #define I_(reg) (reg / sizeof(uint32_t))
66 typedef struct Exynos4210UartReg
{
67 const char *name
; /* the only reason is the debug output */
72 static const Exynos4210UartReg exynos4210_uart_regs
[] = {
73 {"ULCON", ULCON
, 0x00000000},
74 {"UCON", UCON
, 0x00003000},
75 {"UFCON", UFCON
, 0x00000000},
76 {"UMCON", UMCON
, 0x00000000},
77 {"UTRSTAT", UTRSTAT
, 0x00000006}, /* RO */
78 {"UERSTAT", UERSTAT
, 0x00000000}, /* RO */
79 {"UFSTAT", UFSTAT
, 0x00000000}, /* RO */
80 {"UMSTAT", UMSTAT
, 0x00000000}, /* RO */
81 {"UTXH", UTXH
, 0x5c5c5c5c}, /* WO, undefined reset value*/
82 {"URXH", URXH
, 0x00000000}, /* RO */
83 {"UBRDIV", UBRDIV
, 0x00000000},
84 {"UFRACVAL", UFRACVAL
, 0x00000000},
85 {"UINTP", UINTP
, 0x00000000},
86 {"UINTSP", UINTSP
, 0x00000000},
87 {"UINTM", UINTM
, 0x00000000},
90 #define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C
92 /* UART FIFO Control */
93 #define UFCON_FIFO_ENABLE 0x1
94 #define UFCON_Rx_FIFO_RESET 0x2
95 #define UFCON_Tx_FIFO_RESET 0x4
96 #define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8
97 #define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
98 #define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4
99 #define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
101 /* Uart FIFO Status */
102 #define UFSTAT_Rx_FIFO_COUNT 0xff
103 #define UFSTAT_Rx_FIFO_FULL 0x100
104 #define UFSTAT_Rx_FIFO_ERROR 0x200
105 #define UFSTAT_Tx_FIFO_COUNT_SHIFT 16
106 #define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
107 #define UFSTAT_Tx_FIFO_FULL_SHIFT 24
108 #define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
110 /* UART Interrupt Source Pending */
111 #define UINTSP_RXD 0x1 /* Receive interrupt */
112 #define UINTSP_ERROR 0x2 /* Error interrupt */
113 #define UINTSP_TXD 0x4 /* Transmit interrupt */
114 #define UINTSP_MODEM 0x8 /* Modem interrupt */
116 /* UART Line Control */
117 #define ULCON_IR_MODE_SHIFT 6
118 #define ULCON_PARITY_SHIFT 3
119 #define ULCON_STOP_BIT_SHIFT 1
121 /* UART Tx/Rx Status */
122 #define UTRSTAT_Rx_TIMEOUT 0x8
123 #define UTRSTAT_TRANSMITTER_EMPTY 0x4
124 #define UTRSTAT_Tx_BUFFER_EMPTY 0x2
125 #define UTRSTAT_Rx_BUFFER_DATA_READY 0x1
127 /* UART Error Status */
128 #define UERSTAT_OVERRUN 0x1
129 #define UERSTAT_PARITY 0x2
130 #define UERSTAT_FRAME 0x4
131 #define UERSTAT_BREAK 0x8
135 uint32_t sp
, rp
; /* store and retrieve pointers */
137 } Exynos4210UartFIFO
;
139 #define TYPE_EXYNOS4210_UART "exynos4210.uart"
140 #define EXYNOS4210_UART(obj) \
141 OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART)
143 typedef struct Exynos4210UartState
{
144 SysBusDevice parent_obj
;
148 uint32_t reg
[EXYNOS4210_UART_REGS_MEM_SIZE
/ sizeof(uint32_t)];
149 Exynos4210UartFIFO rx
;
150 Exynos4210UartFIFO tx
;
152 QEMUTimer
*fifo_timeout_timer
;
153 uint64_t wordtime
; /* word time in ns */
161 } Exynos4210UartState
;
164 /* Used only for tracing */
165 static const char *exynos4210_uart_regname(hwaddr offset
)
170 for (i
= 0; i
< ARRAY_SIZE(exynos4210_uart_regs
); i
++) {
171 if (offset
== exynos4210_uart_regs
[i
].offset
) {
172 return exynos4210_uart_regs
[i
].name
;
180 static void fifo_store(Exynos4210UartFIFO
*q
, uint8_t ch
)
183 q
->sp
= (q
->sp
+ 1) % q
->size
;
186 static uint8_t fifo_retrieve(Exynos4210UartFIFO
*q
)
188 uint8_t ret
= q
->data
[q
->rp
];
189 q
->rp
= (q
->rp
+ 1) % q
->size
;
193 static int fifo_elements_number(const Exynos4210UartFIFO
*q
)
196 return q
->size
- q
->rp
+ q
->sp
;
199 return q
->sp
- q
->rp
;
202 static int fifo_empty_elements_number(const Exynos4210UartFIFO
*q
)
204 return q
->size
- fifo_elements_number(q
);
207 static void fifo_reset(Exynos4210UartFIFO
*q
)
212 q
->data
= (uint8_t *)g_malloc0(q
->size
);
218 static uint32_t exynos4210_uart_FIFO_trigger_level(uint32_t channel
,
237 trace_exynos_uart_channel_error(channel
);
244 exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState
*s
)
248 reg
= (s
->reg
[I_(UFCON
)] & UFCON_Tx_FIFO_TRIGGER_LEVEL
) >>
249 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT
;
251 return exynos4210_uart_FIFO_trigger_level(s
->channel
, reg
);
255 exynos4210_uart_Rx_FIFO_trigger_level(const Exynos4210UartState
*s
)
259 reg
= ((s
->reg
[I_(UFCON
)] & UFCON_Rx_FIFO_TRIGGER_LEVEL
) >>
260 UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT
) + 1;
262 return exynos4210_uart_FIFO_trigger_level(s
->channel
, reg
);
266 * Update Rx DMA busy signal if Rx DMA is enabled. For simplicity,
267 * mark DMA as busy if DMA is enabled and the receive buffer is empty.
269 static void exynos4210_uart_update_dmabusy(Exynos4210UartState
*s
)
271 bool rx_dma_enabled
= (s
->reg
[I_(UCON
)] & 0x03) == 0x02;
272 uint32_t count
= fifo_elements_number(&s
->rx
);
274 if (rx_dma_enabled
&& !count
) {
275 qemu_irq_raise(s
->dmairq
);
276 trace_exynos_uart_dmabusy(s
->channel
);
278 qemu_irq_lower(s
->dmairq
);
279 trace_exynos_uart_dmaready(s
->channel
);
283 static void exynos4210_uart_update_irq(Exynos4210UartState
*s
)
286 * The Tx interrupt is always requested if the number of data in the
287 * transmit FIFO is smaller than the trigger level.
289 if (s
->reg
[I_(UFCON
)] & UFCON_FIFO_ENABLE
) {
290 uint32_t count
= (s
->reg
[I_(UFSTAT
)] & UFSTAT_Tx_FIFO_COUNT
) >>
291 UFSTAT_Tx_FIFO_COUNT_SHIFT
;
293 if (count
<= exynos4210_uart_Tx_FIFO_trigger_level(s
)) {
294 s
->reg
[I_(UINTSP
)] |= UINTSP_TXD
;
298 * Rx interrupt if trigger level is reached or if rx timeout
299 * interrupt is disabled and there is data in the receive buffer
301 count
= fifo_elements_number(&s
->rx
);
302 if ((count
&& !(s
->reg
[I_(UCON
)] & 0x80)) ||
303 count
>= exynos4210_uart_Rx_FIFO_trigger_level(s
)) {
304 exynos4210_uart_update_dmabusy(s
);
305 s
->reg
[I_(UINTSP
)] |= UINTSP_RXD
;
306 timer_del(s
->fifo_timeout_timer
);
308 } else if (s
->reg
[I_(UTRSTAT
)] & UTRSTAT_Rx_BUFFER_DATA_READY
) {
309 exynos4210_uart_update_dmabusy(s
);
310 s
->reg
[I_(UINTSP
)] |= UINTSP_RXD
;
313 s
->reg
[I_(UINTP
)] = s
->reg
[I_(UINTSP
)] & ~s
->reg
[I_(UINTM
)];
315 if (s
->reg
[I_(UINTP
)]) {
316 qemu_irq_raise(s
->irq
);
317 trace_exynos_uart_irq_raised(s
->channel
, s
->reg
[I_(UINTP
)]);
319 qemu_irq_lower(s
->irq
);
320 trace_exynos_uart_irq_lowered(s
->channel
);
324 static void exynos4210_uart_timeout_int(void *opaque
)
326 Exynos4210UartState
*s
= opaque
;
328 trace_exynos_uart_rx_timeout(s
->channel
, s
->reg
[I_(UTRSTAT
)],
331 if ((s
->reg
[I_(UTRSTAT
)] & UTRSTAT_Rx_BUFFER_DATA_READY
) ||
332 (s
->reg
[I_(UCON
)] & (1 << 11))) {
333 s
->reg
[I_(UINTSP
)] |= UINTSP_RXD
;
334 s
->reg
[I_(UTRSTAT
)] |= UTRSTAT_Rx_TIMEOUT
;
335 exynos4210_uart_update_dmabusy(s
);
336 exynos4210_uart_update_irq(s
);
340 static void exynos4210_uart_update_parameters(Exynos4210UartState
*s
)
342 int speed
, parity
, data_bits
, stop_bits
;
343 QEMUSerialSetParams ssp
;
346 if (s
->reg
[I_(UBRDIV
)] == 0) {
350 if (s
->reg
[I_(ULCON
)] & 0x20) {
351 if (s
->reg
[I_(ULCON
)] & 0x28) {
360 if (s
->reg
[I_(ULCON
)] & 0x4) {
366 data_bits
= (s
->reg
[I_(ULCON
)] & 0x3) + 5;
368 uclk_rate
= 24000000;
370 speed
= uclk_rate
/ ((16 * (s
->reg
[I_(UBRDIV
)]) & 0xffff) +
371 (s
->reg
[I_(UFRACVAL
)] & 0x7) + 16);
375 ssp
.data_bits
= data_bits
;
376 ssp
.stop_bits
= stop_bits
;
378 s
->wordtime
= NANOSECONDS_PER_SECOND
* (data_bits
+ stop_bits
+ 1) / speed
;
380 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
382 trace_exynos_uart_update_params(
383 s
->channel
, speed
, parity
, data_bits
, stop_bits
, s
->wordtime
);
386 static void exynos4210_uart_rx_timeout_set(Exynos4210UartState
*s
)
388 if (s
->reg
[I_(UCON
)] & 0x80) {
389 uint32_t timeout
= ((s
->reg
[I_(UCON
)] >> 12) & 0x0f) * s
->wordtime
;
391 timer_mod(s
->fifo_timeout_timer
,
392 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + timeout
);
394 timer_del(s
->fifo_timeout_timer
);
398 static void exynos4210_uart_write(void *opaque
, hwaddr offset
,
399 uint64_t val
, unsigned size
)
401 Exynos4210UartState
*s
= (Exynos4210UartState
*)opaque
;
404 trace_exynos_uart_write(s
->channel
, offset
,
405 exynos4210_uart_regname(offset
), val
);
411 s
->reg
[I_(offset
)] = val
;
412 exynos4210_uart_update_parameters(s
);
415 s
->reg
[I_(UFCON
)] = val
;
416 if (val
& UFCON_Rx_FIFO_RESET
) {
418 s
->reg
[I_(UFCON
)] &= ~UFCON_Rx_FIFO_RESET
;
419 trace_exynos_uart_rx_fifo_reset(s
->channel
);
421 if (val
& UFCON_Tx_FIFO_RESET
) {
423 s
->reg
[I_(UFCON
)] &= ~UFCON_Tx_FIFO_RESET
;
424 trace_exynos_uart_tx_fifo_reset(s
->channel
);
429 if (qemu_chr_fe_backend_connected(&s
->chr
)) {
430 s
->reg
[I_(UTRSTAT
)] &= ~(UTRSTAT_TRANSMITTER_EMPTY
|
431 UTRSTAT_Tx_BUFFER_EMPTY
);
433 /* XXX this blocks entire thread. Rewrite to use
434 * qemu_chr_fe_write and background I/O callbacks */
435 qemu_chr_fe_write_all(&s
->chr
, &ch
, 1);
436 trace_exynos_uart_tx(s
->channel
, ch
);
437 s
->reg
[I_(UTRSTAT
)] |= UTRSTAT_TRANSMITTER_EMPTY
|
438 UTRSTAT_Tx_BUFFER_EMPTY
;
439 s
->reg
[I_(UINTSP
)] |= UINTSP_TXD
;
440 exynos4210_uart_update_irq(s
);
445 s
->reg
[I_(UINTP
)] &= ~val
;
446 s
->reg
[I_(UINTSP
)] &= ~val
;
447 trace_exynos_uart_intclr(s
->channel
, s
->reg
[I_(UINTP
)]);
448 exynos4210_uart_update_irq(s
);
451 if (val
& UTRSTAT_Rx_TIMEOUT
) {
452 s
->reg
[I_(UTRSTAT
)] &= ~UTRSTAT_Rx_TIMEOUT
;
459 trace_exynos_uart_ro_write(
460 s
->channel
, exynos4210_uart_regname(offset
), offset
);
463 s
->reg
[I_(UINTSP
)] &= ~val
;
466 s
->reg
[I_(UINTM
)] = val
;
467 exynos4210_uart_update_irq(s
);
472 s
->reg
[I_(offset
)] = val
;
477 static uint64_t exynos4210_uart_read(void *opaque
, hwaddr offset
,
480 Exynos4210UartState
*s
= (Exynos4210UartState
*)opaque
;
484 case UERSTAT
: /* Read Only */
485 res
= s
->reg
[I_(UERSTAT
)];
486 s
->reg
[I_(UERSTAT
)] = 0;
487 trace_exynos_uart_read(s
->channel
, offset
,
488 exynos4210_uart_regname(offset
), res
);
490 case UFSTAT
: /* Read Only */
491 s
->reg
[I_(UFSTAT
)] = fifo_elements_number(&s
->rx
) & 0xff;
492 if (fifo_empty_elements_number(&s
->rx
) == 0) {
493 s
->reg
[I_(UFSTAT
)] |= UFSTAT_Rx_FIFO_FULL
;
494 s
->reg
[I_(UFSTAT
)] &= ~0xff;
496 trace_exynos_uart_read(s
->channel
, offset
,
497 exynos4210_uart_regname(offset
),
499 return s
->reg
[I_(UFSTAT
)];
501 if (s
->reg
[I_(UFCON
)] & UFCON_FIFO_ENABLE
) {
502 if (fifo_elements_number(&s
->rx
)) {
503 res
= fifo_retrieve(&s
->rx
);
504 trace_exynos_uart_rx(s
->channel
, res
);
505 if (!fifo_elements_number(&s
->rx
)) {
506 s
->reg
[I_(UTRSTAT
)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY
;
508 s
->reg
[I_(UTRSTAT
)] |= UTRSTAT_Rx_BUFFER_DATA_READY
;
511 trace_exynos_uart_rx_error(s
->channel
);
512 s
->reg
[I_(UINTSP
)] |= UINTSP_ERROR
;
513 exynos4210_uart_update_irq(s
);
517 s
->reg
[I_(UTRSTAT
)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY
;
518 res
= s
->reg
[I_(URXH
)];
520 exynos4210_uart_update_dmabusy(s
);
521 trace_exynos_uart_read(s
->channel
, offset
,
522 exynos4210_uart_regname(offset
), res
);
525 trace_exynos_uart_wo_read(s
->channel
, exynos4210_uart_regname(offset
),
529 trace_exynos_uart_read(s
->channel
, offset
,
530 exynos4210_uart_regname(offset
),
532 return s
->reg
[I_(offset
)];
535 trace_exynos_uart_read(s
->channel
, offset
, exynos4210_uart_regname(offset
),
540 static const MemoryRegionOps exynos4210_uart_ops
= {
541 .read
= exynos4210_uart_read
,
542 .write
= exynos4210_uart_write
,
543 .endianness
= DEVICE_NATIVE_ENDIAN
,
545 .max_access_size
= 4,
550 static int exynos4210_uart_can_receive(void *opaque
)
552 Exynos4210UartState
*s
= (Exynos4210UartState
*)opaque
;
554 return fifo_empty_elements_number(&s
->rx
);
557 static void exynos4210_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
559 Exynos4210UartState
*s
= (Exynos4210UartState
*)opaque
;
562 if (s
->reg
[I_(UFCON
)] & UFCON_FIFO_ENABLE
) {
563 if (fifo_empty_elements_number(&s
->rx
) < size
) {
564 size
= fifo_empty_elements_number(&s
->rx
);
565 s
->reg
[I_(UINTSP
)] |= UINTSP_ERROR
;
567 for (i
= 0; i
< size
; i
++) {
568 fifo_store(&s
->rx
, buf
[i
]);
570 exynos4210_uart_rx_timeout_set(s
);
572 s
->reg
[I_(URXH
)] = buf
[0];
574 s
->reg
[I_(UTRSTAT
)] |= UTRSTAT_Rx_BUFFER_DATA_READY
;
576 exynos4210_uart_update_irq(s
);
580 static void exynos4210_uart_event(void *opaque
, QEMUChrEvent event
)
582 Exynos4210UartState
*s
= (Exynos4210UartState
*)opaque
;
584 if (event
== CHR_EVENT_BREAK
) {
585 /* When the RxDn is held in logic 0, then a null byte is pushed into the
587 fifo_store(&s
->rx
, '\0');
588 s
->reg
[I_(UERSTAT
)] |= UERSTAT_BREAK
;
589 exynos4210_uart_update_irq(s
);
594 static void exynos4210_uart_reset(DeviceState
*dev
)
596 Exynos4210UartState
*s
= EXYNOS4210_UART(dev
);
599 for (i
= 0; i
< ARRAY_SIZE(exynos4210_uart_regs
); i
++) {
600 s
->reg
[I_(exynos4210_uart_regs
[i
].offset
)] =
601 exynos4210_uart_regs
[i
].reset_value
;
607 trace_exynos_uart_rxsize(s
->channel
, s
->rx
.size
);
610 static int exynos4210_uart_post_load(void *opaque
, int version_id
)
612 Exynos4210UartState
*s
= (Exynos4210UartState
*)opaque
;
614 exynos4210_uart_update_parameters(s
);
615 exynos4210_uart_rx_timeout_set(s
);
620 static const VMStateDescription vmstate_exynos4210_uart_fifo
= {
621 .name
= "exynos4210.uart.fifo",
623 .minimum_version_id
= 1,
624 .post_load
= exynos4210_uart_post_load
,
625 .fields
= (VMStateField
[]) {
626 VMSTATE_UINT32(sp
, Exynos4210UartFIFO
),
627 VMSTATE_UINT32(rp
, Exynos4210UartFIFO
),
628 VMSTATE_VBUFFER_UINT32(data
, Exynos4210UartFIFO
, 1, NULL
, size
),
629 VMSTATE_END_OF_LIST()
633 static const VMStateDescription vmstate_exynos4210_uart
= {
634 .name
= "exynos4210.uart",
636 .minimum_version_id
= 1,
637 .fields
= (VMStateField
[]) {
638 VMSTATE_STRUCT(rx
, Exynos4210UartState
, 1,
639 vmstate_exynos4210_uart_fifo
, Exynos4210UartFIFO
),
640 VMSTATE_UINT32_ARRAY(reg
, Exynos4210UartState
,
641 EXYNOS4210_UART_REGS_MEM_SIZE
/ sizeof(uint32_t)),
642 VMSTATE_END_OF_LIST()
646 DeviceState
*exynos4210_uart_create(hwaddr addr
,
655 dev
= qdev_create(NULL
, TYPE_EXYNOS4210_UART
);
657 qdev_prop_set_chr(dev
, "chardev", chr
);
658 qdev_prop_set_uint32(dev
, "channel", channel
);
659 qdev_prop_set_uint32(dev
, "rx-size", fifo_size
);
660 qdev_prop_set_uint32(dev
, "tx-size", fifo_size
);
662 bus
= SYS_BUS_DEVICE(dev
);
663 qdev_init_nofail(dev
);
664 if (addr
!= (hwaddr
)-1) {
665 sysbus_mmio_map(bus
, 0, addr
);
667 sysbus_connect_irq(bus
, 0, irq
);
672 static void exynos4210_uart_init(Object
*obj
)
674 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
675 Exynos4210UartState
*s
= EXYNOS4210_UART(dev
);
677 s
->wordtime
= NANOSECONDS_PER_SECOND
* 10 / 9600;
680 memory_region_init_io(&s
->iomem
, obj
, &exynos4210_uart_ops
, s
,
681 "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE
);
682 sysbus_init_mmio(dev
, &s
->iomem
);
684 sysbus_init_irq(dev
, &s
->irq
);
685 sysbus_init_irq(dev
, &s
->dmairq
);
688 static void exynos4210_uart_realize(DeviceState
*dev
, Error
**errp
)
690 Exynos4210UartState
*s
= EXYNOS4210_UART(dev
);
692 s
->fifo_timeout_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
693 exynos4210_uart_timeout_int
, s
);
695 qemu_chr_fe_set_handlers(&s
->chr
, exynos4210_uart_can_receive
,
696 exynos4210_uart_receive
, exynos4210_uart_event
,
697 NULL
, s
, NULL
, true);
700 static Property exynos4210_uart_properties
[] = {
701 DEFINE_PROP_CHR("chardev", Exynos4210UartState
, chr
),
702 DEFINE_PROP_UINT32("channel", Exynos4210UartState
, channel
, 0),
703 DEFINE_PROP_UINT32("rx-size", Exynos4210UartState
, rx
.size
, 16),
704 DEFINE_PROP_UINT32("tx-size", Exynos4210UartState
, tx
.size
, 16),
705 DEFINE_PROP_END_OF_LIST(),
708 static void exynos4210_uart_class_init(ObjectClass
*klass
, void *data
)
710 DeviceClass
*dc
= DEVICE_CLASS(klass
);
712 dc
->realize
= exynos4210_uart_realize
;
713 dc
->reset
= exynos4210_uart_reset
;
714 device_class_set_props(dc
, exynos4210_uart_properties
);
715 dc
->vmsd
= &vmstate_exynos4210_uart
;
718 static const TypeInfo exynos4210_uart_info
= {
719 .name
= TYPE_EXYNOS4210_UART
,
720 .parent
= TYPE_SYS_BUS_DEVICE
,
721 .instance_size
= sizeof(Exynos4210UartState
),
722 .instance_init
= exynos4210_uart_init
,
723 .class_init
= exynos4210_uart_class_init
,
726 static void exynos4210_uart_register(void)
728 type_register_static(&exynos4210_uart_info
);
731 type_init(exynos4210_uart_register
)