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qjson.h: Remove more GCC_FMT_ATTR markups
[qemu/ar7.git] / linux-user / main.c
blob65f356a4b2df325489d62d79d9d805b8e33a279c
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <sys/mman.h>
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qemu-common.h"
25 #include "qemu.h"
26 #include "qemu/cache-utils.h"
27 #include "cpu.h"
28 #if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64)
29 #include "vsyscall.h"
30 #endif
31 #include "tcg.h"
32 #include "qemu/timer.h"
33 #include "qemu/envlist.h"
34 #include "elf.h"
35
36 char *exec_path;
37
38 int singlestep;
39 const char *filename;
40 const char *argv0;
41 int gdbstub_port;
42 envlist_t *envlist;
43 static const char *cpu_model;
44 unsigned long mmap_min_addr;
45 #if defined(CONFIG_USE_GUEST_BASE)
46 uintptr_t guest_base;
47 int have_guest_base;
48 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
49 /*
50 * When running 32-on-64 we should make sure we can fit all of the possible
51 * guest address space into a contiguous chunk of virtual host memory.
52 *
53 * This way we will never overlap with our own libraries or binaries or stack
54 * or anything else that QEMU maps.
55 */
56 # ifdef TARGET_MIPS
57 /* MIPS only supports 31 bits of virtual address space for user space */
58 uintptr_t reserved_va = 0x77000000;
59 # else
60 uintptr_t reserved_va = 0xf7000000;
61 # endif
62 #else
63 uintptr_t reserved_va;
64 #endif
65 #endif
66
67 static void usage(void);
68
69 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
70 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
71
72 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
73 we allocate a bigger stack. Need a better solution, for example
74 by remapping the process stack directly at the right place */
75 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
76
77 void gemu_log(const char *fmt, ...)
78 {
79 va_list ap;
80
81 va_start(ap, fmt);
82 vfprintf(stderr, fmt, ap);
83 va_end(ap);
84 }
85
86 #if defined(TARGET_I386)
87 int cpu_get_pic_interrupt(CPUX86State *env)
88 {
89 return -1;
90 }
91 #endif
92
93 /***********************************************************/
94 /* Helper routines for implementing atomic operations. */
95
96 /* To implement exclusive operations we force all cpus to syncronise.
97 We don't require a full sync, only that no cpus are executing guest code.
98 The alternative is to map target atomic ops onto host equivalents,
99 which requires quite a lot of per host/target work. */
100 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
101 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
102 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
103 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
104 static int pending_cpus;
105
106 /* Make sure everything is in a consistent state for calling fork(). */
107 void fork_start(void)
108 {
109 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
110 pthread_mutex_lock(&exclusive_lock);
111 mmap_fork_start();
112 }
113
114 void fork_end(int child)
115 {
116 mmap_fork_end(child);
117 if (child) {
118 CPUState *cpu, *next_cpu;
119 /* Child processes created by fork() only have a single thread.
120 Discard information about the parent threads. */
121 CPU_FOREACH_SAFE(cpu, next_cpu) {
122 if (cpu != thread_cpu) {
123 QTAILQ_REMOVE(&cpus, thread_cpu, node);
124 }
125 }
126 pending_cpus = 0;
127 pthread_mutex_init(&exclusive_lock, NULL);
128 pthread_mutex_init(&cpu_list_mutex, NULL);
129 pthread_cond_init(&exclusive_cond, NULL);
130 pthread_cond_init(&exclusive_resume, NULL);
131 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
132 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
133 } else {
134 pthread_mutex_unlock(&exclusive_lock);
135 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
136 }
137 }
138
139 /* Wait for pending exclusive operations to complete. The exclusive lock
140 must be held. */
141 static inline void exclusive_idle(void)
142 {
143 while (pending_cpus) {
144 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
145 }
146 }
147
148 /* Start an exclusive operation.
149 Must only be called from outside cpu_arm_exec. */
150 static inline void start_exclusive(void)
151 {
152 CPUState *other_cpu;
153
154 pthread_mutex_lock(&exclusive_lock);
155 exclusive_idle();
156
157 pending_cpus = 1;
158 /* Make all other cpus stop executing. */
159 CPU_FOREACH(other_cpu) {
160 if (other_cpu->running) {
161 pending_cpus++;
162 cpu_exit(other_cpu);
163 }
164 }
165 if (pending_cpus > 1) {
166 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
167 }
168 }
169
170 /* Finish an exclusive operation. */
171 static inline void end_exclusive(void)
172 {
173 pending_cpus = 0;
174 pthread_cond_broadcast(&exclusive_resume);
175 pthread_mutex_unlock(&exclusive_lock);
176 }
177
178 /* Wait for exclusive ops to finish, and begin cpu execution. */
179 static inline void cpu_exec_start(CPUState *cpu)
180 {
181 pthread_mutex_lock(&exclusive_lock);
182 exclusive_idle();
183 cpu->running = true;
184 pthread_mutex_unlock(&exclusive_lock);
185 }
186
187 /* Mark cpu as not executing, and release pending exclusive ops. */
188 static inline void cpu_exec_end(CPUState *cpu)
189 {
190 pthread_mutex_lock(&exclusive_lock);
191 cpu->running = false;
192 if (pending_cpus > 1) {
193 pending_cpus--;
194 if (pending_cpus == 1) {
195 pthread_cond_signal(&exclusive_cond);
196 }
197 }
198 exclusive_idle();
199 pthread_mutex_unlock(&exclusive_lock);
200 }
201
202 void cpu_list_lock(void)
203 {
204 pthread_mutex_lock(&cpu_list_mutex);
205 }
206
207 void cpu_list_unlock(void)
208 {
209 pthread_mutex_unlock(&cpu_list_mutex);
210 }
211
212
213 #ifdef TARGET_I386
214 /***********************************************************/
215 /* CPUX86 core interface */
216
217 void cpu_smm_update(CPUX86State *env)
218 {
219 }
220
221 uint64_t cpu_get_tsc(CPUX86State *env)
222 {
223 return cpu_get_real_ticks();
224 }
225
226 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
227 int flags)
228 {
229 unsigned int e1, e2;
230 uint32_t *p;
231 e1 = (addr << 16) | (limit & 0xffff);
232 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
233 e2 |= flags;
234 p = ptr;
235 p[0] = tswap32(e1);
236 p[1] = tswap32(e2);
237 }
238
239 static uint64_t *idt_table;
240 #ifdef TARGET_X86_64
241 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
242 uint64_t addr, unsigned int sel)
243 {
244 uint32_t *p, e1, e2;
245 e1 = (addr & 0xffff) | (sel << 16);
246 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
247 p = ptr;
248 p[0] = tswap32(e1);
249 p[1] = tswap32(e2);
250 p[2] = tswap32(addr >> 32);
251 p[3] = 0;
252 }
253 /* only dpl matters as we do only user space emulation */
254 static void set_idt(int n, unsigned int dpl)
255 {
256 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
257 }
258 #else
259 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
260 uint32_t addr, unsigned int sel)
261 {
262 uint32_t *p, e1, e2;
263 e1 = (addr & 0xffff) | (sel << 16);
264 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
265 p = ptr;
266 p[0] = tswap32(e1);
267 p[1] = tswap32(e2);
268 }
269
270 /* only dpl matters as we do only user space emulation */
271 static void set_idt(int n, unsigned int dpl)
272 {
273 set_gate(idt_table + n, 0, dpl, 0, 0);
274 }
275 #endif
276
277 void cpu_loop(CPUX86State *env)
278 {
279 CPUState *cs = CPU(x86_env_get_cpu(env));
280 int trapnr;
281 abi_ulong pc;
282 target_siginfo_t info;
283 #ifdef TARGET_X86_64
284 int syscall_num;
285 #endif
286
287 for(;;) {
288 trapnr = cpu_x86_exec(env);
289 switch(trapnr) {
290 case 0x80:
291 /* linux syscall from int $0x80 */
292 env->regs[R_EAX] = do_syscall(env,
293 env->regs[R_EAX],
294 env->regs[R_EBX],
295 env->regs[R_ECX],
296 env->regs[R_EDX],
297 env->regs[R_ESI],
298 env->regs[R_EDI],
299 env->regs[R_EBP],
300 0, 0);
301 break;
302 #ifndef TARGET_ABI32
303 case EXCP_SYSCALL:
304 /* linux syscall from syscall instruction */
305 env->regs[R_EAX] = do_syscall(env,
306 env->regs[R_EAX],
307 env->regs[R_EDI],
308 env->regs[R_ESI],
309 env->regs[R_EDX],
310 env->regs[10],
311 env->regs[8],
312 env->regs[9],
313 0, 0);
314 env->eip = env->exception_next_eip;
315 break;
316 #endif
317 #ifdef TARGET_X86_64
318 case EXCP_VSYSCALL:
319 switch (env->eip) {
320 case TARGET_VSYSCALL_ADDR(__NR_vgettimeofday):
321 syscall_num = __NR_gettimeofday;
322 break;
323 case TARGET_VSYSCALL_ADDR(__NR_vtime):
324 #ifdef __NR_time
325 syscall_num = __NR_time;
326 #else
327 /* XXX: not yet implemented (arm eabi host) */
328 cpu_abort(env, "Unimplemented vsyscall vtime");
329 #endif
330 break;
331 case TARGET_VSYSCALL_ADDR(__NR_vgetcpu):
332 /* XXX: not yet implemented */
333 cpu_abort(env, "Unimplemented vsyscall vgetcpu");
334 break;
335 default:
336 cpu_abort(env,
337 "Invalid vsyscall to address " TARGET_FMT_lx "\n",
338 env->eip);
339 }
340 env->regs[R_EAX] = do_syscall(env,
341 syscall_num,
342 env->regs[R_EDI],
343 env->regs[R_ESI],
344 env->regs[R_EDX],
345 env->regs[10],
346 env->regs[8],
347 env->regs[9],
348 0, 0);
349 /* simulate a ret */
350 env->eip = ldq(env->regs[R_ESP]);
351 env->regs[R_ESP] += 8;
352 break;
353 #endif
354 case EXCP0B_NOSEG:
355 case EXCP0C_STACK:
356 info.si_signo = SIGBUS;
357 info.si_errno = 0;
358 info.si_code = TARGET_SI_KERNEL;
359 info._sifields._sigfault._addr = 0;
360 queue_signal(env, info.si_signo, &info);
361 break;
362 case EXCP0D_GPF:
363 /* XXX: potential problem if ABI32 */
364 #ifndef TARGET_X86_64
365 if (env->eflags & VM_MASK) {
366 handle_vm86_fault(env);
367 } else
368 #endif
369 {
370 info.si_signo = SIGSEGV;
371 info.si_errno = 0;
372 info.si_code = TARGET_SI_KERNEL;
373 info._sifields._sigfault._addr = 0;
374 queue_signal(env, info.si_signo, &info);
375 }
376 break;
377 case EXCP0E_PAGE:
378 info.si_signo = SIGSEGV;
379 info.si_errno = 0;
380 if (!(env->error_code & 1))
381 info.si_code = TARGET_SEGV_MAPERR;
382 else
383 info.si_code = TARGET_SEGV_ACCERR;
384 info._sifields._sigfault._addr = env->cr[2];
385 queue_signal(env, info.si_signo, &info);
386 break;
387 case EXCP00_DIVZ:
388 #ifndef TARGET_X86_64
389 if (env->eflags & VM_MASK) {
390 handle_vm86_trap(env, trapnr);
391 } else
392 #endif
393 {
394 /* division by zero */
395 info.si_signo = SIGFPE;
396 info.si_errno = 0;
397 info.si_code = TARGET_FPE_INTDIV;
398 info._sifields._sigfault._addr = env->eip;
399 queue_signal(env, info.si_signo, &info);
400 }
401 break;
402 case EXCP01_DB:
403 case EXCP03_INT3:
404 #ifndef TARGET_X86_64
405 if (env->eflags & VM_MASK) {
406 handle_vm86_trap(env, trapnr);
407 } else
408 #endif
409 {
410 info.si_signo = SIGTRAP;
411 info.si_errno = 0;
412 if (trapnr == EXCP01_DB) {
413 info.si_code = TARGET_TRAP_BRKPT;
414 info._sifields._sigfault._addr = env->eip;
415 } else {
416 info.si_code = TARGET_SI_KERNEL;
417 info._sifields._sigfault._addr = 0;
418 }
419 queue_signal(env, info.si_signo, &info);
420 }
421 break;
422 case EXCP04_INTO:
423 case EXCP05_BOUND:
424 #ifndef TARGET_X86_64
425 if (env->eflags & VM_MASK) {
426 handle_vm86_trap(env, trapnr);
427 } else
428 #endif
429 {
430 info.si_signo = SIGSEGV;
431 info.si_errno = 0;
432 info.si_code = TARGET_SI_KERNEL;
433 info._sifields._sigfault._addr = 0;
434 queue_signal(env, info.si_signo, &info);
435 }
436 break;
437 case EXCP06_ILLOP:
438 info.si_signo = SIGILL;
439 info.si_errno = 0;
440 info.si_code = TARGET_ILL_ILLOPN;
441 info._sifields._sigfault._addr = env->eip;
442 queue_signal(env, info.si_signo, &info);
443 break;
444 case EXCP_INTERRUPT:
445 /* just indicate that signals should be handled asap */
446 break;
447 case EXCP_DEBUG:
448 {
449 int sig;
450
451 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
452 if (sig)
453 {
454 info.si_signo = sig;
455 info.si_errno = 0;
456 info.si_code = TARGET_TRAP_BRKPT;
457 queue_signal(env, info.si_signo, &info);
458 }
459 }
460 break;
461 default:
462 pc = env->segs[R_CS].base + env->eip;
463 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
464 (long)pc, trapnr);
465 abort();
466 }
467 process_pending_signals(env);
468 }
469 }
470 #endif
471
472 #ifdef TARGET_ARM
473
474 #define get_user_code_u32(x, gaddr, doswap) \
475 ({ abi_long __r = get_user_u32((x), (gaddr)); \
476 if (!__r && (doswap)) { \
477 (x) = bswap32(x); \
478 } \
479 __r; \
480 })
481
482 #define get_user_code_u16(x, gaddr, doswap) \
483 ({ abi_long __r = get_user_u16((x), (gaddr)); \
484 if (!__r && (doswap)) { \
485 (x) = bswap16(x); \
486 } \
487 __r; \
488 })
489
490 #ifdef TARGET_ABI32
491 /* Commpage handling -- there is no commpage for AArch64 */
492
493 /*
494 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
495 * Input:
496 * r0 = pointer to oldval
497 * r1 = pointer to newval
498 * r2 = pointer to target value
499 *
500 * Output:
501 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
502 * C set if *ptr was changed, clear if no exchange happened
503 *
504 * Note segv's in kernel helpers are a bit tricky, we can set the
505 * data address sensibly but the PC address is just the entry point.
506 */
507 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
508 {
509 uint64_t oldval, newval, val;
510 uint32_t addr, cpsr;
511 target_siginfo_t info;
512
513 /* Based on the 32 bit code in do_kernel_trap */
514
515 /* XXX: This only works between threads, not between processes.
516 It's probably possible to implement this with native host
517 operations. However things like ldrex/strex are much harder so
518 there's not much point trying. */
519 start_exclusive();
520 cpsr = cpsr_read(env);
521 addr = env->regs[2];
522
523 if (get_user_u64(oldval, env->regs[0])) {
524 env->cp15.c6_data = env->regs[0];
525 goto segv;
526 };
527
528 if (get_user_u64(newval, env->regs[1])) {
529 env->cp15.c6_data = env->regs[1];
530 goto segv;
531 };
532
533 if (get_user_u64(val, addr)) {
534 env->cp15.c6_data = addr;
535 goto segv;
536 }
537
538 if (val == oldval) {
539 val = newval;
540
541 if (put_user_u64(val, addr)) {
542 env->cp15.c6_data = addr;
543 goto segv;
544 };
545
546 env->regs[0] = 0;
547 cpsr |= CPSR_C;
548 } else {
549 env->regs[0] = -1;
550 cpsr &= ~CPSR_C;
551 }
552 cpsr_write(env, cpsr, CPSR_C);
553 end_exclusive();
554 return;
555
556 segv:
557 end_exclusive();
558 /* We get the PC of the entry address - which is as good as anything,
559 on a real kernel what you get depends on which mode it uses. */
560 info.si_signo = SIGSEGV;
561 info.si_errno = 0;
562 /* XXX: check env->error_code */
563 info.si_code = TARGET_SEGV_MAPERR;
564 info._sifields._sigfault._addr = env->cp15.c6_data;
565 queue_signal(env, info.si_signo, &info);
566
567 end_exclusive();
568 }
569
570 /* Handle a jump to the kernel code page. */
571 static int
572 do_kernel_trap(CPUARMState *env)
573 {
574 uint32_t addr;
575 uint32_t cpsr;
576 uint32_t val;
577
578 switch (env->regs[15]) {
579 case 0xffff0fa0: /* __kernel_memory_barrier */
580 /* ??? No-op. Will need to do better for SMP. */
581 break;
582 case 0xffff0fc0: /* __kernel_cmpxchg */
583 /* XXX: This only works between threads, not between processes.
584 It's probably possible to implement this with native host
585 operations. However things like ldrex/strex are much harder so
586 there's not much point trying. */
587 start_exclusive();
588 cpsr = cpsr_read(env);
589 addr = env->regs[2];
590 /* FIXME: This should SEGV if the access fails. */
591 if (get_user_u32(val, addr))
592 val = ~env->regs[0];
593 if (val == env->regs[0]) {
594 val = env->regs[1];
595 /* FIXME: Check for segfaults. */
596 put_user_u32(val, addr);
597 env->regs[0] = 0;
598 cpsr |= CPSR_C;
599 } else {
600 env->regs[0] = -1;
601 cpsr &= ~CPSR_C;
602 }
603 cpsr_write(env, cpsr, CPSR_C);
604 end_exclusive();
605 break;
606 case 0xffff0fe0: /* __kernel_get_tls */
607 env->regs[0] = env->cp15.tpidrro_el0;
608 break;
609 case 0xffff0f60: /* __kernel_cmpxchg64 */
610 arm_kernel_cmpxchg64_helper(env);
611 break;
612
613 default:
614 return 1;
615 }
616 /* Jump back to the caller. */
617 addr = env->regs[14];
618 if (addr & 1) {
619 env->thumb = 1;
620 addr &= ~1;
621 }
622 env->regs[15] = addr;
623
624 return 0;
625 }
626
627 /* Store exclusive handling for AArch32 */
628 static int do_strex(CPUARMState *env)
629 {
630 uint64_t val;
631 int size;
632 int rc = 1;
633 int segv = 0;
634 uint32_t addr;
635 start_exclusive();
636 if (env->exclusive_addr != env->exclusive_test) {
637 goto fail;
638 }
639 /* We know we're always AArch32 so the address is in uint32_t range
640 * unless it was the -1 exclusive-monitor-lost value (which won't
641 * match exclusive_test above).
642 */
643 assert(extract64(env->exclusive_addr, 32, 32) == 0);
644 addr = env->exclusive_addr;
645 size = env->exclusive_info & 0xf;
646 switch (size) {
647 case 0:
648 segv = get_user_u8(val, addr);
649 break;
650 case 1:
651 segv = get_user_u16(val, addr);
652 break;
653 case 2:
654 case 3:
655 segv = get_user_u32(val, addr);
656 break;
657 default:
658 abort();
659 }
660 if (segv) {
661 env->cp15.c6_data = addr;
662 goto done;
663 }
664 if (size == 3) {
665 uint32_t valhi;
666 segv = get_user_u32(valhi, addr + 4);
667 if (segv) {
668 env->cp15.c6_data = addr + 4;
669 goto done;
670 }
671 val = deposit64(val, 32, 32, valhi);
672 }
673 if (val != env->exclusive_val) {
674 goto fail;
675 }
676
677 val = env->regs[(env->exclusive_info >> 8) & 0xf];
678 switch (size) {
679 case 0:
680 segv = put_user_u8(val, addr);
681 break;
682 case 1:
683 segv = put_user_u16(val, addr);
684 break;
685 case 2:
686 case 3:
687 segv = put_user_u32(val, addr);
688 break;
689 }
690 if (segv) {
691 env->cp15.c6_data = addr;
692 goto done;
693 }
694 if (size == 3) {
695 val = env->regs[(env->exclusive_info >> 12) & 0xf];
696 segv = put_user_u32(val, addr + 4);
697 if (segv) {
698 env->cp15.c6_data = addr + 4;
699 goto done;
700 }
701 }
702 rc = 0;
703 fail:
704 env->regs[15] += 4;
705 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
706 done:
707 end_exclusive();
708 return segv;
709 }
710
711 void cpu_loop(CPUARMState *env)
712 {
713 CPUState *cs = CPU(arm_env_get_cpu(env));
714 int trapnr;
715 unsigned int n, insn;
716 target_siginfo_t info;
717 uint32_t addr;
718
719 for(;;) {
720 cpu_exec_start(cs);
721 trapnr = cpu_arm_exec(env);
722 cpu_exec_end(cs);
723 switch(trapnr) {
724 case EXCP_UDEF:
725 {
726 TaskState *ts = env->opaque;
727 uint32_t opcode;
728 int rc;
729
730 /* we handle the FPU emulation here, as Linux */
731 /* we get the opcode */
732 /* FIXME - what to do if get_user() fails? */
733 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
734
735 rc = EmulateAll(opcode, &ts->fpa, env);
736 if (rc == 0) { /* illegal instruction */
737 info.si_signo = SIGILL;
738 info.si_errno = 0;
739 info.si_code = TARGET_ILL_ILLOPN;
740 info._sifields._sigfault._addr = env->regs[15];
741 queue_signal(env, info.si_signo, &info);
742 } else if (rc < 0) { /* FP exception */
743 int arm_fpe=0;
744
745 /* translate softfloat flags to FPSR flags */
746 if (-rc & float_flag_invalid)
747 arm_fpe |= BIT_IOC;
748 if (-rc & float_flag_divbyzero)
749 arm_fpe |= BIT_DZC;
750 if (-rc & float_flag_overflow)
751 arm_fpe |= BIT_OFC;
752 if (-rc & float_flag_underflow)
753 arm_fpe |= BIT_UFC;
754 if (-rc & float_flag_inexact)
755 arm_fpe |= BIT_IXC;
756
757 FPSR fpsr = ts->fpa.fpsr;
758 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
759
760 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
761 info.si_signo = SIGFPE;
762 info.si_errno = 0;
763
764 /* ordered by priority, least first */
765 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
766 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
767 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
768 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
769 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
770
771 info._sifields._sigfault._addr = env->regs[15];
772 queue_signal(env, info.si_signo, &info);
773 } else {
774 env->regs[15] += 4;
775 }
776
777 /* accumulate unenabled exceptions */
778 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
779 fpsr |= BIT_IXC;
780 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
781 fpsr |= BIT_UFC;
782 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
783 fpsr |= BIT_OFC;
784 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
785 fpsr |= BIT_DZC;
786 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
787 fpsr |= BIT_IOC;
788 ts->fpa.fpsr=fpsr;
789 } else { /* everything OK */
790 /* increment PC */
791 env->regs[15] += 4;
792 }
793 }
794 break;
795 case EXCP_SWI:
796 case EXCP_BKPT:
797 {
798 env->eabi = 1;
799 /* system call */
800 if (trapnr == EXCP_BKPT) {
801 if (env->thumb) {
802 /* FIXME - what to do if get_user() fails? */
803 get_user_code_u16(insn, env->regs[15], env->bswap_code);
804 n = insn & 0xff;
805 env->regs[15] += 2;
806 } else {
807 /* FIXME - what to do if get_user() fails? */
808 get_user_code_u32(insn, env->regs[15], env->bswap_code);
809 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
810 env->regs[15] += 4;
811 }
812 } else {
813 if (env->thumb) {
814 /* FIXME - what to do if get_user() fails? */
815 get_user_code_u16(insn, env->regs[15] - 2,
816 env->bswap_code);
817 n = insn & 0xff;
818 } else {
819 /* FIXME - what to do if get_user() fails? */
820 get_user_code_u32(insn, env->regs[15] - 4,
821 env->bswap_code);
822 n = insn & 0xffffff;
823 }
824 }
825
826 if (n == ARM_NR_cacheflush) {
827 /* nop */
828 } else if (n == ARM_NR_semihosting
829 || n == ARM_NR_thumb_semihosting) {
830 env->regs[0] = do_arm_semihosting (env);
831 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
832 /* linux syscall */
833 if (env->thumb || n == 0) {
834 n = env->regs[7];
835 } else {
836 n -= ARM_SYSCALL_BASE;
837 env->eabi = 0;
838 }
839 if ( n > ARM_NR_BASE) {
840 switch (n) {
841 case ARM_NR_cacheflush:
842 /* nop */
843 break;
844 case ARM_NR_set_tls:
845 cpu_set_tls(env, env->regs[0]);
846 env->regs[0] = 0;
847 break;
848 default:
849 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
850 n);
851 env->regs[0] = -TARGET_ENOSYS;
852 break;
853 }
854 } else {
855 env->regs[0] = do_syscall(env,
856 n,
857 env->regs[0],
858 env->regs[1],
859 env->regs[2],
860 env->regs[3],
861 env->regs[4],
862 env->regs[5],
863 0, 0);
864 }
865 } else {
866 goto error;
867 }
868 }
869 break;
870 case EXCP_INTERRUPT:
871 /* just indicate that signals should be handled asap */
872 break;
873 case EXCP_PREFETCH_ABORT:
874 addr = env->cp15.c6_insn;
875 goto do_segv;
876 case EXCP_DATA_ABORT:
877 addr = env->cp15.c6_data;
878 do_segv:
879 {
880 info.si_signo = SIGSEGV;
881 info.si_errno = 0;
882 /* XXX: check env->error_code */
883 info.si_code = TARGET_SEGV_MAPERR;
884 info._sifields._sigfault._addr = addr;
885 queue_signal(env, info.si_signo, &info);
886 }
887 break;
888 case EXCP_DEBUG:
889 {
890 int sig;
891
892 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
893 if (sig)
894 {
895 info.si_signo = sig;
896 info.si_errno = 0;
897 info.si_code = TARGET_TRAP_BRKPT;
898 queue_signal(env, info.si_signo, &info);
899 }
900 }
901 break;
902 case EXCP_KERNEL_TRAP:
903 if (do_kernel_trap(env))
904 goto error;
905 break;
906 case EXCP_STREX:
907 if (do_strex(env)) {
908 addr = env->cp15.c6_data;
909 goto do_segv;
910 }
911 break;
912 default:
913 error:
914 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
915 trapnr);
916 cpu_dump_state(cs, stderr, fprintf, 0);
917 abort();
918 }
919 process_pending_signals(env);
920 }
921 }
922
923 #else
924
925 /*
926 * Handle AArch64 store-release exclusive
927 *
928 * rs = gets the status result of store exclusive
929 * rt = is the register that is stored
930 * rt2 = is the second register store (in STP)
931 *
932 */
933 static int do_strex_a64(CPUARMState *env)
934 {
935 uint64_t val;
936 int size;
937 bool is_pair;
938 int rc = 1;
939 int segv = 0;
940 uint64_t addr;
941 int rs, rt, rt2;
942
943 start_exclusive();
944 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
945 size = extract32(env->exclusive_info, 0, 2);
946 is_pair = extract32(env->exclusive_info, 2, 1);
947 rs = extract32(env->exclusive_info, 4, 5);
948 rt = extract32(env->exclusive_info, 9, 5);
949 rt2 = extract32(env->exclusive_info, 14, 5);
950
951 addr = env->exclusive_addr;
952
953 if (addr != env->exclusive_test) {
954 goto finish;
955 }
956
957 switch (size) {
958 case 0:
959 segv = get_user_u8(val, addr);
960 break;
961 case 1:
962 segv = get_user_u16(val, addr);
963 break;
964 case 2:
965 segv = get_user_u32(val, addr);
966 break;
967 case 3:
968 segv = get_user_u64(val, addr);
969 break;
970 default:
971 abort();
972 }
973 if (segv) {
974 env->cp15.c6_data = addr;
975 goto error;
976 }
977 if (val != env->exclusive_val) {
978 goto finish;
979 }
980 if (is_pair) {
981 if (size == 2) {
982 segv = get_user_u32(val, addr + 4);
983 } else {
984 segv = get_user_u64(val, addr + 8);
985 }
986 if (segv) {
987 env->cp15.c6_data = addr + (size == 2 ? 4 : 8);
988 goto error;
989 }
990 if (val != env->exclusive_high) {
991 goto finish;
992 }
993 }
994 /* handle the zero register */
995 val = rt == 31 ? 0 : env->xregs[rt];
996 switch (size) {
997 case 0:
998 segv = put_user_u8(val, addr);
999 break;
1000 case 1:
1001 segv = put_user_u16(val, addr);
1002 break;
1003 case 2:
1004 segv = put_user_u32(val, addr);
1005 break;
1006 case 3:
1007 segv = put_user_u64(val, addr);
1008 break;
1009 }
1010 if (segv) {
1011 goto error;
1012 }
1013 if (is_pair) {
1014 /* handle the zero register */
1015 val = rt2 == 31 ? 0 : env->xregs[rt2];
1016 if (size == 2) {
1017 segv = put_user_u32(val, addr + 4);
1018 } else {
1019 segv = put_user_u64(val, addr + 8);
1020 }
1021 if (segv) {
1022 env->cp15.c6_data = addr + (size == 2 ? 4 : 8);
1023 goto error;
1024 }
1025 }
1026 rc = 0;
1027 finish:
1028 env->pc += 4;
1029 /* rs == 31 encodes a write to the ZR, thus throwing away
1030 * the status return. This is rather silly but valid.
1031 */
1032 if (rs < 31) {
1033 env->xregs[rs] = rc;
1034 }
1035 error:
1036 /* instruction faulted, PC does not advance */
1037 /* either way a strex releases any exclusive lock we have */
1038 env->exclusive_addr = -1;
1039 end_exclusive();
1040 return segv;
1041 }
1042
1043 /* AArch64 main loop */
1044 void cpu_loop(CPUARMState *env)
1045 {
1046 CPUState *cs = CPU(arm_env_get_cpu(env));
1047 int trapnr, sig;
1048 target_siginfo_t info;
1049 uint32_t addr;
1050
1051 for (;;) {
1052 cpu_exec_start(cs);
1053 trapnr = cpu_arm_exec(env);
1054 cpu_exec_end(cs);
1055
1056 switch (trapnr) {
1057 case EXCP_SWI:
1058 env->xregs[0] = do_syscall(env,
1059 env->xregs[8],
1060 env->xregs[0],
1061 env->xregs[1],
1062 env->xregs[2],
1063 env->xregs[3],
1064 env->xregs[4],
1065 env->xregs[5],
1066 0, 0);
1067 break;
1068 case EXCP_INTERRUPT:
1069 /* just indicate that signals should be handled asap */
1070 break;
1071 case EXCP_UDEF:
1072 info.si_signo = SIGILL;
1073 info.si_errno = 0;
1074 info.si_code = TARGET_ILL_ILLOPN;
1075 info._sifields._sigfault._addr = env->pc;
1076 queue_signal(env, info.si_signo, &info);
1077 break;
1078 case EXCP_PREFETCH_ABORT:
1079 addr = env->cp15.c6_insn;
1080 goto do_segv;
1081 case EXCP_DATA_ABORT:
1082 addr = env->cp15.c6_data;
1083 do_segv:
1084 info.si_signo = SIGSEGV;
1085 info.si_errno = 0;
1086 /* XXX: check env->error_code */
1087 info.si_code = TARGET_SEGV_MAPERR;
1088 info._sifields._sigfault._addr = addr;
1089 queue_signal(env, info.si_signo, &info);
1090 break;
1091 case EXCP_DEBUG:
1092 case EXCP_BKPT:
1093 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1094 if (sig) {
1095 info.si_signo = sig;
1096 info.si_errno = 0;
1097 info.si_code = TARGET_TRAP_BRKPT;
1098 queue_signal(env, info.si_signo, &info);
1099 }
1100 break;
1101 case EXCP_STREX:
1102 if (do_strex_a64(env)) {
1103 addr = env->cp15.c6_data;
1104 goto do_segv;
1105 }
1106 break;
1107 default:
1108 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1109 trapnr);
1110 cpu_dump_state(cs, stderr, fprintf, 0);
1111 abort();
1112 }
1113 process_pending_signals(env);
1114 /* Exception return on AArch64 always clears the exclusive monitor,
1115 * so any return to running guest code implies this.
1116 * A strex (successful or otherwise) also clears the monitor, so
1117 * we don't need to specialcase EXCP_STREX.
1118 */
1119 env->exclusive_addr = -1;
1120 }
1121 }
1122 #endif /* ndef TARGET_ABI32 */
1123
1124 #endif
1125
1126 #ifdef TARGET_UNICORE32
1127
1128 void cpu_loop(CPUUniCore32State *env)
1129 {
1130 CPUState *cs = CPU(uc32_env_get_cpu(env));
1131 int trapnr;
1132 unsigned int n, insn;
1133 target_siginfo_t info;
1134
1135 for (;;) {
1136 cpu_exec_start(cs);
1137 trapnr = uc32_cpu_exec(env);
1138 cpu_exec_end(cs);
1139 switch (trapnr) {
1140 case UC32_EXCP_PRIV:
1141 {
1142 /* system call */
1143 get_user_u32(insn, env->regs[31] - 4);
1144 n = insn & 0xffffff;
1145
1146 if (n >= UC32_SYSCALL_BASE) {
1147 /* linux syscall */
1148 n -= UC32_SYSCALL_BASE;
1149 if (n == UC32_SYSCALL_NR_set_tls) {
1150 cpu_set_tls(env, env->regs[0]);
1151 env->regs[0] = 0;
1152 } else {
1153 env->regs[0] = do_syscall(env,
1154 n,
1155 env->regs[0],
1156 env->regs[1],
1157 env->regs[2],
1158 env->regs[3],
1159 env->regs[4],
1160 env->regs[5],
1161 0, 0);
1162 }
1163 } else {
1164 goto error;
1165 }
1166 }
1167 break;
1168 case UC32_EXCP_DTRAP:
1169 case UC32_EXCP_ITRAP:
1170 info.si_signo = SIGSEGV;
1171 info.si_errno = 0;
1172 /* XXX: check env->error_code */
1173 info.si_code = TARGET_SEGV_MAPERR;
1174 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1175 queue_signal(env, info.si_signo, &info);
1176 break;
1177 case EXCP_INTERRUPT:
1178 /* just indicate that signals should be handled asap */
1179 break;
1180 case EXCP_DEBUG:
1181 {
1182 int sig;
1183
1184 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1185 if (sig) {
1186 info.si_signo = sig;
1187 info.si_errno = 0;
1188 info.si_code = TARGET_TRAP_BRKPT;
1189 queue_signal(env, info.si_signo, &info);
1190 }
1191 }
1192 break;
1193 default:
1194 goto error;
1195 }
1196 process_pending_signals(env);
1197 }
1198
1199 error:
1200 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1201 cpu_dump_state(cs, stderr, fprintf, 0);
1202 abort();
1203 }
1204 #endif
1205
1206 #ifdef TARGET_SPARC
1207 #define SPARC64_STACK_BIAS 2047
1208
1209 //#define DEBUG_WIN
1210
1211 /* WARNING: dealing with register windows _is_ complicated. More info
1212 can be found at http://www.sics.se/~psm/sparcstack.html */
1213 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1214 {
1215 index = (index + cwp * 16) % (16 * env->nwindows);
1216 /* wrap handling : if cwp is on the last window, then we use the
1217 registers 'after' the end */
1218 if (index < 8 && env->cwp == env->nwindows - 1)
1219 index += 16 * env->nwindows;
1220 return index;
1221 }
1222
1223 /* save the register window 'cwp1' */
1224 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1225 {
1226 unsigned int i;
1227 abi_ulong sp_ptr;
1228
1229 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1230 #ifdef TARGET_SPARC64
1231 if (sp_ptr & 3)
1232 sp_ptr += SPARC64_STACK_BIAS;
1233 #endif
1234 #if defined(DEBUG_WIN)
1235 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1236 sp_ptr, cwp1);
1237 #endif
1238 for(i = 0; i < 16; i++) {
1239 /* FIXME - what to do if put_user() fails? */
1240 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1241 sp_ptr += sizeof(abi_ulong);
1242 }
1243 }
1244
1245 static void save_window(CPUSPARCState *env)
1246 {
1247 #ifndef TARGET_SPARC64
1248 unsigned int new_wim;
1249 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1250 ((1LL << env->nwindows) - 1);
1251 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1252 env->wim = new_wim;
1253 #else
1254 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1255 env->cansave++;
1256 env->canrestore--;
1257 #endif
1258 }
1259
1260 static void restore_window(CPUSPARCState *env)
1261 {
1262 #ifndef TARGET_SPARC64
1263 unsigned int new_wim;
1264 #endif
1265 unsigned int i, cwp1;
1266 abi_ulong sp_ptr;
1267
1268 #ifndef TARGET_SPARC64
1269 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1270 ((1LL << env->nwindows) - 1);
1271 #endif
1272
1273 /* restore the invalid window */
1274 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1275 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1276 #ifdef TARGET_SPARC64
1277 if (sp_ptr & 3)
1278 sp_ptr += SPARC64_STACK_BIAS;
1279 #endif
1280 #if defined(DEBUG_WIN)
1281 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1282 sp_ptr, cwp1);
1283 #endif
1284 for(i = 0; i < 16; i++) {
1285 /* FIXME - what to do if get_user() fails? */
1286 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1287 sp_ptr += sizeof(abi_ulong);
1288 }
1289 #ifdef TARGET_SPARC64
1290 env->canrestore++;
1291 if (env->cleanwin < env->nwindows - 1)
1292 env->cleanwin++;
1293 env->cansave--;
1294 #else
1295 env->wim = new_wim;
1296 #endif
1297 }
1298
1299 static void flush_windows(CPUSPARCState *env)
1300 {
1301 int offset, cwp1;
1302
1303 offset = 1;
1304 for(;;) {
1305 /* if restore would invoke restore_window(), then we can stop */
1306 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1307 #ifndef TARGET_SPARC64
1308 if (env->wim & (1 << cwp1))
1309 break;
1310 #else
1311 if (env->canrestore == 0)
1312 break;
1313 env->cansave++;
1314 env->canrestore--;
1315 #endif
1316 save_window_offset(env, cwp1);
1317 offset++;
1318 }
1319 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1320 #ifndef TARGET_SPARC64
1321 /* set wim so that restore will reload the registers */
1322 env->wim = 1 << cwp1;
1323 #endif
1324 #if defined(DEBUG_WIN)
1325 printf("flush_windows: nb=%d\n", offset - 1);
1326 #endif
1327 }
1328
1329 void cpu_loop (CPUSPARCState *env)
1330 {
1331 CPUState *cs = CPU(sparc_env_get_cpu(env));
1332 int trapnr;
1333 abi_long ret;
1334 target_siginfo_t info;
1335
1336 while (1) {
1337 trapnr = cpu_sparc_exec (env);
1338
1339 /* Compute PSR before exposing state. */
1340 if (env->cc_op != CC_OP_FLAGS) {
1341 cpu_get_psr(env);
1342 }
1343
1344 switch (trapnr) {
1345 #ifndef TARGET_SPARC64
1346 case 0x88:
1347 case 0x90:
1348 #else
1349 case 0x110:
1350 case 0x16d:
1351 #endif
1352 ret = do_syscall (env, env->gregs[1],
1353 env->regwptr[0], env->regwptr[1],
1354 env->regwptr[2], env->regwptr[3],
1355 env->regwptr[4], env->regwptr[5],
1356 0, 0);
1357 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1358 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1359 env->xcc |= PSR_CARRY;
1360 #else
1361 env->psr |= PSR_CARRY;
1362 #endif
1363 ret = -ret;
1364 } else {
1365 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1366 env->xcc &= ~PSR_CARRY;
1367 #else
1368 env->psr &= ~PSR_CARRY;
1369 #endif
1370 }
1371 env->regwptr[0] = ret;
1372 /* next instruction */
1373 env->pc = env->npc;
1374 env->npc = env->npc + 4;
1375 break;
1376 case 0x83: /* flush windows */
1377 #ifdef TARGET_ABI32
1378 case 0x103:
1379 #endif
1380 flush_windows(env);
1381 /* next instruction */
1382 env->pc = env->npc;
1383 env->npc = env->npc + 4;
1384 break;
1385 #ifndef TARGET_SPARC64
1386 case TT_WIN_OVF: /* window overflow */
1387 save_window(env);
1388 break;
1389 case TT_WIN_UNF: /* window underflow */
1390 restore_window(env);
1391 break;
1392 case TT_TFAULT:
1393 case TT_DFAULT:
1394 {
1395 info.si_signo = TARGET_SIGSEGV;
1396 info.si_errno = 0;
1397 /* XXX: check env->error_code */
1398 info.si_code = TARGET_SEGV_MAPERR;
1399 info._sifields._sigfault._addr = env->mmuregs[4];
1400 queue_signal(env, info.si_signo, &info);
1401 }
1402 break;
1403 #else
1404 case TT_SPILL: /* window overflow */
1405 save_window(env);
1406 break;
1407 case TT_FILL: /* window underflow */
1408 restore_window(env);
1409 break;
1410 case TT_TFAULT:
1411 case TT_DFAULT:
1412 {
1413 info.si_signo = TARGET_SIGSEGV;
1414 info.si_errno = 0;
1415 /* XXX: check env->error_code */
1416 info.si_code = TARGET_SEGV_MAPERR;
1417 if (trapnr == TT_DFAULT)
1418 info._sifields._sigfault._addr = env->dmmuregs[4];
1419 else
1420 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1421 queue_signal(env, info.si_signo, &info);
1422 }
1423 break;
1424 #ifndef TARGET_ABI32
1425 case 0x16e:
1426 flush_windows(env);
1427 sparc64_get_context(env);
1428 break;
1429 case 0x16f:
1430 flush_windows(env);
1431 sparc64_set_context(env);
1432 break;
1433 #endif
1434 #endif
1435 case EXCP_INTERRUPT:
1436 /* just indicate that signals should be handled asap */
1437 break;
1438 case TT_ILL_INSN:
1439 {
1440 info.si_signo = TARGET_SIGILL;
1441 info.si_errno = 0;
1442 info.si_code = TARGET_ILL_ILLOPC;
1443 info._sifields._sigfault._addr = env->pc;
1444 queue_signal(env, info.si_signo, &info);
1445 }
1446 break;
1447 case EXCP_DEBUG:
1448 {
1449 int sig;
1450
1451 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1452 if (sig)
1453 {
1454 info.si_signo = sig;
1455 info.si_errno = 0;
1456 info.si_code = TARGET_TRAP_BRKPT;
1457 queue_signal(env, info.si_signo, &info);
1458 }
1459 }
1460 break;
1461 default:
1462 printf ("Unhandled trap: 0x%x\n", trapnr);
1463 cpu_dump_state(cs, stderr, fprintf, 0);
1464 exit (1);
1465 }
1466 process_pending_signals (env);
1467 }
1468 }
1469
1470 #endif
1471
1472 #ifdef TARGET_PPC
1473 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1474 {
1475 /* TO FIX */
1476 return 0;
1477 }
1478
1479 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1480 {
1481 return cpu_ppc_get_tb(env);
1482 }
1483
1484 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1485 {
1486 return cpu_ppc_get_tb(env) >> 32;
1487 }
1488
1489 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1490 {
1491 return cpu_ppc_get_tb(env);
1492 }
1493
1494 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1495 {
1496 return cpu_ppc_get_tb(env) >> 32;
1497 }
1498
1499 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1500 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1501
1502 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1503 {
1504 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1505 }
1506
1507 /* XXX: to be fixed */
1508 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1509 {
1510 return -1;
1511 }
1512
1513 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1514 {
1515 return -1;
1516 }
1517
1518 #define EXCP_DUMP(env, fmt, ...) \
1519 do { \
1520 CPUState *cs = ENV_GET_CPU(env); \
1521 fprintf(stderr, fmt , ## __VA_ARGS__); \
1522 cpu_dump_state(cs, stderr, fprintf, 0); \
1523 qemu_log(fmt, ## __VA_ARGS__); \
1524 if (qemu_log_enabled()) { \
1525 log_cpu_state(cs, 0); \
1526 } \
1527 } while (0)
1528
1529 static int do_store_exclusive(CPUPPCState *env)
1530 {
1531 target_ulong addr;
1532 target_ulong page_addr;
1533 target_ulong val;
1534 int flags;
1535 int segv = 0;
1536
1537 addr = env->reserve_ea;
1538 page_addr = addr & TARGET_PAGE_MASK;
1539 start_exclusive();
1540 mmap_lock();
1541 flags = page_get_flags(page_addr);
1542 if ((flags & PAGE_READ) == 0) {
1543 segv = 1;
1544 } else {
1545 int reg = env->reserve_info & 0x1f;
1546 int size = (env->reserve_info >> 5) & 0xf;
1547 int stored = 0;
1548
1549 if (addr == env->reserve_addr) {
1550 switch (size) {
1551 case 1: segv = get_user_u8(val, addr); break;
1552 case 2: segv = get_user_u16(val, addr); break;
1553 case 4: segv = get_user_u32(val, addr); break;
1554 #if defined(TARGET_PPC64)
1555 case 8: segv = get_user_u64(val, addr); break;
1556 #endif
1557 default: abort();
1558 }
1559 if (!segv && val == env->reserve_val) {
1560 val = env->gpr[reg];
1561 switch (size) {
1562 case 1: segv = put_user_u8(val, addr); break;
1563 case 2: segv = put_user_u16(val, addr); break;
1564 case 4: segv = put_user_u32(val, addr); break;
1565 #if defined(TARGET_PPC64)
1566 case 8: segv = put_user_u64(val, addr); break;
1567 #endif
1568 default: abort();
1569 }
1570 if (!segv) {
1571 stored = 1;
1572 }
1573 }
1574 }
1575 env->crf[0] = (stored << 1) | xer_so;
1576 env->reserve_addr = (target_ulong)-1;
1577 }
1578 if (!segv) {
1579 env->nip += 4;
1580 }
1581 mmap_unlock();
1582 end_exclusive();
1583 return segv;
1584 }
1585
1586 void cpu_loop(CPUPPCState *env)
1587 {
1588 CPUState *cs = CPU(ppc_env_get_cpu(env));
1589 target_siginfo_t info;
1590 int trapnr;
1591 target_ulong ret;
1592
1593 for(;;) {
1594 cpu_exec_start(cs);
1595 trapnr = cpu_ppc_exec(env);
1596 cpu_exec_end(cs);
1597 switch(trapnr) {
1598 case POWERPC_EXCP_NONE:
1599 /* Just go on */
1600 break;
1601 case POWERPC_EXCP_CRITICAL: /* Critical input */
1602 cpu_abort(env, "Critical interrupt while in user mode. "
1603 "Aborting\n");
1604 break;
1605 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1606 cpu_abort(env, "Machine check exception while in user mode. "
1607 "Aborting\n");
1608 break;
1609 case POWERPC_EXCP_DSI: /* Data storage exception */
1610 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1611 env->spr[SPR_DAR]);
1612 /* XXX: check this. Seems bugged */
1613 switch (env->error_code & 0xFF000000) {
1614 case 0x40000000:
1615 info.si_signo = TARGET_SIGSEGV;
1616 info.si_errno = 0;
1617 info.si_code = TARGET_SEGV_MAPERR;
1618 break;
1619 case 0x04000000:
1620 info.si_signo = TARGET_SIGILL;
1621 info.si_errno = 0;
1622 info.si_code = TARGET_ILL_ILLADR;
1623 break;
1624 case 0x08000000:
1625 info.si_signo = TARGET_SIGSEGV;
1626 info.si_errno = 0;
1627 info.si_code = TARGET_SEGV_ACCERR;
1628 break;
1629 default:
1630 /* Let's send a regular segfault... */
1631 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1632 env->error_code);
1633 info.si_signo = TARGET_SIGSEGV;
1634 info.si_errno = 0;
1635 info.si_code = TARGET_SEGV_MAPERR;
1636 break;
1637 }
1638 info._sifields._sigfault._addr = env->nip;
1639 queue_signal(env, info.si_signo, &info);
1640 break;
1641 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1642 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1643 "\n", env->spr[SPR_SRR0]);
1644 /* XXX: check this */
1645 switch (env->error_code & 0xFF000000) {
1646 case 0x40000000:
1647 info.si_signo = TARGET_SIGSEGV;
1648 info.si_errno = 0;
1649 info.si_code = TARGET_SEGV_MAPERR;
1650 break;
1651 case 0x10000000:
1652 case 0x08000000:
1653 info.si_signo = TARGET_SIGSEGV;
1654 info.si_errno = 0;
1655 info.si_code = TARGET_SEGV_ACCERR;
1656 break;
1657 default:
1658 /* Let's send a regular segfault... */
1659 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1660 env->error_code);
1661 info.si_signo = TARGET_SIGSEGV;
1662 info.si_errno = 0;
1663 info.si_code = TARGET_SEGV_MAPERR;
1664 break;
1665 }
1666 info._sifields._sigfault._addr = env->nip - 4;
1667 queue_signal(env, info.si_signo, &info);
1668 break;
1669 case POWERPC_EXCP_EXTERNAL: /* External input */
1670 cpu_abort(env, "External interrupt while in user mode. "
1671 "Aborting\n");
1672 break;
1673 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1674 EXCP_DUMP(env, "Unaligned memory access\n");
1675 /* XXX: check this */
1676 info.si_signo = TARGET_SIGBUS;
1677 info.si_errno = 0;
1678 info.si_code = TARGET_BUS_ADRALN;
1679 info._sifields._sigfault._addr = env->nip - 4;
1680 queue_signal(env, info.si_signo, &info);
1681 break;
1682 case POWERPC_EXCP_PROGRAM: /* Program exception */
1683 /* XXX: check this */
1684 switch (env->error_code & ~0xF) {
1685 case POWERPC_EXCP_FP:
1686 EXCP_DUMP(env, "Floating point program exception\n");
1687 info.si_signo = TARGET_SIGFPE;
1688 info.si_errno = 0;
1689 switch (env->error_code & 0xF) {
1690 case POWERPC_EXCP_FP_OX:
1691 info.si_code = TARGET_FPE_FLTOVF;
1692 break;
1693 case POWERPC_EXCP_FP_UX:
1694 info.si_code = TARGET_FPE_FLTUND;
1695 break;
1696 case POWERPC_EXCP_FP_ZX:
1697 case POWERPC_EXCP_FP_VXZDZ:
1698 info.si_code = TARGET_FPE_FLTDIV;
1699 break;
1700 case POWERPC_EXCP_FP_XX:
1701 info.si_code = TARGET_FPE_FLTRES;
1702 break;
1703 case POWERPC_EXCP_FP_VXSOFT:
1704 info.si_code = TARGET_FPE_FLTINV;
1705 break;
1706 case POWERPC_EXCP_FP_VXSNAN:
1707 case POWERPC_EXCP_FP_VXISI:
1708 case POWERPC_EXCP_FP_VXIDI:
1709 case POWERPC_EXCP_FP_VXIMZ:
1710 case POWERPC_EXCP_FP_VXVC:
1711 case POWERPC_EXCP_FP_VXSQRT:
1712 case POWERPC_EXCP_FP_VXCVI:
1713 info.si_code = TARGET_FPE_FLTSUB;
1714 break;
1715 default:
1716 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1717 env->error_code);
1718 break;
1719 }
1720 break;
1721 case POWERPC_EXCP_INVAL:
1722 EXCP_DUMP(env, "Invalid instruction\n");
1723 info.si_signo = TARGET_SIGILL;
1724 info.si_errno = 0;
1725 switch (env->error_code & 0xF) {
1726 case POWERPC_EXCP_INVAL_INVAL:
1727 info.si_code = TARGET_ILL_ILLOPC;
1728 break;
1729 case POWERPC_EXCP_INVAL_LSWX:
1730 info.si_code = TARGET_ILL_ILLOPN;
1731 break;
1732 case POWERPC_EXCP_INVAL_SPR:
1733 info.si_code = TARGET_ILL_PRVREG;
1734 break;
1735 case POWERPC_EXCP_INVAL_FP:
1736 info.si_code = TARGET_ILL_COPROC;
1737 break;
1738 default:
1739 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1740 env->error_code & 0xF);
1741 info.si_code = TARGET_ILL_ILLADR;
1742 break;
1743 }
1744 break;
1745 case POWERPC_EXCP_PRIV:
1746 EXCP_DUMP(env, "Privilege violation\n");
1747 info.si_signo = TARGET_SIGILL;
1748 info.si_errno = 0;
1749 switch (env->error_code & 0xF) {
1750 case POWERPC_EXCP_PRIV_OPC:
1751 info.si_code = TARGET_ILL_PRVOPC;
1752 break;
1753 case POWERPC_EXCP_PRIV_REG:
1754 info.si_code = TARGET_ILL_PRVREG;
1755 break;
1756 default:
1757 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1758 env->error_code & 0xF);
1759 info.si_code = TARGET_ILL_PRVOPC;
1760 break;
1761 }
1762 break;
1763 case POWERPC_EXCP_TRAP:
1764 cpu_abort(env, "Tried to call a TRAP\n");
1765 break;
1766 default:
1767 /* Should not happen ! */
1768 cpu_abort(env, "Unknown program exception (%02x)\n",
1769 env->error_code);
1770 break;
1771 }
1772 info._sifields._sigfault._addr = env->nip - 4;
1773 queue_signal(env, info.si_signo, &info);
1774 break;
1775 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1776 EXCP_DUMP(env, "No floating point allowed\n");
1777 info.si_signo = TARGET_SIGILL;
1778 info.si_errno = 0;
1779 info.si_code = TARGET_ILL_COPROC;
1780 info._sifields._sigfault._addr = env->nip - 4;
1781 queue_signal(env, info.si_signo, &info);
1782 break;
1783 case POWERPC_EXCP_SYSCALL: /* System call exception */
1784 cpu_abort(env, "Syscall exception while in user mode. "
1785 "Aborting\n");
1786 break;
1787 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1788 EXCP_DUMP(env, "No APU instruction allowed\n");
1789 info.si_signo = TARGET_SIGILL;
1790 info.si_errno = 0;
1791 info.si_code = TARGET_ILL_COPROC;
1792 info._sifields._sigfault._addr = env->nip - 4;
1793 queue_signal(env, info.si_signo, &info);
1794 break;
1795 case POWERPC_EXCP_DECR: /* Decrementer exception */
1796 cpu_abort(env, "Decrementer interrupt while in user mode. "
1797 "Aborting\n");
1798 break;
1799 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1800 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1801 "Aborting\n");
1802 break;
1803 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1804 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1805 "Aborting\n");
1806 break;
1807 case POWERPC_EXCP_DTLB: /* Data TLB error */
1808 cpu_abort(env, "Data TLB exception while in user mode. "
1809 "Aborting\n");
1810 break;
1811 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1812 cpu_abort(env, "Instruction TLB exception while in user mode. "
1813 "Aborting\n");
1814 break;
1815 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1816 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1817 info.si_signo = TARGET_SIGILL;
1818 info.si_errno = 0;
1819 info.si_code = TARGET_ILL_COPROC;
1820 info._sifields._sigfault._addr = env->nip - 4;
1821 queue_signal(env, info.si_signo, &info);
1822 break;
1823 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1824 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1825 break;
1826 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1827 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1828 break;
1829 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1830 cpu_abort(env, "Performance monitor exception not handled\n");
1831 break;
1832 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1833 cpu_abort(env, "Doorbell interrupt while in user mode. "
1834 "Aborting\n");
1835 break;
1836 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1837 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1838 "Aborting\n");
1839 break;
1840 case POWERPC_EXCP_RESET: /* System reset exception */
1841 cpu_abort(env, "Reset interrupt while in user mode. "
1842 "Aborting\n");
1843 break;
1844 case POWERPC_EXCP_DSEG: /* Data segment exception */
1845 cpu_abort(env, "Data segment exception while in user mode. "
1846 "Aborting\n");
1847 break;
1848 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1849 cpu_abort(env, "Instruction segment exception "
1850 "while in user mode. Aborting\n");
1851 break;
1852 /* PowerPC 64 with hypervisor mode support */
1853 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1854 cpu_abort(env, "Hypervisor decrementer interrupt "
1855 "while in user mode. Aborting\n");
1856 break;
1857 case POWERPC_EXCP_TRACE: /* Trace exception */
1858 /* Nothing to do:
1859 * we use this exception to emulate step-by-step execution mode.
1860 */
1861 break;
1862 /* PowerPC 64 with hypervisor mode support */
1863 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1864 cpu_abort(env, "Hypervisor data storage exception "
1865 "while in user mode. Aborting\n");
1866 break;
1867 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1868 cpu_abort(env, "Hypervisor instruction storage exception "
1869 "while in user mode. Aborting\n");
1870 break;
1871 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1872 cpu_abort(env, "Hypervisor data segment exception "
1873 "while in user mode. Aborting\n");
1874 break;
1875 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1876 cpu_abort(env, "Hypervisor instruction segment exception "
1877 "while in user mode. Aborting\n");
1878 break;
1879 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1880 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1881 info.si_signo = TARGET_SIGILL;
1882 info.si_errno = 0;
1883 info.si_code = TARGET_ILL_COPROC;
1884 info._sifields._sigfault._addr = env->nip - 4;
1885 queue_signal(env, info.si_signo, &info);
1886 break;
1887 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1888 cpu_abort(env, "Programmable interval timer interrupt "
1889 "while in user mode. Aborting\n");
1890 break;
1891 case POWERPC_EXCP_IO: /* IO error exception */
1892 cpu_abort(env, "IO error exception while in user mode. "
1893 "Aborting\n");
1894 break;
1895 case POWERPC_EXCP_RUNM: /* Run mode exception */
1896 cpu_abort(env, "Run mode exception while in user mode. "
1897 "Aborting\n");
1898 break;
1899 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1900 cpu_abort(env, "Emulation trap exception not handled\n");
1901 break;
1902 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1903 cpu_abort(env, "Instruction fetch TLB exception "
1904 "while in user-mode. Aborting");
1905 break;
1906 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1907 cpu_abort(env, "Data load TLB exception while in user-mode. "
1908 "Aborting");
1909 break;
1910 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1911 cpu_abort(env, "Data store TLB exception while in user-mode. "
1912 "Aborting");
1913 break;
1914 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1915 cpu_abort(env, "Floating-point assist exception not handled\n");
1916 break;
1917 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1918 cpu_abort(env, "Instruction address breakpoint exception "
1919 "not handled\n");
1920 break;
1921 case POWERPC_EXCP_SMI: /* System management interrupt */
1922 cpu_abort(env, "System management interrupt while in user mode. "
1923 "Aborting\n");
1924 break;
1925 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1926 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1927 "Aborting\n");
1928 break;
1929 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1930 cpu_abort(env, "Performance monitor exception not handled\n");
1931 break;
1932 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1933 cpu_abort(env, "Vector assist exception not handled\n");
1934 break;
1935 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1936 cpu_abort(env, "Soft patch exception not handled\n");
1937 break;
1938 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1939 cpu_abort(env, "Maintenance exception while in user mode. "
1940 "Aborting\n");
1941 break;
1942 case POWERPC_EXCP_STOP: /* stop translation */
1943 /* We did invalidate the instruction cache. Go on */
1944 break;
1945 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1946 /* We just stopped because of a branch. Go on */
1947 break;
1948 case POWERPC_EXCP_SYSCALL_USER:
1949 /* system call in user-mode emulation */
1950 /* WARNING:
1951 * PPC ABI uses overflow flag in cr0 to signal an error
1952 * in syscalls.
1953 */
1954 env->crf[0] &= ~0x1;
1955 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1956 env->gpr[5], env->gpr[6], env->gpr[7],
1957 env->gpr[8], 0, 0);
1958 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1959 /* Returning from a successful sigreturn syscall.
1960 Avoid corrupting register state. */
1961 break;
1962 }
1963 if (ret > (target_ulong)(-515)) {
1964 env->crf[0] |= 0x1;
1965 ret = -ret;
1966 }
1967 env->gpr[3] = ret;
1968 break;
1969 case POWERPC_EXCP_STCX:
1970 if (do_store_exclusive(env)) {
1971 info.si_signo = TARGET_SIGSEGV;
1972 info.si_errno = 0;
1973 info.si_code = TARGET_SEGV_MAPERR;
1974 info._sifields._sigfault._addr = env->nip;
1975 queue_signal(env, info.si_signo, &info);
1976 }
1977 break;
1978 case EXCP_DEBUG:
1979 {
1980 int sig;
1981
1982 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1983 if (sig) {
1984 info.si_signo = sig;
1985 info.si_errno = 0;
1986 info.si_code = TARGET_TRAP_BRKPT;
1987 queue_signal(env, info.si_signo, &info);
1988 }
1989 }
1990 break;
1991 case EXCP_INTERRUPT:
1992 /* just indicate that signals should be handled asap */
1993 break;
1994 default:
1995 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1996 break;
1997 }
1998 process_pending_signals(env);
1999 }
2000 }
2001 #endif
2002
2003 #ifdef TARGET_MIPS
2004
2005 # ifdef TARGET_ABI_MIPSO32
2006 # define MIPS_SYS(name, args) args,
2007 static const uint8_t mips_syscall_args[] = {
2008 MIPS_SYS(sys_syscall , 8) /* 4000 */
2009 MIPS_SYS(sys_exit , 1)
2010 MIPS_SYS(sys_fork , 0)
2011 MIPS_SYS(sys_read , 3)
2012 MIPS_SYS(sys_write , 3)
2013 MIPS_SYS(sys_open , 3) /* 4005 */
2014 MIPS_SYS(sys_close , 1)
2015 MIPS_SYS(sys_waitpid , 3)
2016 MIPS_SYS(sys_creat , 2)
2017 MIPS_SYS(sys_link , 2)
2018 MIPS_SYS(sys_unlink , 1) /* 4010 */
2019 MIPS_SYS(sys_execve , 0)
2020 MIPS_SYS(sys_chdir , 1)
2021 MIPS_SYS(sys_time , 1)
2022 MIPS_SYS(sys_mknod , 3)
2023 MIPS_SYS(sys_chmod , 2) /* 4015 */
2024 MIPS_SYS(sys_lchown , 3)
2025 MIPS_SYS(sys_ni_syscall , 0)
2026 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2027 MIPS_SYS(sys_lseek , 3)
2028 MIPS_SYS(sys_getpid , 0) /* 4020 */
2029 MIPS_SYS(sys_mount , 5)
2030 MIPS_SYS(sys_umount , 1)
2031 MIPS_SYS(sys_setuid , 1)
2032 MIPS_SYS(sys_getuid , 0)
2033 MIPS_SYS(sys_stime , 1) /* 4025 */
2034 MIPS_SYS(sys_ptrace , 4)
2035 MIPS_SYS(sys_alarm , 1)
2036 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2037 MIPS_SYS(sys_pause , 0)
2038 MIPS_SYS(sys_utime , 2) /* 4030 */
2039 MIPS_SYS(sys_ni_syscall , 0)
2040 MIPS_SYS(sys_ni_syscall , 0)
2041 MIPS_SYS(sys_access , 2)
2042 MIPS_SYS(sys_nice , 1)
2043 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2044 MIPS_SYS(sys_sync , 0)
2045 MIPS_SYS(sys_kill , 2)
2046 MIPS_SYS(sys_rename , 2)
2047 MIPS_SYS(sys_mkdir , 2)
2048 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2049 MIPS_SYS(sys_dup , 1)
2050 MIPS_SYS(sys_pipe , 0)
2051 MIPS_SYS(sys_times , 1)
2052 MIPS_SYS(sys_ni_syscall , 0)
2053 MIPS_SYS(sys_brk , 1) /* 4045 */
2054 MIPS_SYS(sys_setgid , 1)
2055 MIPS_SYS(sys_getgid , 0)
2056 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2057 MIPS_SYS(sys_geteuid , 0)
2058 MIPS_SYS(sys_getegid , 0) /* 4050 */
2059 MIPS_SYS(sys_acct , 0)
2060 MIPS_SYS(sys_umount2 , 2)
2061 MIPS_SYS(sys_ni_syscall , 0)
2062 MIPS_SYS(sys_ioctl , 3)
2063 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2064 MIPS_SYS(sys_ni_syscall , 2)
2065 MIPS_SYS(sys_setpgid , 2)
2066 MIPS_SYS(sys_ni_syscall , 0)
2067 MIPS_SYS(sys_olduname , 1)
2068 MIPS_SYS(sys_umask , 1) /* 4060 */
2069 MIPS_SYS(sys_chroot , 1)
2070 MIPS_SYS(sys_ustat , 2)
2071 MIPS_SYS(sys_dup2 , 2)
2072 MIPS_SYS(sys_getppid , 0)
2073 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2074 MIPS_SYS(sys_setsid , 0)
2075 MIPS_SYS(sys_sigaction , 3)
2076 MIPS_SYS(sys_sgetmask , 0)
2077 MIPS_SYS(sys_ssetmask , 1)
2078 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2079 MIPS_SYS(sys_setregid , 2)
2080 MIPS_SYS(sys_sigsuspend , 0)
2081 MIPS_SYS(sys_sigpending , 1)
2082 MIPS_SYS(sys_sethostname , 2)
2083 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2084 MIPS_SYS(sys_getrlimit , 2)
2085 MIPS_SYS(sys_getrusage , 2)
2086 MIPS_SYS(sys_gettimeofday, 2)
2087 MIPS_SYS(sys_settimeofday, 2)
2088 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2089 MIPS_SYS(sys_setgroups , 2)
2090 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2091 MIPS_SYS(sys_symlink , 2)
2092 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2093 MIPS_SYS(sys_readlink , 3) /* 4085 */
2094 MIPS_SYS(sys_uselib , 1)
2095 MIPS_SYS(sys_swapon , 2)
2096 MIPS_SYS(sys_reboot , 3)
2097 MIPS_SYS(old_readdir , 3)
2098 MIPS_SYS(old_mmap , 6) /* 4090 */
2099 MIPS_SYS(sys_munmap , 2)
2100 MIPS_SYS(sys_truncate , 2)
2101 MIPS_SYS(sys_ftruncate , 2)
2102 MIPS_SYS(sys_fchmod , 2)
2103 MIPS_SYS(sys_fchown , 3) /* 4095 */
2104 MIPS_SYS(sys_getpriority , 2)
2105 MIPS_SYS(sys_setpriority , 3)
2106 MIPS_SYS(sys_ni_syscall , 0)
2107 MIPS_SYS(sys_statfs , 2)
2108 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2109 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2110 MIPS_SYS(sys_socketcall , 2)
2111 MIPS_SYS(sys_syslog , 3)
2112 MIPS_SYS(sys_setitimer , 3)
2113 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2114 MIPS_SYS(sys_newstat , 2)
2115 MIPS_SYS(sys_newlstat , 2)
2116 MIPS_SYS(sys_newfstat , 2)
2117 MIPS_SYS(sys_uname , 1)
2118 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2119 MIPS_SYS(sys_vhangup , 0)
2120 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2121 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2122 MIPS_SYS(sys_wait4 , 4)
2123 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2124 MIPS_SYS(sys_sysinfo , 1)
2125 MIPS_SYS(sys_ipc , 6)
2126 MIPS_SYS(sys_fsync , 1)
2127 MIPS_SYS(sys_sigreturn , 0)
2128 MIPS_SYS(sys_clone , 6) /* 4120 */
2129 MIPS_SYS(sys_setdomainname, 2)
2130 MIPS_SYS(sys_newuname , 1)
2131 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2132 MIPS_SYS(sys_adjtimex , 1)
2133 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2134 MIPS_SYS(sys_sigprocmask , 3)
2135 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2136 MIPS_SYS(sys_init_module , 5)
2137 MIPS_SYS(sys_delete_module, 1)
2138 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2139 MIPS_SYS(sys_quotactl , 0)
2140 MIPS_SYS(sys_getpgid , 1)
2141 MIPS_SYS(sys_fchdir , 1)
2142 MIPS_SYS(sys_bdflush , 2)
2143 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2144 MIPS_SYS(sys_personality , 1)
2145 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2146 MIPS_SYS(sys_setfsuid , 1)
2147 MIPS_SYS(sys_setfsgid , 1)
2148 MIPS_SYS(sys_llseek , 5) /* 4140 */
2149 MIPS_SYS(sys_getdents , 3)
2150 MIPS_SYS(sys_select , 5)
2151 MIPS_SYS(sys_flock , 2)
2152 MIPS_SYS(sys_msync , 3)
2153 MIPS_SYS(sys_readv , 3) /* 4145 */
2154 MIPS_SYS(sys_writev , 3)
2155 MIPS_SYS(sys_cacheflush , 3)
2156 MIPS_SYS(sys_cachectl , 3)
2157 MIPS_SYS(sys_sysmips , 4)
2158 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2159 MIPS_SYS(sys_getsid , 1)
2160 MIPS_SYS(sys_fdatasync , 0)
2161 MIPS_SYS(sys_sysctl , 1)
2162 MIPS_SYS(sys_mlock , 2)
2163 MIPS_SYS(sys_munlock , 2) /* 4155 */
2164 MIPS_SYS(sys_mlockall , 1)
2165 MIPS_SYS(sys_munlockall , 0)
2166 MIPS_SYS(sys_sched_setparam, 2)
2167 MIPS_SYS(sys_sched_getparam, 2)
2168 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2169 MIPS_SYS(sys_sched_getscheduler, 1)
2170 MIPS_SYS(sys_sched_yield , 0)
2171 MIPS_SYS(sys_sched_get_priority_max, 1)
2172 MIPS_SYS(sys_sched_get_priority_min, 1)
2173 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2174 MIPS_SYS(sys_nanosleep, 2)
2175 MIPS_SYS(sys_mremap , 5)
2176 MIPS_SYS(sys_accept , 3)
2177 MIPS_SYS(sys_bind , 3)
2178 MIPS_SYS(sys_connect , 3) /* 4170 */
2179 MIPS_SYS(sys_getpeername , 3)
2180 MIPS_SYS(sys_getsockname , 3)
2181 MIPS_SYS(sys_getsockopt , 5)
2182 MIPS_SYS(sys_listen , 2)
2183 MIPS_SYS(sys_recv , 4) /* 4175 */
2184 MIPS_SYS(sys_recvfrom , 6)
2185 MIPS_SYS(sys_recvmsg , 3)
2186 MIPS_SYS(sys_send , 4)
2187 MIPS_SYS(sys_sendmsg , 3)
2188 MIPS_SYS(sys_sendto , 6) /* 4180 */
2189 MIPS_SYS(sys_setsockopt , 5)
2190 MIPS_SYS(sys_shutdown , 2)
2191 MIPS_SYS(sys_socket , 3)
2192 MIPS_SYS(sys_socketpair , 4)
2193 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2194 MIPS_SYS(sys_getresuid , 3)
2195 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2196 MIPS_SYS(sys_poll , 3)
2197 MIPS_SYS(sys_nfsservctl , 3)
2198 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2199 MIPS_SYS(sys_getresgid , 3)
2200 MIPS_SYS(sys_prctl , 5)
2201 MIPS_SYS(sys_rt_sigreturn, 0)
2202 MIPS_SYS(sys_rt_sigaction, 4)
2203 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2204 MIPS_SYS(sys_rt_sigpending, 2)
2205 MIPS_SYS(sys_rt_sigtimedwait, 4)
2206 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2207 MIPS_SYS(sys_rt_sigsuspend, 0)
2208 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2209 MIPS_SYS(sys_pwrite64 , 6)
2210 MIPS_SYS(sys_chown , 3)
2211 MIPS_SYS(sys_getcwd , 2)
2212 MIPS_SYS(sys_capget , 2)
2213 MIPS_SYS(sys_capset , 2) /* 4205 */
2214 MIPS_SYS(sys_sigaltstack , 2)
2215 MIPS_SYS(sys_sendfile , 4)
2216 MIPS_SYS(sys_ni_syscall , 0)
2217 MIPS_SYS(sys_ni_syscall , 0)
2218 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2219 MIPS_SYS(sys_truncate64 , 4)
2220 MIPS_SYS(sys_ftruncate64 , 4)
2221 MIPS_SYS(sys_stat64 , 2)
2222 MIPS_SYS(sys_lstat64 , 2)
2223 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2224 MIPS_SYS(sys_pivot_root , 2)
2225 MIPS_SYS(sys_mincore , 3)
2226 MIPS_SYS(sys_madvise , 3)
2227 MIPS_SYS(sys_getdents64 , 3)
2228 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2229 MIPS_SYS(sys_ni_syscall , 0)
2230 MIPS_SYS(sys_gettid , 0)
2231 MIPS_SYS(sys_readahead , 5)
2232 MIPS_SYS(sys_setxattr , 5)
2233 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2234 MIPS_SYS(sys_fsetxattr , 5)
2235 MIPS_SYS(sys_getxattr , 4)
2236 MIPS_SYS(sys_lgetxattr , 4)
2237 MIPS_SYS(sys_fgetxattr , 4)
2238 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2239 MIPS_SYS(sys_llistxattr , 3)
2240 MIPS_SYS(sys_flistxattr , 3)
2241 MIPS_SYS(sys_removexattr , 2)
2242 MIPS_SYS(sys_lremovexattr, 2)
2243 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2244 MIPS_SYS(sys_tkill , 2)
2245 MIPS_SYS(sys_sendfile64 , 5)
2246 MIPS_SYS(sys_futex , 6)
2247 MIPS_SYS(sys_sched_setaffinity, 3)
2248 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2249 MIPS_SYS(sys_io_setup , 2)
2250 MIPS_SYS(sys_io_destroy , 1)
2251 MIPS_SYS(sys_io_getevents, 5)
2252 MIPS_SYS(sys_io_submit , 3)
2253 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2254 MIPS_SYS(sys_exit_group , 1)
2255 MIPS_SYS(sys_lookup_dcookie, 3)
2256 MIPS_SYS(sys_epoll_create, 1)
2257 MIPS_SYS(sys_epoll_ctl , 4)
2258 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2259 MIPS_SYS(sys_remap_file_pages, 5)
2260 MIPS_SYS(sys_set_tid_address, 1)
2261 MIPS_SYS(sys_restart_syscall, 0)
2262 MIPS_SYS(sys_fadvise64_64, 7)
2263 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2264 MIPS_SYS(sys_fstatfs64 , 2)
2265 MIPS_SYS(sys_timer_create, 3)
2266 MIPS_SYS(sys_timer_settime, 4)
2267 MIPS_SYS(sys_timer_gettime, 2)
2268 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2269 MIPS_SYS(sys_timer_delete, 1)
2270 MIPS_SYS(sys_clock_settime, 2)
2271 MIPS_SYS(sys_clock_gettime, 2)
2272 MIPS_SYS(sys_clock_getres, 2)
2273 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2274 MIPS_SYS(sys_tgkill , 3)
2275 MIPS_SYS(sys_utimes , 2)
2276 MIPS_SYS(sys_mbind , 4)
2277 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2278 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2279 MIPS_SYS(sys_mq_open , 4)
2280 MIPS_SYS(sys_mq_unlink , 1)
2281 MIPS_SYS(sys_mq_timedsend, 5)
2282 MIPS_SYS(sys_mq_timedreceive, 5)
2283 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2284 MIPS_SYS(sys_mq_getsetattr, 3)
2285 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2286 MIPS_SYS(sys_waitid , 4)
2287 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2288 MIPS_SYS(sys_add_key , 5)
2289 MIPS_SYS(sys_request_key, 4)
2290 MIPS_SYS(sys_keyctl , 5)
2291 MIPS_SYS(sys_set_thread_area, 1)
2292 MIPS_SYS(sys_inotify_init, 0)
2293 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2294 MIPS_SYS(sys_inotify_rm_watch, 2)
2295 MIPS_SYS(sys_migrate_pages, 4)
2296 MIPS_SYS(sys_openat, 4)
2297 MIPS_SYS(sys_mkdirat, 3)
2298 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2299 MIPS_SYS(sys_fchownat, 5)
2300 MIPS_SYS(sys_futimesat, 3)
2301 MIPS_SYS(sys_fstatat64, 4)
2302 MIPS_SYS(sys_unlinkat, 3)
2303 MIPS_SYS(sys_renameat, 4) /* 4295 */
2304 MIPS_SYS(sys_linkat, 5)
2305 MIPS_SYS(sys_symlinkat, 3)
2306 MIPS_SYS(sys_readlinkat, 4)
2307 MIPS_SYS(sys_fchmodat, 3)
2308 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2309 MIPS_SYS(sys_pselect6, 6)
2310 MIPS_SYS(sys_ppoll, 5)
2311 MIPS_SYS(sys_unshare, 1)
2312 MIPS_SYS(sys_splice, 6)
2313 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2314 MIPS_SYS(sys_tee, 4)
2315 MIPS_SYS(sys_vmsplice, 4)
2316 MIPS_SYS(sys_move_pages, 6)
2317 MIPS_SYS(sys_set_robust_list, 2)
2318 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2319 MIPS_SYS(sys_kexec_load, 4)
2320 MIPS_SYS(sys_getcpu, 3)
2321 MIPS_SYS(sys_epoll_pwait, 6)
2322 MIPS_SYS(sys_ioprio_set, 3)
2323 MIPS_SYS(sys_ioprio_get, 2)
2324 MIPS_SYS(sys_utimensat, 4)
2325 MIPS_SYS(sys_signalfd, 3)
2326 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2327 MIPS_SYS(sys_eventfd, 1)
2328 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2329 MIPS_SYS(sys_timerfd_create, 2)
2330 MIPS_SYS(sys_timerfd_gettime, 2)
2331 MIPS_SYS(sys_timerfd_settime, 4)
2332 MIPS_SYS(sys_signalfd4, 4)
2333 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2334 MIPS_SYS(sys_epoll_create1, 1)
2335 MIPS_SYS(sys_dup3, 3)
2336 MIPS_SYS(sys_pipe2, 2)
2337 MIPS_SYS(sys_inotify_init1, 1)
2338 MIPS_SYS(sys_preadv, 6) /* 4330 */
2339 MIPS_SYS(sys_pwritev, 6)
2340 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2341 MIPS_SYS(sys_perf_event_open, 5)
2342 MIPS_SYS(sys_accept4, 4)
2343 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2344 MIPS_SYS(sys_fanotify_init, 2)
2345 MIPS_SYS(sys_fanotify_mark, 6)
2346 MIPS_SYS(sys_prlimit64, 4)
2347 MIPS_SYS(sys_name_to_handle_at, 5)
2348 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2349 MIPS_SYS(sys_clock_adjtime, 2)
2350 MIPS_SYS(sys_syncfs, 1)
2351 };
2352 # undef MIPS_SYS
2353 # endif /* O32 */
2354
2355 static int do_store_exclusive(CPUMIPSState *env)
2356 {
2357 target_ulong addr;
2358 target_ulong page_addr;
2359 target_ulong val;
2360 int flags;
2361 int segv = 0;
2362 int reg;
2363 int d;
2364
2365 addr = env->lladdr;
2366 page_addr = addr & TARGET_PAGE_MASK;
2367 start_exclusive();
2368 mmap_lock();
2369 flags = page_get_flags(page_addr);
2370 if ((flags & PAGE_READ) == 0) {
2371 segv = 1;
2372 } else {
2373 reg = env->llreg & 0x1f;
2374 d = (env->llreg & 0x20) != 0;
2375 if (d) {
2376 segv = get_user_s64(val, addr);
2377 } else {
2378 segv = get_user_s32(val, addr);
2379 }
2380 if (!segv) {
2381 if (val != env->llval) {
2382 env->active_tc.gpr[reg] = 0;
2383 } else {
2384 if (d) {
2385 segv = put_user_u64(env->llnewval, addr);
2386 } else {
2387 segv = put_user_u32(env->llnewval, addr);
2388 }
2389 if (!segv) {
2390 env->active_tc.gpr[reg] = 1;
2391 }
2392 }
2393 }
2394 }
2395 env->lladdr = -1;
2396 if (!segv) {
2397 env->active_tc.PC += 4;
2398 }
2399 mmap_unlock();
2400 end_exclusive();
2401 return segv;
2402 }
2403
2404 /* Break codes */
2405 enum {
2406 BRK_OVERFLOW = 6,
2407 BRK_DIVZERO = 7
2408 };
2409
2410 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2411 unsigned int code)
2412 {
2413 int ret = -1;
2414
2415 switch (code) {
2416 case BRK_OVERFLOW:
2417 case BRK_DIVZERO:
2418 info->si_signo = TARGET_SIGFPE;
2419 info->si_errno = 0;
2420 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2421 queue_signal(env, info->si_signo, &*info);
2422 ret = 0;
2423 break;
2424 default:
2425 break;
2426 }
2427
2428 return ret;
2429 }
2430
2431 void cpu_loop(CPUMIPSState *env)
2432 {
2433 CPUState *cs = CPU(mips_env_get_cpu(env));
2434 target_siginfo_t info;
2435 int trapnr;
2436 abi_long ret;
2437 # ifdef TARGET_ABI_MIPSO32
2438 unsigned int syscall_num;
2439 # endif
2440
2441 for(;;) {
2442 cpu_exec_start(cs);
2443 trapnr = cpu_mips_exec(env);
2444 cpu_exec_end(cs);
2445 switch(trapnr) {
2446 case EXCP_SYSCALL:
2447 env->active_tc.PC += 4;
2448 # ifdef TARGET_ABI_MIPSO32
2449 syscall_num = env->active_tc.gpr[2] - 4000;
2450 if (syscall_num >= sizeof(mips_syscall_args)) {
2451 ret = -TARGET_ENOSYS;
2452 } else {
2453 int nb_args;
2454 abi_ulong sp_reg;
2455 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2456
2457 nb_args = mips_syscall_args[syscall_num];
2458 sp_reg = env->active_tc.gpr[29];
2459 switch (nb_args) {
2460 /* these arguments are taken from the stack */
2461 case 8:
2462 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2463 goto done_syscall;
2464 }
2465 case 7:
2466 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2467 goto done_syscall;
2468 }
2469 case 6:
2470 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2471 goto done_syscall;
2472 }
2473 case 5:
2474 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2475 goto done_syscall;
2476 }
2477 default:
2478 break;
2479 }
2480 ret = do_syscall(env, env->active_tc.gpr[2],
2481 env->active_tc.gpr[4],
2482 env->active_tc.gpr[5],
2483 env->active_tc.gpr[6],
2484 env->active_tc.gpr[7],
2485 arg5, arg6, arg7, arg8);
2486 }
2487 done_syscall:
2488 # else
2489 ret = do_syscall(env, env->active_tc.gpr[2],
2490 env->active_tc.gpr[4], env->active_tc.gpr[5],
2491 env->active_tc.gpr[6], env->active_tc.gpr[7],
2492 env->active_tc.gpr[8], env->active_tc.gpr[9],
2493 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2494 # endif /* O32 */
2495 if (ret == -TARGET_QEMU_ESIGRETURN) {
2496 /* Returning from a successful sigreturn syscall.
2497 Avoid clobbering register state. */
2498 break;
2499 }
2500 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2501 env->active_tc.gpr[7] = 1; /* error flag */
2502 ret = -ret;
2503 } else {
2504 env->active_tc.gpr[7] = 0; /* error flag */
2505 }
2506 env->active_tc.gpr[2] = ret;
2507 break;
2508 case EXCP_TLBL:
2509 case EXCP_TLBS:
2510 case EXCP_AdEL:
2511 case EXCP_AdES:
2512 info.si_signo = TARGET_SIGSEGV;
2513 info.si_errno = 0;
2514 /* XXX: check env->error_code */
2515 info.si_code = TARGET_SEGV_MAPERR;
2516 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2517 queue_signal(env, info.si_signo, &info);
2518 break;
2519 case EXCP_CpU:
2520 case EXCP_RI:
2521 info.si_signo = TARGET_SIGILL;
2522 info.si_errno = 0;
2523 info.si_code = 0;
2524 queue_signal(env, info.si_signo, &info);
2525 break;
2526 case EXCP_INTERRUPT:
2527 /* just indicate that signals should be handled asap */
2528 break;
2529 case EXCP_DEBUG:
2530 {
2531 int sig;
2532
2533 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2534 if (sig)
2535 {
2536 info.si_signo = sig;
2537 info.si_errno = 0;
2538 info.si_code = TARGET_TRAP_BRKPT;
2539 queue_signal(env, info.si_signo, &info);
2540 }
2541 }
2542 break;
2543 case EXCP_SC:
2544 if (do_store_exclusive(env)) {
2545 info.si_signo = TARGET_SIGSEGV;
2546 info.si_errno = 0;
2547 info.si_code = TARGET_SEGV_MAPERR;
2548 info._sifields._sigfault._addr = env->active_tc.PC;
2549 queue_signal(env, info.si_signo, &info);
2550 }
2551 break;
2552 case EXCP_DSPDIS:
2553 info.si_signo = TARGET_SIGILL;
2554 info.si_errno = 0;
2555 info.si_code = TARGET_ILL_ILLOPC;
2556 queue_signal(env, info.si_signo, &info);
2557 break;
2558 /* The code below was inspired by the MIPS Linux kernel trap
2559 * handling code in arch/mips/kernel/traps.c.
2560 */
2561 case EXCP_BREAK:
2562 {
2563 abi_ulong trap_instr;
2564 unsigned int code;
2565
2566 if (env->hflags & MIPS_HFLAG_M16) {
2567 if (env->insn_flags & ASE_MICROMIPS) {
2568 /* microMIPS mode */
2569 ret = get_user_u16(trap_instr, env->active_tc.PC);
2570 if (ret != 0) {
2571 goto error;
2572 }
2573
2574 if ((trap_instr >> 10) == 0x11) {
2575 /* 16-bit instruction */
2576 code = trap_instr & 0xf;
2577 } else {
2578 /* 32-bit instruction */
2579 abi_ulong instr_lo;
2580
2581 ret = get_user_u16(instr_lo,
2582 env->active_tc.PC + 2);
2583 if (ret != 0) {
2584 goto error;
2585 }
2586 trap_instr = (trap_instr << 16) | instr_lo;
2587 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2588 /* Unfortunately, microMIPS also suffers from
2589 the old assembler bug... */
2590 if (code >= (1 << 10)) {
2591 code >>= 10;
2592 }
2593 }
2594 } else {
2595 /* MIPS16e mode */
2596 ret = get_user_u16(trap_instr, env->active_tc.PC);
2597 if (ret != 0) {
2598 goto error;
2599 }
2600 code = (trap_instr >> 6) & 0x3f;
2601 }
2602 } else {
2603 ret = get_user_ual(trap_instr, env->active_tc.PC);
2604 if (ret != 0) {
2605 goto error;
2606 }
2607
2608 /* As described in the original Linux kernel code, the
2609 * below checks on 'code' are to work around an old
2610 * assembly bug.
2611 */
2612 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2613 if (code >= (1 << 10)) {
2614 code >>= 10;
2615 }
2616 }
2617
2618 if (do_break(env, &info, code) != 0) {
2619 goto error;
2620 }
2621 }
2622 break;
2623 case EXCP_TRAP:
2624 {
2625 abi_ulong trap_instr;
2626 unsigned int code = 0;
2627
2628 if (env->hflags & MIPS_HFLAG_M16) {
2629 /* microMIPS mode */
2630 abi_ulong instr[2];
2631
2632 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2633 get_user_u16(instr[1], env->active_tc.PC + 2);
2634
2635 trap_instr = (instr[0] << 16) | instr[1];
2636 } else {
2637 ret = get_user_ual(trap_instr, env->active_tc.PC);
2638 }
2639
2640 if (ret != 0) {
2641 goto error;
2642 }
2643
2644 /* The immediate versions don't provide a code. */
2645 if (!(trap_instr & 0xFC000000)) {
2646 if (env->hflags & MIPS_HFLAG_M16) {
2647 /* microMIPS mode */
2648 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2649 } else {
2650 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2651 }
2652 }
2653
2654 if (do_break(env, &info, code) != 0) {
2655 goto error;
2656 }
2657 }
2658 break;
2659 default:
2660 error:
2661 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2662 trapnr);
2663 cpu_dump_state(cs, stderr, fprintf, 0);
2664 abort();
2665 }
2666 process_pending_signals(env);
2667 }
2668 }
2669 #endif
2670
2671 #ifdef TARGET_OPENRISC
2672
2673 void cpu_loop(CPUOpenRISCState *env)
2674 {
2675 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2676 int trapnr, gdbsig;
2677
2678 for (;;) {
2679 trapnr = cpu_exec(env);
2680 gdbsig = 0;
2681
2682 switch (trapnr) {
2683 case EXCP_RESET:
2684 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2685 exit(1);
2686 break;
2687 case EXCP_BUSERR:
2688 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2689 gdbsig = SIGBUS;
2690 break;
2691 case EXCP_DPF:
2692 case EXCP_IPF:
2693 cpu_dump_state(cs, stderr, fprintf, 0);
2694 gdbsig = TARGET_SIGSEGV;
2695 break;
2696 case EXCP_TICK:
2697 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2698 break;
2699 case EXCP_ALIGN:
2700 qemu_log("\nAlignment pc is %#x\n", env->pc);
2701 gdbsig = SIGBUS;
2702 break;
2703 case EXCP_ILLEGAL:
2704 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2705 gdbsig = SIGILL;
2706 break;
2707 case EXCP_INT:
2708 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2709 break;
2710 case EXCP_DTLBMISS:
2711 case EXCP_ITLBMISS:
2712 qemu_log("\nTLB miss\n");
2713 break;
2714 case EXCP_RANGE:
2715 qemu_log("\nRange\n");
2716 gdbsig = SIGSEGV;
2717 break;
2718 case EXCP_SYSCALL:
2719 env->pc += 4; /* 0xc00; */
2720 env->gpr[11] = do_syscall(env,
2721 env->gpr[11], /* return value */
2722 env->gpr[3], /* r3 - r7 are params */
2723 env->gpr[4],
2724 env->gpr[5],
2725 env->gpr[6],
2726 env->gpr[7],
2727 env->gpr[8], 0, 0);
2728 break;
2729 case EXCP_FPE:
2730 qemu_log("\nFloating point error\n");
2731 break;
2732 case EXCP_TRAP:
2733 qemu_log("\nTrap\n");
2734 gdbsig = SIGTRAP;
2735 break;
2736 case EXCP_NR:
2737 qemu_log("\nNR\n");
2738 break;
2739 default:
2740 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2741 trapnr);
2742 cpu_dump_state(cs, stderr, fprintf, 0);
2743 gdbsig = TARGET_SIGILL;
2744 break;
2745 }
2746 if (gdbsig) {
2747 gdb_handlesig(cs, gdbsig);
2748 if (gdbsig != TARGET_SIGTRAP) {
2749 exit(1);
2750 }
2751 }
2752
2753 process_pending_signals(env);
2754 }
2755 }
2756
2757 #endif /* TARGET_OPENRISC */
2758
2759 #ifdef TARGET_SH4
2760 void cpu_loop(CPUSH4State *env)
2761 {
2762 CPUState *cs = CPU(sh_env_get_cpu(env));
2763 int trapnr, ret;
2764 target_siginfo_t info;
2765
2766 while (1) {
2767 trapnr = cpu_sh4_exec (env);
2768
2769 switch (trapnr) {
2770 case 0x160:
2771 env->pc += 2;
2772 ret = do_syscall(env,
2773 env->gregs[3],
2774 env->gregs[4],
2775 env->gregs[5],
2776 env->gregs[6],
2777 env->gregs[7],
2778 env->gregs[0],
2779 env->gregs[1],
2780 0, 0);
2781 env->gregs[0] = ret;
2782 break;
2783 case EXCP_INTERRUPT:
2784 /* just indicate that signals should be handled asap */
2785 break;
2786 case EXCP_DEBUG:
2787 {
2788 int sig;
2789
2790 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2791 if (sig)
2792 {
2793 info.si_signo = sig;
2794 info.si_errno = 0;
2795 info.si_code = TARGET_TRAP_BRKPT;
2796 queue_signal(env, info.si_signo, &info);
2797 }
2798 }
2799 break;
2800 case 0xa0:
2801 case 0xc0:
2802 info.si_signo = SIGSEGV;
2803 info.si_errno = 0;
2804 info.si_code = TARGET_SEGV_MAPERR;
2805 info._sifields._sigfault._addr = env->tea;
2806 queue_signal(env, info.si_signo, &info);
2807 break;
2808
2809 default:
2810 printf ("Unhandled trap: 0x%x\n", trapnr);
2811 cpu_dump_state(cs, stderr, fprintf, 0);
2812 exit (1);
2813 }
2814 process_pending_signals (env);
2815 }
2816 }
2817 #endif
2818
2819 #ifdef TARGET_CRIS
2820 void cpu_loop(CPUCRISState *env)
2821 {
2822 CPUState *cs = CPU(cris_env_get_cpu(env));
2823 int trapnr, ret;
2824 target_siginfo_t info;
2825
2826 while (1) {
2827 trapnr = cpu_cris_exec (env);
2828 switch (trapnr) {
2829 case 0xaa:
2830 {
2831 info.si_signo = SIGSEGV;
2832 info.si_errno = 0;
2833 /* XXX: check env->error_code */
2834 info.si_code = TARGET_SEGV_MAPERR;
2835 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2836 queue_signal(env, info.si_signo, &info);
2837 }
2838 break;
2839 case EXCP_INTERRUPT:
2840 /* just indicate that signals should be handled asap */
2841 break;
2842 case EXCP_BREAK:
2843 ret = do_syscall(env,
2844 env->regs[9],
2845 env->regs[10],
2846 env->regs[11],
2847 env->regs[12],
2848 env->regs[13],
2849 env->pregs[7],
2850 env->pregs[11],
2851 0, 0);
2852 env->regs[10] = ret;
2853 break;
2854 case EXCP_DEBUG:
2855 {
2856 int sig;
2857
2858 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2859 if (sig)
2860 {
2861 info.si_signo = sig;
2862 info.si_errno = 0;
2863 info.si_code = TARGET_TRAP_BRKPT;
2864 queue_signal(env, info.si_signo, &info);
2865 }
2866 }
2867 break;
2868 default:
2869 printf ("Unhandled trap: 0x%x\n", trapnr);
2870 cpu_dump_state(cs, stderr, fprintf, 0);
2871 exit (1);
2872 }
2873 process_pending_signals (env);
2874 }
2875 }
2876 #endif
2877
2878 #ifdef TARGET_MICROBLAZE
2879 void cpu_loop(CPUMBState *env)
2880 {
2881 CPUState *cs = CPU(mb_env_get_cpu(env));
2882 int trapnr, ret;
2883 target_siginfo_t info;
2884
2885 while (1) {
2886 trapnr = cpu_mb_exec (env);
2887 switch (trapnr) {
2888 case 0xaa:
2889 {
2890 info.si_signo = SIGSEGV;
2891 info.si_errno = 0;
2892 /* XXX: check env->error_code */
2893 info.si_code = TARGET_SEGV_MAPERR;
2894 info._sifields._sigfault._addr = 0;
2895 queue_signal(env, info.si_signo, &info);
2896 }
2897 break;
2898 case EXCP_INTERRUPT:
2899 /* just indicate that signals should be handled asap */
2900 break;
2901 case EXCP_BREAK:
2902 /* Return address is 4 bytes after the call. */
2903 env->regs[14] += 4;
2904 env->sregs[SR_PC] = env->regs[14];
2905 ret = do_syscall(env,
2906 env->regs[12],
2907 env->regs[5],
2908 env->regs[6],
2909 env->regs[7],
2910 env->regs[8],
2911 env->regs[9],
2912 env->regs[10],
2913 0, 0);
2914 env->regs[3] = ret;
2915 break;
2916 case EXCP_HW_EXCP:
2917 env->regs[17] = env->sregs[SR_PC] + 4;
2918 if (env->iflags & D_FLAG) {
2919 env->sregs[SR_ESR] |= 1 << 12;
2920 env->sregs[SR_PC] -= 4;
2921 /* FIXME: if branch was immed, replay the imm as well. */
2922 }
2923
2924 env->iflags &= ~(IMM_FLAG | D_FLAG);
2925
2926 switch (env->sregs[SR_ESR] & 31) {
2927 case ESR_EC_DIVZERO:
2928 info.si_signo = SIGFPE;
2929 info.si_errno = 0;
2930 info.si_code = TARGET_FPE_FLTDIV;
2931 info._sifields._sigfault._addr = 0;
2932 queue_signal(env, info.si_signo, &info);
2933 break;
2934 case ESR_EC_FPU:
2935 info.si_signo = SIGFPE;
2936 info.si_errno = 0;
2937 if (env->sregs[SR_FSR] & FSR_IO) {
2938 info.si_code = TARGET_FPE_FLTINV;
2939 }
2940 if (env->sregs[SR_FSR] & FSR_DZ) {
2941 info.si_code = TARGET_FPE_FLTDIV;
2942 }
2943 info._sifields._sigfault._addr = 0;
2944 queue_signal(env, info.si_signo, &info);
2945 break;
2946 default:
2947 printf ("Unhandled hw-exception: 0x%x\n",
2948 env->sregs[SR_ESR] & ESR_EC_MASK);
2949 cpu_dump_state(cs, stderr, fprintf, 0);
2950 exit (1);
2951 break;
2952 }
2953 break;
2954 case EXCP_DEBUG:
2955 {
2956 int sig;
2957
2958 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2959 if (sig)
2960 {
2961 info.si_signo = sig;
2962 info.si_errno = 0;
2963 info.si_code = TARGET_TRAP_BRKPT;
2964 queue_signal(env, info.si_signo, &info);
2965 }
2966 }
2967 break;
2968 default:
2969 printf ("Unhandled trap: 0x%x\n", trapnr);
2970 cpu_dump_state(cs, stderr, fprintf, 0);
2971 exit (1);
2972 }
2973 process_pending_signals (env);
2974 }
2975 }
2976 #endif
2977
2978 #ifdef TARGET_M68K
2979
2980 void cpu_loop(CPUM68KState *env)
2981 {
2982 CPUState *cs = CPU(m68k_env_get_cpu(env));
2983 int trapnr;
2984 unsigned int n;
2985 target_siginfo_t info;
2986 TaskState *ts = env->opaque;
2987
2988 for(;;) {
2989 trapnr = cpu_m68k_exec(env);
2990 switch(trapnr) {
2991 case EXCP_ILLEGAL:
2992 {
2993 if (ts->sim_syscalls) {
2994 uint16_t nr;
2995 nr = lduw(env->pc + 2);
2996 env->pc += 4;
2997 do_m68k_simcall(env, nr);
2998 } else {
2999 goto do_sigill;
3000 }
3001 }
3002 break;
3003 case EXCP_HALT_INSN:
3004 /* Semihosing syscall. */
3005 env->pc += 4;
3006 do_m68k_semihosting(env, env->dregs[0]);
3007 break;
3008 case EXCP_LINEA:
3009 case EXCP_LINEF:
3010 case EXCP_UNSUPPORTED:
3011 do_sigill:
3012 info.si_signo = SIGILL;
3013 info.si_errno = 0;
3014 info.si_code = TARGET_ILL_ILLOPN;
3015 info._sifields._sigfault._addr = env->pc;
3016 queue_signal(env, info.si_signo, &info);
3017 break;
3018 case EXCP_TRAP0:
3019 {
3020 ts->sim_syscalls = 0;
3021 n = env->dregs[0];
3022 env->pc += 2;
3023 env->dregs[0] = do_syscall(env,
3024 n,
3025 env->dregs[1],
3026 env->dregs[2],
3027 env->dregs[3],
3028 env->dregs[4],
3029 env->dregs[5],
3030 env->aregs[0],
3031 0, 0);
3032 }
3033 break;
3034 case EXCP_INTERRUPT:
3035 /* just indicate that signals should be handled asap */
3036 break;
3037 case EXCP_ACCESS:
3038 {
3039 info.si_signo = SIGSEGV;
3040 info.si_errno = 0;
3041 /* XXX: check env->error_code */
3042 info.si_code = TARGET_SEGV_MAPERR;
3043 info._sifields._sigfault._addr = env->mmu.ar;
3044 queue_signal(env, info.si_signo, &info);
3045 }
3046 break;
3047 case EXCP_DEBUG:
3048 {
3049 int sig;
3050
3051 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3052 if (sig)
3053 {
3054 info.si_signo = sig;
3055 info.si_errno = 0;
3056 info.si_code = TARGET_TRAP_BRKPT;
3057 queue_signal(env, info.si_signo, &info);
3058 }
3059 }
3060 break;
3061 default:
3062 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
3063 trapnr);
3064 cpu_dump_state(cs, stderr, fprintf, 0);
3065 abort();
3066 }
3067 process_pending_signals(env);
3068 }
3069 }
3070 #endif /* TARGET_M68K */
3071
3072 #ifdef TARGET_ALPHA
3073 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3074 {
3075 target_ulong addr, val, tmp;
3076 target_siginfo_t info;
3077 int ret = 0;
3078
3079 addr = env->lock_addr;
3080 tmp = env->lock_st_addr;
3081 env->lock_addr = -1;
3082 env->lock_st_addr = 0;
3083
3084 start_exclusive();
3085 mmap_lock();
3086
3087 if (addr == tmp) {
3088 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3089 goto do_sigsegv;
3090 }
3091
3092 if (val == env->lock_value) {
3093 tmp = env->ir[reg];
3094 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3095 goto do_sigsegv;
3096 }
3097 ret = 1;
3098 }
3099 }
3100 env->ir[reg] = ret;
3101 env->pc += 4;
3102
3103 mmap_unlock();
3104 end_exclusive();
3105 return;
3106
3107 do_sigsegv:
3108 mmap_unlock();
3109 end_exclusive();
3110
3111 info.si_signo = TARGET_SIGSEGV;
3112 info.si_errno = 0;
3113 info.si_code = TARGET_SEGV_MAPERR;
3114 info._sifields._sigfault._addr = addr;
3115 queue_signal(env, TARGET_SIGSEGV, &info);
3116 }
3117
3118 void cpu_loop(CPUAlphaState *env)
3119 {
3120 CPUState *cs = CPU(alpha_env_get_cpu(env));
3121 int trapnr;
3122 target_siginfo_t info;
3123 abi_long sysret;
3124
3125 while (1) {
3126 trapnr = cpu_alpha_exec (env);
3127
3128 /* All of the traps imply a transition through PALcode, which
3129 implies an REI instruction has been executed. Which means
3130 that the intr_flag should be cleared. */
3131 env->intr_flag = 0;
3132
3133 switch (trapnr) {
3134 case EXCP_RESET:
3135 fprintf(stderr, "Reset requested. Exit\n");
3136 exit(1);
3137 break;
3138 case EXCP_MCHK:
3139 fprintf(stderr, "Machine check exception. Exit\n");
3140 exit(1);
3141 break;
3142 case EXCP_SMP_INTERRUPT:
3143 case EXCP_CLK_INTERRUPT:
3144 case EXCP_DEV_INTERRUPT:
3145 fprintf(stderr, "External interrupt. Exit\n");
3146 exit(1);
3147 break;
3148 case EXCP_MMFAULT:
3149 env->lock_addr = -1;
3150 info.si_signo = TARGET_SIGSEGV;
3151 info.si_errno = 0;
3152 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3153 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3154 info._sifields._sigfault._addr = env->trap_arg0;
3155 queue_signal(env, info.si_signo, &info);
3156 break;
3157 case EXCP_UNALIGN:
3158 env->lock_addr = -1;
3159 info.si_signo = TARGET_SIGBUS;
3160 info.si_errno = 0;
3161 info.si_code = TARGET_BUS_ADRALN;
3162 info._sifields._sigfault._addr = env->trap_arg0;
3163 queue_signal(env, info.si_signo, &info);
3164 break;
3165 case EXCP_OPCDEC:
3166 do_sigill:
3167 env->lock_addr = -1;
3168 info.si_signo = TARGET_SIGILL;
3169 info.si_errno = 0;
3170 info.si_code = TARGET_ILL_ILLOPC;
3171 info._sifields._sigfault._addr = env->pc;
3172 queue_signal(env, info.si_signo, &info);
3173 break;
3174 case EXCP_ARITH:
3175 env->lock_addr = -1;
3176 info.si_signo = TARGET_SIGFPE;
3177 info.si_errno = 0;
3178 info.si_code = TARGET_FPE_FLTINV;
3179 info._sifields._sigfault._addr = env->pc;
3180 queue_signal(env, info.si_signo, &info);
3181 break;
3182 case EXCP_FEN:
3183 /* No-op. Linux simply re-enables the FPU. */
3184 break;
3185 case EXCP_CALL_PAL:
3186 env->lock_addr = -1;
3187 switch (env->error_code) {
3188 case 0x80:
3189 /* BPT */
3190 info.si_signo = TARGET_SIGTRAP;
3191 info.si_errno = 0;
3192 info.si_code = TARGET_TRAP_BRKPT;
3193 info._sifields._sigfault._addr = env->pc;
3194 queue_signal(env, info.si_signo, &info);
3195 break;
3196 case 0x81:
3197 /* BUGCHK */
3198 info.si_signo = TARGET_SIGTRAP;
3199 info.si_errno = 0;
3200 info.si_code = 0;
3201 info._sifields._sigfault._addr = env->pc;
3202 queue_signal(env, info.si_signo, &info);
3203 break;
3204 case 0x83:
3205 /* CALLSYS */
3206 trapnr = env->ir[IR_V0];
3207 sysret = do_syscall(env, trapnr,
3208 env->ir[IR_A0], env->ir[IR_A1],
3209 env->ir[IR_A2], env->ir[IR_A3],
3210 env->ir[IR_A4], env->ir[IR_A5],
3211 0, 0);
3212 if (trapnr == TARGET_NR_sigreturn
3213 || trapnr == TARGET_NR_rt_sigreturn) {
3214 break;
3215 }
3216 /* Syscall writes 0 to V0 to bypass error check, similar
3217 to how this is handled internal to Linux kernel.
3218 (Ab)use trapnr temporarily as boolean indicating error. */
3219 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3220 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3221 env->ir[IR_A3] = trapnr;
3222 break;
3223 case 0x86:
3224 /* IMB */
3225 /* ??? We can probably elide the code using page_unprotect
3226 that is checking for self-modifying code. Instead we
3227 could simply call tb_flush here. Until we work out the
3228 changes required to turn off the extra write protection,
3229 this can be a no-op. */
3230 break;
3231 case 0x9E:
3232 /* RDUNIQUE */
3233 /* Handled in the translator for usermode. */
3234 abort();
3235 case 0x9F:
3236 /* WRUNIQUE */
3237 /* Handled in the translator for usermode. */
3238 abort();
3239 case 0xAA:
3240 /* GENTRAP */
3241 info.si_signo = TARGET_SIGFPE;
3242 switch (env->ir[IR_A0]) {
3243 case TARGET_GEN_INTOVF:
3244 info.si_code = TARGET_FPE_INTOVF;
3245 break;
3246 case TARGET_GEN_INTDIV:
3247 info.si_code = TARGET_FPE_INTDIV;
3248 break;
3249 case TARGET_GEN_FLTOVF:
3250 info.si_code = TARGET_FPE_FLTOVF;
3251 break;
3252 case TARGET_GEN_FLTUND:
3253 info.si_code = TARGET_FPE_FLTUND;
3254 break;
3255 case TARGET_GEN_FLTINV:
3256 info.si_code = TARGET_FPE_FLTINV;
3257 break;
3258 case TARGET_GEN_FLTINE:
3259 info.si_code = TARGET_FPE_FLTRES;
3260 break;
3261 case TARGET_GEN_ROPRAND:
3262 info.si_code = 0;
3263 break;
3264 default:
3265 info.si_signo = TARGET_SIGTRAP;
3266 info.si_code = 0;
3267 break;
3268 }
3269 info.si_errno = 0;
3270 info._sifields._sigfault._addr = env->pc;
3271 queue_signal(env, info.si_signo, &info);
3272 break;
3273 default:
3274 goto do_sigill;
3275 }
3276 break;
3277 case EXCP_DEBUG:
3278 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3279 if (info.si_signo) {
3280 env->lock_addr = -1;
3281 info.si_errno = 0;
3282 info.si_code = TARGET_TRAP_BRKPT;
3283 queue_signal(env, info.si_signo, &info);
3284 }
3285 break;
3286 case EXCP_STL_C:
3287 case EXCP_STQ_C:
3288 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3289 break;
3290 case EXCP_INTERRUPT:
3291 /* Just indicate that signals should be handled asap. */
3292 break;
3293 default:
3294 printf ("Unhandled trap: 0x%x\n", trapnr);
3295 cpu_dump_state(cs, stderr, fprintf, 0);
3296 exit (1);
3297 }
3298 process_pending_signals (env);
3299 }
3300 }
3301 #endif /* TARGET_ALPHA */
3302
3303 #ifdef TARGET_S390X
3304 void cpu_loop(CPUS390XState *env)
3305 {
3306 CPUState *cs = CPU(s390_env_get_cpu(env));
3307 int trapnr, n, sig;
3308 target_siginfo_t info;
3309 target_ulong addr;
3310
3311 while (1) {
3312 trapnr = cpu_s390x_exec(env);
3313 switch (trapnr) {
3314 case EXCP_INTERRUPT:
3315 /* Just indicate that signals should be handled asap. */
3316 break;
3317
3318 case EXCP_SVC:
3319 n = env->int_svc_code;
3320 if (!n) {
3321 /* syscalls > 255 */
3322 n = env->regs[1];
3323 }
3324 env->psw.addr += env->int_svc_ilen;
3325 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3326 env->regs[4], env->regs[5],
3327 env->regs[6], env->regs[7], 0, 0);
3328 break;
3329
3330 case EXCP_DEBUG:
3331 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3332 if (sig) {
3333 n = TARGET_TRAP_BRKPT;
3334 goto do_signal_pc;
3335 }
3336 break;
3337 case EXCP_PGM:
3338 n = env->int_pgm_code;
3339 switch (n) {
3340 case PGM_OPERATION:
3341 case PGM_PRIVILEGED:
3342 sig = SIGILL;
3343 n = TARGET_ILL_ILLOPC;
3344 goto do_signal_pc;
3345 case PGM_PROTECTION:
3346 case PGM_ADDRESSING:
3347 sig = SIGSEGV;
3348 /* XXX: check env->error_code */
3349 n = TARGET_SEGV_MAPERR;
3350 addr = env->__excp_addr;
3351 goto do_signal;
3352 case PGM_EXECUTE:
3353 case PGM_SPECIFICATION:
3354 case PGM_SPECIAL_OP:
3355 case PGM_OPERAND:
3356 do_sigill_opn:
3357 sig = SIGILL;
3358 n = TARGET_ILL_ILLOPN;
3359 goto do_signal_pc;
3360
3361 case PGM_FIXPT_OVERFLOW:
3362 sig = SIGFPE;
3363 n = TARGET_FPE_INTOVF;
3364 goto do_signal_pc;
3365 case PGM_FIXPT_DIVIDE:
3366 sig = SIGFPE;
3367 n = TARGET_FPE_INTDIV;
3368 goto do_signal_pc;
3369
3370 case PGM_DATA:
3371 n = (env->fpc >> 8) & 0xff;
3372 if (n == 0xff) {
3373 /* compare-and-trap */
3374 goto do_sigill_opn;
3375 } else {
3376 /* An IEEE exception, simulated or otherwise. */
3377 if (n & 0x80) {
3378 n = TARGET_FPE_FLTINV;
3379 } else if (n & 0x40) {
3380 n = TARGET_FPE_FLTDIV;
3381 } else if (n & 0x20) {
3382 n = TARGET_FPE_FLTOVF;
3383 } else if (n & 0x10) {
3384 n = TARGET_FPE_FLTUND;
3385 } else if (n & 0x08) {
3386 n = TARGET_FPE_FLTRES;
3387 } else {
3388 /* ??? Quantum exception; BFP, DFP error. */
3389 goto do_sigill_opn;
3390 }
3391 sig = SIGFPE;
3392 goto do_signal_pc;
3393 }
3394
3395 default:
3396 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3397 cpu_dump_state(cs, stderr, fprintf, 0);
3398 exit(1);
3399 }
3400 break;
3401
3402 do_signal_pc:
3403 addr = env->psw.addr;
3404 do_signal:
3405 info.si_signo = sig;
3406 info.si_errno = 0;
3407 info.si_code = n;
3408 info._sifields._sigfault._addr = addr;
3409 queue_signal(env, info.si_signo, &info);
3410 break;
3411
3412 default:
3413 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3414 cpu_dump_state(cs, stderr, fprintf, 0);
3415 exit(1);
3416 }
3417 process_pending_signals (env);
3418 }
3419 }
3420
3421 #endif /* TARGET_S390X */
3422
3423 THREAD CPUState *thread_cpu;
3424
3425 void task_settid(TaskState *ts)
3426 {
3427 if (ts->ts_tid == 0) {
3428 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3429 }
3430 }
3431
3432 void stop_all_tasks(void)
3433 {
3434 /*
3435 * We trust that when using NPTL, start_exclusive()
3436 * handles thread stopping correctly.
3437 */
3438 start_exclusive();
3439 }
3440
3441 /* Assumes contents are already zeroed. */
3442 void init_task_state(TaskState *ts)
3443 {
3444 int i;
3445
3446 ts->used = 1;
3447 ts->first_free = ts->sigqueue_table;
3448 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3449 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3450 }
3451 ts->sigqueue_table[i].next = NULL;
3452 }
3453
3454 CPUArchState *cpu_copy(CPUArchState *env)
3455 {
3456 CPUArchState *new_env = cpu_init(cpu_model);
3457 #if defined(TARGET_HAS_ICE)
3458 CPUBreakpoint *bp;
3459 CPUWatchpoint *wp;
3460 #endif
3461
3462 /* Reset non arch specific state */
3463 cpu_reset(ENV_GET_CPU(new_env));
3464
3465 memcpy(new_env, env, sizeof(CPUArchState));
3466
3467 /* Clone all break/watchpoints.
3468 Note: Once we support ptrace with hw-debug register access, make sure
3469 BP_CPU break/watchpoints are handled correctly on clone. */
3470 QTAILQ_INIT(&env->breakpoints);
3471 QTAILQ_INIT(&env->watchpoints);
3472 #if defined(TARGET_HAS_ICE)
3473 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
3474 cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
3475 }
3476 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
3477 cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
3478 wp->flags, NULL);
3479 }
3480 #endif
3481
3482 return new_env;
3483 }
3484
3485 static void handle_arg_help(const char *arg)
3486 {
3487 usage();
3488 }
3489
3490 static void handle_arg_log(const char *arg)
3491 {
3492 int mask;
3493
3494 mask = qemu_str_to_log_mask(arg);
3495 if (!mask) {
3496 qemu_print_log_usage(stdout);
3497 exit(1);
3498 }
3499 qemu_set_log(mask);
3500 }
3501
3502 static void handle_arg_log_filename(const char *arg)
3503 {
3504 qemu_set_log_filename(arg);
3505 }
3506
3507 static void handle_arg_set_env(const char *arg)
3508 {
3509 char *r, *p, *token;
3510 r = p = strdup(arg);
3511 while ((token = strsep(&p, ",")) != NULL) {
3512 if (envlist_setenv(envlist, token) != 0) {
3513 usage();
3514 }
3515 }
3516 free(r);
3517 }
3518
3519 static void handle_arg_unset_env(const char *arg)
3520 {
3521 char *r, *p, *token;
3522 r = p = strdup(arg);
3523 while ((token = strsep(&p, ",")) != NULL) {
3524 if (envlist_unsetenv(envlist, token) != 0) {
3525 usage();
3526 }
3527 }
3528 free(r);
3529 }
3530
3531 static void handle_arg_argv0(const char *arg)
3532 {
3533 argv0 = strdup(arg);
3534 }
3535
3536 static void handle_arg_stack_size(const char *arg)
3537 {
3538 char *p;
3539 guest_stack_size = strtoul(arg, &p, 0);
3540 if (guest_stack_size == 0) {
3541 usage();
3542 }
3543
3544 if (*p == 'M') {
3545 guest_stack_size *= 1024 * 1024;
3546 } else if (*p == 'k' || *p == 'K') {
3547 guest_stack_size *= 1024;
3548 }
3549 }
3550
3551 static void handle_arg_ld_prefix(const char *arg)
3552 {
3553 interp_prefix = strdup(arg);
3554 }
3555
3556 static void handle_arg_pagesize(const char *arg)
3557 {
3558 qemu_host_page_size = atoi(arg);
3559 if (qemu_host_page_size == 0 ||
3560 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3561 fprintf(stderr, "page size must be a power of two\n");
3562 exit(1);
3563 }
3564 }
3565
3566 static void handle_arg_gdb(const char *arg)
3567 {
3568 gdbstub_port = atoi(arg);
3569 }
3570
3571 static void handle_arg_uname(const char *arg)
3572 {
3573 qemu_uname_release = strdup(arg);
3574 }
3575
3576 static void handle_arg_cpu(const char *arg)
3577 {
3578 cpu_model = strdup(arg);
3579 if (cpu_model == NULL || is_help_option(cpu_model)) {
3580 /* XXX: implement xxx_cpu_list for targets that still miss it */
3581 #if defined(cpu_list_id)
3582 cpu_list_id(stdout, &fprintf, "");
3583 #elif defined(cpu_list)
3584 cpu_list(stdout, &fprintf); /* deprecated */
3585 #else
3586 /* TODO: add cpu selection for alpha, microblaze, unicore32, s390x. */
3587 printf("Target ignores cpu selection\n");
3588 #endif
3589 exit(1);
3590 }
3591 }
3592
3593 #if defined(CONFIG_USE_GUEST_BASE)
3594 static void handle_arg_guest_base(const char *arg)
3595 {
3596 guest_base = strtol(arg, NULL, 0);
3597 have_guest_base = 1;
3598 }
3599
3600 static void handle_arg_reserved_va(const char *arg)
3601 {
3602 char *p;
3603 int shift = 0;
3604 reserved_va = strtoul(arg, &p, 0);
3605 switch (*p) {
3606 case 'k':
3607 case 'K':
3608 shift = 10;
3609 break;
3610 case 'M':
3611 shift = 20;
3612 break;
3613 case 'G':
3614 shift = 30;
3615 break;
3616 }
3617 if (shift) {
3618 unsigned long unshifted = reserved_va;
3619 p++;
3620 reserved_va <<= shift;
3621 if (((reserved_va >> shift) != unshifted)
3622 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3623 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3624 #endif
3625 ) {
3626 fprintf(stderr, "Reserved virtual address too big\n");
3627 exit(1);
3628 }
3629 }
3630 if (*p) {
3631 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3632 exit(1);
3633 }
3634 }
3635 #endif
3636
3637 static void handle_arg_singlestep(const char *arg)
3638 {
3639 singlestep = 1;
3640 }
3641
3642 static void handle_arg_strace(const char *arg)
3643 {
3644 do_strace = 1;
3645 }
3646
3647 static void handle_arg_version(const char *arg)
3648 {
3649 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3650 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3651 exit(0);
3652 }
3653
3654 struct qemu_argument {
3655 const char *argv;
3656 const char *env;
3657 bool has_arg;
3658 void (*handle_opt)(const char *arg);
3659 const char *example;
3660 const char *help;
3661 };
3662
3663 static const struct qemu_argument arg_table[] = {
3664 {"h", "", false, handle_arg_help,
3665 "", "print this help"},
3666 {"g", "QEMU_GDB", true, handle_arg_gdb,
3667 "port", "wait gdb connection to 'port'"},
3668 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3669 "path", "set the elf interpreter prefix to 'path'"},
3670 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3671 "size", "set the stack size to 'size' bytes"},
3672 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3673 "model", "select CPU (-cpu help for list)"},
3674 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3675 "var=value", "sets targets environment variable (see below)"},
3676 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3677 "var", "unsets targets environment variable (see below)"},
3678 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3679 "argv0", "forces target process argv[0] to be 'argv0'"},
3680 {"r", "QEMU_UNAME", true, handle_arg_uname,
3681 "uname", "set qemu uname release string to 'uname'"},
3682 #if defined(CONFIG_USE_GUEST_BASE)
3683 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3684 "address", "set guest_base address to 'address'"},
3685 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3686 "size", "reserve 'size' bytes for guest virtual address space"},
3687 #endif
3688 {"d", "QEMU_LOG", true, handle_arg_log,
3689 "item[,...]", "enable logging of specified items "
3690 "(use '-d help' for a list of items)"},
3691 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3692 "logfile", "write logs to 'logfile' (default stderr)"},
3693 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3694 "pagesize", "set the host page size to 'pagesize'"},
3695 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3696 "", "run in singlestep mode"},
3697 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3698 "", "log system calls"},
3699 {"version", "QEMU_VERSION", false, handle_arg_version,
3700 "", "display version information and exit"},
3701 {NULL, NULL, false, NULL, NULL, NULL}
3702 };
3703
3704 static void QEMU_NORETURN usage(void)
3705 {
3706 const struct qemu_argument *arginfo;
3707 int maxarglen;
3708 int maxenvlen;
3709
3710 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3711 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3712 "\n"
3713 "Options and associated environment variables:\n"
3714 "\n");
3715
3716 /* Calculate column widths. We must always have at least enough space
3717 * for the column header.
3718 */
3719 maxarglen = strlen("Argument");
3720 maxenvlen = strlen("Env-variable");
3721
3722 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3723 int arglen = strlen(arginfo->argv);
3724 if (arginfo->has_arg) {
3725 arglen += strlen(arginfo->example) + 1;
3726 }
3727 if (strlen(arginfo->env) > maxenvlen) {
3728 maxenvlen = strlen(arginfo->env);
3729 }
3730 if (arglen > maxarglen) {
3731 maxarglen = arglen;
3732 }
3733 }
3734
3735 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3736 maxenvlen, "Env-variable");
3737
3738 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3739 if (arginfo->has_arg) {
3740 printf("-%s %-*s %-*s %s\n", arginfo->argv,
3741 (int)(maxarglen - strlen(arginfo->argv) - 1),
3742 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
3743 } else {
3744 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
3745 maxenvlen, arginfo->env,
3746 arginfo->help);
3747 }
3748 }
3749
3750 printf("\n"
3751 "Defaults:\n"
3752 "QEMU_LD_PREFIX = %s\n"
3753 "QEMU_STACK_SIZE = %ld byte\n",
3754 interp_prefix,
3755 guest_stack_size);
3756
3757 printf("\n"
3758 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3759 "QEMU_UNSET_ENV environment variables to set and unset\n"
3760 "environment variables for the target process.\n"
3761 "It is possible to provide several variables by separating them\n"
3762 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3763 "provide the -E and -U options multiple times.\n"
3764 "The following lines are equivalent:\n"
3765 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3766 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3767 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3768 "Note that if you provide several changes to a single variable\n"
3769 "the last change will stay in effect.\n");
3770
3771 exit(1);
3772 }
3773
3774 static int parse_args(int argc, char **argv)
3775 {
3776 const char *r;
3777 int optind;
3778 const struct qemu_argument *arginfo;
3779
3780 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3781 if (arginfo->env == NULL) {
3782 continue;
3783 }
3784
3785 r = getenv(arginfo->env);
3786 if (r != NULL) {
3787 arginfo->handle_opt(r);
3788 }
3789 }
3790
3791 optind = 1;
3792 for (;;) {
3793 if (optind >= argc) {
3794 break;
3795 }
3796 r = argv[optind];
3797 if (r[0] != '-') {
3798 break;
3799 }
3800 optind++;
3801 r++;
3802 if (!strcmp(r, "-")) {
3803 break;
3804 }
3805
3806 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3807 if (!strcmp(r, arginfo->argv)) {
3808 if (arginfo->has_arg) {
3809 if (optind >= argc) {
3810 usage();
3811 }
3812 arginfo->handle_opt(argv[optind]);
3813 optind++;
3814 } else {
3815 arginfo->handle_opt(NULL);
3816 }
3817 break;
3818 }
3819 }
3820
3821 /* no option matched the current argv */
3822 if (arginfo->handle_opt == NULL) {
3823 usage();
3824 }
3825 }
3826
3827 if (optind >= argc) {
3828 usage();
3829 }
3830
3831 filename = argv[optind];
3832 exec_path = argv[optind];
3833
3834 return optind;
3835 }
3836
3837 int main(int argc, char **argv)
3838 {
3839 struct target_pt_regs regs1, *regs = &regs1;
3840 struct image_info info1, *info = &info1;
3841 struct linux_binprm bprm;
3842 TaskState *ts;
3843 CPUArchState *env;
3844 CPUState *cpu;
3845 int optind;
3846 char **target_environ, **wrk;
3847 char **target_argv;
3848 int target_argc;
3849 int i;
3850 int ret;
3851 int execfd;
3852
3853 module_call_init(MODULE_INIT_QOM);
3854
3855 qemu_cache_utils_init();
3856
3857 if ((envlist = envlist_create()) == NULL) {
3858 (void) fprintf(stderr, "Unable to allocate envlist\n");
3859 exit(1);
3860 }
3861
3862 /* add current environment into the list */
3863 for (wrk = environ; *wrk != NULL; wrk++) {
3864 (void) envlist_setenv(envlist, *wrk);
3865 }
3866
3867 /* Read the stack limit from the kernel. If it's "unlimited",
3868 then we can do little else besides use the default. */
3869 {
3870 struct rlimit lim;
3871 if (getrlimit(RLIMIT_STACK, &lim) == 0
3872 && lim.rlim_cur != RLIM_INFINITY
3873 && lim.rlim_cur == (target_long)lim.rlim_cur) {
3874 guest_stack_size = lim.rlim_cur;
3875 }
3876 }
3877
3878 cpu_model = NULL;
3879 #if defined(cpudef_setup)
3880 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3881 #endif
3882
3883 optind = parse_args(argc, argv);
3884
3885 /* Zero out regs */
3886 memset(regs, 0, sizeof(struct target_pt_regs));
3887
3888 /* Zero out image_info */
3889 memset(info, 0, sizeof(struct image_info));
3890
3891 memset(&bprm, 0, sizeof (bprm));
3892
3893 /* Scan interp_prefix dir for replacement files. */
3894 init_paths(interp_prefix);
3895
3896 init_qemu_uname_release();
3897
3898 if (cpu_model == NULL) {
3899 #if defined(TARGET_I386)
3900 #ifdef TARGET_X86_64
3901 cpu_model = "qemu64";
3902 #else
3903 cpu_model = "qemu32";
3904 #endif
3905 #elif defined(TARGET_ARM)
3906 cpu_model = "any";
3907 #elif defined(TARGET_UNICORE32)
3908 cpu_model = "any";
3909 #elif defined(TARGET_M68K)
3910 cpu_model = "any";
3911 #elif defined(TARGET_SPARC)
3912 #ifdef TARGET_SPARC64
3913 cpu_model = "TI UltraSparc II";
3914 #else
3915 cpu_model = "Fujitsu MB86904";
3916 #endif
3917 #elif defined(TARGET_MIPS)
3918 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3919 cpu_model = "20Kc";
3920 #else
3921 cpu_model = "24Kf";
3922 #endif
3923 #elif defined TARGET_OPENRISC
3924 cpu_model = "or1200";
3925 #elif defined(TARGET_PPC)
3926 #ifdef TARGET_PPC64
3927 cpu_model = "970fx";
3928 #else
3929 cpu_model = "750";
3930 #endif
3931 #else
3932 cpu_model = "any";
3933 #endif
3934 }
3935 tcg_exec_init(0);
3936 cpu_exec_init_all();
3937 /* NOTE: we need to init the CPU at this stage to get
3938 qemu_host_page_size */
3939 env = cpu_init(cpu_model);
3940 if (!env) {
3941 fprintf(stderr, "Unable to find CPU definition\n");
3942 exit(1);
3943 }
3944 cpu = ENV_GET_CPU(env);
3945 cpu_reset(cpu);
3946
3947 thread_cpu = cpu;
3948
3949 if (getenv("QEMU_STRACE")) {
3950 do_strace = 1;
3951 }
3952
3953 target_environ = envlist_to_environ(envlist, NULL);
3954 envlist_free(envlist);
3955
3956 #if defined(CONFIG_USE_GUEST_BASE)
3957 /*
3958 * Now that page sizes are configured in cpu_init() we can do
3959 * proper page alignment for guest_base.
3960 */
3961 guest_base = HOST_PAGE_ALIGN(guest_base);
3962
3963 if (reserved_va || have_guest_base) {
3964 guest_base = init_guest_space(guest_base, reserved_va, 0,
3965 have_guest_base);
3966 if (guest_base == (unsigned long)-1) {
3967 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3968 "space for use as guest address space (check your virtual "
3969 "memory ulimit setting or reserve less using -R option)\n",
3970 reserved_va);
3971 exit(1);
3972 }
3973
3974 if (reserved_va) {
3975 mmap_next_start = reserved_va;
3976 }
3977 }
3978 #endif /* CONFIG_USE_GUEST_BASE */
3979
3980 /*
3981 * Read in mmap_min_addr kernel parameter. This value is used
3982 * When loading the ELF image to determine whether guest_base
3983 * is needed. It is also used in mmap_find_vma.
3984 */
3985 {
3986 FILE *fp;
3987
3988 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3989 unsigned long tmp;
3990 if (fscanf(fp, "%lu", &tmp) == 1) {
3991 mmap_min_addr = tmp;
3992 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3993 }
3994 fclose(fp);
3995 }
3996 }
3997
3998 /*
3999 * Prepare copy of argv vector for target.
4000 */
4001 target_argc = argc - optind;
4002 target_argv = calloc(target_argc + 1, sizeof (char *));
4003 if (target_argv == NULL) {
4004 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4005 exit(1);
4006 }
4007
4008 /*
4009 * If argv0 is specified (using '-0' switch) we replace
4010 * argv[0] pointer with the given one.
4011 */
4012 i = 0;
4013 if (argv0 != NULL) {
4014 target_argv[i++] = strdup(argv0);
4015 }
4016 for (; i < target_argc; i++) {
4017 target_argv[i] = strdup(argv[optind + i]);
4018 }
4019 target_argv[target_argc] = NULL;
4020
4021 ts = g_malloc0 (sizeof(TaskState));
4022 init_task_state(ts);
4023 /* build Task State */
4024 ts->info = info;
4025 ts->bprm = &bprm;
4026 env->opaque = ts;
4027 task_settid(ts);
4028
4029 execfd = qemu_getauxval(AT_EXECFD);
4030 if (execfd == 0) {
4031 execfd = open(filename, O_RDONLY);
4032 if (execfd < 0) {
4033 printf("Error while loading %s: %s\n", filename, strerror(errno));
4034 _exit(1);
4035 }
4036 }
4037
4038 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4039 info, &bprm);
4040 if (ret != 0) {
4041 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4042 _exit(1);
4043 }
4044
4045 for (wrk = target_environ; *wrk; wrk++) {
4046 free(*wrk);
4047 }
4048
4049 free(target_environ);
4050
4051 if (qemu_log_enabled()) {
4052 #if defined(CONFIG_USE_GUEST_BASE)
4053 qemu_log("guest_base 0x%" PRIxPTR "\n", guest_base);
4054 #endif
4055 log_page_dump();
4056
4057 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4058 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4059 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4060 info->start_code);
4061 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4062 info->start_data);
4063 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4064 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4065 info->start_stack);
4066 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4067 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4068 }
4069
4070 target_set_brk(info->brk);
4071 syscall_init();
4072 signal_init();
4073
4074 #if defined(CONFIG_USE_GUEST_BASE)
4075 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4076 generating the prologue until now so that the prologue can take
4077 the real value of GUEST_BASE into account. */
4078 tcg_prologue_init(&tcg_ctx);
4079 #endif
4080
4081 #if defined(TARGET_I386)
4082 cpu_x86_set_cpl(env, 3);
4083
4084 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4085 env->hflags |= HF_PE_MASK;
4086 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4087 env->cr[4] |= CR4_OSFXSR_MASK;
4088 env->hflags |= HF_OSFXSR_MASK;
4089 }
4090 #ifndef TARGET_ABI32
4091 /* enable 64 bit mode if possible */
4092 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4093 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4094 exit(1);
4095 }
4096 env->cr[4] |= CR4_PAE_MASK;
4097 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4098 env->hflags |= HF_LMA_MASK;
4099 #endif
4100
4101 /* flags setup : we activate the IRQs by default as in user mode */
4102 env->eflags |= IF_MASK;
4103
4104 /* linux register setup */
4105 #ifndef TARGET_ABI32
4106 env->regs[R_EAX] = regs->rax;
4107 env->regs[R_EBX] = regs->rbx;
4108 env->regs[R_ECX] = regs->rcx;
4109 env->regs[R_EDX] = regs->rdx;
4110 env->regs[R_ESI] = regs->rsi;
4111 env->regs[R_EDI] = regs->rdi;
4112 env->regs[R_EBP] = regs->rbp;
4113 env->regs[R_ESP] = regs->rsp;
4114 env->eip = regs->rip;
4115 #else
4116 env->regs[R_EAX] = regs->eax;
4117 env->regs[R_EBX] = regs->ebx;
4118 env->regs[R_ECX] = regs->ecx;
4119 env->regs[R_EDX] = regs->edx;
4120 env->regs[R_ESI] = regs->esi;
4121 env->regs[R_EDI] = regs->edi;
4122 env->regs[R_EBP] = regs->ebp;
4123 env->regs[R_ESP] = regs->esp;
4124 env->eip = regs->eip;
4125 #endif
4126
4127 /* linux interrupt setup */
4128 #ifndef TARGET_ABI32
4129 env->idt.limit = 511;
4130 #else
4131 env->idt.limit = 255;
4132 #endif
4133 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4134 PROT_READ|PROT_WRITE,
4135 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4136 idt_table = g2h(env->idt.base);
4137 set_idt(0, 0);
4138 set_idt(1, 0);
4139 set_idt(2, 0);
4140 set_idt(3, 3);
4141 set_idt(4, 3);
4142 set_idt(5, 0);
4143 set_idt(6, 0);
4144 set_idt(7, 0);
4145 set_idt(8, 0);
4146 set_idt(9, 0);
4147 set_idt(10, 0);
4148 set_idt(11, 0);
4149 set_idt(12, 0);
4150 set_idt(13, 0);
4151 set_idt(14, 0);
4152 set_idt(15, 0);
4153 set_idt(16, 0);
4154 set_idt(17, 0);
4155 set_idt(18, 0);
4156 set_idt(19, 0);
4157 set_idt(0x80, 3);
4158
4159 /* linux segment setup */
4160 {
4161 uint64_t *gdt_table;
4162 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4163 PROT_READ|PROT_WRITE,
4164 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4165 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4166 gdt_table = g2h(env->gdt.base);
4167 #ifdef TARGET_ABI32
4168 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4169 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4170 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4171 #else
4172 /* 64 bit code segment */
4173 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4174 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4175 DESC_L_MASK |
4176 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4177 #endif
4178 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4179 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4180 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4181 }
4182 cpu_x86_load_seg(env, R_CS, __USER_CS);
4183 cpu_x86_load_seg(env, R_SS, __USER_DS);
4184 #ifdef TARGET_ABI32
4185 cpu_x86_load_seg(env, R_DS, __USER_DS);
4186 cpu_x86_load_seg(env, R_ES, __USER_DS);
4187 cpu_x86_load_seg(env, R_FS, __USER_DS);
4188 cpu_x86_load_seg(env, R_GS, __USER_DS);
4189 /* This hack makes Wine work... */
4190 env->segs[R_FS].selector = 0;
4191 #else
4192 cpu_x86_load_seg(env, R_DS, 0);
4193 cpu_x86_load_seg(env, R_ES, 0);
4194 cpu_x86_load_seg(env, R_FS, 0);
4195 cpu_x86_load_seg(env, R_GS, 0);
4196 #endif
4197 #elif defined(TARGET_AARCH64)
4198 {
4199 int i;
4200
4201 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4202 fprintf(stderr,
4203 "The selected ARM CPU does not support 64 bit mode\n");
4204 exit(1);
4205 }
4206
4207 for (i = 0; i < 31; i++) {
4208 env->xregs[i] = regs->regs[i];
4209 }
4210 env->pc = regs->pc;
4211 env->xregs[31] = regs->sp;
4212 }
4213 #elif defined(TARGET_ARM)
4214 {
4215 int i;
4216 cpsr_write(env, regs->uregs[16], 0xffffffff);
4217 for(i = 0; i < 16; i++) {
4218 env->regs[i] = regs->uregs[i];
4219 }
4220 /* Enable BE8. */
4221 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4222 && (info->elf_flags & EF_ARM_BE8)) {
4223 env->bswap_code = 1;
4224 }
4225 }
4226 #elif defined(TARGET_UNICORE32)
4227 {
4228 int i;
4229 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4230 for (i = 0; i < 32; i++) {
4231 env->regs[i] = regs->uregs[i];
4232 }
4233 }
4234 #elif defined(TARGET_SPARC)
4235 {
4236 int i;
4237 env->pc = regs->pc;
4238 env->npc = regs->npc;
4239 env->y = regs->y;
4240 for(i = 0; i < 8; i++)
4241 env->gregs[i] = regs->u_regs[i];
4242 for(i = 0; i < 8; i++)
4243 env->regwptr[i] = regs->u_regs[i + 8];
4244 }
4245 #elif defined(TARGET_PPC)
4246 {
4247 int i;
4248
4249 #if defined(TARGET_PPC64)
4250 #if defined(TARGET_ABI32)
4251 env->msr &= ~((target_ulong)1 << MSR_SF);
4252 #else
4253 env->msr |= (target_ulong)1 << MSR_SF;
4254 #endif
4255 #endif
4256 env->nip = regs->nip;
4257 for(i = 0; i < 32; i++) {
4258 env->gpr[i] = regs->gpr[i];
4259 }
4260 }
4261 #elif defined(TARGET_M68K)
4262 {
4263 env->pc = regs->pc;
4264 env->dregs[0] = regs->d0;
4265 env->dregs[1] = regs->d1;
4266 env->dregs[2] = regs->d2;
4267 env->dregs[3] = regs->d3;
4268 env->dregs[4] = regs->d4;
4269 env->dregs[5] = regs->d5;
4270 env->dregs[6] = regs->d6;
4271 env->dregs[7] = regs->d7;
4272 env->aregs[0] = regs->a0;
4273 env->aregs[1] = regs->a1;
4274 env->aregs[2] = regs->a2;
4275 env->aregs[3] = regs->a3;
4276 env->aregs[4] = regs->a4;
4277 env->aregs[5] = regs->a5;
4278 env->aregs[6] = regs->a6;
4279 env->aregs[7] = regs->usp;
4280 env->sr = regs->sr;
4281 ts->sim_syscalls = 1;
4282 }
4283 #elif defined(TARGET_MICROBLAZE)
4284 {
4285 env->regs[0] = regs->r0;
4286 env->regs[1] = regs->r1;
4287 env->regs[2] = regs->r2;
4288 env->regs[3] = regs->r3;
4289 env->regs[4] = regs->r4;
4290 env->regs[5] = regs->r5;
4291 env->regs[6] = regs->r6;
4292 env->regs[7] = regs->r7;
4293 env->regs[8] = regs->r8;
4294 env->regs[9] = regs->r9;
4295 env->regs[10] = regs->r10;
4296 env->regs[11] = regs->r11;
4297 env->regs[12] = regs->r12;
4298 env->regs[13] = regs->r13;
4299 env->regs[14] = regs->r14;
4300 env->regs[15] = regs->r15;
4301 env->regs[16] = regs->r16;
4302 env->regs[17] = regs->r17;
4303 env->regs[18] = regs->r18;
4304 env->regs[19] = regs->r19;
4305 env->regs[20] = regs->r20;
4306 env->regs[21] = regs->r21;
4307 env->regs[22] = regs->r22;
4308 env->regs[23] = regs->r23;
4309 env->regs[24] = regs->r24;
4310 env->regs[25] = regs->r25;
4311 env->regs[26] = regs->r26;
4312 env->regs[27] = regs->r27;
4313 env->regs[28] = regs->r28;
4314 env->regs[29] = regs->r29;
4315 env->regs[30] = regs->r30;
4316 env->regs[31] = regs->r31;
4317 env->sregs[SR_PC] = regs->pc;
4318 }
4319 #elif defined(TARGET_MIPS)
4320 {
4321 int i;
4322
4323 for(i = 0; i < 32; i++) {
4324 env->active_tc.gpr[i] = regs->regs[i];
4325 }
4326 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4327 if (regs->cp0_epc & 1) {
4328 env->hflags |= MIPS_HFLAG_M16;
4329 }
4330 }
4331 #elif defined(TARGET_OPENRISC)
4332 {
4333 int i;
4334
4335 for (i = 0; i < 32; i++) {
4336 env->gpr[i] = regs->gpr[i];
4337 }
4338
4339 env->sr = regs->sr;
4340 env->pc = regs->pc;
4341 }
4342 #elif defined(TARGET_SH4)
4343 {
4344 int i;
4345
4346 for(i = 0; i < 16; i++) {
4347 env->gregs[i] = regs->regs[i];
4348 }
4349 env->pc = regs->pc;
4350 }
4351 #elif defined(TARGET_ALPHA)
4352 {
4353 int i;
4354
4355 for(i = 0; i < 28; i++) {
4356 env->ir[i] = ((abi_ulong *)regs)[i];
4357 }
4358 env->ir[IR_SP] = regs->usp;
4359 env->pc = regs->pc;
4360 }
4361 #elif defined(TARGET_CRIS)
4362 {
4363 env->regs[0] = regs->r0;
4364 env->regs[1] = regs->r1;
4365 env->regs[2] = regs->r2;
4366 env->regs[3] = regs->r3;
4367 env->regs[4] = regs->r4;
4368 env->regs[5] = regs->r5;
4369 env->regs[6] = regs->r6;
4370 env->regs[7] = regs->r7;
4371 env->regs[8] = regs->r8;
4372 env->regs[9] = regs->r9;
4373 env->regs[10] = regs->r10;
4374 env->regs[11] = regs->r11;
4375 env->regs[12] = regs->r12;
4376 env->regs[13] = regs->r13;
4377 env->regs[14] = info->start_stack;
4378 env->regs[15] = regs->acr;
4379 env->pc = regs->erp;
4380 }
4381 #elif defined(TARGET_S390X)
4382 {
4383 int i;
4384 for (i = 0; i < 16; i++) {
4385 env->regs[i] = regs->gprs[i];
4386 }
4387 env->psw.mask = regs->psw.mask;
4388 env->psw.addr = regs->psw.addr;
4389 }
4390 #else
4391 #error unsupported target CPU
4392 #endif
4393
4394 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4395 ts->stack_base = info->start_stack;
4396 ts->heap_base = info->brk;
4397 /* This will be filled in on the first SYS_HEAPINFO call. */
4398 ts->heap_limit = 0;
4399 #endif
4400
4401 if (gdbstub_port) {
4402 if (gdbserver_start(gdbstub_port) < 0) {
4403 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4404 gdbstub_port);
4405 exit(1);
4406 }
4407 gdb_handlesig(cpu, 0);
4408 }
4409 cpu_loop(env);
4410 /* never exits */
4411 return 0;
4412 }
AR7 emulation for QEMU