hw/pci-host/q35: Ignore write of reserved PCIEXBAR LENGTH field
[qemu/ar7.git] / include / hw / misc / aspeed_lpc.h
blobdf418cfcd36cbe3994de9964f8f92b9fb39e80ee
1 /*
2 * ASPEED LPC Controller
4 * Copyright (C) 2017-2018 IBM Corp.
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
10 #ifndef ASPEED_LPC_H
11 #define ASPEED_LPC_H
13 #include "hw/sysbus.h"
15 #include <stdint.h>
17 #define TYPE_ASPEED_LPC "aspeed.lpc"
18 #define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC)
20 #define ASPEED_LPC_NR_REGS (0x260 >> 2)
22 enum aspeed_lpc_subdevice {
23 aspeed_lpc_kcs_1 = 0,
24 aspeed_lpc_kcs_2,
25 aspeed_lpc_kcs_3,
26 aspeed_lpc_kcs_4,
27 aspeed_lpc_ibt,
30 #define ASPEED_LPC_NR_SUBDEVS 5
32 typedef struct AspeedLPCState {
33 /* <private> */
34 SysBusDevice parent;
36 /*< public >*/
37 MemoryRegion iomem;
38 qemu_irq irq;
40 qemu_irq subdevice_irqs[ASPEED_LPC_NR_SUBDEVS];
41 uint32_t subdevice_irqs_pending;
43 uint32_t regs[ASPEED_LPC_NR_REGS];
44 uint32_t hicr7;
45 } AspeedLPCState;
47 #endif /* _ASPEED_LPC_H_ */