?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
hw/riscv: shakti_c: Mark as not user creatable
[qemu/ar7.git] / hw / arm / allwinner-h3.c
blobf9b7ed1871126205e93e87293d2fbf0564ab9fa5
1 /*
2 * Allwinner H3 System on Chip emulation
3 *
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "qemu/error-report.h"
23 #include "qemu/module.h"
24 #include "qemu/units.h"
25 #include "hw/qdev-core.h"
26 #include "hw/sysbus.h"
27 #include "hw/char/serial.h"
28 #include "hw/misc/unimp.h"
29 #include "hw/usb/hcd-ehci.h"
30 #include "hw/loader.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/arm/allwinner-h3.h"
33
34 /* Memory map */
35 const hwaddr allwinner_h3_memmap[] = {
36 [AW_H3_DEV_SRAM_A1] = 0x00000000,
37 [AW_H3_DEV_SRAM_A2] = 0x00044000,
38 [AW_H3_DEV_SRAM_C] = 0x00010000,
39 [AW_H3_DEV_SYSCTRL] = 0x01c00000,
40 [AW_H3_DEV_MMC0] = 0x01c0f000,
41 [AW_H3_DEV_SID] = 0x01c14000,
42 [AW_H3_DEV_EHCI0] = 0x01c1a000,
43 [AW_H3_DEV_OHCI0] = 0x01c1a400,
44 [AW_H3_DEV_EHCI1] = 0x01c1b000,
45 [AW_H3_DEV_OHCI1] = 0x01c1b400,
46 [AW_H3_DEV_EHCI2] = 0x01c1c000,
47 [AW_H3_DEV_OHCI2] = 0x01c1c400,
48 [AW_H3_DEV_EHCI3] = 0x01c1d000,
49 [AW_H3_DEV_OHCI3] = 0x01c1d400,
50 [AW_H3_DEV_CCU] = 0x01c20000,
51 [AW_H3_DEV_PIT] = 0x01c20c00,
52 [AW_H3_DEV_UART0] = 0x01c28000,
53 [AW_H3_DEV_UART1] = 0x01c28400,
54 [AW_H3_DEV_UART2] = 0x01c28800,
55 [AW_H3_DEV_UART3] = 0x01c28c00,
56 [AW_H3_DEV_EMAC] = 0x01c30000,
57 [AW_H3_DEV_DRAMCOM] = 0x01c62000,
58 [AW_H3_DEV_DRAMCTL] = 0x01c63000,
59 [AW_H3_DEV_DRAMPHY] = 0x01c65000,
60 [AW_H3_DEV_GIC_DIST] = 0x01c81000,
61 [AW_H3_DEV_GIC_CPU] = 0x01c82000,
62 [AW_H3_DEV_GIC_HYP] = 0x01c84000,
63 [AW_H3_DEV_GIC_VCPU] = 0x01c86000,
64 [AW_H3_DEV_RTC] = 0x01f00000,
65 [AW_H3_DEV_CPUCFG] = 0x01f01c00,
66 [AW_H3_DEV_SDRAM] = 0x40000000
67 };
68
69 /* List of unimplemented devices */
70 struct AwH3Unimplemented {
71 const char *device_name;
72 hwaddr base;
73 hwaddr size;
74 } unimplemented[] = {
75 { "d-engine", 0x01000000, 4 * MiB },
76 { "d-inter", 0x01400000, 128 * KiB },
77 { "dma", 0x01c02000, 4 * KiB },
78 { "nfdc", 0x01c03000, 4 * KiB },
79 { "ts", 0x01c06000, 4 * KiB },
80 { "keymem", 0x01c0b000, 4 * KiB },
81 { "lcd0", 0x01c0c000, 4 * KiB },
82 { "lcd1", 0x01c0d000, 4 * KiB },
83 { "ve", 0x01c0e000, 4 * KiB },
84 { "mmc1", 0x01c10000, 4 * KiB },
85 { "mmc2", 0x01c11000, 4 * KiB },
86 { "crypto", 0x01c15000, 4 * KiB },
87 { "msgbox", 0x01c17000, 4 * KiB },
88 { "spinlock", 0x01c18000, 4 * KiB },
89 { "usb0-otg", 0x01c19000, 4 * KiB },
90 { "usb0-phy", 0x01c1a000, 4 * KiB },
91 { "usb1-phy", 0x01c1b000, 4 * KiB },
92 { "usb2-phy", 0x01c1c000, 4 * KiB },
93 { "usb3-phy", 0x01c1d000, 4 * KiB },
94 { "smc", 0x01c1e000, 4 * KiB },
95 { "pio", 0x01c20800, 1 * KiB },
96 { "owa", 0x01c21000, 1 * KiB },
97 { "pwm", 0x01c21400, 1 * KiB },
98 { "keyadc", 0x01c21800, 1 * KiB },
99 { "pcm0", 0x01c22000, 1 * KiB },
100 { "pcm1", 0x01c22400, 1 * KiB },
101 { "pcm2", 0x01c22800, 1 * KiB },
102 { "audio", 0x01c22c00, 2 * KiB },
103 { "smta", 0x01c23400, 1 * KiB },
104 { "ths", 0x01c25000, 1 * KiB },
105 { "uart0", 0x01c28000, 1 * KiB },
106 { "uart1", 0x01c28400, 1 * KiB },
107 { "uart2", 0x01c28800, 1 * KiB },
108 { "uart3", 0x01c28c00, 1 * KiB },
109 { "twi0", 0x01c2ac00, 1 * KiB },
110 { "twi1", 0x01c2b000, 1 * KiB },
111 { "twi2", 0x01c2b400, 1 * KiB },
112 { "scr", 0x01c2c400, 1 * KiB },
113 { "gpu", 0x01c40000, 64 * KiB },
114 { "hstmr", 0x01c60000, 4 * KiB },
115 { "spi0", 0x01c68000, 4 * KiB },
116 { "spi1", 0x01c69000, 4 * KiB },
117 { "csi", 0x01cb0000, 320 * KiB },
118 { "tve", 0x01e00000, 64 * KiB },
119 { "hdmi", 0x01ee0000, 128 * KiB },
120 { "r_timer", 0x01f00800, 1 * KiB },
121 { "r_intc", 0x01f00c00, 1 * KiB },
122 { "r_wdog", 0x01f01000, 1 * KiB },
123 { "r_prcm", 0x01f01400, 1 * KiB },
124 { "r_twd", 0x01f01800, 1 * KiB },
125 { "r_cir-rx", 0x01f02000, 1 * KiB },
126 { "r_twi", 0x01f02400, 1 * KiB },
127 { "r_uart", 0x01f02800, 1 * KiB },
128 { "r_pio", 0x01f02c00, 1 * KiB },
129 { "r_pwm", 0x01f03800, 1 * KiB },
130 { "core-dbg", 0x3f500000, 128 * KiB },
131 { "tsgen-ro", 0x3f506000, 4 * KiB },
132 { "tsgen-ctl", 0x3f507000, 4 * KiB },
133 { "ddr-mem", 0x40000000, 2 * GiB },
134 { "n-brom", 0xffff0000, 32 * KiB },
135 { "s-brom", 0xffff0000, 64 * KiB }
136 };
137
138 /* Per Processor Interrupts */
139 enum {
140 AW_H3_GIC_PPI_MAINT = 9,
141 AW_H3_GIC_PPI_HYPTIMER = 10,
142 AW_H3_GIC_PPI_VIRTTIMER = 11,
143 AW_H3_GIC_PPI_SECTIMER = 13,
144 AW_H3_GIC_PPI_PHYSTIMER = 14
145 };
146
147 /* Shared Processor Interrupts */
148 enum {
149 AW_H3_GIC_SPI_UART0 = 0,
150 AW_H3_GIC_SPI_UART1 = 1,
151 AW_H3_GIC_SPI_UART2 = 2,
152 AW_H3_GIC_SPI_UART3 = 3,
153 AW_H3_GIC_SPI_TIMER0 = 18,
154 AW_H3_GIC_SPI_TIMER1 = 19,
155 AW_H3_GIC_SPI_MMC0 = 60,
156 AW_H3_GIC_SPI_EHCI0 = 72,
157 AW_H3_GIC_SPI_OHCI0 = 73,
158 AW_H3_GIC_SPI_EHCI1 = 74,
159 AW_H3_GIC_SPI_OHCI1 = 75,
160 AW_H3_GIC_SPI_EHCI2 = 76,
161 AW_H3_GIC_SPI_OHCI2 = 77,
162 AW_H3_GIC_SPI_EHCI3 = 78,
163 AW_H3_GIC_SPI_OHCI3 = 79,
164 AW_H3_GIC_SPI_EMAC = 82
165 };
166
167 /* Allwinner H3 general constants */
168 enum {
169 AW_H3_GIC_NUM_SPI = 128
170 };
171
172 void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
173 {
174 const int64_t rom_size = 32 * KiB;
175 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
176
177 if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {
178 error_setg(&error_fatal, "%s: failed to read BlockBackend data",
179 __func__);
180 return;
181 }
182
183 rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
184 rom_size, s->memmap[AW_H3_DEV_SRAM_A1],
185 NULL, NULL, NULL, NULL, false);
186 }
187
188 static void allwinner_h3_init(Object *obj)
189 {
190 AwH3State *s = AW_H3(obj);
191
192 s->memmap = allwinner_h3_memmap;
193
194 for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
195 object_initialize_child(obj, "cpu[*]", &s->cpus[i],
196 ARM_CPU_TYPE_NAME("cortex-a7"));
197 }
198
199 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
200
201 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
202 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
203 "clk0-freq");
204 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
205 "clk1-freq");
206
207 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_H3_CCU);
208
209 object_initialize_child(obj, "sysctrl", &s->sysctrl, TYPE_AW_H3_SYSCTRL);
210
211 object_initialize_child(obj, "cpucfg", &s->cpucfg, TYPE_AW_CPUCFG);
212
213 object_initialize_child(obj, "sid", &s->sid, TYPE_AW_SID);
214 object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
215 "identifier");
216
217 object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN5I);
218
219 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_SUN8I_EMAC);
220
221 object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_H3_DRAMC);
222 object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
223 "ram-addr");
224 object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
225 "ram-size");
226
227 object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
228 }
229
230 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
231 {
232 AwH3State *s = AW_H3(dev);
233 unsigned i;
234
235 /* CPUs */
236 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
237
238 /* Provide Power State Coordination Interface */
239 qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
240 QEMU_PSCI_CONDUIT_SMC);
241
242 /* Disable secondary CPUs */
243 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
244 i > 0);
245
246 /* All exception levels required */
247 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
248 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
249
250 /* Mark realized */
251 qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
252 }
253
254 /* Generic Interrupt Controller */
255 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
256 GIC_INTERNAL);
257 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
258 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
259 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
260 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
261 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
262
263 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_DEV_GIC_DIST]);
264 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_DEV_GIC_CPU]);
265 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_DEV_GIC_HYP]);
266 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_DEV_GIC_VCPU]);
267
268 /*
269 * Wire the outputs from each CPU's generic timer and the GICv3
270 * maintenance interrupt signal to the appropriate GIC PPI inputs,
271 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
272 */
273 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
274 DeviceState *cpudev = DEVICE(&s->cpus[i]);
275 int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
276 int irq;
277 /*
278 * Mapping from the output timer irq lines from the CPU to the
279 * GIC PPI inputs used for this board.
280 */
281 const int timer_irq[] = {
282 [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
283 [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
284 [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
285 [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
286 };
287
288 /* Connect CPU timer outputs to GIC PPI inputs */
289 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
290 qdev_connect_gpio_out(cpudev, irq,
291 qdev_get_gpio_in(DEVICE(&s->gic),
292 ppibase + timer_irq[irq]));
293 }
294
295 /* Connect GIC outputs to CPU interrupt inputs */
296 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
297 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
298 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
299 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
300 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
301 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
302 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
303 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
304
305 /* GIC maintenance signal */
306 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
307 qdev_get_gpio_in(DEVICE(&s->gic),
308 ppibase + AW_H3_GIC_PPI_MAINT));
309 }
310
311 /* Timer */
312 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
313 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_DEV_PIT]);
314 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
315 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
316 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
317 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
318
319 /* SRAM */
320 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
321 64 * KiB, &error_abort);
322 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
323 32 * KiB, &error_abort);
324 memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
325 44 * KiB, &error_abort);
326 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A1],
327 &s->sram_a1);
328 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A2],
329 &s->sram_a2);
330 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_C],
331 &s->sram_c);
332
333 /* Clock Control Unit */
334 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
335 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_DEV_CCU]);
336
337 /* System Control */
338 sysbus_realize(SYS_BUS_DEVICE(&s->sysctrl), &error_fatal);
339 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_DEV_SYSCTRL]);
340
341 /* CPU Configuration */
342 sysbus_realize(SYS_BUS_DEVICE(&s->cpucfg), &error_fatal);
343 sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_DEV_CPUCFG]);
344
345 /* Security Identifier */
346 sysbus_realize(SYS_BUS_DEVICE(&s->sid), &error_fatal);
347 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_DEV_SID]);
348
349 /* SD/MMC */
350 object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
351 OBJECT(get_system_memory()), &error_fatal);
352 sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
353 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_DEV_MMC0]);
354 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
355 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
356
357 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
358 "sd-bus");
359
360 /* EMAC */
361 /* FIXME use qdev NIC properties instead of nd_table[] */
362 if (nd_table[0].used) {
363 qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
364 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
365 }
366 object_property_set_link(OBJECT(&s->emac), "dma-memory",
367 OBJECT(get_system_memory()), &error_fatal);
368 sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
369 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_DEV_EMAC]);
370 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
371 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
372
373 /* Universal Serial Bus */
374 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI0],
375 qdev_get_gpio_in(DEVICE(&s->gic),
376 AW_H3_GIC_SPI_EHCI0));
377 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI1],
378 qdev_get_gpio_in(DEVICE(&s->gic),
379 AW_H3_GIC_SPI_EHCI1));
380 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI2],
381 qdev_get_gpio_in(DEVICE(&s->gic),
382 AW_H3_GIC_SPI_EHCI2));
383 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI3],
384 qdev_get_gpio_in(DEVICE(&s->gic),
385 AW_H3_GIC_SPI_EHCI3));
386
387 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI0],
388 qdev_get_gpio_in(DEVICE(&s->gic),
389 AW_H3_GIC_SPI_OHCI0));
390 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI1],
391 qdev_get_gpio_in(DEVICE(&s->gic),
392 AW_H3_GIC_SPI_OHCI1));
393 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI2],
394 qdev_get_gpio_in(DEVICE(&s->gic),
395 AW_H3_GIC_SPI_OHCI2));
396 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI3],
397 qdev_get_gpio_in(DEVICE(&s->gic),
398 AW_H3_GIC_SPI_OHCI3));
399
400 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
401 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART0], 2,
402 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
403 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
404 /* UART1 */
405 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART1], 2,
406 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
407 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
408 /* UART2 */
409 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART2], 2,
410 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
411 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
412 /* UART3 */
413 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART3], 2,
414 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
415 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
416
417 /* DRAMC */
418 sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
419 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DEV_DRAMCOM]);
420 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DEV_DRAMCTL]);
421 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DEV_DRAMPHY]);
422
423 /* RTC */
424 sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
425 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
426
427 /* Unimplemented devices */
428 for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
429 create_unimplemented_device(unimplemented[i].device_name,
430 unimplemented[i].base,
431 unimplemented[i].size);
432 }
433 }
434
435 static void allwinner_h3_class_init(ObjectClass *oc, void *data)
436 {
437 DeviceClass *dc = DEVICE_CLASS(oc);
438
439 dc->realize = allwinner_h3_realize;
440 /* Reason: uses serial_hd() in realize function */
441 dc->user_creatable = false;
442 }
443
444 static const TypeInfo allwinner_h3_type_info = {
445 .name = TYPE_AW_H3,
446 .parent = TYPE_DEVICE,
447 .instance_size = sizeof(AwH3State),
448 .instance_init = allwinner_h3_init,
449 .class_init = allwinner_h3_class_init,
450 };
451
452 static void allwinner_h3_register_types(void)
453 {
454 type_register_static(&allwinner_h3_type_info);
455 }
456
457 type_init(allwinner_h3_register_types)
AR7 emulation for QEMU