2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qapi/error.h"
13 #include "qemu/error-report.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "monitor/monitor.h"
17 #include "hw/ppc/fdt.h"
18 #include "hw/ppc/spapr.h"
19 #include "hw/ppc/spapr_xive.h"
20 #include "hw/ppc/xive.h"
21 #include "hw/ppc/xive_regs.h"
24 * XIVE Virtualization Controller BAR and Thread Managment BAR that we
25 * use for the ESB pages and the TIMA pages
27 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
28 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
31 * The allocation of VP blocks is a complex operation in OPAL and the
32 * VP identifiers have a relation with the number of HW chips, the
33 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE
34 * controller model does not have the same constraints and can use a
35 * simple mapping scheme of the CPU vcpu_id
37 * These identifiers are never returned to the OS.
40 #define SPAPR_XIVE_NVT_BASE 0x400
43 * The sPAPR machine has a unique XIVE IC device. Assign a fixed value
44 * to the controller block id value. It can nevertheless be changed
45 * for testing purpose.
47 #define SPAPR_XIVE_BLOCK_ID 0x0
50 * sPAPR NVT and END indexing helpers
52 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk
, uint32_t nvt_idx
)
54 return nvt_idx
- SPAPR_XIVE_NVT_BASE
;
57 static void spapr_xive_cpu_to_nvt(PowerPCCPU
*cpu
,
58 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
63 *out_nvt_blk
= SPAPR_XIVE_BLOCK_ID
;
67 *out_nvt_idx
= SPAPR_XIVE_NVT_BASE
+ cpu
->vcpu_id
;
71 static int spapr_xive_target_to_nvt(uint32_t target
,
72 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
74 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
80 spapr_xive_cpu_to_nvt(cpu
, out_nvt_blk
, out_nvt_idx
);
85 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8
88 static void spapr_xive_cpu_to_end(PowerPCCPU
*cpu
, uint8_t prio
,
89 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
94 *out_end_blk
= SPAPR_XIVE_BLOCK_ID
;
98 *out_end_idx
= (cpu
->vcpu_id
<< 3) + prio
;
102 static int spapr_xive_target_to_end(uint32_t target
, uint8_t prio
,
103 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
105 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
111 spapr_xive_cpu_to_end(cpu
, prio
, out_end_blk
, out_end_idx
);
116 * On sPAPR machines, use a simplified output for the XIVE END
117 * structure dumping only the information related to the OS EQ.
119 static void spapr_xive_end_pic_print_info(sPAPRXive
*xive
, XiveEND
*end
,
122 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
123 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
124 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
125 uint32_t qentries
= 1 << (qsize
+ 10);
126 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
127 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
129 monitor_printf(mon
, "%3d/%d % 6d/%5d ^%d",
130 spapr_xive_nvt_to_target(0, nvt
),
131 priority
, qindex
, qentries
, qgen
);
133 xive_end_queue_pic_print_info(end
, 6, mon
);
134 monitor_printf(mon
, "]");
137 void spapr_xive_pic_print_info(sPAPRXive
*xive
, Monitor
*mon
)
139 XiveSource
*xsrc
= &xive
->source
;
142 monitor_printf(mon
, " LSIN PQ EISN CPU/PRIO EQ\n");
144 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
145 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
146 XiveEAS
*eas
= &xive
->eat
[i
];
148 if (!xive_eas_is_valid(eas
)) {
152 monitor_printf(mon
, " %08x %s %c%c%c %s %08x ", i
,
153 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
154 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
155 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
156 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ',
157 xive_eas_is_masked(eas
) ? "M" : " ",
158 (int) xive_get_field64(EAS_END_DATA
, eas
->w
));
160 if (!xive_eas_is_masked(eas
)) {
161 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
164 assert(end_idx
< xive
->nr_ends
);
165 end
= &xive
->endt
[end_idx
];
167 if (xive_end_is_valid(end
)) {
168 spapr_xive_end_pic_print_info(xive
, end
, mon
);
171 monitor_printf(mon
, "\n");
175 static void spapr_xive_map_mmio(sPAPRXive
*xive
)
177 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 0, xive
->vc_base
);
178 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 1, xive
->end_base
);
179 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 2, xive
->tm_base
);
182 void spapr_xive_mmio_set_enabled(sPAPRXive
*xive
, bool enable
)
184 memory_region_set_enabled(&xive
->source
.esb_mmio
, enable
);
185 memory_region_set_enabled(&xive
->tm_mmio
, enable
);
187 /* Disable the END ESBs until a guest OS makes use of them */
188 memory_region_set_enabled(&xive
->end_source
.esb_mmio
, false);
192 * When a Virtual Processor is scheduled to run on a HW thread, the
193 * hypervisor pushes its identifier in the OS CAM line. Emulate the
194 * same behavior under QEMU.
196 void spapr_xive_set_tctx_os_cam(XiveTCTX
*tctx
)
202 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx
->cs
), &nvt_blk
, &nvt_idx
);
204 nvt_cam
= cpu_to_be32(TM_QW1W2_VO
| xive_nvt_cam_line(nvt_blk
, nvt_idx
));
205 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &nvt_cam
, 4);
208 static void spapr_xive_end_reset(XiveEND
*end
)
210 memset(end
, 0, sizeof(*end
));
212 /* switch off the escalation and notification ESBs */
213 end
->w1
= cpu_to_be32(END_W1_ESe_Q
| END_W1_ESn_Q
);
216 static void spapr_xive_reset(void *dev
)
218 sPAPRXive
*xive
= SPAPR_XIVE(dev
);
222 * The XiveSource has its own reset handler, which mask off all
226 /* Mask all valid EASs in the IRQ number space. */
227 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
228 XiveEAS
*eas
= &xive
->eat
[i
];
229 if (xive_eas_is_valid(eas
)) {
230 eas
->w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
237 for (i
= 0; i
< xive
->nr_ends
; i
++) {
238 spapr_xive_end_reset(&xive
->endt
[i
]);
242 static void spapr_xive_instance_init(Object
*obj
)
244 sPAPRXive
*xive
= SPAPR_XIVE(obj
);
246 object_initialize(&xive
->source
, sizeof(xive
->source
), TYPE_XIVE_SOURCE
);
247 object_property_add_child(obj
, "source", OBJECT(&xive
->source
), NULL
);
249 object_initialize(&xive
->end_source
, sizeof(xive
->end_source
),
250 TYPE_XIVE_END_SOURCE
);
251 object_property_add_child(obj
, "end_source", OBJECT(&xive
->end_source
),
255 static void spapr_xive_realize(DeviceState
*dev
, Error
**errp
)
257 sPAPRXive
*xive
= SPAPR_XIVE(dev
);
258 XiveSource
*xsrc
= &xive
->source
;
259 XiveENDSource
*end_xsrc
= &xive
->end_source
;
260 Error
*local_err
= NULL
;
262 if (!xive
->nr_irqs
) {
263 error_setg(errp
, "Number of interrupt needs to be greater 0");
267 if (!xive
->nr_ends
) {
268 error_setg(errp
, "Number of interrupt needs to be greater 0");
273 * Initialize the internal sources, for IPIs and virtual devices.
275 object_property_set_int(OBJECT(xsrc
), xive
->nr_irqs
, "nr-irqs",
277 object_property_add_const_link(OBJECT(xsrc
), "xive", OBJECT(xive
),
279 object_property_set_bool(OBJECT(xsrc
), true, "realized", &local_err
);
281 error_propagate(errp
, local_err
);
286 * Initialize the END ESB source
288 object_property_set_int(OBJECT(end_xsrc
), xive
->nr_irqs
, "nr-ends",
290 object_property_add_const_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
292 object_property_set_bool(OBJECT(end_xsrc
), true, "realized", &local_err
);
294 error_propagate(errp
, local_err
);
298 /* Set the mapping address of the END ESB pages after the source ESBs */
299 xive
->end_base
= xive
->vc_base
+ (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
;
302 * Allocate the routing tables
304 xive
->eat
= g_new0(XiveEAS
, xive
->nr_irqs
);
305 xive
->endt
= g_new0(XiveEND
, xive
->nr_ends
);
307 /* TIMA initialization */
308 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &xive_tm_ops
, xive
,
309 "xive.tima", 4ull << TM_SHIFT
);
311 /* Define all XIVE MMIO regions on SysBus */
312 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xsrc
->esb_mmio
);
313 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &end_xsrc
->esb_mmio
);
314 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xive
->tm_mmio
);
316 /* Map all regions */
317 spapr_xive_map_mmio(xive
);
319 qemu_register_reset(spapr_xive_reset
, dev
);
322 static int spapr_xive_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
,
323 uint32_t eas_idx
, XiveEAS
*eas
)
325 sPAPRXive
*xive
= SPAPR_XIVE(xrtr
);
327 if (eas_idx
>= xive
->nr_irqs
) {
331 *eas
= xive
->eat
[eas_idx
];
335 static int spapr_xive_get_end(XiveRouter
*xrtr
,
336 uint8_t end_blk
, uint32_t end_idx
, XiveEND
*end
)
338 sPAPRXive
*xive
= SPAPR_XIVE(xrtr
);
340 if (end_idx
>= xive
->nr_ends
) {
344 memcpy(end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
348 static int spapr_xive_write_end(XiveRouter
*xrtr
, uint8_t end_blk
,
349 uint32_t end_idx
, XiveEND
*end
,
352 sPAPRXive
*xive
= SPAPR_XIVE(xrtr
);
354 if (end_idx
>= xive
->nr_ends
) {
358 memcpy(&xive
->endt
[end_idx
], end
, sizeof(XiveEND
));
362 static int spapr_xive_get_nvt(XiveRouter
*xrtr
,
363 uint8_t nvt_blk
, uint32_t nvt_idx
, XiveNVT
*nvt
)
365 uint32_t vcpu_id
= spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
366 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
369 /* TODO: should we assert() if we can find a NVT ? */
374 * sPAPR does not maintain a NVT table. Return that the NVT is
375 * valid if we have found a matching CPU
377 nvt
->w0
= cpu_to_be32(NVT_W0_VALID
);
381 static int spapr_xive_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
,
382 uint32_t nvt_idx
, XiveNVT
*nvt
,
386 * We don't need to write back to the NVTs because the sPAPR
387 * machine should never hit a non-scheduled NVT. It should never
390 g_assert_not_reached();
393 static const VMStateDescription vmstate_spapr_xive_end
= {
394 .name
= TYPE_SPAPR_XIVE
"/end",
396 .minimum_version_id
= 1,
397 .fields
= (VMStateField
[]) {
398 VMSTATE_UINT32(w0
, XiveEND
),
399 VMSTATE_UINT32(w1
, XiveEND
),
400 VMSTATE_UINT32(w2
, XiveEND
),
401 VMSTATE_UINT32(w3
, XiveEND
),
402 VMSTATE_UINT32(w4
, XiveEND
),
403 VMSTATE_UINT32(w5
, XiveEND
),
404 VMSTATE_UINT32(w6
, XiveEND
),
405 VMSTATE_UINT32(w7
, XiveEND
),
406 VMSTATE_END_OF_LIST()
410 static const VMStateDescription vmstate_spapr_xive_eas
= {
411 .name
= TYPE_SPAPR_XIVE
"/eas",
413 .minimum_version_id
= 1,
414 .fields
= (VMStateField
[]) {
415 VMSTATE_UINT64(w
, XiveEAS
),
416 VMSTATE_END_OF_LIST()
420 static const VMStateDescription vmstate_spapr_xive
= {
421 .name
= TYPE_SPAPR_XIVE
,
423 .minimum_version_id
= 1,
424 .fields
= (VMStateField
[]) {
425 VMSTATE_UINT32_EQUAL(nr_irqs
, sPAPRXive
, NULL
),
426 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat
, sPAPRXive
, nr_irqs
,
427 vmstate_spapr_xive_eas
, XiveEAS
),
428 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt
, sPAPRXive
, nr_ends
,
429 vmstate_spapr_xive_end
, XiveEND
),
430 VMSTATE_END_OF_LIST()
434 static Property spapr_xive_properties
[] = {
435 DEFINE_PROP_UINT32("nr-irqs", sPAPRXive
, nr_irqs
, 0),
436 DEFINE_PROP_UINT32("nr-ends", sPAPRXive
, nr_ends
, 0),
437 DEFINE_PROP_UINT64("vc-base", sPAPRXive
, vc_base
, SPAPR_XIVE_VC_BASE
),
438 DEFINE_PROP_UINT64("tm-base", sPAPRXive
, tm_base
, SPAPR_XIVE_TM_BASE
),
439 DEFINE_PROP_END_OF_LIST(),
442 static void spapr_xive_class_init(ObjectClass
*klass
, void *data
)
444 DeviceClass
*dc
= DEVICE_CLASS(klass
);
445 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
447 dc
->desc
= "sPAPR XIVE Interrupt Controller";
448 dc
->props
= spapr_xive_properties
;
449 dc
->realize
= spapr_xive_realize
;
450 dc
->vmsd
= &vmstate_spapr_xive
;
452 xrc
->get_eas
= spapr_xive_get_eas
;
453 xrc
->get_end
= spapr_xive_get_end
;
454 xrc
->write_end
= spapr_xive_write_end
;
455 xrc
->get_nvt
= spapr_xive_get_nvt
;
456 xrc
->write_nvt
= spapr_xive_write_nvt
;
459 static const TypeInfo spapr_xive_info
= {
460 .name
= TYPE_SPAPR_XIVE
,
461 .parent
= TYPE_XIVE_ROUTER
,
462 .instance_init
= spapr_xive_instance_init
,
463 .instance_size
= sizeof(sPAPRXive
),
464 .class_init
= spapr_xive_class_init
,
467 static void spapr_xive_register_types(void)
469 type_register_static(&spapr_xive_info
);
472 type_init(spapr_xive_register_types
)
474 bool spapr_xive_irq_claim(sPAPRXive
*xive
, uint32_t lisn
, bool lsi
)
476 XiveSource
*xsrc
= &xive
->source
;
478 if (lisn
>= xive
->nr_irqs
) {
482 xive
->eat
[lisn
].w
|= cpu_to_be64(EAS_VALID
);
483 xive_source_irq_set(xsrc
, lisn
, lsi
);
487 bool spapr_xive_irq_free(sPAPRXive
*xive
, uint32_t lisn
)
489 XiveSource
*xsrc
= &xive
->source
;
491 if (lisn
>= xive
->nr_irqs
) {
495 xive
->eat
[lisn
].w
&= cpu_to_be64(~EAS_VALID
);
496 xive_source_irq_set(xsrc
, lisn
, false);
503 * The terminology used by the XIVE hcalls is the following :
506 * EQ Event Queue assigned by OS to receive event data
507 * ESB page for source interrupt management
508 * LISN Logical Interrupt Source Number identifying a source in the
510 * EISN Effective Interrupt Source Number used by guest OS to
511 * identify source in the guest
513 * The EAS, END, NVT structures are not exposed.
517 * Linux hosts under OPAL reserve priority 7 for their own escalation
518 * interrupts (DD2.X POWER9). So we only allow the guest to use
521 static bool spapr_xive_priority_is_reserved(uint8_t priority
)
526 case 7: /* OPAL escalation queue */
533 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical
534 * real address of the MMIO page through which the Event State Buffer
535 * entry associated with the value of the "lisn" parameter is managed.
541 * - R5: "lisn" is per "interrupts", "interrupt-map", or
542 * "ibm,xive-lisn-ranges" properties, or as returned by the
543 * ibm,query-interrupt-source-number RTAS call, or as returned
544 * by the H_ALLOCATE_VAS_WINDOW hcall
548 * Bits 0-59: Reserved
549 * Bit 60: H_INT_ESB must be used for Event State Buffer
551 * Bit 61: 1 == LSI 0 == MSI
552 * Bit 62: the full function page supports trigger
553 * Bit 63: Store EOI Supported
554 * - R5: Logical Real address of full function Event State Buffer
555 * management page, -1 if H_INT_ESB hcall flag is set to 1.
556 * - R6: Logical Real Address of trigger only Event State Buffer
557 * management page or -1.
558 * - R7: Power of 2 page size for the ESB management pages returned in
562 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
563 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
564 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
566 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
568 static target_ulong
h_int_get_source_info(PowerPCCPU
*cpu
,
569 sPAPRMachineState
*spapr
,
573 sPAPRXive
*xive
= spapr
->xive
;
574 XiveSource
*xsrc
= &xive
->source
;
575 target_ulong flags
= args
[0];
576 target_ulong lisn
= args
[1];
578 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
586 if (lisn
>= xive
->nr_irqs
) {
587 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
592 if (!xive_eas_is_valid(&xive
->eat
[lisn
])) {
593 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
599 * All sources are emulated under the main XIVE object and share
600 * the same characteristics.
603 if (!xive_source_esb_has_2page(xsrc
)) {
604 args
[0] |= SPAPR_XIVE_SRC_TRIGGER
;
606 if (xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
) {
607 args
[0] |= SPAPR_XIVE_SRC_STORE_EOI
;
611 * Force the use of the H_INT_ESB hcall in case of an LSI
612 * interrupt. This is necessary under KVM to re-trigger the
613 * interrupt if the level is still asserted
615 if (xive_source_irq_is_lsi(xsrc
, lisn
)) {
616 args
[0] |= SPAPR_XIVE_SRC_H_INT_ESB
| SPAPR_XIVE_SRC_LSI
;
619 if (!(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
620 args
[1] = xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
);
625 if (xive_source_esb_has_2page(xsrc
) &&
626 !(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
627 args
[2] = xive
->vc_base
+ xive_source_esb_page(xsrc
, lisn
);
632 if (xive_source_esb_has_2page(xsrc
)) {
633 args
[3] = xsrc
->esb_shift
- 1;
635 args
[3] = xsrc
->esb_shift
;
642 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical
643 * Interrupt Source to a target. The Logical Interrupt Source is
644 * designated with the "lisn" parameter and the target is designated
645 * with the "target" and "priority" parameters. Upon return from the
646 * hcall(), no additional interrupts will be directed to the old EQ.
651 * Bits 0-61: Reserved
652 * Bit 62: set the "eisn" in the EAS
653 * Bit 63: masks the interrupt source in the hardware interrupt
654 * control structure. An interrupt masked by this mechanism will
655 * be dropped, but it's source state bits will still be
656 * set. There is no race-free way of unmasking and restoring the
657 * source. Thus this should only be used in interrupts that are
658 * also masked at the source, and only in cases where the
659 * interrupt is not meant to be used for a large amount of time
660 * because no valid target exists for it for example
661 * - R5: "lisn" is per "interrupts", "interrupt-map", or
662 * "ibm,xive-lisn-ranges" properties, or as returned by the
663 * ibm,query-interrupt-source-number RTAS call, or as returned by
664 * the H_ALLOCATE_VAS_WINDOW hcall
665 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
666 * "ibm,ppc-interrupt-gserver#s"
667 * - R7: "priority" is a valid priority not in
668 * "ibm,plat-res-int-priorities"
669 * - R8: "eisn" is the guest EISN associated with the "lisn"
675 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
676 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
678 static target_ulong
h_int_set_source_config(PowerPCCPU
*cpu
,
679 sPAPRMachineState
*spapr
,
683 sPAPRXive
*xive
= spapr
->xive
;
684 XiveEAS eas
, new_eas
;
685 target_ulong flags
= args
[0];
686 target_ulong lisn
= args
[1];
687 target_ulong target
= args
[2];
688 target_ulong priority
= args
[3];
689 target_ulong eisn
= args
[4];
693 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
697 if (flags
& ~(SPAPR_XIVE_SRC_SET_EISN
| SPAPR_XIVE_SRC_MASK
)) {
701 if (lisn
>= xive
->nr_irqs
) {
702 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
707 eas
= xive
->eat
[lisn
];
708 if (!xive_eas_is_valid(&eas
)) {
709 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
714 /* priority 0xff is used to reset the EAS */
715 if (priority
== 0xff) {
716 new_eas
.w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
720 if (flags
& SPAPR_XIVE_SRC_MASK
) {
721 new_eas
.w
= eas
.w
| cpu_to_be64(EAS_MASKED
);
723 new_eas
.w
= eas
.w
& cpu_to_be64(~EAS_MASKED
);
726 if (spapr_xive_priority_is_reserved(priority
)) {
727 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
728 " is reserved\n", priority
);
733 * Validate that "target" is part of the list of threads allocated
734 * to the partition. For that, find the END corresponding to the
737 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
741 new_eas
.w
= xive_set_field64(EAS_END_BLOCK
, new_eas
.w
, end_blk
);
742 new_eas
.w
= xive_set_field64(EAS_END_INDEX
, new_eas
.w
, end_idx
);
744 if (flags
& SPAPR_XIVE_SRC_SET_EISN
) {
745 new_eas
.w
= xive_set_field64(EAS_END_DATA
, new_eas
.w
, eisn
);
749 xive
->eat
[lisn
] = new_eas
;
754 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which
755 * target/priority pair is assigned to the specified Logical Interrupt
762 * - R5: "lisn" is per "interrupts", "interrupt-map", or
763 * "ibm,xive-lisn-ranges" properties, or as returned by the
764 * ibm,query-interrupt-source-number RTAS call, or as
765 * returned by the H_ALLOCATE_VAS_WINDOW hcall
768 * - R4: Target to which the specified Logical Interrupt Source is
770 * - R5: Priority to which the specified Logical Interrupt Source is
772 * - R6: EISN for the specified Logical Interrupt Source (this will be
773 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG)
775 static target_ulong
h_int_get_source_config(PowerPCCPU
*cpu
,
776 sPAPRMachineState
*spapr
,
780 sPAPRXive
*xive
= spapr
->xive
;
781 target_ulong flags
= args
[0];
782 target_ulong lisn
= args
[1];
786 uint32_t end_idx
, nvt_idx
;
788 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
796 if (lisn
>= xive
->nr_irqs
) {
797 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
802 eas
= xive
->eat
[lisn
];
803 if (!xive_eas_is_valid(&eas
)) {
804 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
809 /* EAS_END_BLOCK is unused on sPAPR */
810 end_idx
= xive_get_field64(EAS_END_INDEX
, eas
.w
);
812 assert(end_idx
< xive
->nr_ends
);
813 end
= &xive
->endt
[end_idx
];
815 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
816 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
817 args
[0] = spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
819 if (xive_eas_is_masked(&eas
)) {
822 args
[1] = xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
825 args
[2] = xive_get_field64(EAS_END_DATA
, eas
.w
);
831 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real
832 * address of the notification management page associated with the
833 * specified target and priority.
839 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
840 * "ibm,ppc-interrupt-gserver#s"
841 * - R6: "priority" is a valid priority not in
842 * "ibm,plat-res-int-priorities"
845 * - R4: Logical real address of notification page
846 * - R5: Power of 2 page size of the notification page
848 static target_ulong
h_int_get_queue_info(PowerPCCPU
*cpu
,
849 sPAPRMachineState
*spapr
,
853 sPAPRXive
*xive
= spapr
->xive
;
854 XiveENDSource
*end_xsrc
= &xive
->end_source
;
855 target_ulong flags
= args
[0];
856 target_ulong target
= args
[1];
857 target_ulong priority
= args
[2];
862 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
871 * H_STATE should be returned if a H_INT_RESET is in progress.
872 * This is not needed when running the emulation under QEMU
875 if (spapr_xive_priority_is_reserved(priority
)) {
876 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
877 " is reserved\n", priority
);
882 * Validate that "target" is part of the list of threads allocated
883 * to the partition. For that, find the END corresponding to the
886 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
890 assert(end_idx
< xive
->nr_ends
);
891 end
= &xive
->endt
[end_idx
];
893 args
[0] = xive
->end_base
+ (1ull << (end_xsrc
->esb_shift
+ 1)) * end_idx
;
894 if (xive_end_is_enqueue(end
)) {
895 args
[1] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
904 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for
905 * a given "target" and "priority". It is also used to set the
906 * notification config associated with the EQ. An EQ size of 0 is
907 * used to reset the EQ config for a given target and priority. If
908 * resetting the EQ config, the END associated with the given "target"
909 * and "priority" will be changed to disable queueing.
911 * Upon return from the hcall(), no additional interrupts will be
912 * directed to the old EQ (if one was set). The old EQ (if one was
913 * set) should be investigated for interrupts that occurred prior to
914 * or during the hcall().
919 * Bits 0-62: Reserved
920 * Bit 63: Unconditional Notify (n) per the XIVE spec
921 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
922 * "ibm,ppc-interrupt-gserver#s"
923 * - R6: "priority" is a valid priority not in
924 * "ibm,plat-res-int-priorities"
925 * - R7: "eventQueue": The logical real address of the start of the EQ
926 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
932 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
934 static target_ulong
h_int_set_queue_config(PowerPCCPU
*cpu
,
935 sPAPRMachineState
*spapr
,
939 sPAPRXive
*xive
= spapr
->xive
;
940 target_ulong flags
= args
[0];
941 target_ulong target
= args
[1];
942 target_ulong priority
= args
[2];
943 target_ulong qpage
= args
[3];
944 target_ulong qsize
= args
[4];
946 uint8_t end_blk
, nvt_blk
;
947 uint32_t end_idx
, nvt_idx
;
949 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
953 if (flags
& ~SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
958 * H_STATE should be returned if a H_INT_RESET is in progress.
959 * This is not needed when running the emulation under QEMU
962 if (spapr_xive_priority_is_reserved(priority
)) {
963 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
964 " is reserved\n", priority
);
969 * Validate that "target" is part of the list of threads allocated
970 * to the partition. For that, find the END corresponding to the
974 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
978 assert(end_idx
< xive
->nr_ends
);
979 memcpy(&end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
986 end
.w2
= cpu_to_be32((qpage
>> 32) & 0x0fffffff);
987 end
.w3
= cpu_to_be32(qpage
& 0xffffffff);
988 end
.w0
|= cpu_to_be32(END_W0_ENQUEUE
);
989 end
.w0
= xive_set_field32(END_W0_QSIZE
, end
.w0
, qsize
- 12);
992 /* reset queue and disable queueing */
993 spapr_xive_end_reset(&end
);
997 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EQ size %"PRIx64
"\n",
1003 hwaddr plen
= 1 << qsize
;
1007 * Validate the guest EQ. We should also check that the queue
1008 * has been zeroed by the OS.
1010 eq
= address_space_map(CPU(cpu
)->as
, qpage
, &plen
, true,
1011 MEMTXATTRS_UNSPECIFIED
);
1012 if (plen
!= 1 << qsize
) {
1013 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to map EQ @0x%"
1014 HWADDR_PRIx
"\n", qpage
);
1017 address_space_unmap(CPU(cpu
)->as
, eq
, plen
, true, plen
);
1020 /* "target" should have been validated above */
1021 if (spapr_xive_target_to_nvt(target
, &nvt_blk
, &nvt_idx
)) {
1022 g_assert_not_reached();
1026 * Ensure the priority and target are correctly set (they will not
1027 * be right after allocation)
1029 end
.w6
= xive_set_field32(END_W6_NVT_BLOCK
, 0ul, nvt_blk
) |
1030 xive_set_field32(END_W6_NVT_INDEX
, 0ul, nvt_idx
);
1031 end
.w7
= xive_set_field32(END_W7_F0_PRIORITY
, 0ul, priority
);
1033 if (flags
& SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1034 end
.w0
|= cpu_to_be32(END_W0_UCOND_NOTIFY
);
1036 end
.w0
&= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY
);
1040 * The generation bit for the END starts at 1 and The END page
1041 * offset counter starts at 0.
1043 end
.w1
= cpu_to_be32(END_W1_GENERATION
) |
1044 xive_set_field32(END_W1_PAGE_OFF
, 0ul, 0ul);
1045 end
.w0
|= cpu_to_be32(END_W0_VALID
);
1048 * TODO: issue syncs required to ensure all in-flight interrupts
1049 * are complete on the old END
1054 memcpy(&xive
->endt
[end_idx
], &end
, sizeof(XiveEND
));
1059 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given
1060 * target and priority.
1065 * Bits 0-62: Reserved
1066 * Bit 63: Debug: Return debug data
1067 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1068 * "ibm,ppc-interrupt-gserver#s"
1069 * - R6: "priority" is a valid priority not in
1070 * "ibm,plat-res-int-priorities"
1074 * Bits 0-61: Reserved
1075 * Bit 62: The value of Event Queue Generation Number (g) per
1076 * the XIVE spec if "Debug" = 1
1077 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec
1078 * - R5: The logical real address of the start of the EQ
1079 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1080 * - R7: The value of Event Queue Offset Counter per XIVE spec
1081 * if "Debug" = 1, else 0
1085 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1087 static target_ulong
h_int_get_queue_config(PowerPCCPU
*cpu
,
1088 sPAPRMachineState
*spapr
,
1089 target_ulong opcode
,
1092 sPAPRXive
*xive
= spapr
->xive
;
1093 target_ulong flags
= args
[0];
1094 target_ulong target
= args
[1];
1095 target_ulong priority
= args
[2];
1100 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1104 if (flags
& ~SPAPR_XIVE_END_DEBUG
) {
1109 * H_STATE should be returned if a H_INT_RESET is in progress.
1110 * This is not needed when running the emulation under QEMU
1113 if (spapr_xive_priority_is_reserved(priority
)) {
1114 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1115 " is reserved\n", priority
);
1120 * Validate that "target" is part of the list of threads allocated
1121 * to the partition. For that, find the END corresponding to the
1124 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1128 assert(end_idx
< xive
->nr_ends
);
1129 end
= &xive
->endt
[end_idx
];
1132 if (xive_end_is_notify(end
)) {
1133 args
[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY
;
1136 if (xive_end_is_enqueue(end
)) {
1137 args
[1] = (uint64_t) be32_to_cpu(end
->w2
& 0x0fffffff) << 32
1138 | be32_to_cpu(end
->w3
);
1139 args
[2] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1145 /* TODO: do we need any locking on the END ? */
1146 if (flags
& SPAPR_XIVE_END_DEBUG
) {
1147 /* Load the event queue generation number into the return flags */
1148 args
[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION
, end
->w1
) << 62;
1150 /* Load R7 with the event queue offset counter */
1151 args
[3] = xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1160 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the
1161 * reporting cache line pair for the calling thread. The reporting
1162 * cache lines will contain the OS interrupt context when the OS
1163 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS
1164 * interrupt. The reporting cache lines can be reset by inputting -1
1165 * in "reportingLine". Issuing the CI store byte without reporting
1166 * cache lines registered will result in the data not being accessible
1172 * Bits 0-63: Reserved
1173 * - R5: "reportingLine": The logical real address of the reporting cache
1179 static target_ulong
h_int_set_os_reporting_line(PowerPCCPU
*cpu
,
1180 sPAPRMachineState
*spapr
,
1181 target_ulong opcode
,
1184 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1189 * H_STATE should be returned if a H_INT_RESET is in progress.
1190 * This is not needed when running the emulation under QEMU
1193 /* TODO: H_INT_SET_OS_REPORTING_LINE */
1198 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical
1199 * real address of the reporting cache line pair set for the input
1200 * "target". If no reporting cache line pair has been set, -1 is
1206 * Bits 0-63: Reserved
1207 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1208 * "ibm,ppc-interrupt-gserver#s"
1209 * - R6: "reportingLine": The logical real address of the reporting
1213 * - R4: The logical real address of the reporting line if set, else -1
1215 static target_ulong
h_int_get_os_reporting_line(PowerPCCPU
*cpu
,
1216 sPAPRMachineState
*spapr
,
1217 target_ulong opcode
,
1220 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1225 * H_STATE should be returned if a H_INT_RESET is in progress.
1226 * This is not needed when running the emulation under QEMU
1229 /* TODO: H_INT_GET_OS_REPORTING_LINE */
1234 * The H_INT_ESB hcall() is used to issue a load or store to the ESB
1235 * page for the input "lisn". This hcall is only supported for LISNs
1236 * that have the ESB hcall flag set to 1 when returned from hcall()
1237 * H_INT_GET_SOURCE_INFO.
1242 * Bits 0-62: Reserved
1243 * bit 63: Store: Store=1, store operation, else load operation
1244 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1245 * "ibm,xive-lisn-ranges" properties, or as returned by the
1246 * ibm,query-interrupt-source-number RTAS call, or as
1247 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1248 * - R6: "esbOffset" is the offset into the ESB page for the load or
1250 * - R7: "storeData" is the data to write for a store operation
1253 * - R4: The value of the load if load operation, else -1
1256 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
1258 static target_ulong
h_int_esb(PowerPCCPU
*cpu
,
1259 sPAPRMachineState
*spapr
,
1260 target_ulong opcode
,
1263 sPAPRXive
*xive
= spapr
->xive
;
1265 target_ulong flags
= args
[0];
1266 target_ulong lisn
= args
[1];
1267 target_ulong offset
= args
[2];
1268 target_ulong data
= args
[3];
1270 XiveSource
*xsrc
= &xive
->source
;
1272 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1276 if (flags
& ~SPAPR_XIVE_ESB_STORE
) {
1280 if (lisn
>= xive
->nr_irqs
) {
1281 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1286 eas
= xive
->eat
[lisn
];
1287 if (!xive_eas_is_valid(&eas
)) {
1288 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1293 if (offset
> (1ull << xsrc
->esb_shift
)) {
1297 mmio_addr
= xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
) + offset
;
1299 if (dma_memory_rw(&address_space_memory
, mmio_addr
, &data
, 8,
1300 (flags
& SPAPR_XIVE_ESB_STORE
))) {
1301 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to access ESB @0x%"
1302 HWADDR_PRIx
"\n", mmio_addr
);
1305 args
[0] = (flags
& SPAPR_XIVE_ESB_STORE
) ? -1 : data
;
1310 * The H_INT_SYNC hcall() is used to issue hardware syncs that will
1311 * ensure any in flight events for the input lisn are in the event
1317 * Bits 0-63: Reserved
1318 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1319 * "ibm,xive-lisn-ranges" properties, or as returned by the
1320 * ibm,query-interrupt-source-number RTAS call, or as
1321 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1326 static target_ulong
h_int_sync(PowerPCCPU
*cpu
,
1327 sPAPRMachineState
*spapr
,
1328 target_ulong opcode
,
1331 sPAPRXive
*xive
= spapr
->xive
;
1333 target_ulong flags
= args
[0];
1334 target_ulong lisn
= args
[1];
1336 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1344 if (lisn
>= xive
->nr_irqs
) {
1345 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1350 eas
= xive
->eat
[lisn
];
1351 if (!xive_eas_is_valid(&eas
)) {
1352 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1358 * H_STATE should be returned if a H_INT_RESET is in progress.
1359 * This is not needed when running the emulation under QEMU
1362 /* This is not real hardware. Nothing to be done */
1367 * The H_INT_RESET hcall() is used to reset all of the partition's
1368 * interrupt exploitation structures to their initial state. This
1369 * means losing all previously set interrupt state set via
1370 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
1375 * Bits 0-63: Reserved
1380 static target_ulong
h_int_reset(PowerPCCPU
*cpu
,
1381 sPAPRMachineState
*spapr
,
1382 target_ulong opcode
,
1385 sPAPRXive
*xive
= spapr
->xive
;
1386 target_ulong flags
= args
[0];
1388 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1396 device_reset(DEVICE(xive
));
1400 void spapr_xive_hcall_init(sPAPRMachineState
*spapr
)
1402 spapr_register_hypercall(H_INT_GET_SOURCE_INFO
, h_int_get_source_info
);
1403 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG
, h_int_set_source_config
);
1404 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG
, h_int_get_source_config
);
1405 spapr_register_hypercall(H_INT_GET_QUEUE_INFO
, h_int_get_queue_info
);
1406 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG
, h_int_set_queue_config
);
1407 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG
, h_int_get_queue_config
);
1408 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE
,
1409 h_int_set_os_reporting_line
);
1410 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE
,
1411 h_int_get_os_reporting_line
);
1412 spapr_register_hypercall(H_INT_ESB
, h_int_esb
);
1413 spapr_register_hypercall(H_INT_SYNC
, h_int_sync
);
1414 spapr_register_hypercall(H_INT_RESET
, h_int_reset
);
1417 void spapr_dt_xive(sPAPRMachineState
*spapr
, uint32_t nr_servers
, void *fdt
,
1420 sPAPRXive
*xive
= spapr
->xive
;
1422 uint64_t timas
[2 * 2];
1423 /* Interrupt number ranges for the IPIs */
1424 uint32_t lisn_ranges
[] = {
1426 cpu_to_be32(nr_servers
),
1429 * EQ size - the sizes of pages supported by the system 4K, 64K,
1430 * 2M, 16M. We only advertise 64K for the moment.
1432 uint32_t eq_sizes
[] = {
1433 cpu_to_be32(16), /* 64K */
1436 * The following array is in sync with the reserved priorities
1437 * defined by the 'spapr_xive_priority_is_reserved' routine.
1439 uint32_t plat_res_int_priorities
[] = {
1440 cpu_to_be32(7), /* start */
1441 cpu_to_be32(0xf8), /* count */
1445 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */
1446 timas
[0] = cpu_to_be64(xive
->tm_base
+
1447 XIVE_TM_USER_PAGE
* (1ull << TM_SHIFT
));
1448 timas
[1] = cpu_to_be64(1ull << TM_SHIFT
);
1449 timas
[2] = cpu_to_be64(xive
->tm_base
+
1450 XIVE_TM_OS_PAGE
* (1ull << TM_SHIFT
));
1451 timas
[3] = cpu_to_be64(1ull << TM_SHIFT
);
1453 nodename
= g_strdup_printf("interrupt-controller@%" PRIx64
,
1454 xive
->tm_base
+ XIVE_TM_USER_PAGE
* (1 << TM_SHIFT
));
1455 _FDT(node
= fdt_add_subnode(fdt
, 0, nodename
));
1458 _FDT(fdt_setprop_string(fdt
, node
, "device_type", "power-ivpe"));
1459 _FDT(fdt_setprop(fdt
, node
, "reg", timas
, sizeof(timas
)));
1461 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "ibm,power-ivpe"));
1462 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-eq-sizes", eq_sizes
,
1464 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-lisn-ranges", lisn_ranges
,
1465 sizeof(lisn_ranges
)));
1467 /* For Linux to link the LSIs to the interrupt controller. */
1468 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
1469 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
1472 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
1473 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));
1476 * The "ibm,plat-res-int-priorities" property defines the priority
1477 * ranges reserved by the hypervisor
1479 _FDT(fdt_setprop(fdt
, 0, "ibm,plat-res-int-priorities",
1480 plat_res_int_priorities
, sizeof(plat_res_int_priorities
)));