target/arm/gdbstub.c

   1 /*
   2  * ARM gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2013 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "exec/gdbstub.h"
  23
  24 typedef struct RegisterSysregXmlParam {
  25     CPUState *cs;
  26     GString *s;
  27     int n;
  28 } RegisterSysregXmlParam;
  29
  30 /* Old gdb always expect FPA registers.  Newer (xml-aware) gdb only expect
  31    whatever the target description contains.  Due to a historical mishap
  32    the FPA registers appear in between core integer regs and the CPSR.
  33    We hack round this by giving the FPA regs zero size when talking to a
  34    newer gdb.  */
  35
  36 int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
  37 {
  38     ARMCPU *cpu = ARM_CPU(cs);
  39     CPUARMState *env = &cpu->env;
  40
  41     if (n < 16) {
  42         /* Core integer register.  */
  43         return gdb_get_reg32(mem_buf, env->regs[n]);
  44     }
  45     if (n < 24) {
  46         /* FPA registers.  */
  47         if (gdb_has_xml) {
  48             return 0;
  49         }
  50         return gdb_get_zeroes(mem_buf, 12);
  51     }
  52     switch (n) {
  53     case 24:
  54         /* FPA status register.  */
  55         if (gdb_has_xml) {
  56             return 0;
  57         }
  58         return gdb_get_reg32(mem_buf, 0);
  59     case 25:
  60         /* CPSR, or XPSR for M-profile */
  61         if (arm_feature(env, ARM_FEATURE_M)) {
  62             return gdb_get_reg32(mem_buf, xpsr_read(env));
  63         } else {
  64             return gdb_get_reg32(mem_buf, cpsr_read(env));
  65         }
  66     }
  67     /* Unknown register.  */
  68     return 0;
  69 }
  70
  71 int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
  72 {
  73     ARMCPU *cpu = ARM_CPU(cs);
  74     CPUARMState *env = &cpu->env;
  75     uint32_t tmp;
  76
  77     tmp = ldl_p(mem_buf);
  78
  79     /* Mask out low bit of PC to workaround gdb bugs.  This will probably
  80        cause problems if we ever implement the Jazelle DBX extensions.  */
  81     if (n == 15) {
  82         tmp &= ~1;
  83     }
  84
  85     if (n < 16) {
  86         /* Core integer register.  */
  87         env->regs[n] = tmp;
  88         return 4;
  89     }
  90     if (n < 24) { /* 16-23 */
  91         /* FPA registers (ignored).  */
  92         if (gdb_has_xml) {
  93             return 0;
  94         }
  95         return 12;
  96     }
  97     switch (n) {
  98     case 24:
  99         /* FPA status register (ignored).  */
 100         if (gdb_has_xml) {
 101             return 0;
 102         }
 103         return 4;
 104     case 25:
 105         /* CPSR, or XPSR for M-profile */
 106         if (arm_feature(env, ARM_FEATURE_M)) {
 107             /*
 108              * Don't allow writing to XPSR.Exception as it can cause
 109              * a transition into or out of handler mode (it's not
 110              * writeable via the MSR insn so this is a reasonable
 111              * restriction). Other fields are safe to update.
 112              */
 113             xpsr_write(env, tmp, ~XPSR_EXCP);
 114         } else {
 115             cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub);
 116         }
 117         return 4;
 118     }
 119     /* Unknown register.  */
 120     return 0;
 121 }
 122
 123 static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
 124                                        ARMCPRegInfo *ri, uint32_t ri_key,
 125                                        int bitsize, int regnum)
 126 {
 127     g_string_append_printf(s, "<reg name=\"%s\"", ri->name);
 128     g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
 129     g_string_append_printf(s, " regnum=\"%d\"", regnum);
 130     g_string_append_printf(s, " group=\"cp_regs\"/>");
 131     dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key;
 132     dyn_xml->num++;
 133 }
 134
 135 static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
 136                                         gpointer p)
 137 {
 138     uint32_t ri_key = *(uint32_t *)key;
 139     ARMCPRegInfo *ri = value;
 140     RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
 141     GString *s = param->s;
 142     ARMCPU *cpu = ARM_CPU(param->cs);
 143     CPUARMState *env = &cpu->env;
 144     DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_sysreg_xml;
 145
 146     if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) {
 147         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 148             if (ri->state == ARM_CP_STATE_AA64) {
 149                 arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
 150                                            param->n++);
 151             }
 152         } else {
 153             if (ri->state == ARM_CP_STATE_AA32) {
 154                 if (!arm_feature(env, ARM_FEATURE_EL3) &&
 155                     (ri->secure & ARM_CP_SECSTATE_S)) {
 156                     return;
 157                 }
 158                 if (ri->type & ARM_CP_64BIT) {
 159                     arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
 160                                                param->n++);
 161                 } else {
 162                     arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32,
 163                                                param->n++);
 164                 }
 165             }
 166         }
 167     }
 168 }
 169
 170 int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
 171 {
 172     ARMCPU *cpu = ARM_CPU(cs);
 173     GString *s = g_string_new(NULL);
 174     RegisterSysregXmlParam param = {cs, s, base_reg};
 175
 176     cpu->dyn_sysreg_xml.num = 0;
 177     cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
 178     g_string_printf(s, "<?xml version=\"1.0\"?>");
 179     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 180     g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
 181     g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, &param);
 182     g_string_append_printf(s, "</feature>");
 183     cpu->dyn_sysreg_xml.desc = g_string_free(s, false);
 184     return cpu->dyn_sysreg_xml.num;
 185 }
 186
 187 struct TypeSize {
 188     const char *gdb_type;
 189     int  size;
 190     const char sz, suffix;
 191 };
 192
 193 static const struct TypeSize vec_lanes[] = {
 194     /* quads */
 195     { "uint128", 128, 'q', 'u' },
 196     { "int128", 128, 'q', 's' },
 197     /* 64 bit */
 198     { "uint64", 64, 'd', 'u' },
 199     { "int64", 64, 'd', 's' },
 200     { "ieee_double", 64, 'd', 'f' },
 201     /* 32 bit */
 202     { "uint32", 32, 's', 'u' },
 203     { "int32", 32, 's', 's' },
 204     { "ieee_single", 32, 's', 'f' },
 205     /* 16 bit */
 206     { "uint16", 16, 'h', 'u' },
 207     { "int16", 16, 'h', 's' },
 208     /*
 209      * TODO: currently there is no reliable way of telling
 210      * if the remote gdb actually understands ieee_half so
 211      * we don't expose it in the target description for now.
 212      * { "ieee_half", 16, 'h', 'f' },
 213      */
 214     /* bytes */
 215     { "uint8", 8, 'b', 'u' },
 216     { "int8", 8, 'b', 's' },
 217 };
 218
 219
 220 int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
 221 {
 222     ARMCPU *cpu = ARM_CPU(cs);
 223     GString *s = g_string_new(NULL);
 224     DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
 225     g_autoptr(GString) ts = g_string_new("");
 226     int i, bits, reg_width = (cpu->sve_max_vq * 128);
 227     info->num = 0;
 228     g_string_printf(s, "<?xml version=\"1.0\"?>");
 229     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
 230     g_string_append_printf(s, "<feature name=\"org.qemu.gdb.aarch64.sve\">");
 231
 232     /* First define types and totals in a whole VL */
 233     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 234         int count = reg_width / vec_lanes[i].size;
 235         g_string_printf(ts, "vq%d%c%c", count,
 236                         vec_lanes[i].sz, vec_lanes[i].suffix);
 237         g_string_append_printf(s,
 238                                "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
 239                                ts->str, vec_lanes[i].gdb_type, count);
 240     }
 241     /*
 242      * Now define a union for each size group containing unsigned and
 243      * signed and potentially float versions of each size from 128 to
 244      * 8 bits.
 245      */
 246     for (bits = 128; bits >= 8; bits /= 2) {
 247         int count = reg_width / bits;
 248         g_string_append_printf(s, "<union id=\"vq%dn\">", count);
 249         for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 250             if (vec_lanes[i].size == bits) {
 251                 g_string_append_printf(s, "<field name=\"%c\" type=\"vq%d%c%c\"/>",
 252                                        vec_lanes[i].suffix,
 253                                        count,
 254                                        vec_lanes[i].sz, vec_lanes[i].suffix);
 255             }
 256         }
 257         g_string_append(s, "</union>");
 258     }
 259     /* And now the final union of unions */
 260     g_string_append(s, "<union id=\"vq\">");
 261     for (bits = 128; bits >= 8; bits /= 2) {
 262         int count = reg_width / bits;
 263         for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
 264             if (vec_lanes[i].size == bits) {
 265                 g_string_append_printf(s, "<field name=\"%c\" type=\"vq%dn\"/>",
 266                                        vec_lanes[i].sz, count);
 267                 break;
 268             }
 269         }
 270     }
 271     g_string_append(s, "</union>");
 272
 273     /* Then define each register in parts for each vq */
 274     for (i = 0; i < 32; i++) {
 275         g_string_append_printf(s,
 276                                "<reg name=\"z%d\" bitsize=\"%d\""
 277                                " regnum=\"%d\" group=\"vector\""
 278                                " type=\"vq\"/>",
 279                                i, reg_width, base_reg++);
 280         info->num++;
 281     }
 282     /* fpscr & status registers */
 283     g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
 284                            " regnum=\"%d\" group=\"float\""
 285                            " type=\"int\"/>", base_reg++);
 286     g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
 287                            " regnum=\"%d\" group=\"float\""
 288                            " type=\"int\"/>", base_reg++);
 289     info->num += 2;
 290     /*
 291      * Predicate registers aren't so big they are worth splitting up
 292      * but we do need to define a type to hold the array of quad
 293      * references.
 294      */
 295     g_string_append_printf(s,
 296                            "<vector id=\"vqp\" type=\"uint16\" count=\"%d\"/>",
 297                            cpu->sve_max_vq);
 298     for (i = 0; i < 16; i++) {
 299         g_string_append_printf(s,
 300                                "<reg name=\"p%d\" bitsize=\"%d\""
 301                                " regnum=\"%d\" group=\"vector\""
 302                                " type=\"vqp\"/>",
 303                                i, cpu->sve_max_vq * 16, base_reg++);
 304         info->num++;
 305     }
 306     g_string_append_printf(s,
 307                            "<reg name=\"ffr\" bitsize=\"%d\""
 308                            " regnum=\"%d\" group=\"vector\""
 309                            " type=\"vqp\"/>",
 310                            cpu->sve_max_vq * 16, base_reg++);
 311     g_string_append_printf(s,
 312                            "<reg name=\"vg\" bitsize=\"64\""
 313                            " regnum=\"%d\" group=\"vector\""
 314                            " type=\"uint32\"/>",
 315                            base_reg++);
 316     info->num += 2;
 317     g_string_append_printf(s, "</feature>");
 318     cpu->dyn_svereg_xml.desc = g_string_free(s, false);
 319
 320     return cpu->dyn_svereg_xml.num;
 321 }
 322
 323
 324 const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 325 {
 326     ARMCPU *cpu = ARM_CPU(cs);
 327
 328     if (strcmp(xmlname, "system-registers.xml") == 0) {
 329         return cpu->dyn_sysreg_xml.desc;
 330     } else if (strcmp(xmlname, "sve-registers.xml") == 0) {
 331         return cpu->dyn_svereg_xml.desc;
 332     }
 333     return NULL;
 334 }