4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
29 #include "internals.h"
30 #include "exec/exec-all.h"
31 #include "hw/qdev-properties.h"
32 #if !defined(CONFIG_USER_ONLY)
33 #include "hw/loader.h"
34 #include "hw/boards.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/hw_accel.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
43 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
45 ARMCPU
*cpu
= ARM_CPU(cs
);
46 CPUARMState
*env
= &cpu
->env
;
52 env
->regs
[15] = value
& ~1;
53 env
->thumb
= value
& 1;
57 static void arm_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
59 ARMCPU
*cpu
= ARM_CPU(cs
);
60 CPUARMState
*env
= &cpu
->env
;
63 * It's OK to look at env for the current mode here, because it's
64 * never possible for an AArch64 TB to chain to an AArch32 TB.
69 env
->regs
[15] = tb
->pc
;
73 static bool arm_cpu_has_work(CPUState
*cs
)
75 ARMCPU
*cpu
= ARM_CPU(cs
);
77 return (cpu
->power_state
!= PSCI_OFF
)
78 && cs
->interrupt_request
&
79 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
80 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
81 | CPU_INTERRUPT_EXITTB
);
84 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
87 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
90 entry
->opaque
= opaque
;
92 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
95 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
98 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
101 entry
->opaque
= opaque
;
103 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
106 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
108 /* Reset a single ARMCPRegInfo register */
109 ARMCPRegInfo
*ri
= value
;
110 ARMCPU
*cpu
= opaque
;
112 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
117 ri
->resetfn(&cpu
->env
, ri
);
121 /* A zero offset is never possible as it would be regs[0]
122 * so we use it to indicate that reset is being handled elsewhere.
123 * This is basically only used for fields in non-core coprocessors
124 * (like the pxa2xx ones).
126 if (!ri
->fieldoffset
) {
130 if (cpreg_field_is_64bit(ri
)) {
131 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
133 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
137 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
139 /* Purely an assertion check: we've already done reset once,
140 * so now check that running the reset for the cpreg doesn't
141 * change its value. This traps bugs where two different cpregs
142 * both try to reset the same state field but to different values.
144 ARMCPRegInfo
*ri
= value
;
145 ARMCPU
*cpu
= opaque
;
146 uint64_t oldvalue
, newvalue
;
148 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
152 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
153 cp_reg_reset(key
, value
, opaque
);
154 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
155 assert(oldvalue
== newvalue
);
158 static void arm_cpu_reset(DeviceState
*dev
)
160 CPUState
*s
= CPU(dev
);
161 ARMCPU
*cpu
= ARM_CPU(s
);
162 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
163 CPUARMState
*env
= &cpu
->env
;
165 acc
->parent_reset(dev
);
167 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
169 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
170 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
172 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
173 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
174 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
175 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
177 cpu
->power_state
= s
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
179 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
180 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
183 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
184 /* 64 bit CPUs always start in 64 bit mode */
186 #if defined(CONFIG_USER_ONLY)
187 env
->pstate
= PSTATE_MODE_EL0t
;
188 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
189 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
190 /* Enable all PAC keys. */
191 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
192 SCTLR_EnDA
| SCTLR_EnDB
);
193 /* and to the FP/Neon instructions */
194 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
195 /* and to the SVE instructions */
196 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
197 /* with reasonable vector length */
198 if (cpu_isar_feature(aa64_sve
, cpu
)) {
199 env
->vfp
.zcr_el
[1] = MIN(cpu
->sve_max_vq
- 1, 3);
202 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
203 * turning on both here will produce smaller code and otherwise
204 * make no difference to the user-level emulation.
206 * In sve_probe_page, we assume that this is set.
207 * Do not modify this without other changes.
209 env
->cp15
.tcr_el
[1].raw_tcr
= (3ULL << 37);
211 /* Reset into the highest available EL */
212 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
213 env
->pstate
= PSTATE_MODE_EL3h
;
214 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
215 env
->pstate
= PSTATE_MODE_EL2h
;
217 env
->pstate
= PSTATE_MODE_EL1h
;
219 env
->pc
= cpu
->rvbar
;
222 #if defined(CONFIG_USER_ONLY)
223 /* Userspace expects access to cp10 and cp11 for FP/Neon */
224 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
228 #if defined(CONFIG_USER_ONLY)
229 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
230 /* For user mode we must enable access to coprocessors */
231 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
232 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
233 env
->cp15
.c15_cpar
= 3;
234 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
235 env
->cp15
.c15_cpar
= 1;
240 * If the highest available EL is EL2, AArch32 will start in Hyp
241 * mode; otherwise it starts in SVC. Note that if we start in
242 * AArch64 then these values in the uncached_cpsr will be ignored.
244 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
245 !arm_feature(env
, ARM_FEATURE_EL3
)) {
246 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
248 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
250 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
252 if (arm_feature(env
, ARM_FEATURE_M
)) {
253 uint32_t initial_msp
; /* Loaded from 0x0 */
254 uint32_t initial_pc
; /* Loaded from 0x4 */
258 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
259 env
->v7m
.secure
= true;
261 /* This bit resets to 0 if security is supported, but 1 if
262 * it is not. The bit is not present in v7M, but we set it
263 * here so we can avoid having to make checks on it conditional
264 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
266 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
268 * Set NSACR to indicate "NS access permitted to everything";
269 * this avoids having to have all the tests of it being
270 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
271 * v8.1M the guest-visible value of NSACR in a CPU without the
272 * Security Extension is 0xcff.
274 env
->v7m
.nsacr
= 0xcff;
277 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
278 * that it resets to 1, so QEMU always does that rather than making
279 * it dependent on CPU model. In v8M it is RES1.
281 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
282 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
283 if (arm_feature(env
, ARM_FEATURE_V8
)) {
284 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
285 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
286 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
288 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
289 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
290 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
293 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
294 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
295 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
296 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
298 /* Unlike A/R profile, M profile defines the reset LR value */
299 env
->regs
[14] = 0xffffffff;
301 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
303 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
304 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
305 rom
= rom_ptr(vecbase
, 8);
307 /* Address zero is covered by ROM which hasn't yet been
308 * copied into physical memory.
310 initial_msp
= ldl_p(rom
);
311 initial_pc
= ldl_p(rom
+ 4);
313 /* Address zero not covered by a ROM blob, or the ROM blob
314 * is in non-modifiable memory and this is a second reset after
315 * it got copied into memory. In the latter case, rom_ptr
316 * will return a NULL pointer and we should use ldl_phys instead.
318 initial_msp
= ldl_phys(s
->as
, vecbase
);
319 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
322 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
323 env
->regs
[15] = initial_pc
& ~1;
324 env
->thumb
= initial_pc
& 1;
327 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
328 * executing as AArch32 then check if highvecs are enabled and
329 * adjust the PC accordingly.
331 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
332 env
->regs
[15] = 0xFFFF0000;
335 /* M profile requires that reset clears the exclusive monitor;
336 * A profile does not, but clearing it makes more sense than having it
337 * set with an exclusive access on address zero.
339 arm_clear_exclusive(env
);
341 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
344 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
345 if (cpu
->pmsav7_dregion
> 0) {
346 if (arm_feature(env
, ARM_FEATURE_V8
)) {
347 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
348 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
349 * cpu
->pmsav7_dregion
);
350 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
351 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
352 * cpu
->pmsav7_dregion
);
353 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
354 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
355 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
356 * cpu
->pmsav7_dregion
);
357 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
358 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
359 * cpu
->pmsav7_dregion
);
361 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
362 memset(env
->pmsav7
.drbar
, 0,
363 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
364 memset(env
->pmsav7
.drsr
, 0,
365 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
366 memset(env
->pmsav7
.dracr
, 0,
367 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
370 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
371 env
->pmsav7
.rnr
[M_REG_S
] = 0;
372 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
373 env
->pmsav8
.mair0
[M_REG_S
] = 0;
374 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
375 env
->pmsav8
.mair1
[M_REG_S
] = 0;
378 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
379 if (cpu
->sau_sregion
> 0) {
380 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
381 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
384 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
385 * the Cortex-M33 does.
390 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
391 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
392 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
393 set_default_nan_mode(1, &env
->vfp
.standard_fp_status_f16
);
394 set_float_detect_tininess(float_tininess_before_rounding
,
395 &env
->vfp
.fp_status
);
396 set_float_detect_tininess(float_tininess_before_rounding
,
397 &env
->vfp
.standard_fp_status
);
398 set_float_detect_tininess(float_tininess_before_rounding
,
399 &env
->vfp
.fp_status_f16
);
400 set_float_detect_tininess(float_tininess_before_rounding
,
401 &env
->vfp
.standard_fp_status_f16
);
402 #ifndef CONFIG_USER_ONLY
404 kvm_arm_reset_vcpu(cpu
);
408 hw_breakpoint_update_all(cpu
);
409 hw_watchpoint_update_all(cpu
);
410 arm_rebuild_hflags(env
);
413 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
414 unsigned int target_el
,
415 unsigned int cur_el
, bool secure
,
418 CPUARMState
*env
= cs
->env_ptr
;
419 bool pstate_unmasked
;
420 bool unmasked
= false;
423 * Don't take exceptions if they target a lower EL.
424 * This check should catch any exceptions that would not be taken
427 if (cur_el
> target_el
) {
433 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
437 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
441 if (secure
|| !(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
442 /* VFIQs are only taken when hypervized and non-secure. */
445 return !(env
->daif
& PSTATE_F
);
447 if (secure
|| !(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
448 /* VIRQs are only taken when hypervized and non-secure. */
451 return !(env
->daif
& PSTATE_I
);
453 g_assert_not_reached();
457 * Use the target EL, current execution state and SCR/HCR settings to
458 * determine whether the corresponding CPSR bit is used to mask the
461 if ((target_el
> cur_el
) && (target_el
!= 1)) {
462 /* Exceptions targeting a higher EL may not be maskable */
463 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
465 * 64-bit masking rules are simple: exceptions to EL3
466 * can't be masked, and exceptions to EL2 can only be
467 * masked from Secure state. The HCR and SCR settings
468 * don't affect the masking logic, only the interrupt routing.
470 if (target_el
== 3 || !secure
) {
475 * The old 32-bit-only environment has a more complicated
476 * masking setup. HCR and SCR bits not only affect interrupt
477 * routing but also change the behaviour of masking.
484 * If FIQs are routed to EL3 or EL2 then there are cases where
485 * we override the CPSR.F in determining if the exception is
486 * masked or not. If neither of these are set then we fall back
487 * to the CPSR.F setting otherwise we further assess the state
490 hcr
= hcr_el2
& HCR_FMO
;
491 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
494 * When EL3 is 32-bit, the SCR.FW bit controls whether the
495 * CPSR.F bit masks FIQ interrupts when taken in non-secure
496 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
497 * when non-secure but only when FIQs are only routed to EL3.
499 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
503 * When EL3 execution state is 32-bit, if HCR.IMO is set then
504 * we may override the CPSR.I masking when in non-secure state.
505 * The SCR.IRQ setting has already been taken into consideration
506 * when setting the target EL, so it does not have a further
509 hcr
= hcr_el2
& HCR_IMO
;
513 g_assert_not_reached();
516 if ((scr
|| hcr
) && !secure
) {
523 * The PSTATE bits only mask the interrupt if we have not overriden the
526 return unmasked
|| pstate_unmasked
;
529 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
531 CPUClass
*cc
= CPU_GET_CLASS(cs
);
532 CPUARMState
*env
= cs
->env_ptr
;
533 uint32_t cur_el
= arm_current_el(env
);
534 bool secure
= arm_is_secure(env
);
535 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
539 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
541 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
543 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
544 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
545 cur_el
, secure
, hcr_el2
)) {
549 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
551 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
552 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
553 cur_el
, secure
, hcr_el2
)) {
557 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
558 excp_idx
= EXCP_VIRQ
;
560 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
561 cur_el
, secure
, hcr_el2
)) {
565 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
566 excp_idx
= EXCP_VFIQ
;
568 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
569 cur_el
, secure
, hcr_el2
)) {
576 cs
->exception_index
= excp_idx
;
577 env
->exception
.target_el
= target_el
;
578 cc
->do_interrupt(cs
);
582 void arm_cpu_update_virq(ARMCPU
*cpu
)
585 * Update the interrupt level for VIRQ, which is the logical OR of
586 * the HCR_EL2.VI bit and the input line level from the GIC.
588 CPUARMState
*env
= &cpu
->env
;
589 CPUState
*cs
= CPU(cpu
);
591 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
592 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
594 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
596 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
598 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
603 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
606 * Update the interrupt level for VFIQ, which is the logical OR of
607 * the HCR_EL2.VF bit and the input line level from the GIC.
609 CPUARMState
*env
= &cpu
->env
;
610 CPUState
*cs
= CPU(cpu
);
612 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
613 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
615 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
617 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
619 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
624 #ifndef CONFIG_USER_ONLY
625 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
627 ARMCPU
*cpu
= opaque
;
628 CPUARMState
*env
= &cpu
->env
;
629 CPUState
*cs
= CPU(cpu
);
630 static const int mask
[] = {
631 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
632 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
633 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
634 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
638 env
->irq_line_state
|= mask
[irq
];
640 env
->irq_line_state
&= ~mask
[irq
];
645 assert(arm_feature(env
, ARM_FEATURE_EL2
));
646 arm_cpu_update_virq(cpu
);
649 assert(arm_feature(env
, ARM_FEATURE_EL2
));
650 arm_cpu_update_vfiq(cpu
);
655 cpu_interrupt(cs
, mask
[irq
]);
657 cpu_reset_interrupt(cs
, mask
[irq
]);
661 g_assert_not_reached();
665 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
668 ARMCPU
*cpu
= opaque
;
669 CPUARMState
*env
= &cpu
->env
;
670 CPUState
*cs
= CPU(cpu
);
671 uint32_t linestate_bit
;
676 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
677 linestate_bit
= CPU_INTERRUPT_HARD
;
680 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
681 linestate_bit
= CPU_INTERRUPT_FIQ
;
684 g_assert_not_reached();
688 env
->irq_line_state
|= linestate_bit
;
690 env
->irq_line_state
&= ~linestate_bit
;
692 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
696 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
698 ARMCPU
*cpu
= ARM_CPU(cs
);
699 CPUARMState
*env
= &cpu
->env
;
701 cpu_synchronize_state(cs
);
702 return arm_cpu_data_is_big_endian(env
);
708 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
710 return print_insn_arm(pc
| 1, info
);
713 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
715 ARMCPU
*ac
= ARM_CPU(cpu
);
716 CPUARMState
*env
= &ac
->env
;
720 /* We might not be compiled with the A64 disassembler
721 * because it needs a C++ compiler. Leave print_insn
722 * unset in this case to use the caller default behaviour.
724 #if defined(CONFIG_ARM_A64_DIS)
725 info
->print_insn
= print_insn_arm_a64
;
727 info
->cap_arch
= CS_ARCH_ARM64
;
728 info
->cap_insn_unit
= 4;
729 info
->cap_insn_split
= 4;
733 info
->print_insn
= print_insn_thumb1
;
734 info
->cap_insn_unit
= 2;
735 info
->cap_insn_split
= 4;
736 cap_mode
= CS_MODE_THUMB
;
738 info
->print_insn
= print_insn_arm
;
739 info
->cap_insn_unit
= 4;
740 info
->cap_insn_split
= 4;
741 cap_mode
= CS_MODE_ARM
;
743 if (arm_feature(env
, ARM_FEATURE_V8
)) {
744 cap_mode
|= CS_MODE_V8
;
746 if (arm_feature(env
, ARM_FEATURE_M
)) {
747 cap_mode
|= CS_MODE_MCLASS
;
749 info
->cap_arch
= CS_ARCH_ARM
;
750 info
->cap_mode
= cap_mode
;
753 sctlr_b
= arm_sctlr_b(env
);
754 if (bswap_code(sctlr_b
)) {
755 #ifdef TARGET_WORDS_BIGENDIAN
756 info
->endian
= BFD_ENDIAN_LITTLE
;
758 info
->endian
= BFD_ENDIAN_BIG
;
761 info
->flags
&= ~INSN_ARM_BE32
;
762 #ifndef CONFIG_USER_ONLY
764 info
->flags
|= INSN_ARM_BE32
;
769 #ifdef TARGET_AARCH64
771 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
773 ARMCPU
*cpu
= ARM_CPU(cs
);
774 CPUARMState
*env
= &cpu
->env
;
775 uint32_t psr
= pstate_read(env
);
777 int el
= arm_current_el(env
);
778 const char *ns_status
;
780 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
781 for (i
= 0; i
< 32; i
++) {
783 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
785 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
786 (i
+ 2) % 3 ? " " : "\n");
790 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
791 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
795 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
797 psr
& PSTATE_N
? 'N' : '-',
798 psr
& PSTATE_Z
? 'Z' : '-',
799 psr
& PSTATE_C
? 'C' : '-',
800 psr
& PSTATE_V
? 'V' : '-',
803 psr
& PSTATE_SP
? 'h' : 't');
805 if (cpu_isar_feature(aa64_bti
, cpu
)) {
806 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
808 if (!(flags
& CPU_DUMP_FPU
)) {
809 qemu_fprintf(f
, "\n");
812 if (fp_exception_el(env
, el
) != 0) {
813 qemu_fprintf(f
, " FPU disabled\n");
816 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
817 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
819 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
820 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
822 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
824 if (i
== FFR_PRED_NUM
) {
825 qemu_fprintf(f
, "FFR=");
826 /* It's last, so end the line. */
829 qemu_fprintf(f
, "P%02d=", i
);
842 /* More than one quadword per predicate. */
847 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
849 if (j
* 4 + 4 <= zcr_len
+ 1) {
852 digits
= (zcr_len
% 4 + 1) * 4;
854 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
855 env
->vfp
.pregs
[i
].p
[j
],
856 j
? ":" : eol
? "\n" : " ");
860 for (i
= 0; i
< 32; i
++) {
862 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
863 i
, env
->vfp
.zregs
[i
].d
[1],
864 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
865 } else if (zcr_len
== 1) {
866 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
867 ":%016" PRIx64
":%016" PRIx64
"\n",
868 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
869 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
871 for (j
= zcr_len
; j
>= 0; j
--) {
872 bool odd
= (zcr_len
- j
) % 2 != 0;
874 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
877 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
879 qemu_fprintf(f
, " [%x]=", j
);
882 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
883 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
884 env
->vfp
.zregs
[i
].d
[j
* 2],
885 odd
|| j
== 0 ? "\n" : ":");
890 for (i
= 0; i
< 32; i
++) {
891 uint64_t *q
= aa64_vfp_qreg(env
, i
);
892 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
893 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
900 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
902 g_assert_not_reached();
907 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
909 ARMCPU
*cpu
= ARM_CPU(cs
);
910 CPUARMState
*env
= &cpu
->env
;
914 aarch64_cpu_dump_state(cs
, f
, flags
);
918 for (i
= 0; i
< 16; i
++) {
919 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
921 qemu_fprintf(f
, "\n");
923 qemu_fprintf(f
, " ");
927 if (arm_feature(env
, ARM_FEATURE_M
)) {
928 uint32_t xpsr
= xpsr_read(env
);
930 const char *ns_status
= "";
932 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
933 ns_status
= env
->v7m
.secure
? "S " : "NS ";
936 if (xpsr
& XPSR_EXCP
) {
939 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
940 mode
= "unpriv-thread";
942 mode
= "priv-thread";
946 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
948 xpsr
& XPSR_N
? 'N' : '-',
949 xpsr
& XPSR_Z
? 'Z' : '-',
950 xpsr
& XPSR_C
? 'C' : '-',
951 xpsr
& XPSR_V
? 'V' : '-',
952 xpsr
& XPSR_T
? 'T' : 'A',
956 uint32_t psr
= cpsr_read(env
);
957 const char *ns_status
= "";
959 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
960 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
961 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
964 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
966 psr
& CPSR_N
? 'N' : '-',
967 psr
& CPSR_Z
? 'Z' : '-',
968 psr
& CPSR_C
? 'C' : '-',
969 psr
& CPSR_V
? 'V' : '-',
970 psr
& CPSR_T
? 'T' : 'A',
972 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
975 if (flags
& CPU_DUMP_FPU
) {
977 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
979 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
982 for (i
= 0; i
< numvfpregs
; i
++) {
983 uint64_t v
= *aa32_vfp_dreg(env
, i
);
984 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
986 i
* 2 + 1, (uint32_t)(v
>> 32),
989 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
993 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
995 uint32_t Aff1
= idx
/ clustersz
;
996 uint32_t Aff0
= idx
% clustersz
;
997 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1000 static void cpreg_hashtable_data_destroy(gpointer data
)
1003 * Destroy function for cpu->cp_regs hashtable data entries.
1004 * We must free the name string because it was g_strdup()ed in
1005 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1006 * from r->name because we know we definitely allocated it.
1008 ARMCPRegInfo
*r
= data
;
1010 g_free((void *)r
->name
);
1014 static void arm_cpu_initfn(Object
*obj
)
1016 ARMCPU
*cpu
= ARM_CPU(obj
);
1018 cpu_set_cpustate_pointers(cpu
);
1019 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
1020 g_free
, cpreg_hashtable_data_destroy
);
1022 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1023 QLIST_INIT(&cpu
->el_change_hooks
);
1025 #ifndef CONFIG_USER_ONLY
1026 /* Our inbound IRQ and FIQ lines */
1027 if (kvm_enabled()) {
1028 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1029 * the same interface as non-KVM CPUs.
1031 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1033 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1036 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1037 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1039 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1040 "gicv3-maintenance-interrupt", 1);
1041 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1042 "pmu-interrupt", 1);
1045 /* DTB consumers generally don't in fact care what the 'compatible'
1046 * string is, so always provide some string and trust that a hypothetical
1047 * picky DTB consumer will also provide a helpful error message.
1049 cpu
->dtb_compatible
= "qemu,unknown";
1050 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
1051 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1053 if (tcg_enabled()) {
1054 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
1058 static Property arm_cpu_gt_cntfrq_property
=
1059 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1060 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1062 static Property arm_cpu_reset_cbar_property
=
1063 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1065 static Property arm_cpu_reset_hivecs_property
=
1066 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1068 static Property arm_cpu_rvbar_property
=
1069 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
1071 #ifndef CONFIG_USER_ONLY
1072 static Property arm_cpu_has_el2_property
=
1073 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1075 static Property arm_cpu_has_el3_property
=
1076 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1079 static Property arm_cpu_cfgend_property
=
1080 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1082 static Property arm_cpu_has_vfp_property
=
1083 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1085 static Property arm_cpu_has_neon_property
=
1086 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1088 static Property arm_cpu_has_dsp_property
=
1089 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1091 static Property arm_cpu_has_mpu_property
=
1092 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1094 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1095 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1096 * the right value for that particular CPU type, and we don't want
1097 * to override that with an incorrect constant value.
1099 static Property arm_cpu_pmsav7_dregion_property
=
1100 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1102 qdev_prop_uint32
, uint32_t);
1104 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1106 ARMCPU
*cpu
= ARM_CPU(obj
);
1108 return cpu
->has_pmu
;
1111 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1113 ARMCPU
*cpu
= ARM_CPU(obj
);
1116 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1117 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1120 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1122 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1124 cpu
->has_pmu
= value
;
1127 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1130 * The exact approach to calculating guest ticks is:
1132 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1133 * NANOSECONDS_PER_SECOND);
1135 * We don't do that. Rather we intentionally use integer division
1136 * truncation below and in the caller for the conversion of host monotonic
1137 * time to guest ticks to provide the exact inverse for the semantics of
1138 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1139 * it loses precision when representing frequencies where
1140 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1141 * provide an exact inverse leads to scheduling timers with negative
1142 * periods, which in turn leads to sticky behaviour in the guest.
1144 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1145 * cannot become zero.
1147 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1148 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1151 void arm_cpu_post_init(Object
*obj
)
1153 ARMCPU
*cpu
= ARM_CPU(obj
);
1155 /* M profile implies PMSA. We have to do this here rather than
1156 * in realize with the other feature-implication checks because
1157 * we look at the PMSA bit to see if we should add some properties.
1159 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1160 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1163 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1164 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1165 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1168 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1169 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1172 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1173 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
);
1176 #ifndef CONFIG_USER_ONLY
1177 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1178 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1179 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1181 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1183 object_property_add_link(obj
, "secure-memory",
1185 (Object
**)&cpu
->secure_memory
,
1186 qdev_prop_allow_set_link_before_realize
,
1187 OBJ_PROP_LINK_STRONG
);
1190 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1191 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1195 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1196 cpu
->has_pmu
= true;
1197 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
);
1201 * Allow user to turn off VFP and Neon support, but only for TCG --
1202 * KVM does not currently allow us to lie to the guest about its
1203 * ID/feature registers, so the guest always sees what the host has.
1205 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)
1206 ? cpu_isar_feature(aa64_fp_simd
, cpu
)
1207 : cpu_isar_feature(aa32_vfp
, cpu
)) {
1208 cpu
->has_vfp
= true;
1209 if (!kvm_enabled()) {
1210 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
);
1214 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1215 cpu
->has_neon
= true;
1216 if (!kvm_enabled()) {
1217 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1221 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1222 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1223 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1226 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1227 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1228 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1229 qdev_property_add_static(DEVICE(obj
),
1230 &arm_cpu_pmsav7_dregion_property
);
1234 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1235 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1236 qdev_prop_allow_set_link_before_realize
,
1237 OBJ_PROP_LINK_STRONG
);
1239 * M profile: initial value of the Secure VTOR. We can't just use
1240 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1241 * the property to be set after realize.
1243 object_property_add_uint32_ptr(obj
, "init-svtor",
1245 OBJ_PROP_FLAG_READWRITE
);
1248 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1250 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1251 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1254 if (kvm_enabled()) {
1255 kvm_arm_add_vcpu_properties(obj
);
1258 #ifndef CONFIG_USER_ONLY
1259 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) &&
1260 cpu_isar_feature(aa64_mte
, cpu
)) {
1261 object_property_add_link(obj
, "tag-memory",
1263 (Object
**)&cpu
->tag_memory
,
1264 qdev_prop_allow_set_link_before_realize
,
1265 OBJ_PROP_LINK_STRONG
);
1267 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1268 object_property_add_link(obj
, "secure-tag-memory",
1270 (Object
**)&cpu
->secure_tag_memory
,
1271 qdev_prop_allow_set_link_before_realize
,
1272 OBJ_PROP_LINK_STRONG
);
1278 static void arm_cpu_finalizefn(Object
*obj
)
1280 ARMCPU
*cpu
= ARM_CPU(obj
);
1281 ARMELChangeHook
*hook
, *next
;
1283 g_hash_table_destroy(cpu
->cp_regs
);
1285 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1286 QLIST_REMOVE(hook
, node
);
1289 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1290 QLIST_REMOVE(hook
, node
);
1293 #ifndef CONFIG_USER_ONLY
1294 if (cpu
->pmu_timer
) {
1295 timer_del(cpu
->pmu_timer
);
1296 timer_deinit(cpu
->pmu_timer
);
1297 timer_free(cpu
->pmu_timer
);
1302 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1304 Error
*local_err
= NULL
;
1306 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1307 arm_cpu_sve_finalize(cpu
, &local_err
);
1308 if (local_err
!= NULL
) {
1309 error_propagate(errp
, local_err
);
1315 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1317 CPUState
*cs
= CPU(dev
);
1318 ARMCPU
*cpu
= ARM_CPU(dev
);
1319 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1320 CPUARMState
*env
= &cpu
->env
;
1322 Error
*local_err
= NULL
;
1323 bool no_aa32
= false;
1325 /* If we needed to query the host kernel for the CPU features
1326 * then it's possible that might have failed in the initfn, but
1327 * this is the first point where we can report it.
1329 if (cpu
->host_cpu_probe_failed
) {
1330 if (!kvm_enabled()) {
1331 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
1333 error_setg(errp
, "Failed to retrieve host CPU features");
1338 #ifndef CONFIG_USER_ONLY
1339 /* The NVIC and M-profile CPU are two halves of a single piece of
1340 * hardware; trying to use one without the other is a command line
1341 * error and will result in segfaults if not caught here.
1343 if (arm_feature(env
, ARM_FEATURE_M
)) {
1345 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1350 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1358 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1359 if (!cpu
->gt_cntfrq_hz
) {
1360 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1364 scale
= gt_cntfrq_period_ns(cpu
);
1366 scale
= GTIMER_SCALE
;
1369 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1370 arm_gt_ptimer_cb
, cpu
);
1371 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1372 arm_gt_vtimer_cb
, cpu
);
1373 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1374 arm_gt_htimer_cb
, cpu
);
1375 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1376 arm_gt_stimer_cb
, cpu
);
1377 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1378 arm_gt_hvtimer_cb
, cpu
);
1382 cpu_exec_realizefn(cs
, &local_err
);
1383 if (local_err
!= NULL
) {
1384 error_propagate(errp
, local_err
);
1388 arm_cpu_finalize_features(cpu
, &local_err
);
1389 if (local_err
!= NULL
) {
1390 error_propagate(errp
, local_err
);
1394 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1395 cpu
->has_vfp
!= cpu
->has_neon
) {
1397 * This is an architectural requirement for AArch64; AArch32 is
1398 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1401 "AArch64 CPUs must have both VFP and Neon or neither");
1405 if (!cpu
->has_vfp
) {
1409 t
= cpu
->isar
.id_aa64isar1
;
1410 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1411 cpu
->isar
.id_aa64isar1
= t
;
1413 t
= cpu
->isar
.id_aa64pfr0
;
1414 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1415 cpu
->isar
.id_aa64pfr0
= t
;
1417 u
= cpu
->isar
.id_isar6
;
1418 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1419 cpu
->isar
.id_isar6
= u
;
1421 u
= cpu
->isar
.mvfr0
;
1422 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1423 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1424 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1425 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1426 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1427 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1428 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1429 cpu
->isar
.mvfr0
= u
;
1431 u
= cpu
->isar
.mvfr1
;
1432 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1433 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1434 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1435 cpu
->isar
.mvfr1
= u
;
1437 u
= cpu
->isar
.mvfr2
;
1438 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1439 cpu
->isar
.mvfr2
= u
;
1442 if (!cpu
->has_neon
) {
1446 unset_feature(env
, ARM_FEATURE_NEON
);
1448 t
= cpu
->isar
.id_aa64isar0
;
1449 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1450 cpu
->isar
.id_aa64isar0
= t
;
1452 t
= cpu
->isar
.id_aa64isar1
;
1453 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1454 cpu
->isar
.id_aa64isar1
= t
;
1456 t
= cpu
->isar
.id_aa64pfr0
;
1457 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1458 cpu
->isar
.id_aa64pfr0
= t
;
1460 u
= cpu
->isar
.id_isar5
;
1461 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1462 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1463 cpu
->isar
.id_isar5
= u
;
1465 u
= cpu
->isar
.id_isar6
;
1466 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1467 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1468 cpu
->isar
.id_isar6
= u
;
1470 u
= cpu
->isar
.mvfr1
;
1471 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1472 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1473 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1474 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1475 cpu
->isar
.mvfr1
= u
;
1477 u
= cpu
->isar
.mvfr2
;
1478 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1479 cpu
->isar
.mvfr2
= u
;
1482 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1486 t
= cpu
->isar
.id_aa64isar0
;
1487 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1488 cpu
->isar
.id_aa64isar0
= t
;
1490 t
= cpu
->isar
.id_aa64isar1
;
1491 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1492 cpu
->isar
.id_aa64isar1
= t
;
1494 u
= cpu
->isar
.mvfr0
;
1495 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1496 cpu
->isar
.mvfr0
= u
;
1498 /* Despite the name, this field covers both VFP and Neon */
1499 u
= cpu
->isar
.mvfr1
;
1500 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1501 cpu
->isar
.mvfr1
= u
;
1504 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1507 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1509 u
= cpu
->isar
.id_isar1
;
1510 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1511 cpu
->isar
.id_isar1
= u
;
1513 u
= cpu
->isar
.id_isar2
;
1514 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1515 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1516 cpu
->isar
.id_isar2
= u
;
1518 u
= cpu
->isar
.id_isar3
;
1519 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1520 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1521 cpu
->isar
.id_isar3
= u
;
1524 /* Some features automatically imply others: */
1525 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1526 if (arm_feature(env
, ARM_FEATURE_M
)) {
1527 set_feature(env
, ARM_FEATURE_V7
);
1529 set_feature(env
, ARM_FEATURE_V7VE
);
1534 * There exist AArch64 cpus without AArch32 support. When KVM
1535 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1536 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1537 * As a general principle, we also do not make ID register
1538 * consistency checks anywhere unless using TCG, because only
1539 * for TCG would a consistency-check failure be a QEMU bug.
1541 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1542 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1545 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1546 /* v7 Virtualization Extensions. In real hardware this implies
1547 * EL2 and also the presence of the Security Extensions.
1548 * For QEMU, for backwards-compatibility we implement some
1549 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1550 * include the various other features that V7VE implies.
1551 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1552 * Security Extensions is ARM_FEATURE_EL3.
1554 assert(!tcg_enabled() || no_aa32
||
1555 cpu_isar_feature(aa32_arm_div
, cpu
));
1556 set_feature(env
, ARM_FEATURE_LPAE
);
1557 set_feature(env
, ARM_FEATURE_V7
);
1559 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1560 set_feature(env
, ARM_FEATURE_VAPA
);
1561 set_feature(env
, ARM_FEATURE_THUMB2
);
1562 set_feature(env
, ARM_FEATURE_MPIDR
);
1563 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1564 set_feature(env
, ARM_FEATURE_V6K
);
1566 set_feature(env
, ARM_FEATURE_V6
);
1569 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1570 * non-EL3 configs. This is needed by some legacy boards.
1572 set_feature(env
, ARM_FEATURE_VBAR
);
1574 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1575 set_feature(env
, ARM_FEATURE_V6
);
1576 set_feature(env
, ARM_FEATURE_MVFR
);
1578 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1579 set_feature(env
, ARM_FEATURE_V5
);
1580 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1581 assert(!tcg_enabled() || no_aa32
||
1582 cpu_isar_feature(aa32_jazelle
, cpu
));
1583 set_feature(env
, ARM_FEATURE_AUXCR
);
1586 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1587 set_feature(env
, ARM_FEATURE_V4T
);
1589 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1590 set_feature(env
, ARM_FEATURE_V7MP
);
1592 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1593 set_feature(env
, ARM_FEATURE_CBAR
);
1595 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1596 !arm_feature(env
, ARM_FEATURE_M
)) {
1597 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1601 * We rely on no XScale CPU having VFP so we can use the same bits in the
1602 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1604 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
1605 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
1606 !arm_feature(env
, ARM_FEATURE_XSCALE
));
1608 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1609 !arm_feature(env
, ARM_FEATURE_M
) &&
1610 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1611 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1616 /* For CPUs which might have tiny 1K pages, or which have an
1617 * MPU and might have small region sizes, stick with 1K pages.
1621 if (!set_preferred_target_page_bits(pagebits
)) {
1622 /* This can only ever happen for hotplugging a CPU, or if
1623 * the board code incorrectly creates a CPU which it has
1624 * promised via minimum_page_size that it will not.
1626 error_setg(errp
, "This CPU requires a smaller page size than the "
1631 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1632 * We don't support setting cluster ID ([16..23]) (known as Aff2
1633 * in later ARM ARM versions), or any of the higher affinity level fields,
1634 * so these bits always RAZ.
1636 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1637 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1638 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1641 if (cpu
->reset_hivecs
) {
1642 cpu
->reset_sctlr
|= (1 << 13);
1646 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1647 cpu
->reset_sctlr
|= SCTLR_EE
;
1649 cpu
->reset_sctlr
|= SCTLR_B
;
1653 if (!cpu
->has_el3
) {
1654 /* If the has_el3 CPU property is disabled then we need to disable the
1657 unset_feature(env
, ARM_FEATURE_EL3
);
1659 /* Disable the security extension feature bits in the processor feature
1660 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1662 cpu
->isar
.id_pfr1
&= ~0xf0;
1663 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1666 if (!cpu
->has_el2
) {
1667 unset_feature(env
, ARM_FEATURE_EL2
);
1670 if (!cpu
->has_pmu
) {
1671 unset_feature(env
, ARM_FEATURE_PMU
);
1673 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1676 if (!kvm_enabled()) {
1677 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1678 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1681 #ifndef CONFIG_USER_ONLY
1682 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1686 cpu
->isar
.id_aa64dfr0
=
1687 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
1688 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
1693 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1694 /* Disable the hypervisor feature bits in the processor feature
1695 * registers if we don't have EL2. These are id_pfr1[15:12] and
1696 * id_aa64pfr0_el1[11:8].
1698 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1699 cpu
->isar
.id_pfr1
&= ~0xf000;
1702 #ifndef CONFIG_USER_ONLY
1703 if (cpu
->tag_memory
== NULL
&& cpu_isar_feature(aa64_mte
, cpu
)) {
1705 * Disable the MTE feature bits if we do not have tag-memory
1706 * provided by the machine.
1708 cpu
->isar
.id_aa64pfr1
=
1709 FIELD_DP64(cpu
->isar
.id_aa64pfr1
, ID_AA64PFR1
, MTE
, 0);
1713 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1714 * to false or by setting pmsav7-dregion to 0.
1716 if (!cpu
->has_mpu
) {
1717 cpu
->pmsav7_dregion
= 0;
1719 if (cpu
->pmsav7_dregion
== 0) {
1720 cpu
->has_mpu
= false;
1723 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1724 arm_feature(env
, ARM_FEATURE_V7
)) {
1725 uint32_t nr
= cpu
->pmsav7_dregion
;
1728 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1733 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1735 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1736 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1737 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1738 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1739 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1742 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1743 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1744 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1749 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1750 uint32_t nr
= cpu
->sau_sregion
;
1753 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1758 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1759 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1763 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1764 set_feature(env
, ARM_FEATURE_VBAR
);
1767 register_cp_regs_for_features(cpu
);
1768 arm_cpu_register_gdb_regs_for_features(cpu
);
1770 init_cpreg_list(cpu
);
1772 #ifndef CONFIG_USER_ONLY
1773 MachineState
*ms
= MACHINE(qdev_get_machine());
1774 unsigned int smp_cpus
= ms
->smp
.cpus
;
1775 bool has_secure
= cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
);
1778 * We must set cs->num_ases to the final value before
1779 * the first call to cpu_address_space_init.
1781 if (cpu
->tag_memory
!= NULL
) {
1782 cs
->num_ases
= 3 + has_secure
;
1784 cs
->num_ases
= 1 + has_secure
;
1788 if (!cpu
->secure_memory
) {
1789 cpu
->secure_memory
= cs
->memory
;
1791 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1792 cpu
->secure_memory
);
1795 if (cpu
->tag_memory
!= NULL
) {
1796 cpu_address_space_init(cs
, ARMASIdx_TagNS
, "cpu-tag-memory",
1799 cpu_address_space_init(cs
, ARMASIdx_TagS
, "cpu-tag-memory",
1800 cpu
->secure_tag_memory
);
1804 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1806 /* No core_count specified, default to smp_cpus. */
1807 if (cpu
->core_count
== -1) {
1808 cpu
->core_count
= smp_cpus
;
1812 if (tcg_enabled()) {
1813 int dcz_blocklen
= 4 << cpu
->dcz_blocksize
;
1816 * We only support DCZ blocklen that fits on one page.
1818 * Architectually this is always true. However TARGET_PAGE_SIZE
1819 * is variable and, for compatibility with -machine virt-2.7,
1820 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
1821 * But even then, while the largest architectural DCZ blocklen
1822 * is 2KiB, no cpu actually uses such a large blocklen.
1824 assert(dcz_blocklen
<= TARGET_PAGE_SIZE
);
1827 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
1828 * both nibbles of each byte storing tag data may be written at once.
1829 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
1831 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1832 assert(dcz_blocklen
>= 2 * TAG_GRANULE
);
1839 acc
->parent_realize(dev
, errp
);
1842 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1847 const char *cpunamestr
;
1849 cpuname
= g_strsplit(cpu_model
, ",", 1);
1850 cpunamestr
= cpuname
[0];
1851 #ifdef CONFIG_USER_ONLY
1852 /* For backwards compatibility usermode emulation allows "-cpu any",
1853 * which has the same semantics as "-cpu max".
1855 if (!strcmp(cpunamestr
, "any")) {
1859 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1860 oc
= object_class_by_name(typename
);
1861 g_strfreev(cpuname
);
1863 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1864 object_class_is_abstract(oc
)) {
1870 /* CPU models. These are not needed for the AArch64 linux-user build. */
1871 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1873 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
1874 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
1875 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1876 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1877 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1881 static void cortex_a8_initfn(Object
*obj
)
1883 ARMCPU
*cpu
= ARM_CPU(obj
);
1885 cpu
->dtb_compatible
= "arm,cortex-a8";
1886 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1887 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1888 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1889 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1890 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1891 cpu
->midr
= 0x410fc080;
1892 cpu
->reset_fpsid
= 0x410330c0;
1893 cpu
->isar
.mvfr0
= 0x11110222;
1894 cpu
->isar
.mvfr1
= 0x00011111;
1895 cpu
->ctr
= 0x82048004;
1896 cpu
->reset_sctlr
= 0x00c50078;
1897 cpu
->isar
.id_pfr0
= 0x1031;
1898 cpu
->isar
.id_pfr1
= 0x11;
1899 cpu
->isar
.id_dfr0
= 0x400;
1901 cpu
->isar
.id_mmfr0
= 0x31100003;
1902 cpu
->isar
.id_mmfr1
= 0x20000000;
1903 cpu
->isar
.id_mmfr2
= 0x01202000;
1904 cpu
->isar
.id_mmfr3
= 0x11;
1905 cpu
->isar
.id_isar0
= 0x00101111;
1906 cpu
->isar
.id_isar1
= 0x12112111;
1907 cpu
->isar
.id_isar2
= 0x21232031;
1908 cpu
->isar
.id_isar3
= 0x11112131;
1909 cpu
->isar
.id_isar4
= 0x00111142;
1910 cpu
->isar
.dbgdidr
= 0x15141000;
1911 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1912 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1913 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1914 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1915 cpu
->reset_auxcr
= 2;
1916 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1919 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1920 /* power_control should be set to maximum latency. Again,
1921 * default to 0 and set by private hook
1923 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1924 .access
= PL1_RW
, .resetvalue
= 0,
1925 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1926 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1927 .access
= PL1_RW
, .resetvalue
= 0,
1928 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1929 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1930 .access
= PL1_RW
, .resetvalue
= 0,
1931 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1932 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1933 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1934 /* TLB lockdown control */
1935 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1936 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1937 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1938 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1939 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1940 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1941 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1942 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1943 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1944 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1948 static void cortex_a9_initfn(Object
*obj
)
1950 ARMCPU
*cpu
= ARM_CPU(obj
);
1952 cpu
->dtb_compatible
= "arm,cortex-a9";
1953 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1954 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1955 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1956 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1957 /* Note that A9 supports the MP extensions even for
1958 * A9UP and single-core A9MP (which are both different
1959 * and valid configurations; we don't model A9UP).
1961 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1962 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1963 cpu
->midr
= 0x410fc090;
1964 cpu
->reset_fpsid
= 0x41033090;
1965 cpu
->isar
.mvfr0
= 0x11110222;
1966 cpu
->isar
.mvfr1
= 0x01111111;
1967 cpu
->ctr
= 0x80038003;
1968 cpu
->reset_sctlr
= 0x00c50078;
1969 cpu
->isar
.id_pfr0
= 0x1031;
1970 cpu
->isar
.id_pfr1
= 0x11;
1971 cpu
->isar
.id_dfr0
= 0x000;
1973 cpu
->isar
.id_mmfr0
= 0x00100103;
1974 cpu
->isar
.id_mmfr1
= 0x20000000;
1975 cpu
->isar
.id_mmfr2
= 0x01230000;
1976 cpu
->isar
.id_mmfr3
= 0x00002111;
1977 cpu
->isar
.id_isar0
= 0x00101111;
1978 cpu
->isar
.id_isar1
= 0x13112111;
1979 cpu
->isar
.id_isar2
= 0x21232041;
1980 cpu
->isar
.id_isar3
= 0x11112131;
1981 cpu
->isar
.id_isar4
= 0x00111142;
1982 cpu
->isar
.dbgdidr
= 0x35141000;
1983 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1984 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1985 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1986 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1989 #ifndef CONFIG_USER_ONLY
1990 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1992 MachineState
*ms
= MACHINE(qdev_get_machine());
1994 /* Linux wants the number of processors from here.
1995 * Might as well set the interrupt-controller bit too.
1997 return ((ms
->smp
.cpus
- 1) << 24) | (1 << 23);
2001 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
2002 #ifndef CONFIG_USER_ONLY
2003 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
2004 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
2005 .writefn
= arm_cp_write_ignore
, },
2007 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
2008 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2012 static void cortex_a7_initfn(Object
*obj
)
2014 ARMCPU
*cpu
= ARM_CPU(obj
);
2016 cpu
->dtb_compatible
= "arm,cortex-a7";
2017 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2018 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2019 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2020 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2021 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2022 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2023 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2024 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2025 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2026 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
2027 cpu
->midr
= 0x410fc075;
2028 cpu
->reset_fpsid
= 0x41023075;
2029 cpu
->isar
.mvfr0
= 0x10110222;
2030 cpu
->isar
.mvfr1
= 0x11111111;
2031 cpu
->ctr
= 0x84448003;
2032 cpu
->reset_sctlr
= 0x00c50078;
2033 cpu
->isar
.id_pfr0
= 0x00001131;
2034 cpu
->isar
.id_pfr1
= 0x00011011;
2035 cpu
->isar
.id_dfr0
= 0x02010555;
2036 cpu
->id_afr0
= 0x00000000;
2037 cpu
->isar
.id_mmfr0
= 0x10101105;
2038 cpu
->isar
.id_mmfr1
= 0x40000000;
2039 cpu
->isar
.id_mmfr2
= 0x01240000;
2040 cpu
->isar
.id_mmfr3
= 0x02102211;
2041 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2042 * table 4-41 gives 0x02101110, which includes the arm div insns.
2044 cpu
->isar
.id_isar0
= 0x02101110;
2045 cpu
->isar
.id_isar1
= 0x13112111;
2046 cpu
->isar
.id_isar2
= 0x21232041;
2047 cpu
->isar
.id_isar3
= 0x11112131;
2048 cpu
->isar
.id_isar4
= 0x10011142;
2049 cpu
->isar
.dbgdidr
= 0x3515f005;
2050 cpu
->clidr
= 0x0a200023;
2051 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2052 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2053 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2054 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
2057 static void cortex_a15_initfn(Object
*obj
)
2059 ARMCPU
*cpu
= ARM_CPU(obj
);
2061 cpu
->dtb_compatible
= "arm,cortex-a15";
2062 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2063 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2064 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2065 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2066 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2067 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2068 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2069 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2070 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2071 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
2072 cpu
->midr
= 0x412fc0f1;
2073 cpu
->reset_fpsid
= 0x410430f0;
2074 cpu
->isar
.mvfr0
= 0x10110222;
2075 cpu
->isar
.mvfr1
= 0x11111111;
2076 cpu
->ctr
= 0x8444c004;
2077 cpu
->reset_sctlr
= 0x00c50078;
2078 cpu
->isar
.id_pfr0
= 0x00001131;
2079 cpu
->isar
.id_pfr1
= 0x00011011;
2080 cpu
->isar
.id_dfr0
= 0x02010555;
2081 cpu
->id_afr0
= 0x00000000;
2082 cpu
->isar
.id_mmfr0
= 0x10201105;
2083 cpu
->isar
.id_mmfr1
= 0x20000000;
2084 cpu
->isar
.id_mmfr2
= 0x01240000;
2085 cpu
->isar
.id_mmfr3
= 0x02102211;
2086 cpu
->isar
.id_isar0
= 0x02101110;
2087 cpu
->isar
.id_isar1
= 0x13112111;
2088 cpu
->isar
.id_isar2
= 0x21232041;
2089 cpu
->isar
.id_isar3
= 0x11112131;
2090 cpu
->isar
.id_isar4
= 0x10011142;
2091 cpu
->isar
.dbgdidr
= 0x3515f021;
2092 cpu
->clidr
= 0x0a200023;
2093 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2094 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2095 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2096 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
2099 #ifndef TARGET_AARCH64
2101 * -cpu max: a CPU with as many features enabled as our emulation supports.
2102 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2103 * this only needs to handle 32 bits, and need not care about KVM.
2105 static void arm_max_initfn(Object
*obj
)
2107 ARMCPU
*cpu
= ARM_CPU(obj
);
2109 cortex_a15_initfn(obj
);
2111 /* old-style VFP short-vector support */
2112 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
2114 #ifdef CONFIG_USER_ONLY
2116 * We don't set these in system emulation mode for the moment,
2117 * since we don't correctly set (all of) the ID registers to
2120 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2124 t
= cpu
->isar
.id_isar5
;
2125 t
= FIELD_DP32(t
, ID_ISAR5
, AES
, 2);
2126 t
= FIELD_DP32(t
, ID_ISAR5
, SHA1
, 1);
2127 t
= FIELD_DP32(t
, ID_ISAR5
, SHA2
, 1);
2128 t
= FIELD_DP32(t
, ID_ISAR5
, CRC32
, 1);
2129 t
= FIELD_DP32(t
, ID_ISAR5
, RDM
, 1);
2130 t
= FIELD_DP32(t
, ID_ISAR5
, VCMA
, 1);
2131 cpu
->isar
.id_isar5
= t
;
2133 t
= cpu
->isar
.id_isar6
;
2134 t
= FIELD_DP32(t
, ID_ISAR6
, JSCVT
, 1);
2135 t
= FIELD_DP32(t
, ID_ISAR6
, DP
, 1);
2136 t
= FIELD_DP32(t
, ID_ISAR6
, FHM
, 1);
2137 t
= FIELD_DP32(t
, ID_ISAR6
, SB
, 1);
2138 t
= FIELD_DP32(t
, ID_ISAR6
, SPECRES
, 1);
2139 cpu
->isar
.id_isar6
= t
;
2141 t
= cpu
->isar
.mvfr1
;
2142 t
= FIELD_DP32(t
, MVFR1
, FPHP
, 3); /* v8.2-FP16 */
2143 t
= FIELD_DP32(t
, MVFR1
, SIMDHP
, 2); /* v8.2-FP16 */
2144 cpu
->isar
.mvfr1
= t
;
2146 t
= cpu
->isar
.mvfr2
;
2147 t
= FIELD_DP32(t
, MVFR2
, SIMDMISC
, 3); /* SIMD MaxNum */
2148 t
= FIELD_DP32(t
, MVFR2
, FPMISC
, 4); /* FP MaxNum */
2149 cpu
->isar
.mvfr2
= t
;
2151 t
= cpu
->isar
.id_mmfr3
;
2152 t
= FIELD_DP32(t
, ID_MMFR3
, PAN
, 2); /* ATS1E1 */
2153 cpu
->isar
.id_mmfr3
= t
;
2155 t
= cpu
->isar
.id_mmfr4
;
2156 t
= FIELD_DP32(t
, ID_MMFR4
, HPDS
, 1); /* AA32HPD */
2157 t
= FIELD_DP32(t
, ID_MMFR4
, AC2
, 1); /* ACTLR2, HACTLR2 */
2158 t
= FIELD_DP32(t
, ID_MMFR4
, CNP
, 1); /* TTCNP */
2159 t
= FIELD_DP32(t
, ID_MMFR4
, XNX
, 1); /* TTS2UXN */
2160 cpu
->isar
.id_mmfr4
= t
;
2166 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2168 static const ARMCPUInfo arm_cpus
[] = {
2169 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2170 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
2171 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
2172 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
2173 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
2174 #ifndef TARGET_AARCH64
2175 { .name
= "max", .initfn
= arm_max_initfn
},
2177 #ifdef CONFIG_USER_ONLY
2178 { .name
= "any", .initfn
= arm_max_initfn
},
2183 static Property arm_cpu_properties
[] = {
2184 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
2185 DEFINE_PROP_UINT64("midr", ARMCPU
, midr
, 0),
2186 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2187 mp_affinity
, ARM64_AFFINITY_INVALID
),
2188 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2189 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2190 DEFINE_PROP_END_OF_LIST()
2193 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2195 ARMCPU
*cpu
= ARM_CPU(cs
);
2196 CPUARMState
*env
= &cpu
->env
;
2198 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2199 return g_strdup("iwmmxt");
2201 return g_strdup("arm");
2204 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2206 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2207 CPUClass
*cc
= CPU_CLASS(acc
);
2208 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2210 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2211 &acc
->parent_realize
);
2213 device_class_set_props(dc
, arm_cpu_properties
);
2214 device_class_set_parent_reset(dc
, arm_cpu_reset
, &acc
->parent_reset
);
2216 cc
->class_by_name
= arm_cpu_class_by_name
;
2217 cc
->has_work
= arm_cpu_has_work
;
2218 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
2219 cc
->dump_state
= arm_cpu_dump_state
;
2220 cc
->set_pc
= arm_cpu_set_pc
;
2221 cc
->synchronize_from_tb
= arm_cpu_synchronize_from_tb
;
2222 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2223 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2224 #ifndef CONFIG_USER_ONLY
2225 cc
->do_interrupt
= arm_cpu_do_interrupt
;
2226 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
2227 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
2228 cc
->vmsd
= &vmstate_arm_cpu
;
2229 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
2230 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
2231 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
2233 cc
->gdb_num_core_regs
= 26;
2234 cc
->gdb_core_xml_file
= "arm-core.xml";
2235 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2236 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2237 cc
->gdb_stop_before_watchpoint
= true;
2238 cc
->disas_set_info
= arm_disas_set_info
;
2240 cc
->tcg_initialize
= arm_translate_init
;
2241 cc
->tlb_fill
= arm_cpu_tlb_fill
;
2242 cc
->debug_excp_handler
= arm_debug_excp_handler
;
2243 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
2244 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
2245 #if !defined(CONFIG_USER_ONLY)
2246 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
2247 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
2248 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
2253 static void arm_host_initfn(Object
*obj
)
2255 ARMCPU
*cpu
= ARM_CPU(obj
);
2257 kvm_arm_set_cpu_features_from_host(cpu
);
2258 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
2259 aarch64_add_sve_properties(obj
);
2261 arm_cpu_post_init(obj
);
2264 static const TypeInfo host_arm_cpu_type_info
= {
2265 .name
= TYPE_ARM_HOST_CPU
,
2266 .parent
= TYPE_AARCH64_CPU
,
2267 .instance_init
= arm_host_initfn
,
2272 static void arm_cpu_instance_init(Object
*obj
)
2274 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2276 acc
->info
->initfn(obj
);
2277 arm_cpu_post_init(obj
);
2280 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2282 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2287 void arm_cpu_register(const ARMCPUInfo
*info
)
2289 TypeInfo type_info
= {
2290 .parent
= TYPE_ARM_CPU
,
2291 .instance_size
= sizeof(ARMCPU
),
2292 .instance_align
= __alignof__(ARMCPU
),
2293 .instance_init
= arm_cpu_instance_init
,
2294 .class_size
= sizeof(ARMCPUClass
),
2295 .class_init
= info
->class_init
?: cpu_register_class_init
,
2296 .class_data
= (void *)info
,
2299 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2300 type_register(&type_info
);
2301 g_free((void *)type_info
.name
);
2304 static const TypeInfo arm_cpu_type_info
= {
2305 .name
= TYPE_ARM_CPU
,
2307 .instance_size
= sizeof(ARMCPU
),
2308 .instance_align
= __alignof__(ARMCPU
),
2309 .instance_init
= arm_cpu_initfn
,
2310 .instance_finalize
= arm_cpu_finalizefn
,
2312 .class_size
= sizeof(ARMCPUClass
),
2313 .class_init
= arm_cpu_class_init
,
2316 static const TypeInfo idau_interface_type_info
= {
2317 .name
= TYPE_IDAU_INTERFACE
,
2318 .parent
= TYPE_INTERFACE
,
2319 .class_size
= sizeof(IDAUInterfaceClass
),
2322 static void arm_cpu_register_types(void)
2324 const size_t cpu_count
= ARRAY_SIZE(arm_cpus
);
2326 type_register_static(&arm_cpu_type_info
);
2329 type_register_static(&host_arm_cpu_type_info
);
2335 type_register_static(&idau_interface_type_info
);
2336 for (i
= 0; i
< cpu_count
; ++i
) {
2337 arm_cpu_register(&arm_cpus
[i
]);
2342 type_init(arm_cpu_register_types
)