target-cris/cpu.c

   1 /*
   2  * QEMU CRIS CPU
   3  *
   4  * Copyright (c) 2008 AXIS Communications AB
   5  * Written by Edgar E. Iglesias.
   6  *
   7  * Copyright (c) 2012 SUSE LINUX Products GmbH
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "cpu.h"
  25 #include "qemu-common.h"
  26 #include "mmu.h"
  27
  28
  29 static void cris_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     CRISCPU *cpu = CRIS_CPU(cs);
  32
  33     cpu->env.pc = value;
  34 }
  35
  36 static bool cris_cpu_has_work(CPUState *cs)
  37 {
  38     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  39 }
  40
  41 /* CPUClass::reset() */
  42 static void cris_cpu_reset(CPUState *s)
  43 {
  44     CRISCPU *cpu = CRIS_CPU(s);
  45     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
  46     CPUCRISState *env = &cpu->env;
  47     uint32_t vr;
  48
  49     ccc->parent_reset(s);
  50
  51     vr = env->pregs[PR_VR];
  52     memset(env, 0, offsetof(CPUCRISState, load_info));
  53     env->pregs[PR_VR] = vr;
  54     tlb_flush(s, 1);
  55
  56 #if defined(CONFIG_USER_ONLY)
  57     /* start in user mode with interrupts enabled.  */
  58     env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
  59 #else
  60     cris_mmu_init(env);
  61     env->pregs[PR_CCS] = 0;
  62 #endif
  63 }
  64
  65 static ObjectClass *cris_cpu_class_by_name(const char *cpu_model)
  66 {
  67     ObjectClass *oc;
  68     char *typename;
  69
  70     if (cpu_model == NULL) {
  71         return NULL;
  72     }
  73
  74 #if defined(CONFIG_USER_ONLY)
  75     if (strcasecmp(cpu_model, "any") == 0) {
  76         return object_class_by_name("crisv32-" TYPE_CRIS_CPU);
  77     }
  78 #endif
  79
  80     typename = g_strdup_printf("%s-" TYPE_CRIS_CPU, cpu_model);
  81     oc = object_class_by_name(typename);
  82     g_free(typename);
  83     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_CRIS_CPU) ||
  84                        object_class_is_abstract(oc))) {
  85         oc = NULL;
  86     }
  87     return oc;
  88 }
  89
  90 CRISCPU *cpu_cris_init(const char *cpu_model)
  91 {
  92     return CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model));
  93 }
  94
  95 /* Sort alphabetically by VR. */
  96 static gint cris_cpu_list_compare(gconstpointer a, gconstpointer b)
  97 {
  98     CRISCPUClass *ccc_a = CRIS_CPU_CLASS(a);
  99     CRISCPUClass *ccc_b = CRIS_CPU_CLASS(b);
 100
 101     /*  */
 102     if (ccc_a->vr > ccc_b->vr) {
 103         return 1;
 104     } else if (ccc_a->vr < ccc_b->vr) {
 105         return -1;
 106     } else {
 107         return 0;
 108     }
 109 }
 110
 111 static void cris_cpu_list_entry(gpointer data, gpointer user_data)
 112 {
 113     ObjectClass *oc = data;
 114     CPUListState *s = user_data;
 115     const char *typename = object_class_get_name(oc);
 116     char *name;
 117
 118     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_CRIS_CPU));
 119     (*s->cpu_fprintf)(s->file, "  %s\n", name);
 120     g_free(name);
 121 }
 122
 123 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 124 {
 125     CPUListState s = {
 126         .file = f,
 127         .cpu_fprintf = cpu_fprintf,
 128     };
 129     GSList *list;
 130
 131     list = object_class_get_list(TYPE_CRIS_CPU, false);
 132     list = g_slist_sort(list, cris_cpu_list_compare);
 133     (*cpu_fprintf)(f, "Available CPUs:\n");
 134     g_slist_foreach(list, cris_cpu_list_entry, &s);
 135     g_slist_free(list);
 136 }
 137
 138 static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
 139 {
 140     CPUState *cs = CPU(dev);
 141     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
 142
 143     cpu_reset(cs);
 144     qemu_init_vcpu(cs);
 145
 146     ccc->parent_realize(dev, errp);
 147 }
 148
 149 #ifndef CONFIG_USER_ONLY
 150 static void cris_cpu_set_irq(void *opaque, int irq, int level)
 151 {
 152     CRISCPU *cpu = opaque;
 153     CPUState *cs = CPU(cpu);
 154     int type = irq == CRIS_CPU_IRQ ? CPU_INTERRUPT_HARD : CPU_INTERRUPT_NMI;
 155
 156     if (level) {
 157         cpu_interrupt(cs, type);
 158     } else {
 159         cpu_reset_interrupt(cs, type);
 160     }
 161 }
 162 #endif
 163
 164 static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
 165 {
 166     CRISCPU *cc = CRIS_CPU(cpu);
 167     CPUCRISState *env = &cc->env;
 168
 169     if (env->pregs[PR_VR] != 32) {
 170         info->mach = bfd_mach_cris_v0_v10;
 171         info->print_insn = print_insn_crisv10;
 172     } else {
 173         info->mach = bfd_mach_cris_v32;
 174         info->print_insn = print_insn_crisv32;
 175     }
 176 }
 177
 178 static void cris_cpu_initfn(Object *obj)
 179 {
 180     CPUState *cs = CPU(obj);
 181     CRISCPU *cpu = CRIS_CPU(obj);
 182     CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
 183     CPUCRISState *env = &cpu->env;
 184     static bool tcg_initialized;
 185
 186     cs->env_ptr = env;
 187     cpu_exec_init(cs, &error_abort);
 188
 189     env->pregs[PR_VR] = ccc->vr;
 190
 191 #ifndef CONFIG_USER_ONLY
 192     /* IRQ and NMI lines.  */
 193     qdev_init_gpio_in(DEVICE(cpu), cris_cpu_set_irq, 2);
 194 #endif
 195
 196     if (tcg_enabled() && !tcg_initialized) {
 197         tcg_initialized = true;
 198         if (env->pregs[PR_VR] < 32) {
 199             cris_initialize_crisv10_tcg();
 200         } else {
 201             cris_initialize_tcg();
 202         }
 203     }
 204 }
 205
 206 static void crisv8_cpu_class_init(ObjectClass *oc, void *data)
 207 {
 208     CPUClass *cc = CPU_CLASS(oc);
 209     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 210
 211     ccc->vr = 8;
 212     cc->do_interrupt = crisv10_cpu_do_interrupt;
 213     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 214 }
 215
 216 static void crisv9_cpu_class_init(ObjectClass *oc, void *data)
 217 {
 218     CPUClass *cc = CPU_CLASS(oc);
 219     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 220
 221     ccc->vr = 9;
 222     cc->do_interrupt = crisv10_cpu_do_interrupt;
 223     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 224 }
 225
 226 static void crisv10_cpu_class_init(ObjectClass *oc, void *data)
 227 {
 228     CPUClass *cc = CPU_CLASS(oc);
 229     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 230
 231     ccc->vr = 10;
 232     cc->do_interrupt = crisv10_cpu_do_interrupt;
 233     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 234 }
 235
 236 static void crisv11_cpu_class_init(ObjectClass *oc, void *data)
 237 {
 238     CPUClass *cc = CPU_CLASS(oc);
 239     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 240
 241     ccc->vr = 11;
 242     cc->do_interrupt = crisv10_cpu_do_interrupt;
 243     cc->gdb_read_register = crisv10_cpu_gdb_read_register;
 244 }
 245
 246 static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
 247 {
 248     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 249
 250     ccc->vr = 32;
 251 }
 252
 253 #define TYPE(model) model "-" TYPE_CRIS_CPU
 254
 255 static const TypeInfo cris_cpu_model_type_infos[] = {
 256     {
 257         .name = TYPE("crisv8"),
 258         .parent = TYPE_CRIS_CPU,
 259         .class_init = crisv8_cpu_class_init,
 260     }, {
 261         .name = TYPE("crisv9"),
 262         .parent = TYPE_CRIS_CPU,
 263         .class_init = crisv9_cpu_class_init,
 264     }, {
 265         .name = TYPE("crisv10"),
 266         .parent = TYPE_CRIS_CPU,
 267         .class_init = crisv10_cpu_class_init,
 268     }, {
 269         .name = TYPE("crisv11"),
 270         .parent = TYPE_CRIS_CPU,
 271         .class_init = crisv11_cpu_class_init,
 272     }, {
 273         .name = TYPE("crisv32"),
 274         .parent = TYPE_CRIS_CPU,
 275         .class_init = crisv32_cpu_class_init,
 276     }
 277 };
 278
 279 #undef TYPE
 280
 281 static void cris_cpu_class_init(ObjectClass *oc, void *data)
 282 {
 283     DeviceClass *dc = DEVICE_CLASS(oc);
 284     CPUClass *cc = CPU_CLASS(oc);
 285     CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
 286
 287     ccc->parent_realize = dc->realize;
 288     dc->realize = cris_cpu_realizefn;
 289
 290     ccc->parent_reset = cc->reset;
 291     cc->reset = cris_cpu_reset;
 292
 293     cc->class_by_name = cris_cpu_class_by_name;
 294     cc->has_work = cris_cpu_has_work;
 295     cc->do_interrupt = cris_cpu_do_interrupt;
 296     cc->cpu_exec_interrupt = cris_cpu_exec_interrupt;
 297     cc->dump_state = cris_cpu_dump_state;
 298     cc->set_pc = cris_cpu_set_pc;
 299     cc->gdb_read_register = cris_cpu_gdb_read_register;
 300     cc->gdb_write_register = cris_cpu_gdb_write_register;
 301 #ifdef CONFIG_USER_ONLY
 302     cc->handle_mmu_fault = cris_cpu_handle_mmu_fault;
 303 #else
 304     cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
 305 #endif
 306
 307     cc->gdb_num_core_regs = 49;
 308     cc->gdb_stop_before_watchpoint = true;
 309
 310     cc->disas_set_info = cris_disas_set_info;
 311 }
 312
 313 static const TypeInfo cris_cpu_type_info = {
 314     .name = TYPE_CRIS_CPU,
 315     .parent = TYPE_CPU,
 316     .instance_size = sizeof(CRISCPU),
 317     .instance_init = cris_cpu_initfn,
 318     .abstract = true,
 319     .class_size = sizeof(CRISCPUClass),
 320     .class_init = cris_cpu_class_init,
 321 };
 322
 323 static void cris_cpu_register_types(void)
 324 {
 325     int i;
 326
 327     type_register_static(&cris_cpu_type_info);
 328     for (i = 0; i < ARRAY_SIZE(cris_cpu_model_type_infos); i++) {
 329         type_register_static(&cris_cpu_model_type_infos[i]);
 330     }
 331 }
 332
 333 type_init(cris_cpu_register_types)