target-ppc/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "sysemu/kvm.h"
   4
   5 void cpu_save(QEMUFile *f, void *opaque)
   6 {
   7     CPUPPCState *env = (CPUPPCState *)opaque;
   8     unsigned int i, j;
   9     uint32_t fpscr;
  10     target_ulong xer;
  11
  12     for (i = 0; i < 32; i++)
  13         qemu_put_betls(f, &env->gpr[i]);
  14 #if !defined(TARGET_PPC64)
  15     for (i = 0; i < 32; i++)
  16         qemu_put_betls(f, &env->gprh[i]);
  17 #endif
  18     qemu_put_betls(f, &env->lr);
  19     qemu_put_betls(f, &env->ctr);
  20     for (i = 0; i < 8; i++)
  21         qemu_put_be32s(f, &env->crf[i]);
  22     xer = cpu_read_xer(env);
  23     qemu_put_betls(f, &xer);
  24     qemu_put_betls(f, &env->reserve_addr);
  25     qemu_put_betls(f, &env->msr);
  26     for (i = 0; i < 4; i++)
  27         qemu_put_betls(f, &env->tgpr[i]);
  28     for (i = 0; i < 32; i++) {
  29         union {
  30             float64 d;
  31             uint64_t l;
  32         } u;
  33         u.d = env->fpr[i];
  34         qemu_put_be64(f, u.l);
  35     }
  36     fpscr = env->fpscr;
  37     qemu_put_be32s(f, &fpscr);
  38     qemu_put_sbe32s(f, &env->access_type);
  39 #if defined(TARGET_PPC64)
  40     qemu_put_betls(f, &env->spr[SPR_ASR]);
  41     qemu_put_sbe32s(f, &env->slb_nr);
  42 #endif
  43     qemu_put_betls(f, &env->spr[SPR_SDR1]);
  44     for (i = 0; i < 32; i++)
  45         qemu_put_betls(f, &env->sr[i]);
  46     for (i = 0; i < 2; i++)
  47         for (j = 0; j < 8; j++)
  48             qemu_put_betls(f, &env->DBAT[i][j]);
  49     for (i = 0; i < 2; i++)
  50         for (j = 0; j < 8; j++)
  51             qemu_put_betls(f, &env->IBAT[i][j]);
  52     qemu_put_sbe32s(f, &env->nb_tlb);
  53     qemu_put_sbe32s(f, &env->tlb_per_way);
  54     qemu_put_sbe32s(f, &env->nb_ways);
  55     qemu_put_sbe32s(f, &env->last_way);
  56     qemu_put_sbe32s(f, &env->id_tlbs);
  57     qemu_put_sbe32s(f, &env->nb_pids);
  58     if (env->tlb.tlb6) {
  59         // XXX assumes 6xx
  60         for (i = 0; i < env->nb_tlb; i++) {
  61             qemu_put_betls(f, &env->tlb.tlb6[i].pte0);
  62             qemu_put_betls(f, &env->tlb.tlb6[i].pte1);
  63             qemu_put_betls(f, &env->tlb.tlb6[i].EPN);
  64         }
  65     }
  66     for (i = 0; i < 4; i++)
  67         qemu_put_betls(f, &env->pb[i]);
  68     for (i = 0; i < 1024; i++)
  69         qemu_put_betls(f, &env->spr[i]);
  70     qemu_put_be32s(f, &env->vscr);
  71     qemu_put_be64s(f, &env->spe_acc);
  72     qemu_put_be32s(f, &env->spe_fscr);
  73     qemu_put_betls(f, &env->msr_mask);
  74     qemu_put_be32s(f, &env->flags);
  75     qemu_put_sbe32s(f, &env->error_code);
  76     qemu_put_be32s(f, &env->pending_interrupts);
  77     qemu_put_be32s(f, &env->irq_input_state);
  78     for (i = 0; i < POWERPC_EXCP_NB; i++)
  79         qemu_put_betls(f, &env->excp_vectors[i]);
  80     qemu_put_betls(f, &env->excp_prefix);
  81     qemu_put_betls(f, &env->hreset_excp_prefix);
  82     qemu_put_betls(f, &env->ivor_mask);
  83     qemu_put_betls(f, &env->ivpr_mask);
  84     qemu_put_betls(f, &env->hreset_vector);
  85     qemu_put_betls(f, &env->nip);
  86     qemu_put_betls(f, &env->hflags);
  87     qemu_put_betls(f, &env->hflags_nmsr);
  88     qemu_put_sbe32s(f, &env->mmu_idx);
  89     qemu_put_sbe32(f, 0);
  90 }
  91
  92 int cpu_load(QEMUFile *f, void *opaque, int version_id)
  93 {
  94     CPUPPCState *env = (CPUPPCState *)opaque;
  95     unsigned int i, j;
  96     target_ulong sdr1;
  97     uint32_t fpscr;
  98     target_ulong xer;
  99
 100     for (i = 0; i < 32; i++)
 101         qemu_get_betls(f, &env->gpr[i]);
 102 #if !defined(TARGET_PPC64)
 103     for (i = 0; i < 32; i++)
 104         qemu_get_betls(f, &env->gprh[i]);
 105 #endif
 106     qemu_get_betls(f, &env->lr);
 107     qemu_get_betls(f, &env->ctr);
 108     for (i = 0; i < 8; i++)
 109         qemu_get_be32s(f, &env->crf[i]);
 110     qemu_get_betls(f, &xer);
 111     cpu_write_xer(env, xer);
 112     qemu_get_betls(f, &env->reserve_addr);
 113     qemu_get_betls(f, &env->msr);
 114     for (i = 0; i < 4; i++)
 115         qemu_get_betls(f, &env->tgpr[i]);
 116     for (i = 0; i < 32; i++) {
 117         union {
 118             float64 d;
 119             uint64_t l;
 120         } u;
 121         u.l = qemu_get_be64(f);
 122         env->fpr[i] = u.d;
 123     }
 124     qemu_get_be32s(f, &fpscr);
 125     env->fpscr = fpscr;
 126     qemu_get_sbe32s(f, &env->access_type);
 127 #if defined(TARGET_PPC64)
 128     qemu_get_betls(f, &env->spr[SPR_ASR]);
 129     qemu_get_sbe32s(f, &env->slb_nr);
 130 #endif
 131     qemu_get_betls(f, &sdr1);
 132     for (i = 0; i < 32; i++)
 133         qemu_get_betls(f, &env->sr[i]);
 134     for (i = 0; i < 2; i++)
 135         for (j = 0; j < 8; j++)
 136             qemu_get_betls(f, &env->DBAT[i][j]);
 137     for (i = 0; i < 2; i++)
 138         for (j = 0; j < 8; j++)
 139             qemu_get_betls(f, &env->IBAT[i][j]);
 140     qemu_get_sbe32s(f, &env->nb_tlb);
 141     qemu_get_sbe32s(f, &env->tlb_per_way);
 142     qemu_get_sbe32s(f, &env->nb_ways);
 143     qemu_get_sbe32s(f, &env->last_way);
 144     qemu_get_sbe32s(f, &env->id_tlbs);
 145     qemu_get_sbe32s(f, &env->nb_pids);
 146     if (env->tlb.tlb6) {
 147         // XXX assumes 6xx
 148         for (i = 0; i < env->nb_tlb; i++) {
 149             qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
 150             qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
 151             qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
 152         }
 153     }
 154     for (i = 0; i < 4; i++)
 155         qemu_get_betls(f, &env->pb[i]);
 156     for (i = 0; i < 1024; i++)
 157         qemu_get_betls(f, &env->spr[i]);
 158     ppc_store_sdr1(env, sdr1);
 159     qemu_get_be32s(f, &env->vscr);
 160     qemu_get_be64s(f, &env->spe_acc);
 161     qemu_get_be32s(f, &env->spe_fscr);
 162     qemu_get_betls(f, &env->msr_mask);
 163     qemu_get_be32s(f, &env->flags);
 164     qemu_get_sbe32s(f, &env->error_code);
 165     qemu_get_be32s(f, &env->pending_interrupts);
 166     qemu_get_be32s(f, &env->irq_input_state);
 167     for (i = 0; i < POWERPC_EXCP_NB; i++)
 168         qemu_get_betls(f, &env->excp_vectors[i]);
 169     qemu_get_betls(f, &env->excp_prefix);
 170     qemu_get_betls(f, &env->hreset_excp_prefix);
 171     qemu_get_betls(f, &env->ivor_mask);
 172     qemu_get_betls(f, &env->ivpr_mask);
 173     qemu_get_betls(f, &env->hreset_vector);
 174     qemu_get_betls(f, &env->nip);
 175     qemu_get_betls(f, &env->hflags);
 176     qemu_get_betls(f, &env->hflags_nmsr);
 177     qemu_get_sbe32s(f, &env->mmu_idx);
 178     qemu_get_sbe32(f); /* Discard unused power_mode */
 179
 180     return 0;
 181 }