2 * i.MX Fast Ethernet Controller emulation.
4 * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
6 * Based on Coldfire Fast Ethernet Controller emulation.
8 * Copyright (c) 2007 CodeSourcery.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
24 #include "qemu/osdep.h"
25 #include "hw/net/imx_fec.h"
26 #include "sysemu/dma.h"
28 #include "qemu/module.h"
29 #include "net/checksum.h"
36 #define DEBUG_IMX_FEC 0
39 #define FEC_PRINTF(fmt, args...) \
41 if (DEBUG_IMX_FEC) { \
42 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_FEC, \
48 #define DEBUG_IMX_PHY 0
51 #define PHY_PRINTF(fmt, args...) \
53 if (DEBUG_IMX_PHY) { \
54 fprintf(stderr, "[%s.phy]%s: " fmt , TYPE_IMX_FEC, \
59 #define IMX_MAX_DESC 1024
61 static const char *imx_default_reg_name(IMXFECState
*s
, uint32_t index
)
64 sprintf(tmp
, "index %d", index
);
68 static const char *imx_fec_reg_name(IMXFECState
*s
, uint32_t index
)
75 case ENET_MIIGSK_CFGR
:
80 return imx_default_reg_name(s
, index
);
84 static const char *imx_enet_reg_name(IMXFECState
*s
, uint32_t index
)
142 return imx_default_reg_name(s
, index
);
146 static const char *imx_eth_reg_name(IMXFECState
*s
, uint32_t index
)
193 return imx_fec_reg_name(s
, index
);
195 return imx_enet_reg_name(s
, index
);
201 * Versions of this device with more than one TX descriptor save the
202 * 2nd and 3rd descriptors in a subsection, to maintain migration
203 * compatibility with previous versions of the device that only
204 * supported a single descriptor.
206 static bool imx_eth_is_multi_tx_ring(void *opaque
)
208 IMXFECState
*s
= IMX_FEC(opaque
);
210 return s
->tx_ring_num
> 1;
213 static const VMStateDescription vmstate_imx_eth_txdescs
= {
214 .name
= "imx.fec/txdescs",
216 .minimum_version_id
= 1,
217 .needed
= imx_eth_is_multi_tx_ring
,
218 .fields
= (VMStateField
[]) {
219 VMSTATE_UINT32(tx_descriptor
[1], IMXFECState
),
220 VMSTATE_UINT32(tx_descriptor
[2], IMXFECState
),
221 VMSTATE_END_OF_LIST()
225 static const VMStateDescription vmstate_imx_eth
= {
226 .name
= TYPE_IMX_FEC
,
228 .minimum_version_id
= 2,
229 .fields
= (VMStateField
[]) {
230 VMSTATE_UINT32_ARRAY(regs
, IMXFECState
, ENET_MAX
),
231 VMSTATE_UINT32(rx_descriptor
, IMXFECState
),
232 VMSTATE_UINT32(tx_descriptor
[0], IMXFECState
),
233 VMSTATE_UINT32(phy_status
, IMXFECState
),
234 VMSTATE_UINT32(phy_control
, IMXFECState
),
235 VMSTATE_UINT32(phy_advertise
, IMXFECState
),
236 VMSTATE_UINT32(phy_int
, IMXFECState
),
237 VMSTATE_UINT32(phy_int_mask
, IMXFECState
),
238 VMSTATE_END_OF_LIST()
240 .subsections
= (const VMStateDescription
* []) {
241 &vmstate_imx_eth_txdescs
,
246 #define PHY_INT_ENERGYON (1 << 7)
247 #define PHY_INT_AUTONEG_COMPLETE (1 << 6)
248 #define PHY_INT_FAULT (1 << 5)
249 #define PHY_INT_DOWN (1 << 4)
250 #define PHY_INT_AUTONEG_LP (1 << 3)
251 #define PHY_INT_PARFAULT (1 << 2)
252 #define PHY_INT_AUTONEG_PAGE (1 << 1)
254 static void imx_eth_update(IMXFECState
*s
);
257 * The MII phy could raise a GPIO to the processor which in turn
258 * could be handled as an interrpt by the OS.
259 * For now we don't handle any GPIO/interrupt line, so the OS will
260 * have to poll for the PHY status.
262 static void phy_update_irq(IMXFECState
*s
)
267 static void phy_update_link(IMXFECState
*s
)
269 /* Autonegotiation status mirrors link status. */
270 if (qemu_get_queue(s
->nic
)->link_down
) {
271 PHY_PRINTF("link is down\n");
272 s
->phy_status
&= ~0x0024;
273 s
->phy_int
|= PHY_INT_DOWN
;
275 PHY_PRINTF("link is up\n");
276 s
->phy_status
|= 0x0024;
277 s
->phy_int
|= PHY_INT_ENERGYON
;
278 s
->phy_int
|= PHY_INT_AUTONEG_COMPLETE
;
283 static void imx_eth_set_link(NetClientState
*nc
)
285 phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc
)));
288 static void phy_reset(IMXFECState
*s
)
290 s
->phy_status
= 0x7809;
291 s
->phy_control
= 0x3000;
292 s
->phy_advertise
= 0x01e1;
298 static uint32_t do_phy_read(IMXFECState
*s
, int reg
)
303 /* we only advertise one phy */
308 case 0: /* Basic Control */
309 val
= s
->phy_control
;
311 case 1: /* Basic Status */
320 case 4: /* Auto-neg advertisement */
321 val
= s
->phy_advertise
;
323 case 5: /* Auto-neg Link Partner Ability */
326 case 6: /* Auto-neg Expansion */
329 case 29: /* Interrupt source. */
334 case 30: /* Interrupt mask */
335 val
= s
->phy_int_mask
;
341 qemu_log_mask(LOG_UNIMP
, "[%s.phy]%s: reg %d not implemented\n",
342 TYPE_IMX_FEC
, __func__
, reg
);
346 qemu_log_mask(LOG_GUEST_ERROR
, "[%s.phy]%s: Bad address at offset %d\n",
347 TYPE_IMX_FEC
, __func__
, reg
);
352 PHY_PRINTF("read 0x%04x @ %d\n", val
, reg
);
357 static void do_phy_write(IMXFECState
*s
, int reg
, uint32_t val
)
359 PHY_PRINTF("write 0x%04x @ %d\n", val
, reg
);
362 /* we only advertise one phy */
367 case 0: /* Basic Control */
371 s
->phy_control
= val
& 0x7980;
372 /* Complete autonegotiation immediately. */
374 s
->phy_status
|= 0x0020;
378 case 4: /* Auto-neg advertisement */
379 s
->phy_advertise
= (val
& 0x2d7f) | 0x80;
381 case 30: /* Interrupt mask */
382 s
->phy_int_mask
= val
& 0xff;
389 qemu_log_mask(LOG_UNIMP
, "[%s.phy)%s: reg %d not implemented\n",
390 TYPE_IMX_FEC
, __func__
, reg
);
393 qemu_log_mask(LOG_GUEST_ERROR
, "[%s.phy]%s: Bad address at offset %d\n",
394 TYPE_IMX_FEC
, __func__
, reg
);
399 static void imx_fec_read_bd(IMXFECBufDesc
*bd
, dma_addr_t addr
)
401 dma_memory_read(&address_space_memory
, addr
, bd
, sizeof(*bd
));
404 static void imx_fec_write_bd(IMXFECBufDesc
*bd
, dma_addr_t addr
)
406 dma_memory_write(&address_space_memory
, addr
, bd
, sizeof(*bd
));
409 static void imx_enet_read_bd(IMXENETBufDesc
*bd
, dma_addr_t addr
)
411 dma_memory_read(&address_space_memory
, addr
, bd
, sizeof(*bd
));
414 static void imx_enet_write_bd(IMXENETBufDesc
*bd
, dma_addr_t addr
)
416 dma_memory_write(&address_space_memory
, addr
, bd
, sizeof(*bd
));
419 static void imx_eth_update(IMXFECState
*s
)
422 * Previous versions of qemu had the ENET_INT_MAC and ENET_INT_TS_TIMER
423 * interrupts swapped. This worked with older versions of Linux (4.14
424 * and older) since Linux associated both interrupt lines with Ethernet
425 * MAC interrupts. Specifically,
426 * - Linux 4.15 and later have separate interrupt handlers for the MAC and
427 * timer interrupts. Those versions of Linux fail with versions of QEMU
428 * with swapped interrupt assignments.
429 * - In linux 4.14, both interrupt lines were registered with the Ethernet
430 * MAC interrupt handler. As a result, all versions of qemu happen to
431 * work, though that is accidental.
432 * - In Linux 4.9 and older, the timer interrupt was registered directly
433 * with the Ethernet MAC interrupt handler. The MAC interrupt was
434 * redirected to a GPIO interrupt to work around erratum ERR006687.
435 * This was implemented using the SOC's IOMUX block. In qemu, this GPIO
436 * interrupt never fired since IOMUX is currently not supported in qemu.
437 * Linux instead received MAC interrupts on the timer interrupt.
438 * As a result, qemu versions with the swapped interrupt assignment work,
439 * albeit accidentally, but qemu versions with the correct interrupt
442 * To ensure that all versions of Linux work, generate ENET_INT_MAC
443 * interrrupts on both interrupt lines. This should be changed if and when
444 * qemu supports IOMUX.
446 if (s
->regs
[ENET_EIR
] & s
->regs
[ENET_EIMR
] &
447 (ENET_INT_MAC
| ENET_INT_TS_TIMER
)) {
448 qemu_set_irq(s
->irq
[1], 1);
450 qemu_set_irq(s
->irq
[1], 0);
453 if (s
->regs
[ENET_EIR
] & s
->regs
[ENET_EIMR
] & ENET_INT_MAC
) {
454 qemu_set_irq(s
->irq
[0], 1);
456 qemu_set_irq(s
->irq
[0], 0);
460 static void imx_fec_do_tx(IMXFECState
*s
)
462 int frame_size
= 0, descnt
= 0;
463 uint8_t *ptr
= s
->frame
;
464 uint32_t addr
= s
->tx_descriptor
[0];
466 while (descnt
++ < IMX_MAX_DESC
) {
470 imx_fec_read_bd(&bd
, addr
);
471 FEC_PRINTF("tx_bd %x flags %04x len %d data %08x\n",
472 addr
, bd
.flags
, bd
.length
, bd
.data
);
473 if ((bd
.flags
& ENET_BD_R
) == 0) {
474 /* Run out of descriptors to transmit. */
475 FEC_PRINTF("tx_bd ran out of descriptors to transmit\n");
479 if (frame_size
+ len
> ENET_MAX_FRAME_SIZE
) {
480 len
= ENET_MAX_FRAME_SIZE
- frame_size
;
481 s
->regs
[ENET_EIR
] |= ENET_INT_BABT
;
483 dma_memory_read(&address_space_memory
, bd
.data
, ptr
, len
);
486 if (bd
.flags
& ENET_BD_L
) {
487 /* Last buffer in frame. */
488 qemu_send_packet(qemu_get_queue(s
->nic
), s
->frame
, frame_size
);
491 s
->regs
[ENET_EIR
] |= ENET_INT_TXF
;
493 s
->regs
[ENET_EIR
] |= ENET_INT_TXB
;
494 bd
.flags
&= ~ENET_BD_R
;
495 /* Write back the modified descriptor. */
496 imx_fec_write_bd(&bd
, addr
);
497 /* Advance to the next descriptor. */
498 if ((bd
.flags
& ENET_BD_W
) != 0) {
499 addr
= s
->regs
[ENET_TDSR
];
505 s
->tx_descriptor
[0] = addr
;
510 static void imx_enet_do_tx(IMXFECState
*s
, uint32_t index
)
512 int frame_size
= 0, descnt
= 0;
514 uint8_t *ptr
= s
->frame
;
515 uint32_t addr
, int_txb
, int_txf
, tdsr
;
521 int_txb
= ENET_INT_TXB
;
522 int_txf
= ENET_INT_TXF
;
527 int_txb
= ENET_INT_TXB1
;
528 int_txf
= ENET_INT_TXF1
;
533 int_txb
= ENET_INT_TXB2
;
534 int_txf
= ENET_INT_TXF2
;
538 qemu_log_mask(LOG_GUEST_ERROR
,
539 "%s: bogus value for index %x\n",
545 addr
= s
->tx_descriptor
[ring
];
547 while (descnt
++ < IMX_MAX_DESC
) {
551 imx_enet_read_bd(&bd
, addr
);
552 FEC_PRINTF("tx_bd %x flags %04x len %d data %08x option %04x "
553 "status %04x\n", addr
, bd
.flags
, bd
.length
, bd
.data
,
554 bd
.option
, bd
.status
);
555 if ((bd
.flags
& ENET_BD_R
) == 0) {
556 /* Run out of descriptors to transmit. */
560 if (frame_size
+ len
> ENET_MAX_FRAME_SIZE
) {
561 len
= ENET_MAX_FRAME_SIZE
- frame_size
;
562 s
->regs
[ENET_EIR
] |= ENET_INT_BABT
;
564 dma_memory_read(&address_space_memory
, bd
.data
, ptr
, len
);
567 if (bd
.flags
& ENET_BD_L
) {
568 if (bd
.option
& ENET_BD_PINS
) {
569 struct ip_header
*ip_hd
= PKT_GET_IP_HDR(s
->frame
);
570 if (IP_HEADER_VERSION(ip_hd
) == 4) {
571 net_checksum_calculate(s
->frame
, frame_size
);
574 if (bd
.option
& ENET_BD_IINS
) {
575 struct ip_header
*ip_hd
= PKT_GET_IP_HDR(s
->frame
);
576 /* We compute checksum only for IPv4 frames */
577 if (IP_HEADER_VERSION(ip_hd
) == 4) {
580 csum
= net_raw_checksum((uint8_t *)ip_hd
, sizeof(*ip_hd
));
581 ip_hd
->ip_sum
= cpu_to_be16(csum
);
584 /* Last buffer in frame. */
586 qemu_send_packet(qemu_get_queue(s
->nic
), s
->frame
, frame_size
);
590 if (bd
.option
& ENET_BD_TX_INT
) {
591 s
->regs
[ENET_EIR
] |= int_txf
;
594 if (bd
.option
& ENET_BD_TX_INT
) {
595 s
->regs
[ENET_EIR
] |= int_txb
;
597 bd
.flags
&= ~ENET_BD_R
;
598 /* Write back the modified descriptor. */
599 imx_enet_write_bd(&bd
, addr
);
600 /* Advance to the next descriptor. */
601 if ((bd
.flags
& ENET_BD_W
) != 0) {
602 addr
= s
->regs
[tdsr
];
608 s
->tx_descriptor
[ring
] = addr
;
613 static void imx_eth_do_tx(IMXFECState
*s
, uint32_t index
)
615 if (!s
->is_fec
&& (s
->regs
[ENET_ECR
] & ENET_ECR_EN1588
)) {
616 imx_enet_do_tx(s
, index
);
622 static void imx_eth_enable_rx(IMXFECState
*s
, bool flush
)
626 imx_fec_read_bd(&bd
, s
->rx_descriptor
);
628 s
->regs
[ENET_RDAR
] = (bd
.flags
& ENET_BD_E
) ? ENET_RDAR_RDAR
: 0;
630 if (!s
->regs
[ENET_RDAR
]) {
631 FEC_PRINTF("RX buffer full\n");
633 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
637 static void imx_eth_reset(DeviceState
*d
)
639 IMXFECState
*s
= IMX_FEC(d
);
641 /* Reset the Device */
642 memset(s
->regs
, 0, sizeof(s
->regs
));
643 s
->regs
[ENET_ECR
] = 0xf0000000;
644 s
->regs
[ENET_MIBC
] = 0xc0000000;
645 s
->regs
[ENET_RCR
] = 0x05ee0001;
646 s
->regs
[ENET_OPD
] = 0x00010000;
648 s
->regs
[ENET_PALR
] = (s
->conf
.macaddr
.a
[0] << 24)
649 | (s
->conf
.macaddr
.a
[1] << 16)
650 | (s
->conf
.macaddr
.a
[2] << 8)
651 | s
->conf
.macaddr
.a
[3];
652 s
->regs
[ENET_PAUR
] = (s
->conf
.macaddr
.a
[4] << 24)
653 | (s
->conf
.macaddr
.a
[5] << 16)
657 s
->regs
[ENET_FRBR
] = 0x00000600;
658 s
->regs
[ENET_FRSR
] = 0x00000500;
659 s
->regs
[ENET_MIIGSK_ENR
] = 0x00000006;
661 s
->regs
[ENET_RAEM
] = 0x00000004;
662 s
->regs
[ENET_RAFL
] = 0x00000004;
663 s
->regs
[ENET_TAEM
] = 0x00000004;
664 s
->regs
[ENET_TAFL
] = 0x00000008;
665 s
->regs
[ENET_TIPG
] = 0x0000000c;
666 s
->regs
[ENET_FTRL
] = 0x000007ff;
667 s
->regs
[ENET_ATPER
] = 0x3b9aca00;
670 s
->rx_descriptor
= 0;
671 memset(s
->tx_descriptor
, 0, sizeof(s
->tx_descriptor
));
673 /* We also reset the PHY */
677 static uint32_t imx_default_read(IMXFECState
*s
, uint32_t index
)
679 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
680 PRIx32
"\n", TYPE_IMX_FEC
, __func__
, index
* 4);
684 static uint32_t imx_fec_read(IMXFECState
*s
, uint32_t index
)
689 case ENET_MIIGSK_CFGR
:
690 case ENET_MIIGSK_ENR
:
691 return s
->regs
[index
];
693 return imx_default_read(s
, index
);
697 static uint32_t imx_enet_read(IMXFECState
*s
, uint32_t index
)
727 return s
->regs
[index
];
729 return imx_default_read(s
, index
);
733 static uint64_t imx_eth_read(void *opaque
, hwaddr offset
, unsigned size
)
736 IMXFECState
*s
= IMX_FEC(opaque
);
737 uint32_t index
= offset
>> 2;
761 value
= s
->regs
[index
];
765 value
= imx_fec_read(s
, index
);
767 value
= imx_enet_read(s
, index
);
772 FEC_PRINTF("reg[%s] => 0x%" PRIx32
"\n", imx_eth_reg_name(s
, index
),
778 static void imx_default_write(IMXFECState
*s
, uint32_t index
, uint32_t value
)
780 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad address at offset 0x%"
781 PRIx32
"\n", TYPE_IMX_FEC
, __func__
, index
* 4);
785 static void imx_fec_write(IMXFECState
*s
, uint32_t index
, uint32_t value
)
789 /* FRBR is read only */
790 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Register FRBR is read only\n",
791 TYPE_IMX_FEC
, __func__
);
794 s
->regs
[index
] = (value
& 0x000003fc) | 0x00000400;
796 case ENET_MIIGSK_CFGR
:
797 s
->regs
[index
] = value
& 0x00000053;
799 case ENET_MIIGSK_ENR
:
800 s
->regs
[index
] = (value
& 0x00000002) ? 0x00000006 : 0;
803 imx_default_write(s
, index
, value
);
808 static void imx_enet_write(IMXFECState
*s
, uint32_t index
, uint32_t value
)
818 s
->regs
[index
] = value
& 0x000001ff;
821 s
->regs
[index
] = value
& 0x0000001f;
824 s
->regs
[index
] = value
& 0x00003fff;
827 s
->regs
[index
] = value
& 0x00000019;
830 s
->regs
[index
] = value
& 0x000000C7;
833 s
->regs
[index
] = value
& 0x00002a9d;
838 s
->regs
[index
] = value
;
841 /* ATSTMP is read only */
842 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Register ATSTMP is read only\n",
843 TYPE_IMX_FEC
, __func__
);
846 s
->regs
[index
] = value
& 0x7fffffff;
849 s
->regs
[index
] = value
& 0x00007f7f;
852 /* implement clear timer flag */
853 value
= value
& 0x0000000f;
859 value
= value
& 0x000000fd;
865 s
->regs
[index
] = value
;
868 imx_default_write(s
, index
, value
);
873 static void imx_eth_write(void *opaque
, hwaddr offset
, uint64_t value
,
876 IMXFECState
*s
= IMX_FEC(opaque
);
877 const bool single_tx_ring
= !imx_eth_is_multi_tx_ring(s
);
878 uint32_t index
= offset
>> 2;
880 FEC_PRINTF("reg[%s] <= 0x%" PRIx32
"\n", imx_eth_reg_name(s
, index
),
885 s
->regs
[index
] &= ~value
;
888 s
->regs
[index
] = value
;
891 if (s
->regs
[ENET_ECR
] & ENET_ECR_ETHEREN
) {
892 if (!s
->regs
[index
]) {
893 imx_eth_enable_rx(s
, true);
899 case ENET_TDAR1
: /* FALLTHROUGH */
900 case ENET_TDAR2
: /* FALLTHROUGH */
901 if (unlikely(single_tx_ring
)) {
902 qemu_log_mask(LOG_GUEST_ERROR
,
903 "[%s]%s: trying to access TDAR2 or TDAR1\n",
904 TYPE_IMX_FEC
, __func__
);
907 case ENET_TDAR
: /* FALLTHROUGH */
908 if (s
->regs
[ENET_ECR
] & ENET_ECR_ETHEREN
) {
909 s
->regs
[index
] = ENET_TDAR_TDAR
;
910 imx_eth_do_tx(s
, index
);
915 if (value
& ENET_ECR_RESET
) {
916 return imx_eth_reset(DEVICE(s
));
918 s
->regs
[index
] = value
;
919 if ((s
->regs
[index
] & ENET_ECR_ETHEREN
) == 0) {
920 s
->regs
[ENET_RDAR
] = 0;
921 s
->rx_descriptor
= s
->regs
[ENET_RDSR
];
922 s
->regs
[ENET_TDAR
] = 0;
923 s
->regs
[ENET_TDAR1
] = 0;
924 s
->regs
[ENET_TDAR2
] = 0;
925 s
->tx_descriptor
[0] = s
->regs
[ENET_TDSR
];
926 s
->tx_descriptor
[1] = s
->regs
[ENET_TDSR1
];
927 s
->tx_descriptor
[2] = s
->regs
[ENET_TDSR2
];
931 s
->regs
[index
] = value
;
932 if (extract32(value
, 29, 1)) {
933 /* This is a read operation */
934 s
->regs
[ENET_MMFR
] = deposit32(s
->regs
[ENET_MMFR
], 0, 16,
939 /* This a write operation */
940 do_phy_write(s
, extract32(value
, 18, 10), extract32(value
, 0, 16));
942 /* raise the interrupt as the PHY operation is done */
943 s
->regs
[ENET_EIR
] |= ENET_INT_MII
;
946 s
->regs
[index
] = value
& 0xfe;
949 /* TODO: Implement MIB. */
950 s
->regs
[index
] = (value
& 0x80000000) ? 0xc0000000 : 0;
953 s
->regs
[index
] = value
& 0x07ff003f;
954 /* TODO: Implement LOOP mode. */
957 /* We transmit immediately, so raise GRA immediately. */
958 s
->regs
[index
] = value
;
960 s
->regs
[ENET_EIR
] |= ENET_INT_GRA
;
964 s
->regs
[index
] = value
;
965 s
->conf
.macaddr
.a
[0] = value
>> 24;
966 s
->conf
.macaddr
.a
[1] = value
>> 16;
967 s
->conf
.macaddr
.a
[2] = value
>> 8;
968 s
->conf
.macaddr
.a
[3] = value
;
971 s
->regs
[index
] = (value
| 0x0000ffff) & 0xffff8808;
972 s
->conf
.macaddr
.a
[4] = value
>> 24;
973 s
->conf
.macaddr
.a
[5] = value
>> 16;
976 s
->regs
[index
] = (value
& 0x0000ffff) | 0x00010000;
982 /* TODO: implement MAC hash filtering. */
986 s
->regs
[index
] = value
& 0x3;
988 s
->regs
[index
] = value
& 0x13f;
993 s
->regs
[index
] = value
& ~3;
995 s
->regs
[index
] = value
& ~7;
997 s
->rx_descriptor
= s
->regs
[index
];
1001 s
->regs
[index
] = value
& ~3;
1003 s
->regs
[index
] = value
& ~7;
1005 s
->tx_descriptor
[0] = s
->regs
[index
];
1008 if (unlikely(single_tx_ring
)) {
1009 qemu_log_mask(LOG_GUEST_ERROR
,
1010 "[%s]%s: trying to access TDSR1\n",
1011 TYPE_IMX_FEC
, __func__
);
1015 s
->regs
[index
] = value
& ~7;
1016 s
->tx_descriptor
[1] = s
->regs
[index
];
1019 if (unlikely(single_tx_ring
)) {
1020 qemu_log_mask(LOG_GUEST_ERROR
,
1021 "[%s]%s: trying to access TDSR2\n",
1022 TYPE_IMX_FEC
, __func__
);
1026 s
->regs
[index
] = value
& ~7;
1027 s
->tx_descriptor
[2] = s
->regs
[index
];
1030 s
->regs
[index
] = value
& 0x00003ff0;
1034 imx_fec_write(s
, index
, value
);
1036 imx_enet_write(s
, index
, value
);
1044 static int imx_eth_can_receive(NetClientState
*nc
)
1046 IMXFECState
*s
= IMX_FEC(qemu_get_nic_opaque(nc
));
1050 return !!s
->regs
[ENET_RDAR
];
1053 static ssize_t
imx_fec_receive(NetClientState
*nc
, const uint8_t *buf
,
1056 IMXFECState
*s
= IMX_FEC(qemu_get_nic_opaque(nc
));
1063 unsigned int buf_len
;
1066 FEC_PRINTF("len %d\n", (int)size
);
1068 if (!s
->regs
[ENET_RDAR
]) {
1069 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Unexpected packet\n",
1070 TYPE_IMX_FEC
, __func__
);
1074 /* 4 bytes for the CRC. */
1076 crc
= cpu_to_be32(crc32(~0, buf
, size
));
1077 crc_ptr
= (uint8_t *) &crc
;
1079 /* Huge frames are truncated. */
1080 if (size
> ENET_MAX_FRAME_SIZE
) {
1081 size
= ENET_MAX_FRAME_SIZE
;
1082 flags
|= ENET_BD_TR
| ENET_BD_LG
;
1085 /* Frames larger than the user limit just set error flags. */
1086 if (size
> (s
->regs
[ENET_RCR
] >> 16)) {
1087 flags
|= ENET_BD_LG
;
1090 addr
= s
->rx_descriptor
;
1092 imx_fec_read_bd(&bd
, addr
);
1093 if ((bd
.flags
& ENET_BD_E
) == 0) {
1094 /* No descriptors available. Bail out. */
1096 * FIXME: This is wrong. We should probably either
1097 * save the remainder for when more RX buffers are
1098 * available, or flag an error.
1100 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Lost end of frame\n",
1101 TYPE_IMX_FEC
, __func__
);
1104 buf_len
= (size
<= s
->regs
[ENET_MRBR
]) ? size
: s
->regs
[ENET_MRBR
];
1105 bd
.length
= buf_len
;
1108 FEC_PRINTF("rx_bd 0x%x length %d\n", addr
, bd
.length
);
1110 /* The last 4 bytes are the CRC. */
1112 buf_len
+= size
- 4;
1115 dma_memory_write(&address_space_memory
, buf_addr
, buf
, buf_len
);
1118 dma_memory_write(&address_space_memory
, buf_addr
+ buf_len
,
1120 crc_ptr
+= 4 - size
;
1122 bd
.flags
&= ~ENET_BD_E
;
1124 /* Last buffer in frame. */
1125 bd
.flags
|= flags
| ENET_BD_L
;
1126 FEC_PRINTF("rx frame flags %04x\n", bd
.flags
);
1127 s
->regs
[ENET_EIR
] |= ENET_INT_RXF
;
1129 s
->regs
[ENET_EIR
] |= ENET_INT_RXB
;
1131 imx_fec_write_bd(&bd
, addr
);
1132 /* Advance to the next descriptor. */
1133 if ((bd
.flags
& ENET_BD_W
) != 0) {
1134 addr
= s
->regs
[ENET_RDSR
];
1139 s
->rx_descriptor
= addr
;
1140 imx_eth_enable_rx(s
, false);
1145 static ssize_t
imx_enet_receive(NetClientState
*nc
, const uint8_t *buf
,
1148 IMXFECState
*s
= IMX_FEC(qemu_get_nic_opaque(nc
));
1155 unsigned int buf_len
;
1157 bool shift16
= s
->regs
[ENET_RACC
] & ENET_RACC_SHIFT16
;
1159 FEC_PRINTF("len %d\n", (int)size
);
1161 if (!s
->regs
[ENET_RDAR
]) {
1162 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Unexpected packet\n",
1163 TYPE_IMX_FEC
, __func__
);
1167 /* 4 bytes for the CRC. */
1169 crc
= cpu_to_be32(crc32(~0, buf
, size
));
1170 crc_ptr
= (uint8_t *) &crc
;
1176 /* Huge frames are truncated. */
1177 if (size
> s
->regs
[ENET_FTRL
]) {
1178 size
= s
->regs
[ENET_FTRL
];
1179 flags
|= ENET_BD_TR
| ENET_BD_LG
;
1182 /* Frames larger than the user limit just set error flags. */
1183 if (size
> (s
->regs
[ENET_RCR
] >> 16)) {
1184 flags
|= ENET_BD_LG
;
1187 addr
= s
->rx_descriptor
;
1189 imx_enet_read_bd(&bd
, addr
);
1190 if ((bd
.flags
& ENET_BD_E
) == 0) {
1191 /* No descriptors available. Bail out. */
1193 * FIXME: This is wrong. We should probably either
1194 * save the remainder for when more RX buffers are
1195 * available, or flag an error.
1197 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Lost end of frame\n",
1198 TYPE_IMX_FEC
, __func__
);
1201 buf_len
= MIN(size
, s
->regs
[ENET_MRBR
]);
1202 bd
.length
= buf_len
;
1205 FEC_PRINTF("rx_bd 0x%x length %d\n", addr
, bd
.length
);
1207 /* The last 4 bytes are the CRC. */
1209 buf_len
+= size
- 4;
1215 * If SHIFT16 bit of ENETx_RACC register is set we need to
1216 * align the payload to 4-byte boundary.
1218 const uint8_t zeros
[2] = { 0 };
1220 dma_memory_write(&address_space_memory
, buf_addr
,
1221 zeros
, sizeof(zeros
));
1223 buf_addr
+= sizeof(zeros
);
1224 buf_len
-= sizeof(zeros
);
1226 /* We only do this once per Ethernet frame */
1230 dma_memory_write(&address_space_memory
, buf_addr
, buf
, buf_len
);
1233 dma_memory_write(&address_space_memory
, buf_addr
+ buf_len
,
1235 crc_ptr
+= 4 - size
;
1237 bd
.flags
&= ~ENET_BD_E
;
1239 /* Last buffer in frame. */
1240 bd
.flags
|= flags
| ENET_BD_L
;
1241 FEC_PRINTF("rx frame flags %04x\n", bd
.flags
);
1242 if (bd
.option
& ENET_BD_RX_INT
) {
1243 s
->regs
[ENET_EIR
] |= ENET_INT_RXF
;
1246 if (bd
.option
& ENET_BD_RX_INT
) {
1247 s
->regs
[ENET_EIR
] |= ENET_INT_RXB
;
1250 imx_enet_write_bd(&bd
, addr
);
1251 /* Advance to the next descriptor. */
1252 if ((bd
.flags
& ENET_BD_W
) != 0) {
1253 addr
= s
->regs
[ENET_RDSR
];
1258 s
->rx_descriptor
= addr
;
1259 imx_eth_enable_rx(s
, false);
1264 static ssize_t
imx_eth_receive(NetClientState
*nc
, const uint8_t *buf
,
1267 IMXFECState
*s
= IMX_FEC(qemu_get_nic_opaque(nc
));
1269 if (!s
->is_fec
&& (s
->regs
[ENET_ECR
] & ENET_ECR_EN1588
)) {
1270 return imx_enet_receive(nc
, buf
, len
);
1272 return imx_fec_receive(nc
, buf
, len
);
1276 static const MemoryRegionOps imx_eth_ops
= {
1277 .read
= imx_eth_read
,
1278 .write
= imx_eth_write
,
1279 .valid
.min_access_size
= 4,
1280 .valid
.max_access_size
= 4,
1281 .endianness
= DEVICE_NATIVE_ENDIAN
,
1284 static void imx_eth_cleanup(NetClientState
*nc
)
1286 IMXFECState
*s
= IMX_FEC(qemu_get_nic_opaque(nc
));
1291 static NetClientInfo imx_eth_net_info
= {
1292 .type
= NET_CLIENT_DRIVER_NIC
,
1293 .size
= sizeof(NICState
),
1294 .can_receive
= imx_eth_can_receive
,
1295 .receive
= imx_eth_receive
,
1296 .cleanup
= imx_eth_cleanup
,
1297 .link_status_changed
= imx_eth_set_link
,
1301 static void imx_eth_realize(DeviceState
*dev
, Error
**errp
)
1303 IMXFECState
*s
= IMX_FEC(dev
);
1304 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1306 memory_region_init_io(&s
->iomem
, OBJECT(dev
), &imx_eth_ops
, s
,
1307 TYPE_IMX_FEC
, FSL_IMX25_FEC_SIZE
);
1308 sysbus_init_mmio(sbd
, &s
->iomem
);
1309 sysbus_init_irq(sbd
, &s
->irq
[0]);
1310 sysbus_init_irq(sbd
, &s
->irq
[1]);
1312 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
1314 s
->nic
= qemu_new_nic(&imx_eth_net_info
, &s
->conf
,
1315 object_get_typename(OBJECT(dev
)),
1316 DEVICE(dev
)->id
, s
);
1318 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
1321 static Property imx_eth_properties
[] = {
1322 DEFINE_NIC_PROPERTIES(IMXFECState
, conf
),
1323 DEFINE_PROP_UINT32("tx-ring-num", IMXFECState
, tx_ring_num
, 1),
1324 DEFINE_PROP_END_OF_LIST(),
1327 static void imx_eth_class_init(ObjectClass
*klass
, void *data
)
1329 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1331 dc
->vmsd
= &vmstate_imx_eth
;
1332 dc
->reset
= imx_eth_reset
;
1333 dc
->props
= imx_eth_properties
;
1334 dc
->realize
= imx_eth_realize
;
1335 dc
->desc
= "i.MX FEC/ENET Ethernet Controller";
1338 static void imx_fec_init(Object
*obj
)
1340 IMXFECState
*s
= IMX_FEC(obj
);
1345 static void imx_enet_init(Object
*obj
)
1347 IMXFECState
*s
= IMX_FEC(obj
);
1352 static const TypeInfo imx_fec_info
= {
1353 .name
= TYPE_IMX_FEC
,
1354 .parent
= TYPE_SYS_BUS_DEVICE
,
1355 .instance_size
= sizeof(IMXFECState
),
1356 .instance_init
= imx_fec_init
,
1357 .class_init
= imx_eth_class_init
,
1360 static const TypeInfo imx_enet_info
= {
1361 .name
= TYPE_IMX_ENET
,
1362 .parent
= TYPE_IMX_FEC
,
1363 .instance_init
= imx_enet_init
,
1366 static void imx_eth_register_types(void)
1368 type_register_static(&imx_fec_info
);
1369 type_register_static(&imx_enet_info
);
1372 type_init(imx_eth_register_types
)