2 * QEMU ESCC (Z8030/Z8530/Z85C30/SCC/ESCC) serial port emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/sysbus.h"
28 #include "qemu/module.h"
29 #include "hw/char/escc.h"
30 #include "ui/console.h"
35 * "Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual",
36 * http://www.zilog.com/docs/serial/scc_escc_um.pdf
38 * On Sparc32 this is the serial port, mouse and keyboard part of chip STP2001
39 * (Slave I/O), also produced as NCR89C105. See
40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
42 * The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
43 * mouse and keyboard ports don't implement all functions and they are
44 * only asynchronous. There is no DMA.
46 * Z85C30 is also used on PowerMacs. There are some small differences
47 * between Sparc version (sunzilog) and PowerMac (pmac):
48 * Offset between control and data registers
49 * There is some kind of lockup bug, but we can ignore it
51 * DMA on pmac using DBDMA chip
52 * pmac can do IRDA and faster rates, sunzilog can only do 38400
53 * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz
58 * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented
60 * Implemented serial mouse protocol.
62 * 2010-May-23 Artyom Tarasenko: Reworked IUS logic
65 #define CHN_C(s) ((s)->chn == escc_chn_b ? 'b' : 'a')
71 #define CMD_PTR_MASK 0x07
72 #define CMD_CMD_MASK 0x38
74 #define CMD_CLR_TXINT 0x28
75 #define CMD_CLR_IUS 0x38
77 #define INTR_INTALL 0x01
78 #define INTR_TXINT 0x02
79 #define INTR_RXMODEMSK 0x18
80 #define INTR_RXINT1ST 0x08
81 #define INTR_RXINTALL 0x10
84 #define RXCTRL_RXEN 0x01
86 #define TXCTRL1_PAREN 0x01
87 #define TXCTRL1_PAREV 0x02
88 #define TXCTRL1_1STOP 0x04
89 #define TXCTRL1_1HSTOP 0x08
90 #define TXCTRL1_2STOP 0x0c
91 #define TXCTRL1_STPMSK 0x0c
92 #define TXCTRL1_CLK1X 0x00
93 #define TXCTRL1_CLK16X 0x40
94 #define TXCTRL1_CLK32X 0x80
95 #define TXCTRL1_CLK64X 0xc0
96 #define TXCTRL1_CLKMSK 0xc0
98 #define TXCTRL2_TXEN 0x08
99 #define TXCTRL2_BITMSK 0x60
100 #define TXCTRL2_5BITS 0x00
101 #define TXCTRL2_7BITS 0x20
102 #define TXCTRL2_6BITS 0x40
103 #define TXCTRL2_8BITS 0x60
108 #define MINTR_STATUSHI 0x10
109 #define MINTR_RST_MASK 0xc0
110 #define MINTR_RST_B 0x40
111 #define MINTR_RST_A 0x80
112 #define MINTR_RST_ALL 0xc0
115 #define CLOCK_TRXC 0x08
119 #define MISC2_PLLDIS 0x30
121 #define EXTINT_DCD 0x08
122 #define EXTINT_SYNCINT 0x10
123 #define EXTINT_CTSINT 0x20
124 #define EXTINT_TXUNDRN 0x40
125 #define EXTINT_BRKINT 0x80
128 #define STATUS_RXAV 0x01
129 #define STATUS_ZERO 0x02
130 #define STATUS_TXEMPTY 0x04
131 #define STATUS_DCD 0x08
132 #define STATUS_SYNC 0x10
133 #define STATUS_CTS 0x20
134 #define STATUS_TXUNDRN 0x40
135 #define STATUS_BRK 0x80
137 #define SPEC_ALLSENT 0x01
138 #define SPEC_BITS8 0x06
140 #define IVEC_TXINTB 0x00
141 #define IVEC_LONOINT 0x06
142 #define IVEC_LORXINTA 0x0c
143 #define IVEC_LORXINTB 0x04
144 #define IVEC_LOTXINTA 0x08
145 #define IVEC_HINOINT 0x60
146 #define IVEC_HIRXINTA 0x30
147 #define IVEC_HIRXINTB 0x20
148 #define IVEC_HITXINTA 0x10
150 #define INTR_EXTINTB 0x01
151 #define INTR_TXINTB 0x02
152 #define INTR_RXINTB 0x04
153 #define INTR_EXTINTA 0x08
154 #define INTR_TXINTA 0x10
155 #define INTR_RXINTA 0x20
169 static void handle_kbd_command(ESCCChannelState
*s
, int val
);
170 static int serial_can_receive(void *opaque
);
171 static void serial_receive_byte(ESCCChannelState
*s
, int ch
);
173 static void clear_queue(void *opaque
)
175 ESCCChannelState
*s
= opaque
;
176 ESCCSERIOQueue
*q
= &s
->queue
;
177 q
->rptr
= q
->wptr
= q
->count
= 0;
180 static void put_queue(void *opaque
, int b
)
182 ESCCChannelState
*s
= opaque
;
183 ESCCSERIOQueue
*q
= &s
->queue
;
185 trace_escc_put_queue(CHN_C(s
), b
);
186 if (q
->count
>= ESCC_SERIO_QUEUE_SIZE
) {
189 q
->data
[q
->wptr
] = b
;
190 if (++q
->wptr
== ESCC_SERIO_QUEUE_SIZE
) {
194 serial_receive_byte(s
, 0);
197 static uint32_t get_queue(void *opaque
)
199 ESCCChannelState
*s
= opaque
;
200 ESCCSERIOQueue
*q
= &s
->queue
;
206 val
= q
->data
[q
->rptr
];
207 if (++q
->rptr
== ESCC_SERIO_QUEUE_SIZE
) {
212 trace_escc_get_queue(CHN_C(s
), val
);
214 serial_receive_byte(s
, 0);
218 static int escc_update_irq_chn(ESCCChannelState
*s
)
220 if ((((s
->wregs
[W_INTR
] & INTR_TXINT
) && (s
->txint
== 1)) ||
221 // tx ints enabled, pending
222 ((((s
->wregs
[W_INTR
] & INTR_RXMODEMSK
) == INTR_RXINT1ST
) ||
223 ((s
->wregs
[W_INTR
] & INTR_RXMODEMSK
) == INTR_RXINTALL
)) &&
224 s
->rxint
== 1) || // rx ints enabled, pending
225 ((s
->wregs
[W_EXTINT
] & EXTINT_BRKINT
) &&
226 (s
->rregs
[R_STATUS
] & STATUS_BRK
)))) { // break int e&p
232 static void escc_update_irq(ESCCChannelState
*s
)
236 irq
= escc_update_irq_chn(s
);
237 irq
|= escc_update_irq_chn(s
->otherchn
);
239 trace_escc_update_irq(irq
);
240 qemu_set_irq(s
->irq
, irq
);
243 static void escc_reset_chn(ESCCChannelState
*s
)
248 for (i
= 0; i
< ESCC_SERIAL_REGS
; i
++) {
252 s
->wregs
[W_TXCTRL1
] = TXCTRL1_1STOP
; // 1X divisor, 1 stop bit, no parity
253 s
->wregs
[W_MINTR
] = MINTR_RST_ALL
;
254 s
->wregs
[W_CLOCK
] = CLOCK_TRXC
; // Synch mode tx clock = TRxC
255 s
->wregs
[W_MISC2
] = MISC2_PLLDIS
; // PLL disabled
256 s
->wregs
[W_EXTINT
] = EXTINT_DCD
| EXTINT_SYNCINT
| EXTINT_CTSINT
|
257 EXTINT_TXUNDRN
| EXTINT_BRKINT
; // Enable most interrupts
259 s
->rregs
[R_STATUS
] = STATUS_TXEMPTY
| STATUS_DCD
| STATUS_SYNC
|
260 STATUS_CTS
| STATUS_TXUNDRN
;
262 s
->rregs
[R_STATUS
] = STATUS_TXEMPTY
| STATUS_TXUNDRN
;
263 s
->rregs
[R_SPEC
] = SPEC_BITS8
| SPEC_ALLSENT
;
266 s
->rxint
= s
->txint
= 0;
267 s
->rxint_under_svc
= s
->txint_under_svc
= 0;
268 s
->e0_mode
= s
->led_mode
= s
->caps_lock_mode
= s
->num_lock_mode
= 0;
272 static void escc_reset(DeviceState
*d
)
274 ESCCState
*s
= ESCC(d
);
276 escc_reset_chn(&s
->chn
[0]);
277 escc_reset_chn(&s
->chn
[1]);
280 static inline void set_rxint(ESCCChannelState
*s
)
283 /* XXX: missing daisy chainnig: escc_chn_b rx should have a lower priority
284 than chn_a rx/tx/special_condition service*/
285 s
->rxint_under_svc
= 1;
286 if (s
->chn
== escc_chn_a
) {
287 s
->rregs
[R_INTR
] |= INTR_RXINTA
;
288 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
289 s
->otherchn
->rregs
[R_IVEC
] = IVEC_HIRXINTA
;
291 s
->otherchn
->rregs
[R_IVEC
] = IVEC_LORXINTA
;
293 s
->otherchn
->rregs
[R_INTR
] |= INTR_RXINTB
;
294 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
295 s
->rregs
[R_IVEC
] = IVEC_HIRXINTB
;
297 s
->rregs
[R_IVEC
] = IVEC_LORXINTB
;
302 static inline void set_txint(ESCCChannelState
*s
)
305 if (!s
->rxint_under_svc
) {
306 s
->txint_under_svc
= 1;
307 if (s
->chn
== escc_chn_a
) {
308 if (s
->wregs
[W_INTR
] & INTR_TXINT
) {
309 s
->rregs
[R_INTR
] |= INTR_TXINTA
;
311 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
312 s
->otherchn
->rregs
[R_IVEC
] = IVEC_HITXINTA
;
314 s
->otherchn
->rregs
[R_IVEC
] = IVEC_LOTXINTA
;
316 s
->rregs
[R_IVEC
] = IVEC_TXINTB
;
317 if (s
->wregs
[W_INTR
] & INTR_TXINT
) {
318 s
->otherchn
->rregs
[R_INTR
] |= INTR_TXINTB
;
325 static inline void clr_rxint(ESCCChannelState
*s
)
328 s
->rxint_under_svc
= 0;
329 if (s
->chn
== escc_chn_a
) {
330 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
331 s
->otherchn
->rregs
[R_IVEC
] = IVEC_HINOINT
;
333 s
->otherchn
->rregs
[R_IVEC
] = IVEC_LONOINT
;
334 s
->rregs
[R_INTR
] &= ~INTR_RXINTA
;
336 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
337 s
->rregs
[R_IVEC
] = IVEC_HINOINT
;
339 s
->rregs
[R_IVEC
] = IVEC_LONOINT
;
340 s
->otherchn
->rregs
[R_INTR
] &= ~INTR_RXINTB
;
347 static inline void clr_txint(ESCCChannelState
*s
)
350 s
->txint_under_svc
= 0;
351 if (s
->chn
== escc_chn_a
) {
352 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
353 s
->otherchn
->rregs
[R_IVEC
] = IVEC_HINOINT
;
355 s
->otherchn
->rregs
[R_IVEC
] = IVEC_LONOINT
;
356 s
->rregs
[R_INTR
] &= ~INTR_TXINTA
;
358 s
->otherchn
->rregs
[R_INTR
] &= ~INTR_TXINTB
;
359 if (s
->wregs
[W_MINTR
] & MINTR_STATUSHI
)
360 s
->rregs
[R_IVEC
] = IVEC_HINOINT
;
362 s
->rregs
[R_IVEC
] = IVEC_LONOINT
;
363 s
->otherchn
->rregs
[R_INTR
] &= ~INTR_TXINTB
;
370 static void escc_update_parameters(ESCCChannelState
*s
)
372 int speed
, parity
, data_bits
, stop_bits
;
373 QEMUSerialSetParams ssp
;
375 if (!qemu_chr_fe_backend_connected(&s
->chr
) || s
->type
!= escc_serial
)
378 if (s
->wregs
[W_TXCTRL1
] & TXCTRL1_PAREN
) {
379 if (s
->wregs
[W_TXCTRL1
] & TXCTRL1_PAREV
)
386 if ((s
->wregs
[W_TXCTRL1
] & TXCTRL1_STPMSK
) == TXCTRL1_2STOP
)
390 switch (s
->wregs
[W_TXCTRL2
] & TXCTRL2_BITMSK
) {
405 speed
= s
->clock
/ ((s
->wregs
[W_BRGLO
] | (s
->wregs
[W_BRGHI
] << 8)) + 2);
406 switch (s
->wregs
[W_TXCTRL1
] & TXCTRL1_CLKMSK
) {
422 ssp
.data_bits
= data_bits
;
423 ssp
.stop_bits
= stop_bits
;
424 trace_escc_update_parameters(CHN_C(s
), speed
, parity
, data_bits
, stop_bits
);
425 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
428 static void escc_mem_write(void *opaque
, hwaddr addr
,
429 uint64_t val
, unsigned size
)
431 ESCCState
*serial
= opaque
;
437 saddr
= (addr
>> serial
->it_shift
) & 1;
438 channel
= (addr
>> (serial
->it_shift
+ 1)) & 1;
439 s
= &serial
->chn
[channel
];
442 trace_escc_mem_writeb_ctrl(CHN_C(s
), s
->reg
, val
& 0xff);
446 newreg
= val
& CMD_PTR_MASK
;
456 if (s
->rxint_under_svc
) {
457 s
->rxint_under_svc
= 0;
461 } else if (s
->txint_under_svc
) {
462 s
->txint_under_svc
= 0;
470 case W_INTR
... W_RXCTRL
:
471 case W_SYNC1
... W_TXBUF
:
472 case W_MISC1
... W_CLOCK
:
473 case W_MISC2
... W_EXTINT
:
474 s
->wregs
[s
->reg
] = val
;
478 s
->wregs
[s
->reg
] = val
;
479 escc_update_parameters(s
);
483 s
->wregs
[s
->reg
] = val
;
484 s
->rregs
[s
->reg
] = val
;
485 escc_update_parameters(s
);
488 switch (val
& MINTR_RST_MASK
) {
493 escc_reset_chn(&serial
->chn
[0]);
496 escc_reset_chn(&serial
->chn
[1]);
499 escc_reset(DEVICE(serial
));
512 trace_escc_mem_writeb_data(CHN_C(s
), val
);
514 * Lower the irq when data is written to the Tx buffer and no other
515 * interrupts are currently pending. The irq will be raised again once
516 * the Tx buffer becomes empty below.
521 if (s
->wregs
[W_TXCTRL2
] & TXCTRL2_TXEN
) { // tx enabled
522 if (qemu_chr_fe_backend_connected(&s
->chr
)) {
523 /* XXX this blocks entire thread. Rewrite to use
524 * qemu_chr_fe_write and background I/O callbacks */
525 qemu_chr_fe_write_all(&s
->chr
, &s
->tx
, 1);
526 } else if (s
->type
== escc_kbd
&& !s
->disabled
) {
527 handle_kbd_command(s
, val
);
530 s
->rregs
[R_STATUS
] |= STATUS_TXEMPTY
; // Tx buffer empty
531 s
->rregs
[R_SPEC
] |= SPEC_ALLSENT
; // All sent
539 static uint64_t escc_mem_read(void *opaque
, hwaddr addr
,
542 ESCCState
*serial
= opaque
;
548 saddr
= (addr
>> serial
->it_shift
) & 1;
549 channel
= (addr
>> (serial
->it_shift
+ 1)) & 1;
550 s
= &serial
->chn
[channel
];
553 trace_escc_mem_readb_ctrl(CHN_C(s
), s
->reg
, s
->rregs
[s
->reg
]);
554 ret
= s
->rregs
[s
->reg
];
558 s
->rregs
[R_STATUS
] &= ~STATUS_RXAV
;
560 if (s
->type
== escc_kbd
|| s
->type
== escc_mouse
) {
565 trace_escc_mem_readb_data(CHN_C(s
), ret
);
566 qemu_chr_fe_accept_input(&s
->chr
);
574 static const MemoryRegionOps escc_mem_ops
= {
575 .read
= escc_mem_read
,
576 .write
= escc_mem_write
,
577 .endianness
= DEVICE_NATIVE_ENDIAN
,
579 .min_access_size
= 1,
580 .max_access_size
= 1,
584 static int serial_can_receive(void *opaque
)
586 ESCCChannelState
*s
= opaque
;
589 if (((s
->wregs
[W_RXCTRL
] & RXCTRL_RXEN
) == 0) // Rx not enabled
590 || ((s
->rregs
[R_STATUS
] & STATUS_RXAV
) == STATUS_RXAV
))
591 // char already available
598 static void serial_receive_byte(ESCCChannelState
*s
, int ch
)
600 trace_escc_serial_receive_byte(CHN_C(s
), ch
);
601 s
->rregs
[R_STATUS
] |= STATUS_RXAV
;
606 static void serial_receive_break(ESCCChannelState
*s
)
608 s
->rregs
[R_STATUS
] |= STATUS_BRK
;
612 static void serial_receive1(void *opaque
, const uint8_t *buf
, int size
)
614 ESCCChannelState
*s
= opaque
;
615 serial_receive_byte(s
, buf
[0]);
618 static void serial_event(void *opaque
, int event
)
620 ESCCChannelState
*s
= opaque
;
621 if (event
== CHR_EVENT_BREAK
)
622 serial_receive_break(s
);
625 static const VMStateDescription vmstate_escc_chn
= {
628 .minimum_version_id
= 1,
629 .fields
= (VMStateField
[]) {
630 VMSTATE_UINT32(vmstate_dummy
, ESCCChannelState
),
631 VMSTATE_UINT32(reg
, ESCCChannelState
),
632 VMSTATE_UINT32(rxint
, ESCCChannelState
),
633 VMSTATE_UINT32(txint
, ESCCChannelState
),
634 VMSTATE_UINT32(rxint_under_svc
, ESCCChannelState
),
635 VMSTATE_UINT32(txint_under_svc
, ESCCChannelState
),
636 VMSTATE_UINT8(rx
, ESCCChannelState
),
637 VMSTATE_UINT8(tx
, ESCCChannelState
),
638 VMSTATE_BUFFER(wregs
, ESCCChannelState
),
639 VMSTATE_BUFFER(rregs
, ESCCChannelState
),
640 VMSTATE_END_OF_LIST()
644 static const VMStateDescription vmstate_escc
= {
647 .minimum_version_id
= 1,
648 .fields
= (VMStateField
[]) {
649 VMSTATE_STRUCT_ARRAY(chn
, ESCCState
, 2, 2, vmstate_escc_chn
,
651 VMSTATE_END_OF_LIST()
655 static void sunkbd_handle_event(DeviceState
*dev
, QemuConsole
*src
,
658 ESCCChannelState
*s
= (ESCCChannelState
*)dev
;
662 assert(evt
->type
== INPUT_EVENT_KIND_KEY
);
663 key
= evt
->u
.key
.data
;
664 qcode
= qemu_input_key_value_to_qcode(key
->key
);
665 trace_escc_sunkbd_event_in(qcode
, QKeyCode_str(qcode
),
668 if (qcode
== Q_KEY_CODE_CAPS_LOCK
) {
670 s
->caps_lock_mode
^= 1;
671 if (s
->caps_lock_mode
== 2) {
672 return; /* Drop second press */
675 s
->caps_lock_mode
^= 2;
676 if (s
->caps_lock_mode
== 3) {
677 return; /* Drop first release */
682 if (qcode
== Q_KEY_CODE_NUM_LOCK
) {
684 s
->num_lock_mode
^= 1;
685 if (s
->num_lock_mode
== 2) {
686 return; /* Drop second press */
689 s
->num_lock_mode
^= 2;
690 if (s
->num_lock_mode
== 3) {
691 return; /* Drop first release */
696 if (qcode
> qemu_input_map_qcode_to_sun_len
) {
700 keycode
= qemu_input_map_qcode_to_sun
[qcode
];
704 trace_escc_sunkbd_event_out(keycode
);
705 put_queue(s
, keycode
);
708 static QemuInputHandler sunkbd_handler
= {
709 .name
= "sun keyboard",
710 .mask
= INPUT_EVENT_MASK_KEY
,
711 .event
= sunkbd_handle_event
,
714 static void handle_kbd_command(ESCCChannelState
*s
, int val
)
716 trace_escc_kbd_command(val
);
717 if (s
->led_mode
) { // Ignore led byte
722 case 1: // Reset, return type code
725 put_queue(s
, 4); // Type 4
728 case 0xe: // Set leds
731 case 7: // Query layout
735 put_queue(s
, 0x21); /* en-us layout */
742 static void sunmouse_event(void *opaque
,
743 int dx
, int dy
, int dz
, int buttons_state
)
745 ESCCChannelState
*s
= opaque
;
748 trace_escc_sunmouse_event(dx
, dy
, buttons_state
);
749 ch
= 0x80 | 0x7; /* protocol start byte, no buttons pressed */
751 if (buttons_state
& MOUSE_EVENT_LBUTTON
)
753 if (buttons_state
& MOUSE_EVENT_MBUTTON
)
755 if (buttons_state
& MOUSE_EVENT_RBUTTON
)
767 put_queue(s
, ch
& 0xff);
776 put_queue(s
, ch
& 0xff);
778 // MSC protocol specify two extra motion bytes
784 static void escc_init1(Object
*obj
)
786 ESCCState
*s
= ESCC(obj
);
787 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
790 for (i
= 0; i
< 2; i
++) {
791 sysbus_init_irq(dev
, &s
->chn
[i
].irq
);
792 s
->chn
[i
].chn
= 1 - i
;
794 s
->chn
[0].otherchn
= &s
->chn
[1];
795 s
->chn
[1].otherchn
= &s
->chn
[0];
797 sysbus_init_mmio(dev
, &s
->mmio
);
800 static void escc_realize(DeviceState
*dev
, Error
**errp
)
802 ESCCState
*s
= ESCC(dev
);
805 s
->chn
[0].disabled
= s
->disabled
;
806 s
->chn
[1].disabled
= s
->disabled
;
808 memory_region_init_io(&s
->mmio
, OBJECT(dev
), &escc_mem_ops
, s
, "escc",
809 ESCC_SIZE
<< s
->it_shift
);
811 for (i
= 0; i
< 2; i
++) {
812 if (qemu_chr_fe_backend_connected(&s
->chn
[i
].chr
)) {
813 s
->chn
[i
].clock
= s
->frequency
/ 2;
814 qemu_chr_fe_set_handlers(&s
->chn
[i
].chr
, serial_can_receive
,
815 serial_receive1
, serial_event
, NULL
,
816 &s
->chn
[i
], NULL
, true);
820 if (s
->chn
[0].type
== escc_mouse
) {
821 qemu_add_mouse_event_handler(sunmouse_event
, &s
->chn
[0], 0,
824 if (s
->chn
[1].type
== escc_kbd
) {
825 s
->chn
[1].hs
= qemu_input_handler_register((DeviceState
*)(&s
->chn
[1]),
830 static Property escc_properties
[] = {
831 DEFINE_PROP_UINT32("frequency", ESCCState
, frequency
, 0),
832 DEFINE_PROP_UINT32("it_shift", ESCCState
, it_shift
, 0),
833 DEFINE_PROP_UINT32("disabled", ESCCState
, disabled
, 0),
834 DEFINE_PROP_UINT32("chnBtype", ESCCState
, chn
[0].type
, 0),
835 DEFINE_PROP_UINT32("chnAtype", ESCCState
, chn
[1].type
, 0),
836 DEFINE_PROP_CHR("chrB", ESCCState
, chn
[0].chr
),
837 DEFINE_PROP_CHR("chrA", ESCCState
, chn
[1].chr
),
838 DEFINE_PROP_END_OF_LIST(),
841 static void escc_class_init(ObjectClass
*klass
, void *data
)
843 DeviceClass
*dc
= DEVICE_CLASS(klass
);
845 dc
->reset
= escc_reset
;
846 dc
->realize
= escc_realize
;
847 dc
->vmsd
= &vmstate_escc
;
848 dc
->props
= escc_properties
;
849 set_bit(DEVICE_CATEGORY_INPUT
, dc
->categories
);
852 static const TypeInfo escc_info
= {
854 .parent
= TYPE_SYS_BUS_DEVICE
,
855 .instance_size
= sizeof(ESCCState
),
856 .instance_init
= escc_init1
,
857 .class_init
= escc_class_init
,
860 static void escc_register_types(void)
862 type_register_static(&escc_info
);
865 type_init(escc_register_types
)