2 * QEMU RISC-V Boot Helper
4 * Copyright (c) 2017 SiFive, Inc.
5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "exec/cpu-defs.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "hw/riscv/boot.h"
28 #include "hw/riscv/boot_opensbi.h"
30 #include "sysemu/device_tree.h"
31 #include "sysemu/qtest.h"
32 #include "sysemu/kvm.h"
36 bool riscv_is_32bit(RISCVHartArrayState
*harts
)
38 return harts
->harts
[0].env
.misa_mxl_max
== MXL_RV32
;
42 * Return the per-socket PLIC hart topology configuration string
43 * (caller must free with g_free())
45 char *riscv_plic_hart_config_string(int hart_count
)
47 g_autofree
const char **vals
= g_new(const char *, hart_count
+ 1);
50 for (i
= 0; i
< hart_count
; i
++) {
51 CPUState
*cs
= qemu_get_cpu(i
);
52 CPURISCVState
*env
= &RISCV_CPU(cs
)->env
;
56 } else if (riscv_has_ext(env
, RVS
)) {
64 /* g_strjoinv() obliges us to cast away const here */
65 return g_strjoinv(",", (char **)vals
);
68 target_ulong
riscv_calc_kernel_start_addr(RISCVHartArrayState
*harts
,
69 target_ulong firmware_end_addr
) {
70 if (riscv_is_32bit(harts
)) {
71 return QEMU_ALIGN_UP(firmware_end_addr
, 4 * MiB
);
73 return QEMU_ALIGN_UP(firmware_end_addr
, 2 * MiB
);
77 target_ulong
riscv_find_and_load_firmware(MachineState
*machine
,
78 const char *default_machine_firmware
,
79 hwaddr firmware_load_addr
,
82 char *firmware_filename
= NULL
;
83 target_ulong firmware_end_addr
= firmware_load_addr
;
85 if ((!machine
->firmware
) || (!strcmp(machine
->firmware
, "default"))) {
87 * The user didn't specify -bios, or has specified "-bios default".
88 * That means we are going to load the OpenSBI binary included in
91 firmware_filename
= riscv_find_firmware(default_machine_firmware
);
92 } else if (strcmp(machine
->firmware
, "none")) {
93 firmware_filename
= riscv_find_firmware(machine
->firmware
);
96 if (firmware_filename
) {
97 /* If not "none" load the firmware */
98 firmware_end_addr
= riscv_load_firmware(firmware_filename
,
99 firmware_load_addr
, sym_cb
);
100 g_free(firmware_filename
);
103 return firmware_end_addr
;
106 char *riscv_find_firmware(const char *firmware_filename
)
110 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, firmware_filename
);
111 if (filename
== NULL
) {
112 if (!qtest_enabled()) {
114 * We only ship plain binary bios images in the QEMU source.
115 * With Spike machine that uses ELF images as the default bios,
116 * running QEMU test will complain hence let's suppress the error
117 * report for QEMU testing.
119 error_report("Unable to load the RISC-V firmware \"%s\"",
128 target_ulong
riscv_load_firmware(const char *firmware_filename
,
129 hwaddr firmware_load_addr
,
132 uint64_t firmware_entry
, firmware_size
, firmware_end
;
134 if (load_elf_ram_sym(firmware_filename
, NULL
, NULL
, NULL
,
135 &firmware_entry
, NULL
, &firmware_end
, NULL
,
136 0, EM_RISCV
, 1, 0, NULL
, true, sym_cb
) > 0) {
140 firmware_size
= load_image_targphys_as(firmware_filename
,
142 current_machine
->ram_size
, NULL
);
144 if (firmware_size
> 0) {
145 return firmware_load_addr
+ firmware_size
;
148 error_report("could not load firmware '%s'", firmware_filename
);
152 target_ulong
riscv_load_kernel(const char *kernel_filename
,
153 target_ulong kernel_start_addr
,
156 uint64_t kernel_load_base
, kernel_entry
;
159 * NB: Use low address not ELF entry point to ensure that the fw_dynamic
160 * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL
161 * behaviour, as well as fw_dynamic with a raw binary, all of which jump to
162 * the (expected) load address load address. This allows kernels to have
163 * separate SBI and ELF entry points (used by FreeBSD, for example).
165 if (load_elf_ram_sym(kernel_filename
, NULL
, NULL
, NULL
,
166 NULL
, &kernel_load_base
, NULL
, NULL
, 0,
167 EM_RISCV
, 1, 0, NULL
, true, sym_cb
) > 0) {
168 return kernel_load_base
;
171 if (load_uimage_as(kernel_filename
, &kernel_entry
, NULL
, NULL
,
172 NULL
, NULL
, NULL
) > 0) {
176 if (load_image_targphys_as(kernel_filename
, kernel_start_addr
,
177 current_machine
->ram_size
, NULL
) > 0) {
178 return kernel_start_addr
;
181 error_report("could not load kernel '%s'", kernel_filename
);
185 hwaddr
riscv_load_initrd(const char *filename
, uint64_t mem_size
,
186 uint64_t kernel_entry
, hwaddr
*start
)
191 * We want to put the initrd far enough into RAM that when the
192 * kernel is uncompressed it will not clobber the initrd. However
193 * on boards without much RAM we must ensure that we still leave
194 * enough room for a decent sized initrd, and on boards with large
195 * amounts of RAM we must avoid the initrd being so far up in RAM
196 * that it is outside lowmem and inaccessible to the kernel.
197 * So for boards with less than 256MB of RAM we put the initrd
198 * halfway into RAM, and for boards with 256MB of RAM or more we put
199 * the initrd at 128MB.
201 *start
= kernel_entry
+ MIN(mem_size
/ 2, 128 * MiB
);
203 size
= load_ramdisk(filename
, *start
, mem_size
- *start
);
205 size
= load_image_targphys(filename
, *start
, mem_size
- *start
);
207 error_report("could not load ramdisk '%s'", filename
);
212 return *start
+ size
;
215 uint32_t riscv_load_fdt(hwaddr dram_base
, uint64_t mem_size
, void *fdt
)
217 uint32_t temp
, fdt_addr
;
218 hwaddr dram_end
= dram_base
+ mem_size
;
219 int ret
, fdtsize
= fdt_totalsize(fdt
);
222 error_report("invalid device-tree");
227 * We should put fdt as far as possible to avoid kernel/initrd overwriting
228 * its content. But it should be addressable by 32 bit system as well.
229 * Thus, put it at an 16MB aligned address that less than fdt size from the
230 * end of dram or 3GB whichever is lesser.
232 temp
= MIN(dram_end
, 3072 * MiB
);
233 fdt_addr
= QEMU_ALIGN_DOWN(temp
- fdtsize
, 16 * MiB
);
236 /* Should only fail if we've built a corrupted tree */
238 /* copy in the device tree */
239 qemu_fdt_dumpdtb(fdt
, fdtsize
);
241 rom_add_blob_fixed_as("fdt", fdt
, fdtsize
, fdt_addr
,
242 &address_space_memory
);
247 void riscv_rom_copy_firmware_info(MachineState
*machine
, hwaddr rom_base
,
248 hwaddr rom_size
, uint32_t reset_vec_size
,
249 uint64_t kernel_entry
)
251 struct fw_dynamic_info dinfo
;
254 if (sizeof(dinfo
.magic
) == 4) {
255 dinfo
.magic
= cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE
);
256 dinfo
.version
= cpu_to_le32(FW_DYNAMIC_INFO_VERSION
);
257 dinfo
.next_mode
= cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S
);
258 dinfo
.next_addr
= cpu_to_le32(kernel_entry
);
260 dinfo
.magic
= cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE
);
261 dinfo
.version
= cpu_to_le64(FW_DYNAMIC_INFO_VERSION
);
262 dinfo
.next_mode
= cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S
);
263 dinfo
.next_addr
= cpu_to_le64(kernel_entry
);
267 dinfo_len
= sizeof(dinfo
);
270 * copy the dynamic firmware info. This information is specific to
271 * OpenSBI but doesn't break any other firmware as long as they don't
272 * expect any certain value in "a2" register.
274 if (dinfo_len
> (rom_size
- reset_vec_size
)) {
275 error_report("not enough space to store dynamic firmware info");
279 rom_add_blob_fixed_as("mrom.finfo", &dinfo
, dinfo_len
,
280 rom_base
+ reset_vec_size
,
281 &address_space_memory
);
284 void riscv_setup_rom_reset_vec(MachineState
*machine
, RISCVHartArrayState
*harts
,
286 hwaddr rom_base
, hwaddr rom_size
,
287 uint64_t kernel_entry
,
288 uint32_t fdt_load_addr
, void *fdt
)
291 uint32_t start_addr_hi32
= 0x00000000;
293 if (!riscv_is_32bit(harts
)) {
294 start_addr_hi32
= start_addr
>> 32;
297 uint32_t reset_vec
[10] = {
298 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
299 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
300 0xf1402573, /* csrr a0, mhartid */
303 0x00028067, /* jr t0 */
304 start_addr
, /* start: .dword */
306 fdt_load_addr
, /* fdt_laddr: .dword */
310 if (riscv_is_32bit(harts
)) {
311 reset_vec
[3] = 0x0202a583; /* lw a1, 32(t0) */
312 reset_vec
[4] = 0x0182a283; /* lw t0, 24(t0) */
314 reset_vec
[3] = 0x0202b583; /* ld a1, 32(t0) */
315 reset_vec
[4] = 0x0182b283; /* ld t0, 24(t0) */
318 /* copy in the reset vector in little_endian byte order */
319 for (i
= 0; i
< ARRAY_SIZE(reset_vec
); i
++) {
320 reset_vec
[i
] = cpu_to_le32(reset_vec
[i
]);
322 rom_add_blob_fixed_as("mrom.reset", reset_vec
, sizeof(reset_vec
),
323 rom_base
, &address_space_memory
);
324 riscv_rom_copy_firmware_info(machine
, rom_base
, rom_size
, sizeof(reset_vec
),
330 void riscv_setup_direct_kernel(hwaddr kernel_addr
, hwaddr fdt_addr
)
334 for (cs
= first_cpu
; cs
; cs
= CPU_NEXT(cs
)) {
335 RISCVCPU
*riscv_cpu
= RISCV_CPU(cs
);
336 riscv_cpu
->env
.kernel_addr
= kernel_addr
;
337 riscv_cpu
->env
.fdt_addr
= fdt_addr
;