2 * Q35 chipset based pc system emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on pc.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "hw/loader.h"
32 #include "sysemu/arch_init.h"
33 #include "hw/i2c/smbus.h"
34 #include "hw/boards.h"
35 #include "hw/timer/mc146818rtc.h"
36 #include "hw/xen/xen.h"
37 #include "sysemu/kvm.h"
38 #include "hw/kvm/clock.h"
39 #include "hw/pci-host/q35.h"
40 #include "exec/address-spaces.h"
41 #include "hw/i386/ich9.h"
42 #include "hw/i386/smbios.h"
43 #include "hw/ide/pci.h"
44 #include "hw/ide/ahci.h"
46 #include "hw/cpu/icc_bus.h"
47 #include "qemu/error-report.h"
48 #include "migration/migration.h"
50 /* ICH9 AHCI has 6 ports */
51 #define MAX_SATA_PORTS 6
53 static bool has_acpi_build
= true;
54 static bool rsdp_in_ram
= true;
55 static bool smbios_defaults
= true;
56 static bool smbios_legacy_mode
;
57 static bool smbios_uuid_encoded
= true;
58 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
59 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte
62 static bool gigabyte_align
= true;
63 static bool has_reserved_memory
= true;
65 /* PC hardware initialisation */
66 static void pc_q35_init(MachineState
*machine
)
68 PCMachineState
*pc_machine
= PC_MACHINE(machine
);
69 ram_addr_t below_4g_mem_size
, above_4g_mem_size
;
74 BusState
*idebus
[MAX_SATA_PORTS
];
76 MemoryRegion
*pci_memory
;
77 MemoryRegion
*rom_memory
;
78 MemoryRegion
*ram_memory
;
85 ICH9LPCState
*ich9_lpc
;
87 DeviceState
*icc_bridge
;
88 PcGuestInfo
*guest_info
;
90 DriveInfo
*hd
[MAX_SATA_PORTS
];
91 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
93 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
94 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
95 * also known as MMCFG).
96 * If it doesn't, we need to split it in chunks below and above 4G.
97 * In any case, try to make sure that guest addresses aligned at
98 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
99 * For old machine types, use whatever split we used historically to avoid
100 * breaking migration.
102 if (machine
->ram_size
>= 0xb0000000) {
103 lowmem
= gigabyte_align
? 0x80000000 : 0xb0000000;
108 /* Handle the machine opt max-ram-below-4g. It is basically doing
109 * min(qemu limit, user limit).
111 if (lowmem
> pc_machine
->max_ram_below_4g
) {
112 lowmem
= pc_machine
->max_ram_below_4g
;
113 if (machine
->ram_size
- lowmem
> lowmem
&&
114 lowmem
& ((1ULL << 30) - 1)) {
115 error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
116 ") not a multiple of 1G; possible bad performance.",
117 pc_machine
->max_ram_below_4g
);
121 if (machine
->ram_size
>= lowmem
) {
122 above_4g_mem_size
= machine
->ram_size
- lowmem
;
123 below_4g_mem_size
= lowmem
;
125 above_4g_mem_size
= 0;
126 below_4g_mem_size
= machine
->ram_size
;
129 if (xen_enabled() && xen_hvm_init(&below_4g_mem_size
, &above_4g_mem_size
,
131 fprintf(stderr
, "xen hardware virtual machine initialisation failed\n");
135 icc_bridge
= qdev_create(NULL
, TYPE_ICC_BRIDGE
);
136 object_property_add_child(qdev_get_machine(), "icc-bridge",
137 OBJECT(icc_bridge
), NULL
);
139 pc_cpus_init(machine
->cpu_model
, icc_bridge
);
140 pc_acpi_init("q35-acpi-dsdt.aml");
146 pci_memory
= g_new(MemoryRegion
, 1);
147 memory_region_init(pci_memory
, NULL
, "pci", UINT64_MAX
);
148 rom_memory
= pci_memory
;
151 rom_memory
= get_system_memory();
154 guest_info
= pc_guest_info_init(below_4g_mem_size
, above_4g_mem_size
);
155 guest_info
->isapc_ram_fw
= false;
156 guest_info
->has_acpi_build
= has_acpi_build
;
157 guest_info
->has_reserved_memory
= has_reserved_memory
;
158 guest_info
->rsdp_in_ram
= rsdp_in_ram
;
160 /* Migration was not supported in 2.0 for Q35, so do not bother
161 * with this hack (see hw/i386/acpi-build.c).
163 guest_info
->legacy_acpi_table_size
= 0;
165 if (smbios_defaults
) {
166 /* These values are guest ABI, do not change */
167 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
168 mc
->name
, smbios_legacy_mode
, smbios_uuid_encoded
);
171 /* allocate ram and load rom/bios */
172 if (!xen_enabled()) {
173 pc_memory_init(machine
, get_system_memory(),
174 below_4g_mem_size
, above_4g_mem_size
,
175 rom_memory
, &ram_memory
, guest_info
);
179 gsi_state
= g_malloc0(sizeof(*gsi_state
));
180 if (kvm_irqchip_in_kernel()) {
181 kvm_pc_setup_irq_routing(pci_enabled
);
182 gsi
= qemu_allocate_irqs(kvm_pc_gsi_handler
, gsi_state
,
185 gsi
= qemu_allocate_irqs(gsi_handler
, gsi_state
, GSI_NUM_PINS
);
188 /* create pci host bus */
189 q35_host
= Q35_HOST_DEVICE(qdev_create(NULL
, TYPE_Q35_HOST_DEVICE
));
191 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host
), NULL
);
192 q35_host
->mch
.ram_memory
= ram_memory
;
193 q35_host
->mch
.pci_address_space
= pci_memory
;
194 q35_host
->mch
.system_memory
= get_system_memory();
195 q35_host
->mch
.address_space_io
= get_system_io();
196 q35_host
->mch
.below_4g_mem_size
= below_4g_mem_size
;
197 q35_host
->mch
.above_4g_mem_size
= above_4g_mem_size
;
198 q35_host
->mch
.guest_info
= guest_info
;
200 qdev_init_nofail(DEVICE(q35_host
));
201 phb
= PCI_HOST_BRIDGE(q35_host
);
204 lpc
= pci_create_simple_multifunction(host_bus
, PCI_DEVFN(ICH9_LPC_DEV
,
205 ICH9_LPC_FUNC
), true,
206 TYPE_ICH9_LPC_DEVICE
);
208 object_property_add_link(OBJECT(machine
), PC_MACHINE_ACPI_DEVICE_PROP
,
209 TYPE_HOTPLUG_HANDLER
,
210 (Object
**)&pc_machine
->acpi_dev
,
211 object_property_allow_set_link
,
212 OBJ_PROP_LINK_UNREF_ON_RELEASE
, &error_abort
);
213 object_property_set_link(OBJECT(machine
), OBJECT(lpc
),
214 PC_MACHINE_ACPI_DEVICE_PROP
, &error_abort
);
216 ich9_lpc
= ICH9_LPC_DEVICE(lpc
);
218 ich9_lpc
->ioapic
= gsi_state
->ioapic_irq
;
219 pci_bus_irqs(host_bus
, ich9_lpc_set_irq
, ich9_lpc_map_irq
, ich9_lpc
,
221 pci_bus_set_route_irq_fn(host_bus
, ich9_route_intx_pin_to_irq
);
222 isa_bus
= ich9_lpc
->isa_bus
;
225 isa_bus_irqs(isa_bus
, gsi
);
227 if (kvm_irqchip_in_kernel()) {
228 i8259
= kvm_i8259_init(isa_bus
);
229 } else if (xen_enabled()) {
230 i8259
= xen_interrupt_controller_init();
232 i8259
= i8259_init(isa_bus
, pc_allocate_cpu_irq());
235 for (i
= 0; i
< ISA_NUM_IRQS
; i
++) {
236 gsi_state
->i8259_irq
[i
] = i8259
[i
];
239 ioapic_init_gsi(gsi_state
, "q35");
241 qdev_init_nofail(icc_bridge
);
243 pc_register_ferr_irq(gsi
[13]);
245 assert(pc_machine
->vmport
!= ON_OFF_AUTO_MAX
);
246 if (pc_machine
->vmport
== ON_OFF_AUTO_AUTO
) {
247 pc_machine
->vmport
= xen_enabled() ? ON_OFF_AUTO_OFF
: ON_OFF_AUTO_ON
;
250 /* init basic PC hardware */
251 pc_basic_device_init(isa_bus
, gsi
, &rtc_state
, !mc
->no_floppy
,
252 (pc_machine
->vmport
!= ON_OFF_AUTO_ON
), 0xff0104);
254 /* connect pm stuff to lpc */
255 ich9_lpc_pm_init(lpc
, pc_machine_is_smm_enabled(pc_machine
), !mc
->no_tco
);
257 /* ahci and SATA device, for q35 1 ahci controller is built-in */
258 ahci
= pci_create_simple_multifunction(host_bus
,
259 PCI_DEVFN(ICH9_SATA1_DEV
,
262 idebus
[0] = qdev_get_child_bus(&ahci
->qdev
, "ide.0");
263 idebus
[1] = qdev_get_child_bus(&ahci
->qdev
, "ide.1");
264 g_assert(MAX_SATA_PORTS
== ICH_AHCI(ahci
)->ahci
.ports
);
265 ide_drive_get(hd
, ICH_AHCI(ahci
)->ahci
.ports
);
266 ahci_ide_create_devs(ahci
, hd
);
269 /* Should we create 6 UHCI according to ich9 spec? */
270 ehci_create_ich9_with_companions(host_bus
, 0x1d);
273 /* TODO: Populate SPD eeprom data. */
274 smbus_eeprom_init(ich9_smb_init(host_bus
,
275 PCI_DEVFN(ICH9_SMB_DEV
, ICH9_SMB_FUNC
),
279 pc_cmos_init(below_4g_mem_size
, above_4g_mem_size
, machine
->boot_order
,
280 machine
, idebus
[0], idebus
[1], rtc_state
);
282 /* the rest devices to which pci devfn is automatically assigned */
283 pc_vga_init(isa_bus
, host_bus
);
284 pc_nic_init(isa_bus
, host_bus
);
286 pc_pci_device_init(host_bus
);
290 static void pc_compat_2_3(MachineState
*machine
)
292 PCMachineState
*pcms
= PC_MACHINE(machine
);
293 savevm_skip_section_footers();
295 pcms
->smm
= ON_OFF_AUTO_OFF
;
297 global_state_set_optional();
298 savevm_skip_configuration();
301 static void pc_compat_2_2(MachineState
*machine
)
303 pc_compat_2_3(machine
);
305 x86_cpu_compat_set_features("kvm64", FEAT_1_EDX
, 0, CPUID_VME
);
306 x86_cpu_compat_set_features("kvm32", FEAT_1_EDX
, 0, CPUID_VME
);
307 x86_cpu_compat_set_features("Conroe", FEAT_1_EDX
, 0, CPUID_VME
);
308 x86_cpu_compat_set_features("Penryn", FEAT_1_EDX
, 0, CPUID_VME
);
309 x86_cpu_compat_set_features("Nehalem", FEAT_1_EDX
, 0, CPUID_VME
);
310 x86_cpu_compat_set_features("Westmere", FEAT_1_EDX
, 0, CPUID_VME
);
311 x86_cpu_compat_set_features("SandyBridge", FEAT_1_EDX
, 0, CPUID_VME
);
312 x86_cpu_compat_set_features("Haswell", FEAT_1_EDX
, 0, CPUID_VME
);
313 x86_cpu_compat_set_features("Broadwell", FEAT_1_EDX
, 0, CPUID_VME
);
314 x86_cpu_compat_set_features("Opteron_G1", FEAT_1_EDX
, 0, CPUID_VME
);
315 x86_cpu_compat_set_features("Opteron_G2", FEAT_1_EDX
, 0, CPUID_VME
);
316 x86_cpu_compat_set_features("Opteron_G3", FEAT_1_EDX
, 0, CPUID_VME
);
317 x86_cpu_compat_set_features("Opteron_G4", FEAT_1_EDX
, 0, CPUID_VME
);
318 x86_cpu_compat_set_features("Opteron_G5", FEAT_1_EDX
, 0, CPUID_VME
);
319 x86_cpu_compat_set_features("Haswell", FEAT_1_ECX
, 0, CPUID_EXT_F16C
);
320 x86_cpu_compat_set_features("Haswell", FEAT_1_ECX
, 0, CPUID_EXT_RDRAND
);
321 x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX
, 0, CPUID_EXT_F16C
);
322 x86_cpu_compat_set_features("Broadwell", FEAT_1_ECX
, 0, CPUID_EXT_RDRAND
);
323 machine
->suppress_vmdesc
= true;
326 static void pc_compat_2_1(MachineState
*machine
)
328 PCMachineState
*pcms
= PC_MACHINE(machine
);
330 pc_compat_2_2(machine
);
331 pcms
->enforce_aligned_dimm
= false;
332 smbios_uuid_encoded
= false;
333 x86_cpu_compat_set_features("coreduo", FEAT_1_ECX
, CPUID_EXT_VMX
, 0);
334 x86_cpu_compat_set_features("core2duo", FEAT_1_ECX
, CPUID_EXT_VMX
, 0);
335 x86_cpu_compat_kvm_no_autodisable(FEAT_8000_0001_ECX
, CPUID_EXT3_SVM
);
338 static void pc_compat_2_0(MachineState
*machine
)
340 pc_compat_2_1(machine
);
341 smbios_legacy_mode
= true;
342 has_reserved_memory
= false;
343 pc_set_legacy_acpi_data_size();
346 static void pc_compat_1_7(MachineState
*machine
)
348 pc_compat_2_0(machine
);
349 smbios_defaults
= false;
350 gigabyte_align
= false;
351 option_rom_has_mr
= true;
352 x86_cpu_compat_kvm_no_autoenable(FEAT_1_ECX
, CPUID_EXT_X2APIC
);
355 static void pc_compat_1_6(MachineState
*machine
)
357 pc_compat_1_7(machine
);
358 rom_file_has_mr
= false;
359 has_acpi_build
= false;
362 static void pc_compat_1_5(MachineState
*machine
)
364 pc_compat_1_6(machine
);
367 static void pc_compat_1_4(MachineState
*machine
)
369 pc_compat_1_5(machine
);
370 x86_cpu_compat_set_features("n270", FEAT_1_ECX
, 0, CPUID_EXT_MOVBE
);
371 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX
, 0, CPUID_EXT_PCLMULQDQ
);
374 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
375 static void pc_init_##suffix(MachineState *machine) \
377 void (*compat)(MachineState *m) = (compatfn); \
381 pc_q35_init(machine); \
383 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
386 static void pc_q35_machine_options(MachineClass
*m
)
388 pc_default_machine_options(m
);
389 m
->family
= "pc_q35";
390 m
->desc
= "Standard PC (Q35 + ICH9, 2009)";
391 m
->hot_add_cpu
= pc_hot_add_cpu
;
392 m
->units_per_default_bus
= 1;
395 static void pc_q35_2_4_machine_options(MachineClass
*m
)
397 pc_q35_machine_options(m
);
398 m
->default_machine_opts
= "firmware=bios-256k.bin";
399 m
->default_display
= "std";
405 DEFINE_Q35_MACHINE(v2_4
, "pc-q35-2.4", NULL
,
406 pc_q35_2_4_machine_options
);
409 static void pc_q35_2_3_machine_options(MachineClass
*m
)
411 pc_q35_2_4_machine_options(m
);
415 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_3
);
418 DEFINE_Q35_MACHINE(v2_3
, "pc-q35-2.3", pc_compat_2_3
,
419 pc_q35_2_3_machine_options
);
422 static void pc_q35_2_2_machine_options(MachineClass
*m
)
424 pc_q35_2_3_machine_options(m
);
425 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_2
);
428 DEFINE_Q35_MACHINE(v2_2
, "pc-q35-2.2", pc_compat_2_2
,
429 pc_q35_2_2_machine_options
);
432 static void pc_q35_2_1_machine_options(MachineClass
*m
)
434 pc_q35_2_2_machine_options(m
);
435 m
->default_display
= NULL
;
436 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_1
);
439 DEFINE_Q35_MACHINE(v2_1
, "pc-q35-2.1", pc_compat_2_1
,
440 pc_q35_2_1_machine_options
);
443 static void pc_q35_2_0_machine_options(MachineClass
*m
)
445 pc_q35_2_1_machine_options(m
);
446 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_0
);
449 DEFINE_Q35_MACHINE(v2_0
, "pc-q35-2.0", pc_compat_2_0
,
450 pc_q35_2_0_machine_options
);
453 static void pc_q35_1_7_machine_options(MachineClass
*m
)
455 pc_q35_2_0_machine_options(m
);
456 m
->default_machine_opts
= NULL
;
457 SET_MACHINE_COMPAT(m
, PC_COMPAT_1_7
);
460 DEFINE_Q35_MACHINE(v1_7
, "pc-q35-1.7", pc_compat_1_7
,
461 pc_q35_1_7_machine_options
);
464 static void pc_q35_1_6_machine_options(MachineClass
*m
)
466 pc_q35_machine_options(m
);
467 SET_MACHINE_COMPAT(m
, PC_COMPAT_1_6
);
470 DEFINE_Q35_MACHINE(v1_6
, "pc-q35-1.6", pc_compat_1_6
,
471 pc_q35_1_6_machine_options
);
474 static void pc_q35_1_5_machine_options(MachineClass
*m
)
476 pc_q35_1_6_machine_options(m
);
477 SET_MACHINE_COMPAT(m
, PC_COMPAT_1_5
);
480 DEFINE_Q35_MACHINE(v1_5
, "pc-q35-1.5", pc_compat_1_5
,
481 pc_q35_1_5_machine_options
);
484 static void pc_q35_1_4_machine_options(MachineClass
*m
)
486 pc_q35_1_5_machine_options(m
);
487 m
->hot_add_cpu
= NULL
;
488 SET_MACHINE_COMPAT(m
, PC_COMPAT_1_4
);
491 DEFINE_Q35_MACHINE(v1_4
, "pc-q35-1.4", pc_compat_1_4
,
492 pc_q35_1_4_machine_options
);