hw/char/etraxfs_ser.c

   1 /*
   2  * QEMU ETRAX System Emulator
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "sysemu/char.h"
  28 #include "qemu/log.h"
  29
  30 #define D(x)
  31
  32 #define RW_TR_CTRL     (0x00 / 4)
  33 #define RW_TR_DMA_EN   (0x04 / 4)
  34 #define RW_REC_CTRL    (0x08 / 4)
  35 #define RW_DOUT        (0x1c / 4)
  36 #define RS_STAT_DIN    (0x20 / 4)
  37 #define R_STAT_DIN     (0x24 / 4)
  38 #define RW_INTR_MASK   (0x2c / 4)
  39 #define RW_ACK_INTR    (0x30 / 4)
  40 #define R_INTR         (0x34 / 4)
  41 #define R_MASKED_INTR  (0x38 / 4)
  42 #define R_MAX          (0x3c / 4)
  43
  44 #define STAT_DAV     16
  45 #define STAT_TR_IDLE 22
  46 #define STAT_TR_RDY  24
  47
  48 #define TYPE_ETRAX_FS_SERIAL "etraxfs,serial"
  49 #define ETRAX_SERIAL(obj) \
  50     OBJECT_CHECK(ETRAXSerial, (obj), TYPE_ETRAX_FS_SERIAL)
  51
  52 typedef struct ETRAXSerial {
  53     SysBusDevice parent_obj;
  54
  55     MemoryRegion mmio;
  56     CharDriverState *chr;
  57     qemu_irq irq;
  58
  59     int pending_tx;
  60
  61     uint8_t rx_fifo[16];
  62     unsigned int rx_fifo_pos;
  63     unsigned int rx_fifo_len;
  64
  65     /* Control registers.  */
  66     uint32_t regs[R_MAX];
  67 } ETRAXSerial;
  68
  69 static void ser_update_irq(ETRAXSerial *s)
  70 {
  71
  72     if (s->rx_fifo_len) {
  73         s->regs[R_INTR] |= 8;
  74     } else {
  75         s->regs[R_INTR] &= ~8;
  76     }
  77
  78     s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
  79     qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
  80 }
  81
  82 static uint64_t
  83 ser_read(void *opaque, hwaddr addr, unsigned int size)
  84 {
  85     ETRAXSerial *s = opaque;
  86     uint32_t r = 0;
  87
  88     addr >>= 2;
  89     switch (addr)
  90     {
  91         case R_STAT_DIN:
  92             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
  93             if (s->rx_fifo_len) {
  94                 r |= 1 << STAT_DAV;
  95             }
  96             r |= 1 << STAT_TR_RDY;
  97             r |= 1 << STAT_TR_IDLE;
  98             break;
  99         case RS_STAT_DIN:
 100             r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
 101             if (s->rx_fifo_len) {
 102                 r |= 1 << STAT_DAV;
 103                 s->rx_fifo_len--;
 104             }
 105             r |= 1 << STAT_TR_RDY;
 106             r |= 1 << STAT_TR_IDLE;
 107             break;
 108         default:
 109             r = s->regs[addr];
 110             D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
 111             break;
 112     }
 113     return r;
 114 }
 115
 116 static void
 117 ser_write(void *opaque, hwaddr addr,
 118           uint64_t val64, unsigned int size)
 119 {
 120     ETRAXSerial *s = opaque;
 121     uint32_t value = val64;
 122     unsigned char ch = val64;
 123
 124     D(qemu_log("%s " TARGET_FMT_plx "=%x\n",  __func__, addr, value));
 125     addr >>= 2;
 126     switch (addr)
 127     {
 128         case RW_DOUT:
 129             qemu_chr_fe_write(s->chr, &ch, 1);
 130             s->regs[R_INTR] |= 3;
 131             s->pending_tx = 1;
 132             s->regs[addr] = value;
 133             break;
 134         case RW_ACK_INTR:
 135             if (s->pending_tx) {
 136                 value &= ~1;
 137                 s->pending_tx = 0;
 138                 D(qemu_log("fixedup value=%x r_intr=%x\n",
 139                            value, s->regs[R_INTR]));
 140             }
 141             s->regs[addr] = value;
 142             s->regs[R_INTR] &= ~value;
 143             D(printf("r_intr=%x\n", s->regs[R_INTR]));
 144             break;
 145         default:
 146             s->regs[addr] = value;
 147             break;
 148     }
 149     ser_update_irq(s);
 150 }
 151
 152 static const MemoryRegionOps ser_ops = {
 153     .read = ser_read,
 154     .write = ser_write,
 155     .endianness = DEVICE_NATIVE_ENDIAN,
 156     .valid = {
 157         .min_access_size = 4,
 158         .max_access_size = 4
 159     }
 160 };
 161
 162 static void serial_receive(void *opaque, const uint8_t *buf, int size)
 163 {
 164     ETRAXSerial *s = opaque;
 165     int i;
 166
 167     /* Got a byte.  */
 168     if (s->rx_fifo_len >= 16) {
 169         D(qemu_log("WARNING: UART dropped char.\n"));
 170         return;
 171     }
 172
 173     for (i = 0; i < size; i++) {
 174         s->rx_fifo[s->rx_fifo_pos] = buf[i];
 175         s->rx_fifo_pos++;
 176         s->rx_fifo_pos &= 15;
 177         s->rx_fifo_len++;
 178     }
 179
 180     ser_update_irq(s);
 181 }
 182
 183 static int serial_can_receive(void *opaque)
 184 {
 185     ETRAXSerial *s = opaque;
 186
 187     /* Is the receiver enabled?  */
 188     if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
 189         return 0;
 190     }
 191
 192     return sizeof(s->rx_fifo) - s->rx_fifo_len;
 193 }
 194
 195 static void serial_event(void *opaque, int event)
 196 {
 197
 198 }
 199
 200 static void etraxfs_ser_reset(DeviceState *d)
 201 {
 202     ETRAXSerial *s = ETRAX_SERIAL(d);
 203
 204     /* transmitter begins ready and idle.  */
 205     s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
 206     s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
 207
 208     s->regs[RW_REC_CTRL] = 0x10000;
 209
 210 }
 211
 212 static int etraxfs_ser_init(SysBusDevice *dev)
 213 {
 214     ETRAXSerial *s = ETRAX_SERIAL(dev);
 215
 216     sysbus_init_irq(dev, &s->irq);
 217     memory_region_init_io(&s->mmio, OBJECT(s), &ser_ops, s,
 218                           "etraxfs-serial", R_MAX * 4);
 219     sysbus_init_mmio(dev, &s->mmio);
 220
 221     /* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
 222     s->chr = qemu_char_get_next_serial();
 223     if (s->chr) {
 224         qemu_chr_add_handlers(s->chr,
 225                               serial_can_receive, serial_receive,
 226                               serial_event, s);
 227     }
 228     return 0;
 229 }
 230
 231 static void etraxfs_ser_class_init(ObjectClass *klass, void *data)
 232 {
 233     DeviceClass *dc = DEVICE_CLASS(klass);
 234     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 235
 236     k->init = etraxfs_ser_init;
 237     dc->reset = etraxfs_ser_reset;
 238     /* Reason: init() method uses qemu_char_get_next_serial() */
 239     dc->cannot_instantiate_with_device_add_yet = true;
 240 }
 241
 242 static const TypeInfo etraxfs_ser_info = {
 243     .name          = TYPE_ETRAX_FS_SERIAL,
 244     .parent        = TYPE_SYS_BUS_DEVICE,
 245     .instance_size = sizeof(ETRAXSerial),
 246     .class_init    = etraxfs_ser_class_init,
 247 };
 248
 249 static void etraxfs_serial_register_types(void)
 250 {
 251     type_register_static(&etraxfs_ser_info);
 252 }
 253
 254 type_init(etraxfs_serial_register_types)