hw/vmware_vga.c

   1 /*
   2  * QEMU VMware-SVGA "chipset".
   3  *
   4  * Copyright (c) 2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "loader.h"
  26 #include "console.h"
  27 #include "pci.h"
  28
  29 #undef VERBOSE
  30 #define HW_RECT_ACCEL
  31 #define HW_FILL_ACCEL
  32 #define HW_MOUSE_ACCEL
  33
  34 # include "vga_int.h"
  35
  36 struct vmsvga_state_s {
  37     VGACommonState vga;
  38
  39     int width;
  40     int height;
  41     int invalidated;
  42     int depth;
  43     int bypp;
  44     int enable;
  45     int config;
  46     struct {
  47         int id;
  48         int x;
  49         int y;
  50         int on;
  51     } cursor;
  52
  53     int index;
  54     int scratch_size;
  55     uint32_t *scratch;
  56     int new_width;
  57     int new_height;
  58     uint32_t guest;
  59     uint32_t svgaid;
  60     uint32_t wred;
  61     uint32_t wgreen;
  62     uint32_t wblue;
  63     int syncing;
  64     int fb_size;
  65
  66     MemoryRegion fifo_ram;
  67     uint8_t *fifo_ptr;
  68     unsigned int fifo_size;
  69
  70     union {
  71         uint32_t *fifo;
  72         struct QEMU_PACKED {
  73             uint32_t min;
  74             uint32_t max;
  75             uint32_t next_cmd;
  76             uint32_t stop;
  77             /* Add registers here when adding capabilities.  */
  78             uint32_t fifo[0];
  79         } *cmd;
  80     };
  81
  82 #define REDRAW_FIFO_LEN 512
  83     struct vmsvga_rect_s {
  84         int x, y, w, h;
  85     } redraw_fifo[REDRAW_FIFO_LEN];
  86     int redraw_fifo_first, redraw_fifo_last;
  87 };
  88
  89 struct pci_vmsvga_state_s {
  90     PCIDevice card;
  91     struct vmsvga_state_s chip;
  92     MemoryRegion io_bar;
  93 };
  94
  95 #define SVGA_MAGIC              0x900000UL
  96 #define SVGA_MAKE_ID(ver)       (SVGA_MAGIC << 8 | (ver))
  97 #define SVGA_ID_0               SVGA_MAKE_ID(0)
  98 #define SVGA_ID_1               SVGA_MAKE_ID(1)
  99 #define SVGA_ID_2               SVGA_MAKE_ID(2)
 100
 101 #define SVGA_LEGACY_BASE_PORT   0x4560
 102 #define SVGA_INDEX_PORT         0x0
 103 #define SVGA_VALUE_PORT         0x1
 104 #define SVGA_BIOS_PORT          0x2
 105
 106 #define SVGA_VERSION_2
 107
 108 #ifdef SVGA_VERSION_2
 109 # define SVGA_ID                SVGA_ID_2
 110 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 111 # define SVGA_IO_MUL            1
 112 # define SVGA_FIFO_SIZE         0x10000
 113 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA2
 114 #else
 115 # define SVGA_ID                SVGA_ID_1
 116 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 117 # define SVGA_IO_MUL            4
 118 # define SVGA_FIFO_SIZE         0x10000
 119 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA
 120 #endif
 121
 122 enum {
 123     /* ID 0, 1 and 2 registers */
 124     SVGA_REG_ID = 0,
 125     SVGA_REG_ENABLE = 1,
 126     SVGA_REG_WIDTH = 2,
 127     SVGA_REG_HEIGHT = 3,
 128     SVGA_REG_MAX_WIDTH = 4,
 129     SVGA_REG_MAX_HEIGHT = 5,
 130     SVGA_REG_DEPTH = 6,
 131     SVGA_REG_BITS_PER_PIXEL = 7,        /* Current bpp in the guest */
 132     SVGA_REG_PSEUDOCOLOR = 8,
 133     SVGA_REG_RED_MASK = 9,
 134     SVGA_REG_GREEN_MASK = 10,
 135     SVGA_REG_BLUE_MASK = 11,
 136     SVGA_REG_BYTES_PER_LINE = 12,
 137     SVGA_REG_FB_START = 13,
 138     SVGA_REG_FB_OFFSET = 14,
 139     SVGA_REG_VRAM_SIZE = 15,
 140     SVGA_REG_FB_SIZE = 16,
 141
 142     /* ID 1 and 2 registers */
 143     SVGA_REG_CAPABILITIES = 17,
 144     SVGA_REG_MEM_START = 18,            /* Memory for command FIFO */
 145     SVGA_REG_MEM_SIZE = 19,
 146     SVGA_REG_CONFIG_DONE = 20,          /* Set when memory area configured */
 147     SVGA_REG_SYNC = 21,                 /* Write to force synchronization */
 148     SVGA_REG_BUSY = 22,                 /* Read to check if sync is done */
 149     SVGA_REG_GUEST_ID = 23,             /* Set guest OS identifier */
 150     SVGA_REG_CURSOR_ID = 24,            /* ID of cursor */
 151     SVGA_REG_CURSOR_X = 25,             /* Set cursor X position */
 152     SVGA_REG_CURSOR_Y = 26,             /* Set cursor Y position */
 153     SVGA_REG_CURSOR_ON = 27,            /* Turn cursor on/off */
 154     SVGA_REG_HOST_BITS_PER_PIXEL = 28,  /* Current bpp in the host */
 155     SVGA_REG_SCRATCH_SIZE = 29,         /* Number of scratch registers */
 156     SVGA_REG_MEM_REGS = 30,             /* Number of FIFO registers */
 157     SVGA_REG_NUM_DISPLAYS = 31,         /* Number of guest displays */
 158     SVGA_REG_PITCHLOCK = 32,            /* Fixed pitch for all modes */
 159
 160     SVGA_PALETTE_BASE = 1024,           /* Base of SVGA color map */
 161     SVGA_PALETTE_END  = SVGA_PALETTE_BASE + 767,
 162     SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
 163 };
 164
 165 #define SVGA_CAP_NONE                   0
 166 #define SVGA_CAP_RECT_FILL              (1 << 0)
 167 #define SVGA_CAP_RECT_COPY              (1 << 1)
 168 #define SVGA_CAP_RECT_PAT_FILL          (1 << 2)
 169 #define SVGA_CAP_LEGACY_OFFSCREEN       (1 << 3)
 170 #define SVGA_CAP_RASTER_OP              (1 << 4)
 171 #define SVGA_CAP_CURSOR                 (1 << 5)
 172 #define SVGA_CAP_CURSOR_BYPASS          (1 << 6)
 173 #define SVGA_CAP_CURSOR_BYPASS_2        (1 << 7)
 174 #define SVGA_CAP_8BIT_EMULATION         (1 << 8)
 175 #define SVGA_CAP_ALPHA_CURSOR           (1 << 9)
 176 #define SVGA_CAP_GLYPH                  (1 << 10)
 177 #define SVGA_CAP_GLYPH_CLIPPING         (1 << 11)
 178 #define SVGA_CAP_OFFSCREEN_1            (1 << 12)
 179 #define SVGA_CAP_ALPHA_BLEND            (1 << 13)
 180 #define SVGA_CAP_3D                     (1 << 14)
 181 #define SVGA_CAP_EXTENDED_FIFO          (1 << 15)
 182 #define SVGA_CAP_MULTIMON               (1 << 16)
 183 #define SVGA_CAP_PITCHLOCK              (1 << 17)
 184
 185 /*
 186  * FIFO offsets (seen as an array of 32-bit words)
 187  */
 188 enum {
 189     /*
 190      * The original defined FIFO offsets
 191      */
 192     SVGA_FIFO_MIN = 0,
 193     SVGA_FIFO_MAX,      /* The distance from MIN to MAX must be at least 10K */
 194     SVGA_FIFO_NEXT_CMD,
 195     SVGA_FIFO_STOP,
 196
 197     /*
 198      * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
 199      */
 200     SVGA_FIFO_CAPABILITIES = 4,
 201     SVGA_FIFO_FLAGS,
 202     SVGA_FIFO_FENCE,
 203     SVGA_FIFO_3D_HWVERSION,
 204     SVGA_FIFO_PITCHLOCK,
 205 };
 206
 207 #define SVGA_FIFO_CAP_NONE              0
 208 #define SVGA_FIFO_CAP_FENCE             (1 << 0)
 209 #define SVGA_FIFO_CAP_ACCELFRONT        (1 << 1)
 210 #define SVGA_FIFO_CAP_PITCHLOCK         (1 << 2)
 211
 212 #define SVGA_FIFO_FLAG_NONE             0
 213 #define SVGA_FIFO_FLAG_ACCELFRONT       (1 << 0)
 214
 215 /* These values can probably be changed arbitrarily.  */
 216 #define SVGA_SCRATCH_SIZE               0x8000
 217 #define SVGA_MAX_WIDTH                  2360
 218 #define SVGA_MAX_HEIGHT                 1770
 219
 220 #ifdef VERBOSE
 221 # define GUEST_OS_BASE          0x5001
 222 static const char *vmsvga_guest_id[] = {
 223     [0x00] = "Dos",
 224     [0x01] = "Windows 3.1",
 225     [0x02] = "Windows 95",
 226     [0x03] = "Windows 98",
 227     [0x04] = "Windows ME",
 228     [0x05] = "Windows NT",
 229     [0x06] = "Windows 2000",
 230     [0x07] = "Linux",
 231     [0x08] = "OS/2",
 232     [0x09] = "an unknown OS",
 233     [0x0a] = "BSD",
 234     [0x0b] = "Whistler",
 235     [0x0c] = "an unknown OS",
 236     [0x0d] = "an unknown OS",
 237     [0x0e] = "an unknown OS",
 238     [0x0f] = "an unknown OS",
 239     [0x10] = "an unknown OS",
 240     [0x11] = "an unknown OS",
 241     [0x12] = "an unknown OS",
 242     [0x13] = "an unknown OS",
 243     [0x14] = "an unknown OS",
 244     [0x15] = "Windows 2003",
 245 };
 246 #endif
 247
 248 enum {
 249     SVGA_CMD_INVALID_CMD = 0,
 250     SVGA_CMD_UPDATE = 1,
 251     SVGA_CMD_RECT_FILL = 2,
 252     SVGA_CMD_RECT_COPY = 3,
 253     SVGA_CMD_DEFINE_BITMAP = 4,
 254     SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
 255     SVGA_CMD_DEFINE_PIXMAP = 6,
 256     SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
 257     SVGA_CMD_RECT_BITMAP_FILL = 8,
 258     SVGA_CMD_RECT_PIXMAP_FILL = 9,
 259     SVGA_CMD_RECT_BITMAP_COPY = 10,
 260     SVGA_CMD_RECT_PIXMAP_COPY = 11,
 261     SVGA_CMD_FREE_OBJECT = 12,
 262     SVGA_CMD_RECT_ROP_FILL = 13,
 263     SVGA_CMD_RECT_ROP_COPY = 14,
 264     SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
 265     SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
 266     SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
 267     SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
 268     SVGA_CMD_DEFINE_CURSOR = 19,
 269     SVGA_CMD_DISPLAY_CURSOR = 20,
 270     SVGA_CMD_MOVE_CURSOR = 21,
 271     SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
 272     SVGA_CMD_DRAW_GLYPH = 23,
 273     SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
 274     SVGA_CMD_UPDATE_VERBOSE = 25,
 275     SVGA_CMD_SURFACE_FILL = 26,
 276     SVGA_CMD_SURFACE_COPY = 27,
 277     SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
 278     SVGA_CMD_FRONT_ROP_FILL = 29,
 279     SVGA_CMD_FENCE = 30,
 280 };
 281
 282 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
 283 enum {
 284     SVGA_CURSOR_ON_HIDE = 0,
 285     SVGA_CURSOR_ON_SHOW = 1,
 286     SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
 287     SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
 288 };
 289
 290 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
 291                 int x, int y, int w, int h)
 292 {
 293     int line;
 294     int bypl;
 295     int width;
 296     int start;
 297     uint8_t *src;
 298     uint8_t *dst;
 299
 300     if (x + w > s->width) {
 301         fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
 302                         __FUNCTION__, x, w);
 303         x = MIN(x, s->width);
 304         w = s->width - x;
 305     }
 306
 307     if (y + h > s->height) {
 308         fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
 309                         __FUNCTION__, y, h);
 310         y = MIN(y, s->height);
 311         h = s->height - y;
 312     }
 313
 314     line = h;
 315     bypl = s->bypp * s->width;
 316     width = s->bypp * w;
 317     start = s->bypp * x + bypl * y;
 318     src = s->vga.vram_ptr + start;
 319     dst = ds_get_data(s->vga.ds) + start;
 320
 321     for (; line > 0; line --, src += bypl, dst += bypl)
 322         memcpy(dst, src, width);
 323
 324     dpy_update(s->vga.ds, x, y, w, h);
 325 }
 326
 327 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
 328 {
 329     memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr,
 330            s->bypp * s->width * s->height);
 331     dpy_update(s->vga.ds, 0, 0, s->width, s->height);
 332 }
 333
 334 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
 335                 int x, int y, int w, int h)
 336 {
 337     struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
 338     s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
 339     rect->x = x;
 340     rect->y = y;
 341     rect->w = w;
 342     rect->h = h;
 343 }
 344
 345 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
 346 {
 347     struct vmsvga_rect_s *rect;
 348     if (s->invalidated) {
 349         s->redraw_fifo_first = s->redraw_fifo_last;
 350         return;
 351     }
 352     /* Overlapping region updates can be optimised out here - if someone
 353      * knows a smart algorithm to do that, please share.  */
 354     while (s->redraw_fifo_first != s->redraw_fifo_last) {
 355         rect = &s->redraw_fifo[s->redraw_fifo_first ++];
 356         s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
 357         vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
 358     }
 359 }
 360
 361 #ifdef HW_RECT_ACCEL
 362 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
 363                 int x0, int y0, int x1, int y1, int w, int h)
 364 {
 365     uint8_t *vram = s->vga.vram_ptr;
 366     int bypl = s->bypp * s->width;
 367     int width = s->bypp * w;
 368     int line = h;
 369     uint8_t *ptr[2];
 370
 371     if (y1 > y0) {
 372         ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
 373         ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
 374         for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
 375             memmove(ptr[1], ptr[0], width);
 376         }
 377     } else {
 378         ptr[0] = vram + s->bypp * x0 + bypl * y0;
 379         ptr[1] = vram + s->bypp * x1 + bypl * y1;
 380         for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
 381             memmove(ptr[1], ptr[0], width);
 382         }
 383     }
 384
 385     vmsvga_update_rect_delayed(s, x1, y1, w, h);
 386 }
 387 #endif
 388
 389 #ifdef HW_FILL_ACCEL
 390 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
 391                 uint32_t c, int x, int y, int w, int h)
 392 {
 393     uint8_t *vram = s->vga.vram_ptr;
 394     int bypp = s->bypp;
 395     int bypl = bypp * s->width;
 396     int width = bypp * w;
 397     int line = h;
 398     int column;
 399     uint8_t *fst = vram + bypp * x + bypl * y;
 400     uint8_t *dst;
 401     uint8_t *src;
 402     uint8_t col[4];
 403
 404     col[0] = c;
 405     col[1] = c >> 8;
 406     col[2] = c >> 16;
 407     col[3] = c >> 24;
 408
 409     if (line--) {
 410         dst = fst;
 411         src = col;
 412         for (column = width; column > 0; column--) {
 413             *(dst++) = *(src++);
 414             if (src - col == bypp) {
 415                 src = col;
 416             }
 417         }
 418         dst = fst;
 419         for (; line > 0; line--) {
 420             dst += bypl;
 421             memcpy(dst, fst, width);
 422         }
 423     }
 424
 425     vmsvga_update_rect_delayed(s, x, y, w, h);
 426 }
 427 #endif
 428
 429 struct vmsvga_cursor_definition_s {
 430     int width;
 431     int height;
 432     int id;
 433     int bpp;
 434     int hot_x;
 435     int hot_y;
 436     uint32_t mask[1024];
 437     uint32_t image[4096];
 438 };
 439
 440 #define SVGA_BITMAP_SIZE(w, h)          ((((w) + 31) >> 5) * (h))
 441 #define SVGA_PIXMAP_SIZE(w, h, bpp)     (((((w) * (bpp)) + 31) >> 5) * (h))
 442
 443 #ifdef HW_MOUSE_ACCEL
 444 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
 445                 struct vmsvga_cursor_definition_s *c)
 446 {
 447     QEMUCursor *qc;
 448     int i, pixels;
 449
 450     qc = cursor_alloc(c->width, c->height);
 451     qc->hot_x = c->hot_x;
 452     qc->hot_y = c->hot_y;
 453     switch (c->bpp) {
 454     case 1:
 455         cursor_set_mono(qc, 0xffffff, 0x000000, (void*)c->image,
 456                         1, (void*)c->mask);
 457 #ifdef DEBUG
 458         cursor_print_ascii_art(qc, "vmware/mono");
 459 #endif
 460         break;
 461     case 32:
 462         /* fill alpha channel from mask, set color to zero */
 463         cursor_set_mono(qc, 0x000000, 0x000000, (void*)c->mask,
 464                         1, (void*)c->mask);
 465         /* add in rgb values */
 466         pixels = c->width * c->height;
 467         for (i = 0; i < pixels; i++) {
 468             qc->data[i] |= c->image[i] & 0xffffff;
 469         }
 470 #ifdef DEBUG
 471         cursor_print_ascii_art(qc, "vmware/32bit");
 472 #endif
 473         break;
 474     default:
 475         fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
 476                 __FUNCTION__, c->bpp);
 477         cursor_put(qc);
 478         qc = cursor_builtin_left_ptr();
 479     }
 480
 481     if (s->vga.ds->cursor_define)
 482         s->vga.ds->cursor_define(qc);
 483     cursor_put(qc);
 484 }
 485 #endif
 486
 487 #define CMD(f)  le32_to_cpu(s->cmd->f)
 488
 489 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
 490 {
 491     int num;
 492     if (!s->config || !s->enable)
 493         return 0;
 494     num = CMD(next_cmd) - CMD(stop);
 495     if (num < 0)
 496         num += CMD(max) - CMD(min);
 497     return num >> 2;
 498 }
 499
 500 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
 501 {
 502     uint32_t cmd = s->fifo[CMD(stop) >> 2];
 503     s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
 504     if (CMD(stop) >= CMD(max))
 505         s->cmd->stop = s->cmd->min;
 506     return cmd;
 507 }
 508
 509 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
 510 {
 511     return le32_to_cpu(vmsvga_fifo_read_raw(s));
 512 }
 513
 514 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
 515 {
 516     uint32_t cmd, colour;
 517     int args, len;
 518     int x, y, dx, dy, width, height;
 519     struct vmsvga_cursor_definition_s cursor;
 520     uint32_t cmd_start;
 521
 522     len = vmsvga_fifo_length(s);
 523     while (len > 0) {
 524         /* May need to go back to the start of the command if incomplete */
 525         cmd_start = s->cmd->stop;
 526
 527         switch (cmd = vmsvga_fifo_read(s)) {
 528         case SVGA_CMD_UPDATE:
 529         case SVGA_CMD_UPDATE_VERBOSE:
 530             len -= 5;
 531             if (len < 0)
 532                 goto rewind;
 533
 534             x = vmsvga_fifo_read(s);
 535             y = vmsvga_fifo_read(s);
 536             width = vmsvga_fifo_read(s);
 537             height = vmsvga_fifo_read(s);
 538             vmsvga_update_rect_delayed(s, x, y, width, height);
 539             break;
 540
 541         case SVGA_CMD_RECT_FILL:
 542             len -= 6;
 543             if (len < 0)
 544                 goto rewind;
 545
 546             colour = vmsvga_fifo_read(s);
 547             x = vmsvga_fifo_read(s);
 548             y = vmsvga_fifo_read(s);
 549             width = vmsvga_fifo_read(s);
 550             height = vmsvga_fifo_read(s);
 551 #ifdef HW_FILL_ACCEL
 552             vmsvga_fill_rect(s, colour, x, y, width, height);
 553             break;
 554 #else
 555             args = 0;
 556             goto badcmd;
 557 #endif
 558
 559         case SVGA_CMD_RECT_COPY:
 560             len -= 7;
 561             if (len < 0)
 562                 goto rewind;
 563
 564             x = vmsvga_fifo_read(s);
 565             y = vmsvga_fifo_read(s);
 566             dx = vmsvga_fifo_read(s);
 567             dy = vmsvga_fifo_read(s);
 568             width = vmsvga_fifo_read(s);
 569             height = vmsvga_fifo_read(s);
 570 #ifdef HW_RECT_ACCEL
 571             vmsvga_copy_rect(s, x, y, dx, dy, width, height);
 572             break;
 573 #else
 574             args = 0;
 575             goto badcmd;
 576 #endif
 577
 578         case SVGA_CMD_DEFINE_CURSOR:
 579             len -= 8;
 580             if (len < 0)
 581                 goto rewind;
 582
 583             cursor.id = vmsvga_fifo_read(s);
 584             cursor.hot_x = vmsvga_fifo_read(s);
 585             cursor.hot_y = vmsvga_fifo_read(s);
 586             cursor.width = x = vmsvga_fifo_read(s);
 587             cursor.height = y = vmsvga_fifo_read(s);
 588             vmsvga_fifo_read(s);
 589             cursor.bpp = vmsvga_fifo_read(s);
 590
 591             args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
 592             if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
 593                 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image)
 594                     goto badcmd;
 595
 596             len -= args;
 597             if (len < 0)
 598                 goto rewind;
 599
 600             for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
 601                 cursor.mask[args] = vmsvga_fifo_read_raw(s);
 602             for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
 603                 cursor.image[args] = vmsvga_fifo_read_raw(s);
 604 #ifdef HW_MOUSE_ACCEL
 605             vmsvga_cursor_define(s, &cursor);
 606             break;
 607 #else
 608             args = 0;
 609             goto badcmd;
 610 #endif
 611
 612         /*
 613          * Other commands that we at least know the number of arguments
 614          * for so we can avoid FIFO desync if driver uses them illegally.
 615          */
 616         case SVGA_CMD_DEFINE_ALPHA_CURSOR:
 617             len -= 6;
 618             if (len < 0)
 619                 goto rewind;
 620
 621             vmsvga_fifo_read(s);
 622             vmsvga_fifo_read(s);
 623             vmsvga_fifo_read(s);
 624             x = vmsvga_fifo_read(s);
 625             y = vmsvga_fifo_read(s);
 626             args = x * y;
 627             goto badcmd;
 628         case SVGA_CMD_RECT_ROP_FILL:
 629             args = 6;
 630             goto badcmd;
 631         case SVGA_CMD_RECT_ROP_COPY:
 632             args = 7;
 633             goto badcmd;
 634         case SVGA_CMD_DRAW_GLYPH_CLIPPED:
 635             len -= 4;
 636             if (len < 0)
 637                 goto rewind;
 638
 639             vmsvga_fifo_read(s);
 640             vmsvga_fifo_read(s);
 641             args = 7 + (vmsvga_fifo_read(s) >> 2);
 642             goto badcmd;
 643         case SVGA_CMD_SURFACE_ALPHA_BLEND:
 644             args = 12;
 645             goto badcmd;
 646
 647         /*
 648          * Other commands that are not listed as depending on any
 649          * CAPABILITIES bits, but are not described in the README either.
 650          */
 651         case SVGA_CMD_SURFACE_FILL:
 652         case SVGA_CMD_SURFACE_COPY:
 653         case SVGA_CMD_FRONT_ROP_FILL:
 654         case SVGA_CMD_FENCE:
 655         case SVGA_CMD_INVALID_CMD:
 656             break; /* Nop */
 657
 658         default:
 659             args = 0;
 660         badcmd:
 661             len -= args;
 662             if (len < 0)
 663                 goto rewind;
 664             while (args --)
 665                 vmsvga_fifo_read(s);
 666             printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
 667                             __FUNCTION__, cmd);
 668             break;
 669
 670         rewind:
 671             s->cmd->stop = cmd_start;
 672             break;
 673         }
 674     }
 675
 676     s->syncing = 0;
 677 }
 678
 679 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
 680 {
 681     struct vmsvga_state_s *s = opaque;
 682     return s->index;
 683 }
 684
 685 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
 686 {
 687     struct vmsvga_state_s *s = opaque;
 688     s->index = index;
 689 }
 690
 691 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
 692 {
 693     uint32_t caps;
 694     struct vmsvga_state_s *s = opaque;
 695     switch (s->index) {
 696     case SVGA_REG_ID:
 697         return s->svgaid;
 698
 699     case SVGA_REG_ENABLE:
 700         return s->enable;
 701
 702     case SVGA_REG_WIDTH:
 703         return s->width;
 704
 705     case SVGA_REG_HEIGHT:
 706         return s->height;
 707
 708     case SVGA_REG_MAX_WIDTH:
 709         return SVGA_MAX_WIDTH;
 710
 711     case SVGA_REG_MAX_HEIGHT:
 712         return SVGA_MAX_HEIGHT;
 713
 714     case SVGA_REG_DEPTH:
 715         return s->depth;
 716
 717     case SVGA_REG_BITS_PER_PIXEL:
 718         return (s->depth + 7) & ~7;
 719
 720     case SVGA_REG_PSEUDOCOLOR:
 721         return 0x0;
 722
 723     case SVGA_REG_RED_MASK:
 724         return s->wred;
 725     case SVGA_REG_GREEN_MASK:
 726         return s->wgreen;
 727     case SVGA_REG_BLUE_MASK:
 728         return s->wblue;
 729
 730     case SVGA_REG_BYTES_PER_LINE:
 731         return ((s->depth + 7) >> 3) * s->new_width;
 732
 733     case SVGA_REG_FB_START: {
 734         struct pci_vmsvga_state_s *pci_vmsvga
 735             = container_of(s, struct pci_vmsvga_state_s, chip);
 736         return pci_get_bar_addr(&pci_vmsvga->card, 1);
 737     }
 738
 739     case SVGA_REG_FB_OFFSET:
 740         return 0x0;
 741
 742     case SVGA_REG_VRAM_SIZE:
 743         return s->vga.vram_size;
 744
 745     case SVGA_REG_FB_SIZE:
 746         return s->fb_size;
 747
 748     case SVGA_REG_CAPABILITIES:
 749         caps = SVGA_CAP_NONE;
 750 #ifdef HW_RECT_ACCEL
 751         caps |= SVGA_CAP_RECT_COPY;
 752 #endif
 753 #ifdef HW_FILL_ACCEL
 754         caps |= SVGA_CAP_RECT_FILL;
 755 #endif
 756 #ifdef HW_MOUSE_ACCEL
 757         if (s->vga.ds->mouse_set)
 758             caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
 759                     SVGA_CAP_CURSOR_BYPASS;
 760 #endif
 761         return caps;
 762
 763     case SVGA_REG_MEM_START: {
 764         struct pci_vmsvga_state_s *pci_vmsvga
 765             = container_of(s, struct pci_vmsvga_state_s, chip);
 766         return pci_get_bar_addr(&pci_vmsvga->card, 2);
 767     }
 768
 769     case SVGA_REG_MEM_SIZE:
 770         return s->fifo_size;
 771
 772     case SVGA_REG_CONFIG_DONE:
 773         return s->config;
 774
 775     case SVGA_REG_SYNC:
 776     case SVGA_REG_BUSY:
 777         return s->syncing;
 778
 779     case SVGA_REG_GUEST_ID:
 780         return s->guest;
 781
 782     case SVGA_REG_CURSOR_ID:
 783         return s->cursor.id;
 784
 785     case SVGA_REG_CURSOR_X:
 786         return s->cursor.x;
 787
 788     case SVGA_REG_CURSOR_Y:
 789         return s->cursor.x;
 790
 791     case SVGA_REG_CURSOR_ON:
 792         return s->cursor.on;
 793
 794     case SVGA_REG_HOST_BITS_PER_PIXEL:
 795         return (s->depth + 7) & ~7;
 796
 797     case SVGA_REG_SCRATCH_SIZE:
 798         return s->scratch_size;
 799
 800     case SVGA_REG_MEM_REGS:
 801     case SVGA_REG_NUM_DISPLAYS:
 802     case SVGA_REG_PITCHLOCK:
 803     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 804         return 0;
 805
 806     default:
 807         if (s->index >= SVGA_SCRATCH_BASE &&
 808                 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
 809             return s->scratch[s->index - SVGA_SCRATCH_BASE];
 810         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 811     }
 812
 813     return 0;
 814 }
 815
 816 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
 817 {
 818     struct vmsvga_state_s *s = opaque;
 819     switch (s->index) {
 820     case SVGA_REG_ID:
 821         if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
 822             s->svgaid = value;
 823         break;
 824
 825     case SVGA_REG_ENABLE:
 826         s->enable = value;
 827         s->config &= !!value;
 828         s->width = -1;
 829         s->height = -1;
 830         s->invalidated = 1;
 831         s->vga.invalidate(&s->vga);
 832         if (s->enable) {
 833             s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
 834             vga_dirty_log_stop(&s->vga);
 835         } else {
 836             vga_dirty_log_start(&s->vga);
 837         }
 838         break;
 839
 840     case SVGA_REG_WIDTH:
 841         s->new_width = value;
 842         s->invalidated = 1;
 843         break;
 844
 845     case SVGA_REG_HEIGHT:
 846         s->new_height = value;
 847         s->invalidated = 1;
 848         break;
 849
 850     case SVGA_REG_DEPTH:
 851     case SVGA_REG_BITS_PER_PIXEL:
 852         if (value != s->depth) {
 853             printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
 854             s->config = 0;
 855         }
 856         break;
 857
 858     case SVGA_REG_CONFIG_DONE:
 859         if (value) {
 860             s->fifo = (uint32_t *) s->fifo_ptr;
 861             /* Check range and alignment.  */
 862             if ((CMD(min) | CMD(max) |
 863                         CMD(next_cmd) | CMD(stop)) & 3)
 864                 break;
 865             if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
 866                 break;
 867             if (CMD(max) > SVGA_FIFO_SIZE)
 868                 break;
 869             if (CMD(max) < CMD(min) + 10 * 1024)
 870                 break;
 871         }
 872         s->config = !!value;
 873         break;
 874
 875     case SVGA_REG_SYNC:
 876         s->syncing = 1;
 877         vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
 878         break;
 879
 880     case SVGA_REG_GUEST_ID:
 881         s->guest = value;
 882 #ifdef VERBOSE
 883         if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
 884                 ARRAY_SIZE(vmsvga_guest_id))
 885             printf("%s: guest runs %s.\n", __FUNCTION__,
 886                             vmsvga_guest_id[value - GUEST_OS_BASE]);
 887 #endif
 888         break;
 889
 890     case SVGA_REG_CURSOR_ID:
 891         s->cursor.id = value;
 892         break;
 893
 894     case SVGA_REG_CURSOR_X:
 895         s->cursor.x = value;
 896         break;
 897
 898     case SVGA_REG_CURSOR_Y:
 899         s->cursor.y = value;
 900         break;
 901
 902     case SVGA_REG_CURSOR_ON:
 903         s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
 904         s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
 905 #ifdef HW_MOUSE_ACCEL
 906         if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
 907             s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
 908 #endif
 909         break;
 910
 911     case SVGA_REG_MEM_REGS:
 912     case SVGA_REG_NUM_DISPLAYS:
 913     case SVGA_REG_PITCHLOCK:
 914     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 915         break;
 916
 917     default:
 918         if (s->index >= SVGA_SCRATCH_BASE &&
 919                 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 920             s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
 921             break;
 922         }
 923         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 924     }
 925 }
 926
 927 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
 928 {
 929     printf("%s: what are we supposed to return?\n", __FUNCTION__);
 930     return 0xcafe;
 931 }
 932
 933 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
 934 {
 935     printf("%s: what are we supposed to do with (%08x)?\n",
 936                     __FUNCTION__, data);
 937 }
 938
 939 static inline void vmsvga_size(struct vmsvga_state_s *s)
 940 {
 941     if (s->new_width != s->width || s->new_height != s->height) {
 942         s->width = s->new_width;
 943         s->height = s->new_height;
 944         qemu_console_resize(s->vga.ds, s->width, s->height);
 945         s->invalidated = 1;
 946     }
 947 }
 948
 949 static void vmsvga_update_display(void *opaque)
 950 {
 951     struct vmsvga_state_s *s = opaque;
 952     if (!s->enable) {
 953         s->vga.update(&s->vga);
 954         return;
 955     }
 956
 957     vmsvga_size(s);
 958
 959     vmsvga_fifo_run(s);
 960     vmsvga_update_rect_flush(s);
 961
 962     /*
 963      * Is it more efficient to look at vram VGA-dirty bits or wait
 964      * for the driver to issue SVGA_CMD_UPDATE?
 965      */
 966     if (s->invalidated) {
 967         s->invalidated = 0;
 968         vmsvga_update_screen(s);
 969     }
 970 }
 971
 972 static void vmsvga_reset(DeviceState *dev)
 973 {
 974     struct pci_vmsvga_state_s *pci =
 975         DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
 976     struct vmsvga_state_s *s = &pci->chip;
 977
 978     s->index = 0;
 979     s->enable = 0;
 980     s->config = 0;
 981     s->width = -1;
 982     s->height = -1;
 983     s->svgaid = SVGA_ID;
 984     s->cursor.on = 0;
 985     s->redraw_fifo_first = 0;
 986     s->redraw_fifo_last = 0;
 987     s->syncing = 0;
 988
 989     vga_dirty_log_start(&s->vga);
 990 }
 991
 992 static void vmsvga_invalidate_display(void *opaque)
 993 {
 994     struct vmsvga_state_s *s = opaque;
 995     if (!s->enable) {
 996         s->vga.invalidate(&s->vga);
 997         return;
 998     }
 999
1000     s->invalidated = 1;
1001 }
1002
1003 /* save the vga display in a PPM image even if no display is
1004    available */
1005 static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch,
1006                                Error **errp)
1007 {
1008     struct vmsvga_state_s *s = opaque;
1009     if (!s->enable) {
1010         s->vga.screen_dump(&s->vga, filename, cswitch, errp);
1011         return;
1012     }
1013
1014     if (s->depth == 32) {
1015         DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
1016                 s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
1017         ppm_save(filename, ds, errp);
1018         g_free(ds);
1019     }
1020 }
1021
1022 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
1023 {
1024     struct vmsvga_state_s *s = opaque;
1025
1026     if (s->vga.text_update)
1027         s->vga.text_update(&s->vga, chardata);
1028 }
1029
1030 static int vmsvga_post_load(void *opaque, int version_id)
1031 {
1032     struct vmsvga_state_s *s = opaque;
1033
1034     s->invalidated = 1;
1035     if (s->config)
1036         s->fifo = (uint32_t *) s->fifo_ptr;
1037
1038     return 0;
1039 }
1040
1041 static const VMStateDescription vmstate_vmware_vga_internal = {
1042     .name = "vmware_vga_internal",
1043     .version_id = 0,
1044     .minimum_version_id = 0,
1045     .minimum_version_id_old = 0,
1046     .post_load = vmsvga_post_load,
1047     .fields      = (VMStateField []) {
1048         VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
1049         VMSTATE_INT32(enable, struct vmsvga_state_s),
1050         VMSTATE_INT32(config, struct vmsvga_state_s),
1051         VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1052         VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1053         VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1054         VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1055         VMSTATE_INT32(index, struct vmsvga_state_s),
1056         VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1057                              scratch_size, 0, vmstate_info_uint32, uint32_t),
1058         VMSTATE_INT32(new_width, struct vmsvga_state_s),
1059         VMSTATE_INT32(new_height, struct vmsvga_state_s),
1060         VMSTATE_UINT32(guest, struct vmsvga_state_s),
1061         VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1062         VMSTATE_INT32(syncing, struct vmsvga_state_s),
1063         VMSTATE_INT32(fb_size, struct vmsvga_state_s),
1064         VMSTATE_END_OF_LIST()
1065     }
1066 };
1067
1068 static const VMStateDescription vmstate_vmware_vga = {
1069     .name = "vmware_vga",
1070     .version_id = 0,
1071     .minimum_version_id = 0,
1072     .minimum_version_id_old = 0,
1073     .fields      = (VMStateField []) {
1074         VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
1075         VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1076                        vmstate_vmware_vga_internal, struct vmsvga_state_s),
1077         VMSTATE_END_OF_LIST()
1078     }
1079 };
1080
1081 static void vmsvga_init(struct vmsvga_state_s *s,
1082                         MemoryRegion *address_space, MemoryRegion *io)
1083 {
1084     s->scratch_size = SVGA_SCRATCH_SIZE;
1085     s->scratch = g_malloc(s->scratch_size * 4);
1086
1087     s->vga.ds = graphic_console_init(vmsvga_update_display,
1088                                      vmsvga_invalidate_display,
1089                                      vmsvga_screen_dump,
1090                                      vmsvga_text_update, s);
1091
1092
1093     s->fifo_size = SVGA_FIFO_SIZE;
1094     memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
1095     vmstate_register_ram_global(&s->fifo_ram);
1096     s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
1097
1098     vga_common_init(&s->vga);
1099     vga_init(&s->vga, address_space, io, true);
1100     vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
1101
1102     s->depth = ds_get_bits_per_pixel(s->vga.ds);
1103     s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
1104     switch (s->depth) {
1105     case 8:
1106         s->wred   = 0x00000007;
1107         s->wgreen = 0x00000038;
1108         s->wblue  = 0x000000c0;
1109         break;
1110     case 15:
1111         s->wred   = 0x0000001f;
1112         s->wgreen = 0x000003e0;
1113         s->wblue  = 0x00007c00;
1114         break;
1115     case 16:
1116         s->wred   = 0x0000001f;
1117         s->wgreen = 0x000007e0;
1118         s->wblue  = 0x0000f800;
1119         break;
1120     case 24:
1121         s->wred   = 0x00ff0000;
1122         s->wgreen = 0x0000ff00;
1123         s->wblue  = 0x000000ff;
1124         break;
1125     case 32:
1126         s->wred   = 0x00ff0000;
1127         s->wgreen = 0x0000ff00;
1128         s->wblue  = 0x000000ff;
1129         break;
1130     }
1131 }
1132
1133 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr,
1134                                unsigned size)
1135 {
1136     struct vmsvga_state_s *s = opaque;
1137
1138     switch (addr) {
1139     case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
1140     case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
1141     case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
1142     default: return -1u;
1143     }
1144 }
1145
1146 static void vmsvga_io_write(void *opaque, hwaddr addr,
1147                             uint64_t data, unsigned size)
1148 {
1149     struct vmsvga_state_s *s = opaque;
1150
1151     switch (addr) {
1152     case SVGA_IO_MUL * SVGA_INDEX_PORT:
1153         vmsvga_index_write(s, addr, data);
1154         break;
1155     case SVGA_IO_MUL * SVGA_VALUE_PORT:
1156         vmsvga_value_write(s, addr, data);
1157         break;
1158     case SVGA_IO_MUL * SVGA_BIOS_PORT:
1159         vmsvga_bios_write(s, addr, data);
1160         break;
1161     }
1162 }
1163
1164 static const MemoryRegionOps vmsvga_io_ops = {
1165     .read = vmsvga_io_read,
1166     .write = vmsvga_io_write,
1167     .endianness = DEVICE_LITTLE_ENDIAN,
1168     .valid = {
1169         .min_access_size = 4,
1170         .max_access_size = 4,
1171     },
1172 };
1173
1174 static int pci_vmsvga_initfn(PCIDevice *dev)
1175 {
1176     struct pci_vmsvga_state_s *s =
1177         DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
1178     MemoryRegion *iomem;
1179
1180     iomem = &s->chip.vga.vram;
1181
1182     s->card.config[PCI_CACHE_LINE_SIZE] = 0x08;         /* Cache line size */
1183     s->card.config[PCI_LATENCY_TIMER] = 0x40;           /* Latency timer */
1184     s->card.config[PCI_INTERRUPT_LINE] = 0xff;          /* End */
1185
1186     memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip,
1187                           "vmsvga-io", 0x10);
1188     memory_region_set_flush_coalesced(&s->io_bar);
1189     pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1190
1191     vmsvga_init(&s->chip, pci_address_space(dev),
1192                 pci_address_space_io(dev));
1193
1194     pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
1195     pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
1196                      &s->chip.fifo_ram);
1197
1198     if (!dev->rom_bar) {
1199         /* compatibility with pc-0.13 and older */
1200         vga_init_vbe(&s->chip.vga, pci_address_space(dev));
1201     }
1202
1203     return 0;
1204 }
1205
1206 static Property vga_vmware_properties[] = {
1207     DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
1208                        chip.vga.vram_size_mb, 16),
1209     DEFINE_PROP_END_OF_LIST(),
1210 };
1211
1212 static void vmsvga_class_init(ObjectClass *klass, void *data)
1213 {
1214     DeviceClass *dc = DEVICE_CLASS(klass);
1215     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1216
1217     k->no_hotplug = 1;
1218     k->init = pci_vmsvga_initfn;
1219     k->romfile = "vgabios-vmware.bin";
1220     k->vendor_id = PCI_VENDOR_ID_VMWARE;
1221     k->device_id = SVGA_PCI_DEVICE_ID;
1222     k->class_id = PCI_CLASS_DISPLAY_VGA;
1223     k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
1224     k->subsystem_id = SVGA_PCI_DEVICE_ID;
1225     dc->reset = vmsvga_reset;
1226     dc->vmsd = &vmstate_vmware_vga;
1227     dc->props = vga_vmware_properties;
1228 }
1229
1230 static TypeInfo vmsvga_info = {
1231     .name          = "vmware-svga",
1232     .parent        = TYPE_PCI_DEVICE,
1233     .instance_size = sizeof(struct pci_vmsvga_state_s),
1234     .class_init    = vmsvga_class_init,
1235 };
1236
1237 static void vmsvga_register_types(void)
1238 {
1239     type_register_static(&vmsvga_info);
1240 }
1241
1242 type_init(vmsvga_register_types)