linux-headers/asm-riscv/kvm.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * Copyright (C) 2019 Western Digital Corporation or its affiliates.
   4  *
   5  * Authors:
   6  *     Anup Patel <anup.patel@wdc.com>
   7  */
   8
   9 #ifndef __LINUX_KVM_RISCV_H
  10 #define __LINUX_KVM_RISCV_H
  11
  12 #ifndef __ASSEMBLY__
  13
  14 #include <linux/types.h>
  15 #include <asm/ptrace.h>
  16
  17 #define __KVM_HAVE_READONLY_MEM
  18
  19 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  20
  21 #define KVM_INTERRUPT_SET       -1U
  22 #define KVM_INTERRUPT_UNSET     -2U
  23
  24 /* for KVM_GET_REGS and KVM_SET_REGS */
  25 struct kvm_regs {
  26 };
  27
  28 /* for KVM_GET_FPU and KVM_SET_FPU */
  29 struct kvm_fpu {
  30 };
  31
  32 /* KVM Debug exit structure */
  33 struct kvm_debug_exit_arch {
  34 };
  35
  36 /* for KVM_SET_GUEST_DEBUG */
  37 struct kvm_guest_debug_arch {
  38 };
  39
  40 /* definition of registers in kvm_run */
  41 struct kvm_sync_regs {
  42 };
  43
  44 /* for KVM_GET_SREGS and KVM_SET_SREGS */
  45 struct kvm_sregs {
  46 };
  47
  48 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  49 struct kvm_riscv_config {
  50         unsigned long isa;
  51         unsigned long zicbom_block_size;
  52 };
  53
  54 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  55 struct kvm_riscv_core {
  56         struct user_regs_struct regs;
  57         unsigned long mode;
  58 };
  59
  60 /* Possible privilege modes for kvm_riscv_core */
  61 #define KVM_RISCV_MODE_S        1
  62 #define KVM_RISCV_MODE_U        0
  63
  64 /* CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  65 struct kvm_riscv_csr {
  66         unsigned long sstatus;
  67         unsigned long sie;
  68         unsigned long stvec;
  69         unsigned long sscratch;
  70         unsigned long sepc;
  71         unsigned long scause;
  72         unsigned long stval;
  73         unsigned long sip;
  74         unsigned long satp;
  75         unsigned long scounteren;
  76 };
  77
  78 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
  79 struct kvm_riscv_timer {
  80         __u64 frequency;
  81         __u64 time;
  82         __u64 compare;
  83         __u64 state;
  84 };
  85
  86 /*
  87  * ISA extension IDs specific to KVM. This is not the same as the host ISA
  88  * extension IDs as that is internal to the host and should not be exposed
  89  * to the guest. This should always be contiguous to keep the mapping simple
  90  * in KVM implementation.
  91  */
  92 enum KVM_RISCV_ISA_EXT_ID {
  93         KVM_RISCV_ISA_EXT_A = 0,
  94         KVM_RISCV_ISA_EXT_C,
  95         KVM_RISCV_ISA_EXT_D,
  96         KVM_RISCV_ISA_EXT_F,
  97         KVM_RISCV_ISA_EXT_H,
  98         KVM_RISCV_ISA_EXT_I,
  99         KVM_RISCV_ISA_EXT_M,
 100         KVM_RISCV_ISA_EXT_SVPBMT,
 101         KVM_RISCV_ISA_EXT_SSTC,
 102         KVM_RISCV_ISA_EXT_SVINVAL,
 103         KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
 104         KVM_RISCV_ISA_EXT_ZICBOM,
 105         KVM_RISCV_ISA_EXT_MAX,
 106 };
 107
 108 /* Possible states for kvm_riscv_timer */
 109 #define KVM_RISCV_TIMER_STATE_OFF       0
 110 #define KVM_RISCV_TIMER_STATE_ON        1
 111
 112 #define KVM_REG_SIZE(id)                \
 113         (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
 114
 115 /* If you need to interpret the index values, here is the key: */
 116 #define KVM_REG_RISCV_TYPE_MASK         0x00000000FF000000
 117 #define KVM_REG_RISCV_TYPE_SHIFT        24
 118
 119 /* Config registers are mapped as type 1 */
 120 #define KVM_REG_RISCV_CONFIG            (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
 121 #define KVM_REG_RISCV_CONFIG_REG(name)  \
 122         (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
 123
 124 /* Core registers are mapped as type 2 */
 125 #define KVM_REG_RISCV_CORE              (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
 126 #define KVM_REG_RISCV_CORE_REG(name)    \
 127                 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
 128
 129 /* Control and status registers are mapped as type 3 */
 130 #define KVM_REG_RISCV_CSR               (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
 131 #define KVM_REG_RISCV_CSR_REG(name)     \
 132                 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
 133
 134 /* Timer registers are mapped as type 4 */
 135 #define KVM_REG_RISCV_TIMER             (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
 136 #define KVM_REG_RISCV_TIMER_REG(name)   \
 137                 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
 138
 139 /* F extension registers are mapped as type 5 */
 140 #define KVM_REG_RISCV_FP_F              (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
 141 #define KVM_REG_RISCV_FP_F_REG(name)    \
 142                 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
 143
 144 /* D extension registers are mapped as type 6 */
 145 #define KVM_REG_RISCV_FP_D              (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
 146 #define KVM_REG_RISCV_FP_D_REG(name)    \
 147                 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
 148
 149 /* ISA Extension registers are mapped as type 7 */
 150 #define KVM_REG_RISCV_ISA_EXT           (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
 151
 152 #endif
 153
 154 #endif /* __LINUX_KVM_RISCV_H */