target/riscv/cpu.c

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/qemu-print.h"
  22 #include "qemu/ctype.h"
  23 #include "qemu/log.h"
  24 #include "cpu.h"
  25 #include "internals.h"
  26 #include "exec/exec-all.h"
  27 #include "qapi/error.h"
  28 #include "qemu/error-report.h"
  29 #include "hw/qdev-properties.h"
  30 #include "migration/vmstate.h"
  31 #include "fpu/softfloat-helpers.h"
  32
  33 /* RISC-V CPU definitions */
  34
  35 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
  36
  37 const char * const riscv_int_regnames[] = {
  38   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
  39   "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
  40   "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
  41   "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
  42   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
  43 };
  44
  45 const char * const riscv_fpr_regnames[] = {
  46   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
  47   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
  48   "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
  49   "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
  50   "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
  51   "f30/ft10", "f31/ft11"
  52 };
  53
  54 static const char * const riscv_excp_names[] = {
  55     "misaligned_fetch",
  56     "fault_fetch",
  57     "illegal_instruction",
  58     "breakpoint",
  59     "misaligned_load",
  60     "fault_load",
  61     "misaligned_store",
  62     "fault_store",
  63     "user_ecall",
  64     "supervisor_ecall",
  65     "hypervisor_ecall",
  66     "machine_ecall",
  67     "exec_page_fault",
  68     "load_page_fault",
  69     "reserved",
  70     "store_page_fault",
  71     "reserved",
  72     "reserved",
  73     "reserved",
  74     "reserved",
  75     "guest_exec_page_fault",
  76     "guest_load_page_fault",
  77     "reserved",
  78     "guest_store_page_fault",
  79 };
  80
  81 static const char * const riscv_intr_names[] = {
  82     "u_software",
  83     "s_software",
  84     "vs_software",
  85     "m_software",
  86     "u_timer",
  87     "s_timer",
  88     "vs_timer",
  89     "m_timer",
  90     "u_external",
  91     "s_external",
  92     "vs_external",
  93     "m_external",
  94     "reserved",
  95     "reserved",
  96     "reserved",
  97     "reserved"
  98 };
  99
 100 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 101 {
 102     if (async) {
 103         return (cause < ARRAY_SIZE(riscv_intr_names)) ?
 104                riscv_intr_names[cause] : "(unknown)";
 105     } else {
 106         return (cause < ARRAY_SIZE(riscv_excp_names)) ?
 107                riscv_excp_names[cause] : "(unknown)";
 108     }
 109 }
 110
 111 bool riscv_cpu_is_32bit(CPURISCVState *env)
 112 {
 113     if (env->misa & RV64) {
 114         return false;
 115     }
 116
 117     return true;
 118 }
 119
 120 static void set_misa(CPURISCVState *env, target_ulong misa)
 121 {
 122     env->misa_mask = env->misa = misa;
 123 }
 124
 125 static void set_priv_version(CPURISCVState *env, int priv_ver)
 126 {
 127     env->priv_ver = priv_ver;
 128 }
 129
 130 static void set_vext_version(CPURISCVState *env, int vext_ver)
 131 {
 132     env->vext_ver = vext_ver;
 133 }
 134
 135 static void set_feature(CPURISCVState *env, int feature)
 136 {
 137     env->features |= (1ULL << feature);
 138 }
 139
 140 static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
 141 {
 142 #ifndef CONFIG_USER_ONLY
 143     env->resetvec = resetvec;
 144 #endif
 145 }
 146
 147 static void riscv_any_cpu_init(Object *obj)
 148 {
 149     CPURISCVState *env = &RISCV_CPU(obj)->env;
 150 #if defined(TARGET_RISCV32)
 151     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 152 #elif defined(TARGET_RISCV64)
 153     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 154 #endif
 155     set_priv_version(env, PRIV_VERSION_1_11_0);
 156 }
 157
 158 #if defined(TARGET_RISCV64)
 159 static void rv64_base_cpu_init(Object *obj)
 160 {
 161     CPURISCVState *env = &RISCV_CPU(obj)->env;
 162     /* We set this in the realise function */
 163     set_misa(env, RV64);
 164 }
 165
 166 static void rv64_sifive_u_cpu_init(Object *obj)
 167 {
 168     CPURISCVState *env = &RISCV_CPU(obj)->env;
 169     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 170     set_priv_version(env, PRIV_VERSION_1_10_0);
 171 }
 172
 173 static void rv64_sifive_e_cpu_init(Object *obj)
 174 {
 175     CPURISCVState *env = &RISCV_CPU(obj)->env;
 176     set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
 177     set_priv_version(env, PRIV_VERSION_1_10_0);
 178     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 179 }
 180 #else
 181 static void rv32_base_cpu_init(Object *obj)
 182 {
 183     CPURISCVState *env = &RISCV_CPU(obj)->env;
 184     /* We set this in the realise function */
 185     set_misa(env, RV32);
 186 }
 187
 188 static void rv32_sifive_u_cpu_init(Object *obj)
 189 {
 190     CPURISCVState *env = &RISCV_CPU(obj)->env;
 191     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 192     set_priv_version(env, PRIV_VERSION_1_10_0);
 193 }
 194
 195 static void rv32_sifive_e_cpu_init(Object *obj)
 196 {
 197     CPURISCVState *env = &RISCV_CPU(obj)->env;
 198     set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
 199     set_priv_version(env, PRIV_VERSION_1_10_0);
 200     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 201 }
 202
 203 static void rv32_ibex_cpu_init(Object *obj)
 204 {
 205     CPURISCVState *env = &RISCV_CPU(obj)->env;
 206     set_misa(env, RV32 | RVI | RVM | RVC | RVU);
 207     set_priv_version(env, PRIV_VERSION_1_10_0);
 208     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 209     qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
 210 }
 211
 212 static void rv32_imafcu_nommu_cpu_init(Object *obj)
 213 {
 214     CPURISCVState *env = &RISCV_CPU(obj)->env;
 215     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
 216     set_priv_version(env, PRIV_VERSION_1_10_0);
 217     set_resetvec(env, DEFAULT_RSTVEC);
 218     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 219 }
 220 #endif
 221
 222 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 223 {
 224     ObjectClass *oc;
 225     char *typename;
 226     char **cpuname;
 227
 228     cpuname = g_strsplit(cpu_model, ",", 1);
 229     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
 230     oc = object_class_by_name(typename);
 231     g_strfreev(cpuname);
 232     g_free(typename);
 233     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
 234         object_class_is_abstract(oc)) {
 235         return NULL;
 236     }
 237     return oc;
 238 }
 239
 240 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 241 {
 242     RISCVCPU *cpu = RISCV_CPU(cs);
 243     CPURISCVState *env = &cpu->env;
 244     int i;
 245
 246 #if !defined(CONFIG_USER_ONLY)
 247     if (riscv_has_ext(env, RVH)) {
 248         qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
 249     }
 250 #endif
 251     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 252 #ifndef CONFIG_USER_ONLY
 253     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
 254     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
 255     if (riscv_cpu_is_32bit(env)) {
 256         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
 257                      (target_ulong)(env->mstatus >> 32));
 258     }
 259     if (riscv_has_ext(env, RVH)) {
 260         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
 261         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
 262                      (target_ulong)env->vsstatus);
 263     }
 264     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
 265     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
 266     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
 267     if (riscv_has_ext(env, RVH)) {
 268         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
 269     }
 270     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
 271     if (riscv_has_ext(env, RVH)) {
 272         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
 273     }
 274     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
 275     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
 276     if (riscv_has_ext(env, RVH)) {
 277         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
 278     }
 279     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
 280     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
 281     if (riscv_has_ext(env, RVH)) {
 282         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
 283     }
 284     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
 285     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
 286     if (riscv_has_ext(env, RVH)) {
 287         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
 288     }
 289     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval   ", env->mtval);
 290     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval   ", env->stval);
 291     if (riscv_has_ext(env, RVH)) {
 292         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
 293         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
 294     }
 295     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
 296     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
 297     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp    ", env->satp);
 298 #endif
 299
 300     for (i = 0; i < 32; i++) {
 301         qemu_fprintf(f, " %s " TARGET_FMT_lx,
 302                      riscv_int_regnames[i], env->gpr[i]);
 303         if ((i & 3) == 3) {
 304             qemu_fprintf(f, "\n");
 305         }
 306     }
 307     if (flags & CPU_DUMP_FPU) {
 308         for (i = 0; i < 32; i++) {
 309             qemu_fprintf(f, " %s %016" PRIx64,
 310                          riscv_fpr_regnames[i], env->fpr[i]);
 311             if ((i & 3) == 3) {
 312                 qemu_fprintf(f, "\n");
 313             }
 314         }
 315     }
 316 }
 317
 318 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 319 {
 320     RISCVCPU *cpu = RISCV_CPU(cs);
 321     CPURISCVState *env = &cpu->env;
 322     env->pc = value;
 323 }
 324
 325 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
 326                                           const TranslationBlock *tb)
 327 {
 328     RISCVCPU *cpu = RISCV_CPU(cs);
 329     CPURISCVState *env = &cpu->env;
 330     env->pc = tb->pc;
 331 }
 332
 333 static bool riscv_cpu_has_work(CPUState *cs)
 334 {
 335 #ifndef CONFIG_USER_ONLY
 336     RISCVCPU *cpu = RISCV_CPU(cs);
 337     CPURISCVState *env = &cpu->env;
 338     /*
 339      * Definition of the WFI instruction requires it to ignore the privilege
 340      * mode and delegation registers, but respect individual enables
 341      */
 342     return (env->mip & env->mie) != 0;
 343 #else
 344     return true;
 345 #endif
 346 }
 347
 348 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 349                           target_ulong *data)
 350 {
 351     env->pc = data[0];
 352 }
 353
 354 static void riscv_cpu_reset(DeviceState *dev)
 355 {
 356     CPUState *cs = CPU(dev);
 357     RISCVCPU *cpu = RISCV_CPU(cs);
 358     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 359     CPURISCVState *env = &cpu->env;
 360
 361     mcc->parent_reset(dev);
 362 #ifndef CONFIG_USER_ONLY
 363     env->priv = PRV_M;
 364     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 365     env->mcause = 0;
 366     env->pc = env->resetvec;
 367     env->two_stage_lookup = false;
 368 #endif
 369     cs->exception_index = RISCV_EXCP_NONE;
 370     env->load_res = -1;
 371     set_default_nan_mode(1, &env->fp_status);
 372 }
 373
 374 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 375 {
 376     RISCVCPU *cpu = RISCV_CPU(s);
 377     if (riscv_cpu_is_32bit(&cpu->env)) {
 378         info->print_insn = print_insn_riscv32;
 379     } else {
 380         info->print_insn = print_insn_riscv64;
 381     }
 382 }
 383
 384 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 385 {
 386     CPUState *cs = CPU(dev);
 387     RISCVCPU *cpu = RISCV_CPU(dev);
 388     CPURISCVState *env = &cpu->env;
 389     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
 390     int priv_version = 0;
 391     target_ulong target_misa = env->misa;
 392     Error *local_err = NULL;
 393
 394     cpu_exec_realizefn(cs, &local_err);
 395     if (local_err != NULL) {
 396         error_propagate(errp, local_err);
 397         return;
 398     }
 399
 400     if (cpu->cfg.priv_spec) {
 401         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 402             priv_version = PRIV_VERSION_1_11_0;
 403         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 404             priv_version = PRIV_VERSION_1_10_0;
 405         } else {
 406             error_setg(errp,
 407                        "Unsupported privilege spec version '%s'",
 408                        cpu->cfg.priv_spec);
 409             return;
 410         }
 411     }
 412
 413     if (priv_version) {
 414         set_priv_version(env, priv_version);
 415     } else if (!env->priv_ver) {
 416         set_priv_version(env, PRIV_VERSION_1_11_0);
 417     }
 418
 419     if (cpu->cfg.mmu) {
 420         set_feature(env, RISCV_FEATURE_MMU);
 421     }
 422
 423     if (cpu->cfg.pmp) {
 424         set_feature(env, RISCV_FEATURE_PMP);
 425
 426         /*
 427          * Enhanced PMP should only be available
 428          * on harts with PMP support
 429          */
 430         if (cpu->cfg.epmp) {
 431             set_feature(env, RISCV_FEATURE_EPMP);
 432         }
 433     }
 434
 435     set_resetvec(env, cpu->cfg.resetvec);
 436
 437     /* If only XLEN is set for misa, then set misa from properties */
 438     if (env->misa == RV32 || env->misa == RV64) {
 439         /* Do some ISA extension error checking */
 440         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 441             error_setg(errp,
 442                        "I and E extensions are incompatible");
 443                        return;
 444        }
 445
 446         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 447             error_setg(errp,
 448                        "Either I or E extension must be set");
 449                        return;
 450        }
 451
 452        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
 453                                cpu->cfg.ext_a & cpu->cfg.ext_f &
 454                                cpu->cfg.ext_d)) {
 455             warn_report("Setting G will also set IMAFD");
 456             cpu->cfg.ext_i = true;
 457             cpu->cfg.ext_m = true;
 458             cpu->cfg.ext_a = true;
 459             cpu->cfg.ext_f = true;
 460             cpu->cfg.ext_d = true;
 461         }
 462
 463         /* Set the ISA extensions, checks should have happened above */
 464         if (cpu->cfg.ext_i) {
 465             target_misa |= RVI;
 466         }
 467         if (cpu->cfg.ext_e) {
 468             target_misa |= RVE;
 469         }
 470         if (cpu->cfg.ext_m) {
 471             target_misa |= RVM;
 472         }
 473         if (cpu->cfg.ext_a) {
 474             target_misa |= RVA;
 475         }
 476         if (cpu->cfg.ext_f) {
 477             target_misa |= RVF;
 478         }
 479         if (cpu->cfg.ext_d) {
 480             target_misa |= RVD;
 481         }
 482         if (cpu->cfg.ext_c) {
 483             target_misa |= RVC;
 484         }
 485         if (cpu->cfg.ext_s) {
 486             target_misa |= RVS;
 487         }
 488         if (cpu->cfg.ext_u) {
 489             target_misa |= RVU;
 490         }
 491         if (cpu->cfg.ext_h) {
 492             target_misa |= RVH;
 493         }
 494         if (cpu->cfg.ext_v) {
 495             int vext_version = VEXT_VERSION_0_07_1;
 496             target_misa |= RVV;
 497             if (!is_power_of_2(cpu->cfg.vlen)) {
 498                 error_setg(errp,
 499                         "Vector extension VLEN must be power of 2");
 500                 return;
 501             }
 502             if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
 503                 error_setg(errp,
 504                         "Vector extension implementation only supports VLEN "
 505                         "in the range [128, %d]", RV_VLEN_MAX);
 506                 return;
 507             }
 508             if (!is_power_of_2(cpu->cfg.elen)) {
 509                 error_setg(errp,
 510                         "Vector extension ELEN must be power of 2");
 511                 return;
 512             }
 513             if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
 514                 error_setg(errp,
 515                         "Vector extension implementation only supports ELEN "
 516                         "in the range [8, 64]");
 517                 return;
 518             }
 519             if (cpu->cfg.vext_spec) {
 520                 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
 521                     vext_version = VEXT_VERSION_0_07_1;
 522                 } else {
 523                     error_setg(errp,
 524                            "Unsupported vector spec version '%s'",
 525                            cpu->cfg.vext_spec);
 526                     return;
 527                 }
 528             } else {
 529                 qemu_log("vector version is not specified, "
 530                         "use the default value v0.7.1\n");
 531             }
 532             set_vext_version(env, vext_version);
 533         }
 534
 535         set_misa(env, target_misa);
 536     }
 537
 538     riscv_cpu_register_gdb_regs_for_features(cs);
 539
 540     qemu_init_vcpu(cs);
 541     cpu_reset(cs);
 542
 543     mcc->parent_realize(dev, errp);
 544 }
 545
 546 #ifndef CONFIG_USER_ONLY
 547 static void riscv_cpu_set_irq(void *opaque, int irq, int level)
 548 {
 549     RISCVCPU *cpu = RISCV_CPU(opaque);
 550
 551     switch (irq) {
 552     case IRQ_U_SOFT:
 553     case IRQ_S_SOFT:
 554     case IRQ_VS_SOFT:
 555     case IRQ_M_SOFT:
 556     case IRQ_U_TIMER:
 557     case IRQ_S_TIMER:
 558     case IRQ_VS_TIMER:
 559     case IRQ_M_TIMER:
 560     case IRQ_U_EXT:
 561     case IRQ_S_EXT:
 562     case IRQ_VS_EXT:
 563     case IRQ_M_EXT:
 564         riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
 565         break;
 566     default:
 567         g_assert_not_reached();
 568     }
 569 }
 570 #endif /* CONFIG_USER_ONLY */
 571
 572 static void riscv_cpu_init(Object *obj)
 573 {
 574     RISCVCPU *cpu = RISCV_CPU(obj);
 575
 576     cpu_set_cpustate_pointers(cpu);
 577
 578 #ifndef CONFIG_USER_ONLY
 579     qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
 580 #endif /* CONFIG_USER_ONLY */
 581 }
 582
 583 static Property riscv_cpu_properties[] = {
 584     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
 585     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
 586     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
 587     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
 588     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
 589     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 590     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
 591     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 592     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 593     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
 594     /* This is experimental so mark with 'x-' */
 595     DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
 596     DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
 597     DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
 598     DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
 599     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
 600     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
 601     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 602     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 603     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 604     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 605     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
 606     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
 607     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 608     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 609     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 610     /* ePMP 0.9.3 */
 611     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
 612
 613     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
 614     DEFINE_PROP_END_OF_LIST(),
 615 };
 616
 617 static gchar *riscv_gdb_arch_name(CPUState *cs)
 618 {
 619     RISCVCPU *cpu = RISCV_CPU(cs);
 620     CPURISCVState *env = &cpu->env;
 621
 622     if (riscv_cpu_is_32bit(env)) {
 623         return g_strdup("riscv:rv32");
 624     } else {
 625         return g_strdup("riscv:rv64");
 626     }
 627 }
 628
 629 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 630 {
 631     RISCVCPU *cpu = RISCV_CPU(cs);
 632
 633     if (strcmp(xmlname, "riscv-csr.xml") == 0) {
 634         return cpu->dyn_csr_xml;
 635     }
 636
 637     return NULL;
 638 }
 639
 640 #ifndef CONFIG_USER_ONLY
 641 #include "hw/core/sysemu-cpu-ops.h"
 642
 643 static const struct SysemuCPUOps riscv_sysemu_ops = {
 644     .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
 645     .write_elf64_note = riscv_cpu_write_elf64_note,
 646     .write_elf32_note = riscv_cpu_write_elf32_note,
 647     .legacy_vmsd = &vmstate_riscv_cpu,
 648 };
 649 #endif
 650
 651 #include "hw/core/tcg-cpu-ops.h"
 652
 653 static const struct TCGCPUOps riscv_tcg_ops = {
 654     .initialize = riscv_translate_init,
 655     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
 656     .tlb_fill = riscv_cpu_tlb_fill,
 657
 658 #ifndef CONFIG_USER_ONLY
 659     .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
 660     .do_interrupt = riscv_cpu_do_interrupt,
 661     .do_transaction_failed = riscv_cpu_do_transaction_failed,
 662     .do_unaligned_access = riscv_cpu_do_unaligned_access,
 663 #endif /* !CONFIG_USER_ONLY */
 664 };
 665
 666 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 667 {
 668     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 669     CPUClass *cc = CPU_CLASS(c);
 670     DeviceClass *dc = DEVICE_CLASS(c);
 671
 672     device_class_set_parent_realize(dc, riscv_cpu_realize,
 673                                     &mcc->parent_realize);
 674
 675     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 676
 677     cc->class_by_name = riscv_cpu_class_by_name;
 678     cc->has_work = riscv_cpu_has_work;
 679     cc->dump_state = riscv_cpu_dump_state;
 680     cc->set_pc = riscv_cpu_set_pc;
 681     cc->gdb_read_register = riscv_cpu_gdb_read_register;
 682     cc->gdb_write_register = riscv_cpu_gdb_write_register;
 683     cc->gdb_num_core_regs = 33;
 684 #if defined(TARGET_RISCV32)
 685     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 686 #elif defined(TARGET_RISCV64)
 687     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 688 #endif
 689     cc->gdb_stop_before_watchpoint = true;
 690     cc->disas_set_info = riscv_cpu_disas_set_info;
 691 #ifndef CONFIG_USER_ONLY
 692     cc->sysemu_ops = &riscv_sysemu_ops;
 693 #endif
 694     cc->gdb_arch_name = riscv_gdb_arch_name;
 695     cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
 696     cc->tcg_ops = &riscv_tcg_ops;
 697
 698     device_class_set_props(dc, riscv_cpu_properties);
 699 }
 700
 701 char *riscv_isa_string(RISCVCPU *cpu)
 702 {
 703     int i;
 704     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
 705     char *isa_str = g_new(char, maxlen);
 706     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
 707     for (i = 0; i < sizeof(riscv_exts); i++) {
 708         if (cpu->env.misa & RV(riscv_exts[i])) {
 709             *p++ = qemu_tolower(riscv_exts[i]);
 710         }
 711     }
 712     *p = '\0';
 713     return isa_str;
 714 }
 715
 716 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
 717 {
 718     ObjectClass *class_a = (ObjectClass *)a;
 719     ObjectClass *class_b = (ObjectClass *)b;
 720     const char *name_a, *name_b;
 721
 722     name_a = object_class_get_name(class_a);
 723     name_b = object_class_get_name(class_b);
 724     return strcmp(name_a, name_b);
 725 }
 726
 727 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
 728 {
 729     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 730     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
 731
 732     qemu_printf("%.*s\n", len, typename);
 733 }
 734
 735 void riscv_cpu_list(void)
 736 {
 737     GSList *list;
 738
 739     list = object_class_get_list(TYPE_RISCV_CPU, false);
 740     list = g_slist_sort(list, riscv_cpu_list_compare);
 741     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
 742     g_slist_free(list);
 743 }
 744
 745 #define DEFINE_CPU(type_name, initfn)      \
 746     {                                      \
 747         .name = type_name,                 \
 748         .parent = TYPE_RISCV_CPU,          \
 749         .instance_init = initfn            \
 750     }
 751
 752 static const TypeInfo riscv_cpu_type_infos[] = {
 753     {
 754         .name = TYPE_RISCV_CPU,
 755         .parent = TYPE_CPU,
 756         .instance_size = sizeof(RISCVCPU),
 757         .instance_align = __alignof__(RISCVCPU),
 758         .instance_init = riscv_cpu_init,
 759         .abstract = true,
 760         .class_size = sizeof(RISCVCPUClass),
 761         .class_init = riscv_cpu_class_init,
 762     },
 763     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 764 #if defined(TARGET_RISCV32)
 765     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           rv32_base_cpu_init),
 766     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
 767     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
 768     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
 769     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
 770 #elif defined(TARGET_RISCV64)
 771     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           rv64_base_cpu_init),
 772     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
 773     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
 774     DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
 775 #endif
 776 };
 777
 778 DEFINE_TYPES(riscv_cpu_type_infos)