target/riscv/cpu.h

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_CPU_H
  21 #define RISCV_CPU_H
  22
  23 #include "hw/core/cpu.h"
  24 #include "exec/cpu-defs.h"
  25 #include "fpu/softfloat-types.h"
  26
  27 #define TCG_GUEST_DEFAULT_MO 0
  28
  29 #define TYPE_RISCV_CPU "riscv-cpu"
  30
  31 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
  32 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
  33 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
  34
  35 #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
  36 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
  37 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
  38 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
  39 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
  40 #define TYPE_RISCV_CPU_SIFIVE_U34       RISCV_CPU_TYPE_NAME("sifive-u34")
  41 #define TYPE_RISCV_CPU_SIFIVE_U54       RISCV_CPU_TYPE_NAME("sifive-u54")
  42 /* Deprecated */
  43 #define TYPE_RISCV_CPU_RV32IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
  44 #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
  45 #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
  46 #define TYPE_RISCV_CPU_RV64IMACU_NOMMU  RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
  47 #define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
  48 #define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
  49
  50 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
  51 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
  52
  53 #if defined(TARGET_RISCV32)
  54 #define RVXLEN RV32
  55 #elif defined(TARGET_RISCV64)
  56 #define RVXLEN RV64
  57 #endif
  58
  59 #define RV(x) ((target_ulong)1 << (x - 'A'))
  60
  61 #define RVI RV('I')
  62 #define RVE RV('E') /* E and I are mutually exclusive */
  63 #define RVM RV('M')
  64 #define RVA RV('A')
  65 #define RVF RV('F')
  66 #define RVD RV('D')
  67 #define RVC RV('C')
  68 #define RVS RV('S')
  69 #define RVU RV('U')
  70 #define RVH RV('H')
  71
  72 /* S extension denotes that Supervisor mode exists, however it is possible
  73    to have a core that support S mode but does not have an MMU and there
  74    is currently no bit in misa to indicate whether an MMU exists or not
  75    so a cpu features bitfield is required, likewise for optional PMP support */
  76 enum {
  77     RISCV_FEATURE_MMU,
  78     RISCV_FEATURE_PMP,
  79     RISCV_FEATURE_MISA
  80 };
  81
  82 #define PRIV_VERSION_1_09_1 0x00010901
  83 #define PRIV_VERSION_1_10_0 0x00011000
  84 #define PRIV_VERSION_1_11_0 0x00011100
  85
  86 #define TRANSLATE_PMP_FAIL 2
  87 #define TRANSLATE_FAIL 1
  88 #define TRANSLATE_SUCCESS 0
  89 #define MMU_USER_IDX 3
  90
  91 #define MAX_RISCV_PMPS (16)
  92
  93 typedef struct CPURISCVState CPURISCVState;
  94
  95 #include "pmp.h"
  96
  97 struct CPURISCVState {
  98     target_ulong gpr[32];
  99     uint64_t fpr[32]; /* assume both F and D extensions */
 100     target_ulong pc;
 101     target_ulong load_res;
 102     target_ulong load_val;
 103
 104     target_ulong frm;
 105
 106     target_ulong badaddr;
 107     target_ulong guest_phys_fault_addr;
 108
 109     target_ulong priv_ver;
 110     target_ulong misa;
 111     target_ulong misa_mask;
 112
 113     uint32_t features;
 114
 115 #ifdef CONFIG_USER_ONLY
 116     uint32_t elf_flags;
 117 #endif
 118
 119 #ifndef CONFIG_USER_ONLY
 120     target_ulong priv;
 121     /* This contains QEMU specific information about the virt state. */
 122     target_ulong virt;
 123     target_ulong resetvec;
 124
 125     target_ulong mhartid;
 126     target_ulong mstatus;
 127
 128     target_ulong mip;
 129
 130 #ifdef TARGET_RISCV32
 131     target_ulong mstatush;
 132 #endif
 133
 134     uint32_t miclaim;
 135
 136     target_ulong mie;
 137     target_ulong mideleg;
 138
 139     target_ulong sptbr;  /* until: priv-1.9.1 */
 140     target_ulong satp;   /* since: priv-1.10.0 */
 141     target_ulong sbadaddr;
 142     target_ulong mbadaddr;
 143     target_ulong medeleg;
 144
 145     target_ulong stvec;
 146     target_ulong sepc;
 147     target_ulong scause;
 148
 149     target_ulong mtvec;
 150     target_ulong mepc;
 151     target_ulong mcause;
 152     target_ulong mtval;  /* since: priv-1.10.0 */
 153
 154     /* Hypervisor CSRs */
 155     target_ulong hstatus;
 156     target_ulong hedeleg;
 157     target_ulong hideleg;
 158     target_ulong hcounteren;
 159     target_ulong htval;
 160     target_ulong htinst;
 161     target_ulong hgatp;
 162     uint64_t htimedelta;
 163
 164     /* Virtual CSRs */
 165     target_ulong vsstatus;
 166     target_ulong vstvec;
 167     target_ulong vsscratch;
 168     target_ulong vsepc;
 169     target_ulong vscause;
 170     target_ulong vstval;
 171     target_ulong vsatp;
 172 #ifdef TARGET_RISCV32
 173     target_ulong vsstatush;
 174 #endif
 175
 176     target_ulong mtval2;
 177     target_ulong mtinst;
 178
 179     /* HS Backup CSRs */
 180     target_ulong stvec_hs;
 181     target_ulong sscratch_hs;
 182     target_ulong sepc_hs;
 183     target_ulong scause_hs;
 184     target_ulong stval_hs;
 185     target_ulong satp_hs;
 186     target_ulong mstatus_hs;
 187 #ifdef TARGET_RISCV32
 188     target_ulong mstatush_hs;
 189 #endif
 190
 191     target_ulong scounteren;
 192     target_ulong mcounteren;
 193
 194     target_ulong sscratch;
 195     target_ulong mscratch;
 196
 197     /* temporary htif regs */
 198     uint64_t mfromhost;
 199     uint64_t mtohost;
 200     uint64_t timecmp;
 201
 202     /* physical memory protection */
 203     pmp_table_t pmp_state;
 204
 205     /* machine specific rdtime callback */
 206     uint64_t (*rdtime_fn)(void);
 207
 208     /* True if in debugger mode.  */
 209     bool debugger;
 210 #endif
 211
 212     float_status fp_status;
 213
 214     /* Fields from here on are preserved across CPU reset. */
 215     QEMUTimer *timer; /* Internal timer */
 216 };
 217
 218 #define RISCV_CPU_CLASS(klass) \
 219     OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
 220 #define RISCV_CPU(obj) \
 221     OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
 222 #define RISCV_CPU_GET_CLASS(obj) \
 223     OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
 224
 225 /**
 226  * RISCVCPUClass:
 227  * @parent_realize: The parent class' realize handler.
 228  * @parent_reset: The parent class' reset handler.
 229  *
 230  * A RISCV CPU model.
 231  */
 232 typedef struct RISCVCPUClass {
 233     /*< private >*/
 234     CPUClass parent_class;
 235     /*< public >*/
 236     DeviceRealize parent_realize;
 237     DeviceReset parent_reset;
 238 } RISCVCPUClass;
 239
 240 /**
 241  * RISCVCPU:
 242  * @env: #CPURISCVState
 243  *
 244  * A RISCV CPU.
 245  */
 246 typedef struct RISCVCPU {
 247     /*< private >*/
 248     CPUState parent_obj;
 249     /*< public >*/
 250     CPUNegativeOffsetState neg;
 251     CPURISCVState env;
 252
 253     /* Configuration Settings */
 254     struct {
 255         bool ext_i;
 256         bool ext_e;
 257         bool ext_g;
 258         bool ext_m;
 259         bool ext_a;
 260         bool ext_f;
 261         bool ext_d;
 262         bool ext_c;
 263         bool ext_s;
 264         bool ext_u;
 265         bool ext_h;
 266         bool ext_counters;
 267         bool ext_ifencei;
 268         bool ext_icsr;
 269
 270         char *priv_spec;
 271         char *user_spec;
 272         bool mmu;
 273         bool pmp;
 274     } cfg;
 275 } RISCVCPU;
 276
 277 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 278 {
 279     return (env->misa & ext) != 0;
 280 }
 281
 282 static inline bool riscv_feature(CPURISCVState *env, int feature)
 283 {
 284     return env->features & (1ULL << feature);
 285 }
 286
 287 #include "cpu_user.h"
 288 #include "cpu_bits.h"
 289
 290 extern const char * const riscv_int_regnames[];
 291 extern const char * const riscv_fpr_regnames[];
 292 extern const char * const riscv_excp_names[];
 293 extern const char * const riscv_intr_names[];
 294
 295 void riscv_cpu_do_interrupt(CPUState *cpu);
 296 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 297 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 298 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 299 bool riscv_cpu_fp_enabled(CPURISCVState *env);
 300 bool riscv_cpu_virt_enabled(CPURISCVState *env);
 301 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 302 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
 303 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
 304 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 305 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 306 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 307                                     MMUAccessType access_type, int mmu_idx,
 308                                     uintptr_t retaddr);
 309 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 310                         MMUAccessType access_type, int mmu_idx,
 311                         bool probe, uintptr_t retaddr);
 312 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 313                                      vaddr addr, unsigned size,
 314                                      MMUAccessType access_type,
 315                                      int mmu_idx, MemTxAttrs attrs,
 316                                      MemTxResult response, uintptr_t retaddr);
 317 char *riscv_isa_string(RISCVCPU *cpu);
 318 void riscv_cpu_list(void);
 319
 320 #define cpu_signal_handler riscv_cpu_signal_handler
 321 #define cpu_list riscv_cpu_list
 322 #define cpu_mmu_index riscv_cpu_mmu_index
 323
 324 #ifndef CONFIG_USER_ONLY
 325 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 326 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
 327 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
 328 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
 329 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
 330 #endif
 331 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 332
 333 void riscv_translate_init(void);
 334 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
 335 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
 336                                          uint32_t exception, uintptr_t pc);
 337
 338 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 339 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 340
 341 #define TB_FLAGS_MMU_MASK   3
 342 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 343
 344 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 345                                         target_ulong *cs_base, uint32_t *flags)
 346 {
 347     *pc = env->pc;
 348     *cs_base = 0;
 349 #ifdef CONFIG_USER_ONLY
 350     *flags = TB_FLAGS_MSTATUS_FS;
 351 #else
 352     *flags = cpu_mmu_index(env, 0);
 353     if (riscv_cpu_fp_enabled(env)) {
 354         *flags |= env->mstatus & MSTATUS_FS;
 355     }
 356 #endif
 357 }
 358
 359 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 360                 target_ulong new_value, target_ulong write_mask);
 361 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
 362                       target_ulong new_value, target_ulong write_mask);
 363
 364 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
 365                                    target_ulong val)
 366 {
 367     riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
 368 }
 369
 370 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
 371 {
 372     target_ulong val = 0;
 373     riscv_csrrw(env, csrno, &val, 0, 0);
 374     return val;
 375 }
 376
 377 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
 378 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
 379     target_ulong *ret_value);
 380 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
 381     target_ulong new_value);
 382 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
 383     target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
 384
 385 typedef struct {
 386     riscv_csr_predicate_fn predicate;
 387     riscv_csr_read_fn read;
 388     riscv_csr_write_fn write;
 389     riscv_csr_op_fn op;
 390 } riscv_csr_operations;
 391
 392 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
 393 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 394
 395 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 396
 397 typedef CPURISCVState CPUArchState;
 398 typedef RISCVCPU ArchCPU;
 399
 400 #include "exec/cpu-all.h"
 401
 402 #endif /* RISCV_CPU_H */