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loader: rename in_ram/has_mr
[qemu/ar7.git] / target-sparc / ldst_helper.c
blob92761ad17bd439d9e6f76061e2aa921c8733baa0
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "helper.h"
22
23 //#define DEBUG_MMU
24 //#define DEBUG_MXCC
25 //#define DEBUG_UNALIGNED
26 //#define DEBUG_UNASSIGNED
27 //#define DEBUG_ASI
28 //#define DEBUG_CACHE_CONTROL
29
30 #ifdef DEBUG_MMU
31 #define DPRINTF_MMU(fmt, ...) \
32 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
33 #else
34 #define DPRINTF_MMU(fmt, ...) do {} while (0)
35 #endif
36
37 #ifdef DEBUG_MXCC
38 #define DPRINTF_MXCC(fmt, ...) \
39 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
40 #else
41 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
42 #endif
43
44 #ifdef DEBUG_ASI
45 #define DPRINTF_ASI(fmt, ...) \
46 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
47 #endif
48
49 #ifdef DEBUG_CACHE_CONTROL
50 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
51 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
52 #else
53 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
54 #endif
55
56 #ifdef TARGET_SPARC64
57 #ifndef TARGET_ABI32
58 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
59 #else
60 #define AM_CHECK(env1) (1)
61 #endif
62 #endif
63
64 #define QT0 (env->qt0)
65 #define QT1 (env->qt1)
66
67 #if !defined(CONFIG_USER_ONLY)
68 static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
69 target_ulong addr, int is_write,
70 int is_user, uintptr_t retaddr);
71 #include "exec/softmmu_exec.h"
72 #define MMUSUFFIX _mmu
73 #define ALIGNED_ONLY
74
75 #define SHIFT 0
76 #include "exec/softmmu_template.h"
77
78 #define SHIFT 1
79 #include "exec/softmmu_template.h"
80
81 #define SHIFT 2
82 #include "exec/softmmu_template.h"
83
84 #define SHIFT 3
85 #include "exec/softmmu_template.h"
86 #endif
87
88 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
89 /* Calculates TSB pointer value for fault page size 8k or 64k */
90 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
91 uint64_t tag_access_register,
92 int page_size)
93 {
94 uint64_t tsb_base = tsb_register & ~0x1fffULL;
95 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
96 int tsb_size = tsb_register & 0xf;
97
98 /* discard lower 13 bits which hold tag access context */
99 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
100
101 /* now reorder bits */
102 uint64_t tsb_base_mask = ~0x1fffULL;
103 uint64_t va = tag_access_va;
104
105 /* move va bits to correct position */
106 if (page_size == 8*1024) {
107 va >>= 9;
108 } else if (page_size == 64*1024) {
109 va >>= 12;
110 }
111
112 if (tsb_size) {
113 tsb_base_mask <<= tsb_size;
114 }
115
116 /* calculate tsb_base mask and adjust va if split is in use */
117 if (tsb_split) {
118 if (page_size == 8*1024) {
119 va &= ~(1ULL << (13 + tsb_size));
120 } else if (page_size == 64*1024) {
121 va |= (1ULL << (13 + tsb_size));
122 }
123 tsb_base_mask <<= 1;
124 }
125
126 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
127 }
128
129 /* Calculates tag target register value by reordering bits
130 in tag access register */
131 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
132 {
133 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
134 }
135
136 static void replace_tlb_entry(SparcTLBEntry *tlb,
137 uint64_t tlb_tag, uint64_t tlb_tte,
138 CPUSPARCState *env1)
139 {
140 target_ulong mask, size, va, offset;
141
142 /* flush page range if translation is valid */
143 if (TTE_IS_VALID(tlb->tte)) {
144
145 mask = 0xffffffffffffe000ULL;
146 mask <<= 3 * ((tlb->tte >> 61) & 3);
147 size = ~mask + 1;
148
149 va = tlb->tag & mask;
150
151 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
152 tlb_flush_page(env1, va + offset);
153 }
154 }
155
156 tlb->tag = tlb_tag;
157 tlb->tte = tlb_tte;
158 }
159
160 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
161 const char *strmmu, CPUSPARCState *env1)
162 {
163 unsigned int i;
164 target_ulong mask;
165 uint64_t context;
166
167 int is_demap_context = (demap_addr >> 6) & 1;
168
169 /* demap context */
170 switch ((demap_addr >> 4) & 3) {
171 case 0: /* primary */
172 context = env1->dmmu.mmu_primary_context;
173 break;
174 case 1: /* secondary */
175 context = env1->dmmu.mmu_secondary_context;
176 break;
177 case 2: /* nucleus */
178 context = 0;
179 break;
180 case 3: /* reserved */
181 default:
182 return;
183 }
184
185 for (i = 0; i < 64; i++) {
186 if (TTE_IS_VALID(tlb[i].tte)) {
187
188 if (is_demap_context) {
189 /* will remove non-global entries matching context value */
190 if (TTE_IS_GLOBAL(tlb[i].tte) ||
191 !tlb_compare_context(&tlb[i], context)) {
192 continue;
193 }
194 } else {
195 /* demap page
196 will remove any entry matching VA */
197 mask = 0xffffffffffffe000ULL;
198 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
199
200 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
201 continue;
202 }
203
204 /* entry should be global or matching context value */
205 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
206 !tlb_compare_context(&tlb[i], context)) {
207 continue;
208 }
209 }
210
211 replace_tlb_entry(&tlb[i], 0, 0, env1);
212 #ifdef DEBUG_MMU
213 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
214 dump_mmu(stdout, fprintf, env1);
215 #endif
216 }
217 }
218 }
219
220 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
221 uint64_t tlb_tag, uint64_t tlb_tte,
222 const char *strmmu, CPUSPARCState *env1)
223 {
224 unsigned int i, replace_used;
225
226 /* Try replacing invalid entry */
227 for (i = 0; i < 64; i++) {
228 if (!TTE_IS_VALID(tlb[i].tte)) {
229 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
230 #ifdef DEBUG_MMU
231 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
232 dump_mmu(stdout, fprintf, env1);
233 #endif
234 return;
235 }
236 }
237
238 /* All entries are valid, try replacing unlocked entry */
239
240 for (replace_used = 0; replace_used < 2; ++replace_used) {
241
242 /* Used entries are not replaced on first pass */
243
244 for (i = 0; i < 64; i++) {
245 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
246
247 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
248 #ifdef DEBUG_MMU
249 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
250 strmmu, (replace_used ? "used" : "unused"), i);
251 dump_mmu(stdout, fprintf, env1);
252 #endif
253 return;
254 }
255 }
256
257 /* Now reset used bit and search for unused entries again */
258
259 for (i = 0; i < 64; i++) {
260 TTE_SET_UNUSED(tlb[i].tte);
261 }
262 }
263
264 #ifdef DEBUG_MMU
265 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
266 #endif
267 /* error state? */
268 }
269
270 #endif
271
272 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
273 {
274 #ifdef TARGET_SPARC64
275 if (AM_CHECK(env1)) {
276 addr &= 0xffffffffULL;
277 }
278 #endif
279 return addr;
280 }
281
282 /* returns true if access using this ASI is to have address translated by MMU
283 otherwise access is to raw physical address */
284 static inline int is_translating_asi(int asi)
285 {
286 #ifdef TARGET_SPARC64
287 /* Ultrasparc IIi translating asi
288 - note this list is defined by cpu implementation
289 */
290 switch (asi) {
291 case 0x04 ... 0x11:
292 case 0x16 ... 0x19:
293 case 0x1E ... 0x1F:
294 case 0x24 ... 0x2C:
295 case 0x70 ... 0x73:
296 case 0x78 ... 0x79:
297 case 0x80 ... 0xFF:
298 return 1;
299
300 default:
301 return 0;
302 }
303 #else
304 /* TODO: check sparc32 bits */
305 return 0;
306 #endif
307 }
308
309 static inline target_ulong asi_address_mask(CPUSPARCState *env,
310 int asi, target_ulong addr)
311 {
312 if (is_translating_asi(asi)) {
313 return address_mask(env, addr);
314 } else {
315 return addr;
316 }
317 }
318
319 void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
320 {
321 if (addr & align) {
322 #ifdef DEBUG_UNALIGNED
323 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
324 "\n", addr, env->pc);
325 #endif
326 helper_raise_exception(env, TT_UNALIGNED);
327 }
328 }
329
330 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
331 defined(DEBUG_MXCC)
332 static void dump_mxcc(CPUSPARCState *env)
333 {
334 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
335 "\n",
336 env->mxccdata[0], env->mxccdata[1],
337 env->mxccdata[2], env->mxccdata[3]);
338 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
339 "\n"
340 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
341 "\n",
342 env->mxccregs[0], env->mxccregs[1],
343 env->mxccregs[2], env->mxccregs[3],
344 env->mxccregs[4], env->mxccregs[5],
345 env->mxccregs[6], env->mxccregs[7]);
346 }
347 #endif
348
349 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
350 && defined(DEBUG_ASI)
351 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
352 uint64_t r1)
353 {
354 switch (size) {
355 case 1:
356 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
357 addr, asi, r1 & 0xff);
358 break;
359 case 2:
360 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
361 addr, asi, r1 & 0xffff);
362 break;
363 case 4:
364 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
365 addr, asi, r1 & 0xffffffff);
366 break;
367 case 8:
368 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
369 addr, asi, r1);
370 break;
371 }
372 }
373 #endif
374
375 #ifndef TARGET_SPARC64
376 #ifndef CONFIG_USER_ONLY
377
378
379 /* Leon3 cache control */
380
381 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
382 uint64_t val, int size)
383 {
384 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
385 addr, val, size);
386
387 if (size != 4) {
388 DPRINTF_CACHE_CONTROL("32bits only\n");
389 return;
390 }
391
392 switch (addr) {
393 case 0x00: /* Cache control */
394
395 /* These values must always be read as zeros */
396 val &= ~CACHE_CTRL_FD;
397 val &= ~CACHE_CTRL_FI;
398 val &= ~CACHE_CTRL_IB;
399 val &= ~CACHE_CTRL_IP;
400 val &= ~CACHE_CTRL_DP;
401
402 env->cache_control = val;
403 break;
404 case 0x04: /* Instruction cache configuration */
405 case 0x08: /* Data cache configuration */
406 /* Read Only */
407 break;
408 default:
409 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
410 break;
411 };
412 }
413
414 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
415 int size)
416 {
417 uint64_t ret = 0;
418
419 if (size != 4) {
420 DPRINTF_CACHE_CONTROL("32bits only\n");
421 return 0;
422 }
423
424 switch (addr) {
425 case 0x00: /* Cache control */
426 ret = env->cache_control;
427 break;
428
429 /* Configuration registers are read and only always keep those
430 predefined values */
431
432 case 0x04: /* Instruction cache configuration */
433 ret = 0x10220000;
434 break;
435 case 0x08: /* Data cache configuration */
436 ret = 0x18220000;
437 break;
438 default:
439 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
440 break;
441 };
442 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
443 addr, ret, size);
444 return ret;
445 }
446
447 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
448 int sign)
449 {
450 CPUState *cs = ENV_GET_CPU(env);
451 uint64_t ret = 0;
452 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
453 uint32_t last_addr = addr;
454 #endif
455
456 helper_check_align(env, addr, size - 1);
457 switch (asi) {
458 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
459 switch (addr) {
460 case 0x00: /* Leon3 Cache Control */
461 case 0x08: /* Leon3 Instruction Cache config */
462 case 0x0C: /* Leon3 Date Cache config */
463 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
464 ret = leon3_cache_control_ld(env, addr, size);
465 }
466 break;
467 case 0x01c00a00: /* MXCC control register */
468 if (size == 8) {
469 ret = env->mxccregs[3];
470 } else {
471 qemu_log_mask(LOG_UNIMP,
472 "%08x: unimplemented access size: %d\n", addr,
473 size);
474 }
475 break;
476 case 0x01c00a04: /* MXCC control register */
477 if (size == 4) {
478 ret = env->mxccregs[3];
479 } else {
480 qemu_log_mask(LOG_UNIMP,
481 "%08x: unimplemented access size: %d\n", addr,
482 size);
483 }
484 break;
485 case 0x01c00c00: /* Module reset register */
486 if (size == 8) {
487 ret = env->mxccregs[5];
488 /* should we do something here? */
489 } else {
490 qemu_log_mask(LOG_UNIMP,
491 "%08x: unimplemented access size: %d\n", addr,
492 size);
493 }
494 break;
495 case 0x01c00f00: /* MBus port address register */
496 if (size == 8) {
497 ret = env->mxccregs[7];
498 } else {
499 qemu_log_mask(LOG_UNIMP,
500 "%08x: unimplemented access size: %d\n", addr,
501 size);
502 }
503 break;
504 default:
505 qemu_log_mask(LOG_UNIMP,
506 "%08x: unimplemented address, size: %d\n", addr,
507 size);
508 break;
509 }
510 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
511 "addr = %08x -> ret = %" PRIx64 ","
512 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
513 #ifdef DEBUG_MXCC
514 dump_mxcc(env);
515 #endif
516 break;
517 case 3: /* MMU probe */
518 case 0x18: /* LEON3 MMU probe */
519 {
520 int mmulev;
521
522 mmulev = (addr >> 8) & 15;
523 if (mmulev > 4) {
524 ret = 0;
525 } else {
526 ret = mmu_probe(env, addr, mmulev);
527 }
528 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
529 addr, mmulev, ret);
530 }
531 break;
532 case 4: /* read MMU regs */
533 case 0x19: /* LEON3 read MMU regs */
534 {
535 int reg = (addr >> 8) & 0x1f;
536
537 ret = env->mmuregs[reg];
538 if (reg == 3) { /* Fault status cleared on read */
539 env->mmuregs[3] = 0;
540 } else if (reg == 0x13) { /* Fault status read */
541 ret = env->mmuregs[3];
542 } else if (reg == 0x14) { /* Fault address read */
543 ret = env->mmuregs[4];
544 }
545 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
546 }
547 break;
548 case 5: /* Turbosparc ITLB Diagnostic */
549 case 6: /* Turbosparc DTLB Diagnostic */
550 case 7: /* Turbosparc IOTLB Diagnostic */
551 break;
552 case 9: /* Supervisor code access */
553 switch (size) {
554 case 1:
555 ret = cpu_ldub_code(env, addr);
556 break;
557 case 2:
558 ret = cpu_lduw_code(env, addr);
559 break;
560 default:
561 case 4:
562 ret = cpu_ldl_code(env, addr);
563 break;
564 case 8:
565 ret = cpu_ldq_code(env, addr);
566 break;
567 }
568 break;
569 case 0xa: /* User data access */
570 switch (size) {
571 case 1:
572 ret = cpu_ldub_user(env, addr);
573 break;
574 case 2:
575 ret = cpu_lduw_user(env, addr);
576 break;
577 default:
578 case 4:
579 ret = cpu_ldl_user(env, addr);
580 break;
581 case 8:
582 ret = cpu_ldq_user(env, addr);
583 break;
584 }
585 break;
586 case 0xb: /* Supervisor data access */
587 switch (size) {
588 case 1:
589 ret = cpu_ldub_kernel(env, addr);
590 break;
591 case 2:
592 ret = cpu_lduw_kernel(env, addr);
593 break;
594 default:
595 case 4:
596 ret = cpu_ldl_kernel(env, addr);
597 break;
598 case 8:
599 ret = cpu_ldq_kernel(env, addr);
600 break;
601 }
602 break;
603 case 0xc: /* I-cache tag */
604 case 0xd: /* I-cache data */
605 case 0xe: /* D-cache tag */
606 case 0xf: /* D-cache data */
607 break;
608 case 0x20: /* MMU passthrough */
609 case 0x1c: /* LEON MMU passthrough */
610 switch (size) {
611 case 1:
612 ret = ldub_phys(cs->as, addr);
613 break;
614 case 2:
615 ret = lduw_phys(cs->as, addr);
616 break;
617 default:
618 case 4:
619 ret = ldl_phys(cs->as, addr);
620 break;
621 case 8:
622 ret = ldq_phys(cs->as, addr);
623 break;
624 }
625 break;
626 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
627 switch (size) {
628 case 1:
629 ret = ldub_phys(cs->as, (hwaddr)addr
630 | ((hwaddr)(asi & 0xf) << 32));
631 break;
632 case 2:
633 ret = lduw_phys(cs->as, (hwaddr)addr
634 | ((hwaddr)(asi & 0xf) << 32));
635 break;
636 default:
637 case 4:
638 ret = ldl_phys(cs->as, (hwaddr)addr
639 | ((hwaddr)(asi & 0xf) << 32));
640 break;
641 case 8:
642 ret = ldq_phys(cs->as, (hwaddr)addr
643 | ((hwaddr)(asi & 0xf) << 32));
644 break;
645 }
646 break;
647 case 0x30: /* Turbosparc secondary cache diagnostic */
648 case 0x31: /* Turbosparc RAM snoop */
649 case 0x32: /* Turbosparc page table descriptor diagnostic */
650 case 0x39: /* data cache diagnostic register */
651 ret = 0;
652 break;
653 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
654 {
655 int reg = (addr >> 8) & 3;
656
657 switch (reg) {
658 case 0: /* Breakpoint Value (Addr) */
659 ret = env->mmubpregs[reg];
660 break;
661 case 1: /* Breakpoint Mask */
662 ret = env->mmubpregs[reg];
663 break;
664 case 2: /* Breakpoint Control */
665 ret = env->mmubpregs[reg];
666 break;
667 case 3: /* Breakpoint Status */
668 ret = env->mmubpregs[reg];
669 env->mmubpregs[reg] = 0ULL;
670 break;
671 }
672 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
673 ret);
674 }
675 break;
676 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
677 ret = env->mmubpctrv;
678 break;
679 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
680 ret = env->mmubpctrc;
681 break;
682 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
683 ret = env->mmubpctrs;
684 break;
685 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
686 ret = env->mmubpaction;
687 break;
688 case 8: /* User code access, XXX */
689 default:
690 cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
691 addr, false, false, asi, size);
692 ret = 0;
693 break;
694 }
695 if (sign) {
696 switch (size) {
697 case 1:
698 ret = (int8_t) ret;
699 break;
700 case 2:
701 ret = (int16_t) ret;
702 break;
703 case 4:
704 ret = (int32_t) ret;
705 break;
706 default:
707 break;
708 }
709 }
710 #ifdef DEBUG_ASI
711 dump_asi("read ", last_addr, asi, size, ret);
712 #endif
713 return ret;
714 }
715
716 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
717 int size)
718 {
719 CPUState *cs = ENV_GET_CPU(env);
720 helper_check_align(env, addr, size - 1);
721 switch (asi) {
722 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
723 switch (addr) {
724 case 0x00: /* Leon3 Cache Control */
725 case 0x08: /* Leon3 Instruction Cache config */
726 case 0x0C: /* Leon3 Date Cache config */
727 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
728 leon3_cache_control_st(env, addr, val, size);
729 }
730 break;
731
732 case 0x01c00000: /* MXCC stream data register 0 */
733 if (size == 8) {
734 env->mxccdata[0] = val;
735 } else {
736 qemu_log_mask(LOG_UNIMP,
737 "%08x: unimplemented access size: %d\n", addr,
738 size);
739 }
740 break;
741 case 0x01c00008: /* MXCC stream data register 1 */
742 if (size == 8) {
743 env->mxccdata[1] = val;
744 } else {
745 qemu_log_mask(LOG_UNIMP,
746 "%08x: unimplemented access size: %d\n", addr,
747 size);
748 }
749 break;
750 case 0x01c00010: /* MXCC stream data register 2 */
751 if (size == 8) {
752 env->mxccdata[2] = val;
753 } else {
754 qemu_log_mask(LOG_UNIMP,
755 "%08x: unimplemented access size: %d\n", addr,
756 size);
757 }
758 break;
759 case 0x01c00018: /* MXCC stream data register 3 */
760 if (size == 8) {
761 env->mxccdata[3] = val;
762 } else {
763 qemu_log_mask(LOG_UNIMP,
764 "%08x: unimplemented access size: %d\n", addr,
765 size);
766 }
767 break;
768 case 0x01c00100: /* MXCC stream source */
769 if (size == 8) {
770 env->mxccregs[0] = val;
771 } else {
772 qemu_log_mask(LOG_UNIMP,
773 "%08x: unimplemented access size: %d\n", addr,
774 size);
775 }
776 env->mxccdata[0] = ldq_phys(cs->as,
777 (env->mxccregs[0] & 0xffffffffULL) +
778 0);
779 env->mxccdata[1] = ldq_phys(cs->as,
780 (env->mxccregs[0] & 0xffffffffULL) +
781 8);
782 env->mxccdata[2] = ldq_phys(cs->as,
783 (env->mxccregs[0] & 0xffffffffULL) +
784 16);
785 env->mxccdata[3] = ldq_phys(cs->as,
786 (env->mxccregs[0] & 0xffffffffULL) +
787 24);
788 break;
789 case 0x01c00200: /* MXCC stream destination */
790 if (size == 8) {
791 env->mxccregs[1] = val;
792 } else {
793 qemu_log_mask(LOG_UNIMP,
794 "%08x: unimplemented access size: %d\n", addr,
795 size);
796 }
797 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 0,
798 env->mxccdata[0]);
799 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 8,
800 env->mxccdata[1]);
801 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 16,
802 env->mxccdata[2]);
803 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 24,
804 env->mxccdata[3]);
805 break;
806 case 0x01c00a00: /* MXCC control register */
807 if (size == 8) {
808 env->mxccregs[3] = val;
809 } else {
810 qemu_log_mask(LOG_UNIMP,
811 "%08x: unimplemented access size: %d\n", addr,
812 size);
813 }
814 break;
815 case 0x01c00a04: /* MXCC control register */
816 if (size == 4) {
817 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
818 | val;
819 } else {
820 qemu_log_mask(LOG_UNIMP,
821 "%08x: unimplemented access size: %d\n", addr,
822 size);
823 }
824 break;
825 case 0x01c00e00: /* MXCC error register */
826 /* writing a 1 bit clears the error */
827 if (size == 8) {
828 env->mxccregs[6] &= ~val;
829 } else {
830 qemu_log_mask(LOG_UNIMP,
831 "%08x: unimplemented access size: %d\n", addr,
832 size);
833 }
834 break;
835 case 0x01c00f00: /* MBus port address register */
836 if (size == 8) {
837 env->mxccregs[7] = val;
838 } else {
839 qemu_log_mask(LOG_UNIMP,
840 "%08x: unimplemented access size: %d\n", addr,
841 size);
842 }
843 break;
844 default:
845 qemu_log_mask(LOG_UNIMP,
846 "%08x: unimplemented address, size: %d\n", addr,
847 size);
848 break;
849 }
850 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
851 asi, size, addr, val);
852 #ifdef DEBUG_MXCC
853 dump_mxcc(env);
854 #endif
855 break;
856 case 3: /* MMU flush */
857 case 0x18: /* LEON3 MMU flush */
858 {
859 int mmulev;
860
861 mmulev = (addr >> 8) & 15;
862 DPRINTF_MMU("mmu flush level %d\n", mmulev);
863 switch (mmulev) {
864 case 0: /* flush page */
865 tlb_flush_page(env, addr & 0xfffff000);
866 break;
867 case 1: /* flush segment (256k) */
868 case 2: /* flush region (16M) */
869 case 3: /* flush context (4G) */
870 case 4: /* flush entire */
871 tlb_flush(env, 1);
872 break;
873 default:
874 break;
875 }
876 #ifdef DEBUG_MMU
877 dump_mmu(stdout, fprintf, env);
878 #endif
879 }
880 break;
881 case 4: /* write MMU regs */
882 case 0x19: /* LEON3 write MMU regs */
883 {
884 int reg = (addr >> 8) & 0x1f;
885 uint32_t oldreg;
886
887 oldreg = env->mmuregs[reg];
888 switch (reg) {
889 case 0: /* Control Register */
890 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
891 (val & 0x00ffffff);
892 /* Mappings generated during no-fault mode or MMU
893 disabled mode are invalid in normal mode */
894 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
895 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
896 tlb_flush(env, 1);
897 }
898 break;
899 case 1: /* Context Table Pointer Register */
900 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
901 break;
902 case 2: /* Context Register */
903 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
904 if (oldreg != env->mmuregs[reg]) {
905 /* we flush when the MMU context changes because
906 QEMU has no MMU context support */
907 tlb_flush(env, 1);
908 }
909 break;
910 case 3: /* Synchronous Fault Status Register with Clear */
911 case 4: /* Synchronous Fault Address Register */
912 break;
913 case 0x10: /* TLB Replacement Control Register */
914 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
915 break;
916 case 0x13: /* Synchronous Fault Status Register with Read
917 and Clear */
918 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
919 break;
920 case 0x14: /* Synchronous Fault Address Register */
921 env->mmuregs[4] = val;
922 break;
923 default:
924 env->mmuregs[reg] = val;
925 break;
926 }
927 if (oldreg != env->mmuregs[reg]) {
928 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
929 reg, oldreg, env->mmuregs[reg]);
930 }
931 #ifdef DEBUG_MMU
932 dump_mmu(stdout, fprintf, env);
933 #endif
934 }
935 break;
936 case 5: /* Turbosparc ITLB Diagnostic */
937 case 6: /* Turbosparc DTLB Diagnostic */
938 case 7: /* Turbosparc IOTLB Diagnostic */
939 break;
940 case 0xa: /* User data access */
941 switch (size) {
942 case 1:
943 cpu_stb_user(env, addr, val);
944 break;
945 case 2:
946 cpu_stw_user(env, addr, val);
947 break;
948 default:
949 case 4:
950 cpu_stl_user(env, addr, val);
951 break;
952 case 8:
953 cpu_stq_user(env, addr, val);
954 break;
955 }
956 break;
957 case 0xb: /* Supervisor data access */
958 switch (size) {
959 case 1:
960 cpu_stb_kernel(env, addr, val);
961 break;
962 case 2:
963 cpu_stw_kernel(env, addr, val);
964 break;
965 default:
966 case 4:
967 cpu_stl_kernel(env, addr, val);
968 break;
969 case 8:
970 cpu_stq_kernel(env, addr, val);
971 break;
972 }
973 break;
974 case 0xc: /* I-cache tag */
975 case 0xd: /* I-cache data */
976 case 0xe: /* D-cache tag */
977 case 0xf: /* D-cache data */
978 case 0x10: /* I/D-cache flush page */
979 case 0x11: /* I/D-cache flush segment */
980 case 0x12: /* I/D-cache flush region */
981 case 0x13: /* I/D-cache flush context */
982 case 0x14: /* I/D-cache flush user */
983 break;
984 case 0x17: /* Block copy, sta access */
985 {
986 /* val = src
987 addr = dst
988 copy 32 bytes */
989 unsigned int i;
990 uint32_t src = val & ~3, dst = addr & ~3, temp;
991
992 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
993 temp = cpu_ldl_kernel(env, src);
994 cpu_stl_kernel(env, dst, temp);
995 }
996 }
997 break;
998 case 0x1f: /* Block fill, stda access */
999 {
1000 /* addr = dst
1001 fill 32 bytes with val */
1002 unsigned int i;
1003 uint32_t dst = addr & 7;
1004
1005 for (i = 0; i < 32; i += 8, dst += 8) {
1006 cpu_stq_kernel(env, dst, val);
1007 }
1008 }
1009 break;
1010 case 0x20: /* MMU passthrough */
1011 case 0x1c: /* LEON MMU passthrough */
1012 {
1013 switch (size) {
1014 case 1:
1015 stb_phys(cs->as, addr, val);
1016 break;
1017 case 2:
1018 stw_phys(cs->as, addr, val);
1019 break;
1020 case 4:
1021 default:
1022 stl_phys(cs->as, addr, val);
1023 break;
1024 case 8:
1025 stq_phys(cs->as, addr, val);
1026 break;
1027 }
1028 }
1029 break;
1030 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1031 {
1032 switch (size) {
1033 case 1:
1034 stb_phys(cs->as, (hwaddr)addr
1035 | ((hwaddr)(asi & 0xf) << 32), val);
1036 break;
1037 case 2:
1038 stw_phys(cs->as, (hwaddr)addr
1039 | ((hwaddr)(asi & 0xf) << 32), val);
1040 break;
1041 case 4:
1042 default:
1043 stl_phys(cs->as, (hwaddr)addr
1044 | ((hwaddr)(asi & 0xf) << 32), val);
1045 break;
1046 case 8:
1047 stq_phys(cs->as, (hwaddr)addr
1048 | ((hwaddr)(asi & 0xf) << 32), val);
1049 break;
1050 }
1051 }
1052 break;
1053 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1054 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1055 Turbosparc snoop RAM */
1056 case 0x32: /* store buffer control or Turbosparc page table
1057 descriptor diagnostic */
1058 case 0x36: /* I-cache flash clear */
1059 case 0x37: /* D-cache flash clear */
1060 break;
1061 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1062 {
1063 int reg = (addr >> 8) & 3;
1064
1065 switch (reg) {
1066 case 0: /* Breakpoint Value (Addr) */
1067 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1068 break;
1069 case 1: /* Breakpoint Mask */
1070 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1071 break;
1072 case 2: /* Breakpoint Control */
1073 env->mmubpregs[reg] = (val & 0x7fULL);
1074 break;
1075 case 3: /* Breakpoint Status */
1076 env->mmubpregs[reg] = (val & 0xfULL);
1077 break;
1078 }
1079 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1080 env->mmuregs[reg]);
1081 }
1082 break;
1083 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1084 env->mmubpctrv = val & 0xffffffff;
1085 break;
1086 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1087 env->mmubpctrc = val & 0x3;
1088 break;
1089 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1090 env->mmubpctrs = val & 0x3;
1091 break;
1092 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1093 env->mmubpaction = val & 0x1fff;
1094 break;
1095 case 8: /* User code access, XXX */
1096 case 9: /* Supervisor code access, XXX */
1097 default:
1098 cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
1099 addr, true, false, asi, size);
1100 break;
1101 }
1102 #ifdef DEBUG_ASI
1103 dump_asi("write", addr, asi, size, val);
1104 #endif
1105 }
1106
1107 #endif /* CONFIG_USER_ONLY */
1108 #else /* TARGET_SPARC64 */
1109
1110 #ifdef CONFIG_USER_ONLY
1111 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1112 int sign)
1113 {
1114 uint64_t ret = 0;
1115 #if defined(DEBUG_ASI)
1116 target_ulong last_addr = addr;
1117 #endif
1118
1119 if (asi < 0x80) {
1120 helper_raise_exception(env, TT_PRIV_ACT);
1121 }
1122
1123 helper_check_align(env, addr, size - 1);
1124 addr = asi_address_mask(env, asi, addr);
1125
1126 switch (asi) {
1127 case 0x82: /* Primary no-fault */
1128 case 0x8a: /* Primary no-fault LE */
1129 if (page_check_range(addr, size, PAGE_READ) == -1) {
1130 #ifdef DEBUG_ASI
1131 dump_asi("read ", last_addr, asi, size, ret);
1132 #endif
1133 return 0;
1134 }
1135 /* Fall through */
1136 case 0x80: /* Primary */
1137 case 0x88: /* Primary LE */
1138 {
1139 switch (size) {
1140 case 1:
1141 ret = ldub_raw(addr);
1142 break;
1143 case 2:
1144 ret = lduw_raw(addr);
1145 break;
1146 case 4:
1147 ret = ldl_raw(addr);
1148 break;
1149 default:
1150 case 8:
1151 ret = ldq_raw(addr);
1152 break;
1153 }
1154 }
1155 break;
1156 case 0x83: /* Secondary no-fault */
1157 case 0x8b: /* Secondary no-fault LE */
1158 if (page_check_range(addr, size, PAGE_READ) == -1) {
1159 #ifdef DEBUG_ASI
1160 dump_asi("read ", last_addr, asi, size, ret);
1161 #endif
1162 return 0;
1163 }
1164 /* Fall through */
1165 case 0x81: /* Secondary */
1166 case 0x89: /* Secondary LE */
1167 /* XXX */
1168 break;
1169 default:
1170 break;
1171 }
1172
1173 /* Convert from little endian */
1174 switch (asi) {
1175 case 0x88: /* Primary LE */
1176 case 0x89: /* Secondary LE */
1177 case 0x8a: /* Primary no-fault LE */
1178 case 0x8b: /* Secondary no-fault LE */
1179 switch (size) {
1180 case 2:
1181 ret = bswap16(ret);
1182 break;
1183 case 4:
1184 ret = bswap32(ret);
1185 break;
1186 case 8:
1187 ret = bswap64(ret);
1188 break;
1189 default:
1190 break;
1191 }
1192 default:
1193 break;
1194 }
1195
1196 /* Convert to signed number */
1197 if (sign) {
1198 switch (size) {
1199 case 1:
1200 ret = (int8_t) ret;
1201 break;
1202 case 2:
1203 ret = (int16_t) ret;
1204 break;
1205 case 4:
1206 ret = (int32_t) ret;
1207 break;
1208 default:
1209 break;
1210 }
1211 }
1212 #ifdef DEBUG_ASI
1213 dump_asi("read ", last_addr, asi, size, ret);
1214 #endif
1215 return ret;
1216 }
1217
1218 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1219 int asi, int size)
1220 {
1221 #ifdef DEBUG_ASI
1222 dump_asi("write", addr, asi, size, val);
1223 #endif
1224 if (asi < 0x80) {
1225 helper_raise_exception(env, TT_PRIV_ACT);
1226 }
1227
1228 helper_check_align(env, addr, size - 1);
1229 addr = asi_address_mask(env, asi, addr);
1230
1231 /* Convert to little endian */
1232 switch (asi) {
1233 case 0x88: /* Primary LE */
1234 case 0x89: /* Secondary LE */
1235 switch (size) {
1236 case 2:
1237 val = bswap16(val);
1238 break;
1239 case 4:
1240 val = bswap32(val);
1241 break;
1242 case 8:
1243 val = bswap64(val);
1244 break;
1245 default:
1246 break;
1247 }
1248 default:
1249 break;
1250 }
1251
1252 switch (asi) {
1253 case 0x80: /* Primary */
1254 case 0x88: /* Primary LE */
1255 {
1256 switch (size) {
1257 case 1:
1258 stb_raw(addr, val);
1259 break;
1260 case 2:
1261 stw_raw(addr, val);
1262 break;
1263 case 4:
1264 stl_raw(addr, val);
1265 break;
1266 case 8:
1267 default:
1268 stq_raw(addr, val);
1269 break;
1270 }
1271 }
1272 break;
1273 case 0x81: /* Secondary */
1274 case 0x89: /* Secondary LE */
1275 /* XXX */
1276 return;
1277
1278 case 0x82: /* Primary no-fault, RO */
1279 case 0x83: /* Secondary no-fault, RO */
1280 case 0x8a: /* Primary no-fault LE, RO */
1281 case 0x8b: /* Secondary no-fault LE, RO */
1282 default:
1283 helper_raise_exception(env, TT_DATA_ACCESS);
1284 return;
1285 }
1286 }
1287
1288 #else /* CONFIG_USER_ONLY */
1289
1290 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1291 int sign)
1292 {
1293 CPUState *cs = ENV_GET_CPU(env);
1294 uint64_t ret = 0;
1295 #if defined(DEBUG_ASI)
1296 target_ulong last_addr = addr;
1297 #endif
1298
1299 asi &= 0xff;
1300
1301 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1302 || (cpu_has_hypervisor(env)
1303 && asi >= 0x30 && asi < 0x80
1304 && !(env->hpstate & HS_PRIV))) {
1305 helper_raise_exception(env, TT_PRIV_ACT);
1306 }
1307
1308 helper_check_align(env, addr, size - 1);
1309 addr = asi_address_mask(env, asi, addr);
1310
1311 /* process nonfaulting loads first */
1312 if ((asi & 0xf6) == 0x82) {
1313 int mmu_idx;
1314
1315 /* secondary space access has lowest asi bit equal to 1 */
1316 if (env->pstate & PS_PRIV) {
1317 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1318 } else {
1319 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1320 }
1321
1322 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1323 #ifdef DEBUG_ASI
1324 dump_asi("read ", last_addr, asi, size, ret);
1325 #endif
1326 /* env->exception_index is set in get_physical_address_data(). */
1327 helper_raise_exception(env, env->exception_index);
1328 }
1329
1330 /* convert nonfaulting load ASIs to normal load ASIs */
1331 asi &= ~0x02;
1332 }
1333
1334 switch (asi) {
1335 case 0x10: /* As if user primary */
1336 case 0x11: /* As if user secondary */
1337 case 0x18: /* As if user primary LE */
1338 case 0x19: /* As if user secondary LE */
1339 case 0x80: /* Primary */
1340 case 0x81: /* Secondary */
1341 case 0x88: /* Primary LE */
1342 case 0x89: /* Secondary LE */
1343 case 0xe2: /* UA2007 Primary block init */
1344 case 0xe3: /* UA2007 Secondary block init */
1345 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1346 if (cpu_hypervisor_mode(env)) {
1347 switch (size) {
1348 case 1:
1349 ret = cpu_ldub_hypv(env, addr);
1350 break;
1351 case 2:
1352 ret = cpu_lduw_hypv(env, addr);
1353 break;
1354 case 4:
1355 ret = cpu_ldl_hypv(env, addr);
1356 break;
1357 default:
1358 case 8:
1359 ret = cpu_ldq_hypv(env, addr);
1360 break;
1361 }
1362 } else {
1363 /* secondary space access has lowest asi bit equal to 1 */
1364 if (asi & 1) {
1365 switch (size) {
1366 case 1:
1367 ret = cpu_ldub_kernel_secondary(env, addr);
1368 break;
1369 case 2:
1370 ret = cpu_lduw_kernel_secondary(env, addr);
1371 break;
1372 case 4:
1373 ret = cpu_ldl_kernel_secondary(env, addr);
1374 break;
1375 default:
1376 case 8:
1377 ret = cpu_ldq_kernel_secondary(env, addr);
1378 break;
1379 }
1380 } else {
1381 switch (size) {
1382 case 1:
1383 ret = cpu_ldub_kernel(env, addr);
1384 break;
1385 case 2:
1386 ret = cpu_lduw_kernel(env, addr);
1387 break;
1388 case 4:
1389 ret = cpu_ldl_kernel(env, addr);
1390 break;
1391 default:
1392 case 8:
1393 ret = cpu_ldq_kernel(env, addr);
1394 break;
1395 }
1396 }
1397 }
1398 } else {
1399 /* secondary space access has lowest asi bit equal to 1 */
1400 if (asi & 1) {
1401 switch (size) {
1402 case 1:
1403 ret = cpu_ldub_user_secondary(env, addr);
1404 break;
1405 case 2:
1406 ret = cpu_lduw_user_secondary(env, addr);
1407 break;
1408 case 4:
1409 ret = cpu_ldl_user_secondary(env, addr);
1410 break;
1411 default:
1412 case 8:
1413 ret = cpu_ldq_user_secondary(env, addr);
1414 break;
1415 }
1416 } else {
1417 switch (size) {
1418 case 1:
1419 ret = cpu_ldub_user(env, addr);
1420 break;
1421 case 2:
1422 ret = cpu_lduw_user(env, addr);
1423 break;
1424 case 4:
1425 ret = cpu_ldl_user(env, addr);
1426 break;
1427 default:
1428 case 8:
1429 ret = cpu_ldq_user(env, addr);
1430 break;
1431 }
1432 }
1433 }
1434 break;
1435 case 0x14: /* Bypass */
1436 case 0x15: /* Bypass, non-cacheable */
1437 case 0x1c: /* Bypass LE */
1438 case 0x1d: /* Bypass, non-cacheable LE */
1439 {
1440 switch (size) {
1441 case 1:
1442 ret = ldub_phys(cs->as, addr);
1443 break;
1444 case 2:
1445 ret = lduw_phys(cs->as, addr);
1446 break;
1447 case 4:
1448 ret = ldl_phys(cs->as, addr);
1449 break;
1450 default:
1451 case 8:
1452 ret = ldq_phys(cs->as, addr);
1453 break;
1454 }
1455 break;
1456 }
1457 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1458 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1459 Only ldda allowed */
1460 helper_raise_exception(env, TT_ILL_INSN);
1461 return 0;
1462 case 0x04: /* Nucleus */
1463 case 0x0c: /* Nucleus Little Endian (LE) */
1464 {
1465 switch (size) {
1466 case 1:
1467 ret = cpu_ldub_nucleus(env, addr);
1468 break;
1469 case 2:
1470 ret = cpu_lduw_nucleus(env, addr);
1471 break;
1472 case 4:
1473 ret = cpu_ldl_nucleus(env, addr);
1474 break;
1475 default:
1476 case 8:
1477 ret = cpu_ldq_nucleus(env, addr);
1478 break;
1479 }
1480 break;
1481 }
1482 case 0x4a: /* UPA config */
1483 /* XXX */
1484 break;
1485 case 0x45: /* LSU */
1486 ret = env->lsu;
1487 break;
1488 case 0x50: /* I-MMU regs */
1489 {
1490 int reg = (addr >> 3) & 0xf;
1491
1492 if (reg == 0) {
1493 /* I-TSB Tag Target register */
1494 ret = ultrasparc_tag_target(env->immu.tag_access);
1495 } else {
1496 ret = env->immuregs[reg];
1497 }
1498
1499 break;
1500 }
1501 case 0x51: /* I-MMU 8k TSB pointer */
1502 {
1503 /* env->immuregs[5] holds I-MMU TSB register value
1504 env->immuregs[6] holds I-MMU Tag Access register value */
1505 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1506 8*1024);
1507 break;
1508 }
1509 case 0x52: /* I-MMU 64k TSB pointer */
1510 {
1511 /* env->immuregs[5] holds I-MMU TSB register value
1512 env->immuregs[6] holds I-MMU Tag Access register value */
1513 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1514 64*1024);
1515 break;
1516 }
1517 case 0x55: /* I-MMU data access */
1518 {
1519 int reg = (addr >> 3) & 0x3f;
1520
1521 ret = env->itlb[reg].tte;
1522 break;
1523 }
1524 case 0x56: /* I-MMU tag read */
1525 {
1526 int reg = (addr >> 3) & 0x3f;
1527
1528 ret = env->itlb[reg].tag;
1529 break;
1530 }
1531 case 0x58: /* D-MMU regs */
1532 {
1533 int reg = (addr >> 3) & 0xf;
1534
1535 if (reg == 0) {
1536 /* D-TSB Tag Target register */
1537 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1538 } else {
1539 ret = env->dmmuregs[reg];
1540 }
1541 break;
1542 }
1543 case 0x59: /* D-MMU 8k TSB pointer */
1544 {
1545 /* env->dmmuregs[5] holds D-MMU TSB register value
1546 env->dmmuregs[6] holds D-MMU Tag Access register value */
1547 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1548 8*1024);
1549 break;
1550 }
1551 case 0x5a: /* D-MMU 64k TSB pointer */
1552 {
1553 /* env->dmmuregs[5] holds D-MMU TSB register value
1554 env->dmmuregs[6] holds D-MMU Tag Access register value */
1555 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1556 64*1024);
1557 break;
1558 }
1559 case 0x5d: /* D-MMU data access */
1560 {
1561 int reg = (addr >> 3) & 0x3f;
1562
1563 ret = env->dtlb[reg].tte;
1564 break;
1565 }
1566 case 0x5e: /* D-MMU tag read */
1567 {
1568 int reg = (addr >> 3) & 0x3f;
1569
1570 ret = env->dtlb[reg].tag;
1571 break;
1572 }
1573 case 0x48: /* Interrupt dispatch, RO */
1574 break;
1575 case 0x49: /* Interrupt data receive */
1576 ret = env->ivec_status;
1577 break;
1578 case 0x7f: /* Incoming interrupt vector, RO */
1579 {
1580 int reg = (addr >> 4) & 0x3;
1581 if (reg < 3) {
1582 ret = env->ivec_data[reg];
1583 }
1584 break;
1585 }
1586 case 0x46: /* D-cache data */
1587 case 0x47: /* D-cache tag access */
1588 case 0x4b: /* E-cache error enable */
1589 case 0x4c: /* E-cache asynchronous fault status */
1590 case 0x4d: /* E-cache asynchronous fault address */
1591 case 0x4e: /* E-cache tag data */
1592 case 0x66: /* I-cache instruction access */
1593 case 0x67: /* I-cache tag access */
1594 case 0x6e: /* I-cache predecode */
1595 case 0x6f: /* I-cache LRU etc. */
1596 case 0x76: /* E-cache tag */
1597 case 0x7e: /* E-cache tag */
1598 break;
1599 case 0x5b: /* D-MMU data pointer */
1600 case 0x54: /* I-MMU data in, WO */
1601 case 0x57: /* I-MMU demap, WO */
1602 case 0x5c: /* D-MMU data in, WO */
1603 case 0x5f: /* D-MMU demap, WO */
1604 case 0x77: /* Interrupt vector, WO */
1605 default:
1606 cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
1607 addr, false, false, 1, size);
1608 ret = 0;
1609 break;
1610 }
1611
1612 /* Convert from little endian */
1613 switch (asi) {
1614 case 0x0c: /* Nucleus Little Endian (LE) */
1615 case 0x18: /* As if user primary LE */
1616 case 0x19: /* As if user secondary LE */
1617 case 0x1c: /* Bypass LE */
1618 case 0x1d: /* Bypass, non-cacheable LE */
1619 case 0x88: /* Primary LE */
1620 case 0x89: /* Secondary LE */
1621 switch(size) {
1622 case 2:
1623 ret = bswap16(ret);
1624 break;
1625 case 4:
1626 ret = bswap32(ret);
1627 break;
1628 case 8:
1629 ret = bswap64(ret);
1630 break;
1631 default:
1632 break;
1633 }
1634 default:
1635 break;
1636 }
1637
1638 /* Convert to signed number */
1639 if (sign) {
1640 switch (size) {
1641 case 1:
1642 ret = (int8_t) ret;
1643 break;
1644 case 2:
1645 ret = (int16_t) ret;
1646 break;
1647 case 4:
1648 ret = (int32_t) ret;
1649 break;
1650 default:
1651 break;
1652 }
1653 }
1654 #ifdef DEBUG_ASI
1655 dump_asi("read ", last_addr, asi, size, ret);
1656 #endif
1657 return ret;
1658 }
1659
1660 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1661 int asi, int size)
1662 {
1663 CPUState *cs = ENV_GET_CPU(env);
1664 #ifdef DEBUG_ASI
1665 dump_asi("write", addr, asi, size, val);
1666 #endif
1667
1668 asi &= 0xff;
1669
1670 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1671 || (cpu_has_hypervisor(env)
1672 && asi >= 0x30 && asi < 0x80
1673 && !(env->hpstate & HS_PRIV))) {
1674 helper_raise_exception(env, TT_PRIV_ACT);
1675 }
1676
1677 helper_check_align(env, addr, size - 1);
1678 addr = asi_address_mask(env, asi, addr);
1679
1680 /* Convert to little endian */
1681 switch (asi) {
1682 case 0x0c: /* Nucleus Little Endian (LE) */
1683 case 0x18: /* As if user primary LE */
1684 case 0x19: /* As if user secondary LE */
1685 case 0x1c: /* Bypass LE */
1686 case 0x1d: /* Bypass, non-cacheable LE */
1687 case 0x88: /* Primary LE */
1688 case 0x89: /* Secondary LE */
1689 switch (size) {
1690 case 2:
1691 val = bswap16(val);
1692 break;
1693 case 4:
1694 val = bswap32(val);
1695 break;
1696 case 8:
1697 val = bswap64(val);
1698 break;
1699 default:
1700 break;
1701 }
1702 default:
1703 break;
1704 }
1705
1706 switch (asi) {
1707 case 0x10: /* As if user primary */
1708 case 0x11: /* As if user secondary */
1709 case 0x18: /* As if user primary LE */
1710 case 0x19: /* As if user secondary LE */
1711 case 0x80: /* Primary */
1712 case 0x81: /* Secondary */
1713 case 0x88: /* Primary LE */
1714 case 0x89: /* Secondary LE */
1715 case 0xe2: /* UA2007 Primary block init */
1716 case 0xe3: /* UA2007 Secondary block init */
1717 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1718 if (cpu_hypervisor_mode(env)) {
1719 switch (size) {
1720 case 1:
1721 cpu_stb_hypv(env, addr, val);
1722 break;
1723 case 2:
1724 cpu_stw_hypv(env, addr, val);
1725 break;
1726 case 4:
1727 cpu_stl_hypv(env, addr, val);
1728 break;
1729 case 8:
1730 default:
1731 cpu_stq_hypv(env, addr, val);
1732 break;
1733 }
1734 } else {
1735 /* secondary space access has lowest asi bit equal to 1 */
1736 if (asi & 1) {
1737 switch (size) {
1738 case 1:
1739 cpu_stb_kernel_secondary(env, addr, val);
1740 break;
1741 case 2:
1742 cpu_stw_kernel_secondary(env, addr, val);
1743 break;
1744 case 4:
1745 cpu_stl_kernel_secondary(env, addr, val);
1746 break;
1747 case 8:
1748 default:
1749 cpu_stq_kernel_secondary(env, addr, val);
1750 break;
1751 }
1752 } else {
1753 switch (size) {
1754 case 1:
1755 cpu_stb_kernel(env, addr, val);
1756 break;
1757 case 2:
1758 cpu_stw_kernel(env, addr, val);
1759 break;
1760 case 4:
1761 cpu_stl_kernel(env, addr, val);
1762 break;
1763 case 8:
1764 default:
1765 cpu_stq_kernel(env, addr, val);
1766 break;
1767 }
1768 }
1769 }
1770 } else {
1771 /* secondary space access has lowest asi bit equal to 1 */
1772 if (asi & 1) {
1773 switch (size) {
1774 case 1:
1775 cpu_stb_user_secondary(env, addr, val);
1776 break;
1777 case 2:
1778 cpu_stw_user_secondary(env, addr, val);
1779 break;
1780 case 4:
1781 cpu_stl_user_secondary(env, addr, val);
1782 break;
1783 case 8:
1784 default:
1785 cpu_stq_user_secondary(env, addr, val);
1786 break;
1787 }
1788 } else {
1789 switch (size) {
1790 case 1:
1791 cpu_stb_user(env, addr, val);
1792 break;
1793 case 2:
1794 cpu_stw_user(env, addr, val);
1795 break;
1796 case 4:
1797 cpu_stl_user(env, addr, val);
1798 break;
1799 case 8:
1800 default:
1801 cpu_stq_user(env, addr, val);
1802 break;
1803 }
1804 }
1805 }
1806 break;
1807 case 0x14: /* Bypass */
1808 case 0x15: /* Bypass, non-cacheable */
1809 case 0x1c: /* Bypass LE */
1810 case 0x1d: /* Bypass, non-cacheable LE */
1811 {
1812 switch (size) {
1813 case 1:
1814 stb_phys(cs->as, addr, val);
1815 break;
1816 case 2:
1817 stw_phys(cs->as, addr, val);
1818 break;
1819 case 4:
1820 stl_phys(cs->as, addr, val);
1821 break;
1822 case 8:
1823 default:
1824 stq_phys(cs->as, addr, val);
1825 break;
1826 }
1827 }
1828 return;
1829 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1830 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1831 Only ldda allowed */
1832 helper_raise_exception(env, TT_ILL_INSN);
1833 return;
1834 case 0x04: /* Nucleus */
1835 case 0x0c: /* Nucleus Little Endian (LE) */
1836 {
1837 switch (size) {
1838 case 1:
1839 cpu_stb_nucleus(env, addr, val);
1840 break;
1841 case 2:
1842 cpu_stw_nucleus(env, addr, val);
1843 break;
1844 case 4:
1845 cpu_stl_nucleus(env, addr, val);
1846 break;
1847 default:
1848 case 8:
1849 cpu_stq_nucleus(env, addr, val);
1850 break;
1851 }
1852 break;
1853 }
1854
1855 case 0x4a: /* UPA config */
1856 /* XXX */
1857 return;
1858 case 0x45: /* LSU */
1859 {
1860 uint64_t oldreg;
1861
1862 oldreg = env->lsu;
1863 env->lsu = val & (DMMU_E | IMMU_E);
1864 /* Mappings generated during D/I MMU disabled mode are
1865 invalid in normal mode */
1866 if (oldreg != env->lsu) {
1867 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1868 oldreg, env->lsu);
1869 #ifdef DEBUG_MMU
1870 dump_mmu(stdout, fprintf, env);
1871 #endif
1872 tlb_flush(env, 1);
1873 }
1874 return;
1875 }
1876 case 0x50: /* I-MMU regs */
1877 {
1878 int reg = (addr >> 3) & 0xf;
1879 uint64_t oldreg;
1880
1881 oldreg = env->immuregs[reg];
1882 switch (reg) {
1883 case 0: /* RO */
1884 return;
1885 case 1: /* Not in I-MMU */
1886 case 2:
1887 return;
1888 case 3: /* SFSR */
1889 if ((val & 1) == 0) {
1890 val = 0; /* Clear SFSR */
1891 }
1892 env->immu.sfsr = val;
1893 break;
1894 case 4: /* RO */
1895 return;
1896 case 5: /* TSB access */
1897 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1898 PRIx64 "\n", env->immu.tsb, val);
1899 env->immu.tsb = val;
1900 break;
1901 case 6: /* Tag access */
1902 env->immu.tag_access = val;
1903 break;
1904 case 7:
1905 case 8:
1906 return;
1907 default:
1908 break;
1909 }
1910
1911 if (oldreg != env->immuregs[reg]) {
1912 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1913 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1914 }
1915 #ifdef DEBUG_MMU
1916 dump_mmu(stdout, fprintf, env);
1917 #endif
1918 return;
1919 }
1920 case 0x54: /* I-MMU data in */
1921 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1922 return;
1923 case 0x55: /* I-MMU data access */
1924 {
1925 /* TODO: auto demap */
1926
1927 unsigned int i = (addr >> 3) & 0x3f;
1928
1929 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1930
1931 #ifdef DEBUG_MMU
1932 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1933 dump_mmu(stdout, fprintf, env);
1934 #endif
1935 return;
1936 }
1937 case 0x57: /* I-MMU demap */
1938 demap_tlb(env->itlb, addr, "immu", env);
1939 return;
1940 case 0x58: /* D-MMU regs */
1941 {
1942 int reg = (addr >> 3) & 0xf;
1943 uint64_t oldreg;
1944
1945 oldreg = env->dmmuregs[reg];
1946 switch (reg) {
1947 case 0: /* RO */
1948 case 4:
1949 return;
1950 case 3: /* SFSR */
1951 if ((val & 1) == 0) {
1952 val = 0; /* Clear SFSR, Fault address */
1953 env->dmmu.sfar = 0;
1954 }
1955 env->dmmu.sfsr = val;
1956 break;
1957 case 1: /* Primary context */
1958 env->dmmu.mmu_primary_context = val;
1959 /* can be optimized to only flush MMU_USER_IDX
1960 and MMU_KERNEL_IDX entries */
1961 tlb_flush(env, 1);
1962 break;
1963 case 2: /* Secondary context */
1964 env->dmmu.mmu_secondary_context = val;
1965 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1966 and MMU_KERNEL_SECONDARY_IDX entries */
1967 tlb_flush(env, 1);
1968 break;
1969 case 5: /* TSB access */
1970 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1971 PRIx64 "\n", env->dmmu.tsb, val);
1972 env->dmmu.tsb = val;
1973 break;
1974 case 6: /* Tag access */
1975 env->dmmu.tag_access = val;
1976 break;
1977 case 7: /* Virtual Watchpoint */
1978 case 8: /* Physical Watchpoint */
1979 default:
1980 env->dmmuregs[reg] = val;
1981 break;
1982 }
1983
1984 if (oldreg != env->dmmuregs[reg]) {
1985 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1986 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1987 }
1988 #ifdef DEBUG_MMU
1989 dump_mmu(stdout, fprintf, env);
1990 #endif
1991 return;
1992 }
1993 case 0x5c: /* D-MMU data in */
1994 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1995 return;
1996 case 0x5d: /* D-MMU data access */
1997 {
1998 unsigned int i = (addr >> 3) & 0x3f;
1999
2000 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
2001
2002 #ifdef DEBUG_MMU
2003 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
2004 dump_mmu(stdout, fprintf, env);
2005 #endif
2006 return;
2007 }
2008 case 0x5f: /* D-MMU demap */
2009 demap_tlb(env->dtlb, addr, "dmmu", env);
2010 return;
2011 case 0x49: /* Interrupt data receive */
2012 env->ivec_status = val & 0x20;
2013 return;
2014 case 0x46: /* D-cache data */
2015 case 0x47: /* D-cache tag access */
2016 case 0x4b: /* E-cache error enable */
2017 case 0x4c: /* E-cache asynchronous fault status */
2018 case 0x4d: /* E-cache asynchronous fault address */
2019 case 0x4e: /* E-cache tag data */
2020 case 0x66: /* I-cache instruction access */
2021 case 0x67: /* I-cache tag access */
2022 case 0x6e: /* I-cache predecode */
2023 case 0x6f: /* I-cache LRU etc. */
2024 case 0x76: /* E-cache tag */
2025 case 0x7e: /* E-cache tag */
2026 return;
2027 case 0x51: /* I-MMU 8k TSB pointer, RO */
2028 case 0x52: /* I-MMU 64k TSB pointer, RO */
2029 case 0x56: /* I-MMU tag read, RO */
2030 case 0x59: /* D-MMU 8k TSB pointer, RO */
2031 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2032 case 0x5b: /* D-MMU data pointer, RO */
2033 case 0x5e: /* D-MMU tag read, RO */
2034 case 0x48: /* Interrupt dispatch, RO */
2035 case 0x7f: /* Incoming interrupt vector, RO */
2036 case 0x82: /* Primary no-fault, RO */
2037 case 0x83: /* Secondary no-fault, RO */
2038 case 0x8a: /* Primary no-fault LE, RO */
2039 case 0x8b: /* Secondary no-fault LE, RO */
2040 default:
2041 cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
2042 addr, true, false, 1, size);
2043 return;
2044 }
2045 }
2046 #endif /* CONFIG_USER_ONLY */
2047
2048 void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi, int rd)
2049 {
2050 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2051 || (cpu_has_hypervisor(env)
2052 && asi >= 0x30 && asi < 0x80
2053 && !(env->hpstate & HS_PRIV))) {
2054 helper_raise_exception(env, TT_PRIV_ACT);
2055 }
2056
2057 addr = asi_address_mask(env, asi, addr);
2058
2059 switch (asi) {
2060 #if !defined(CONFIG_USER_ONLY)
2061 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2062 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2063 helper_check_align(env, addr, 0xf);
2064 if (rd == 0) {
2065 env->gregs[1] = cpu_ldq_nucleus(env, addr + 8);
2066 if (asi == 0x2c) {
2067 bswap64s(&env->gregs[1]);
2068 }
2069 } else if (rd < 8) {
2070 env->gregs[rd] = cpu_ldq_nucleus(env, addr);
2071 env->gregs[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2072 if (asi == 0x2c) {
2073 bswap64s(&env->gregs[rd]);
2074 bswap64s(&env->gregs[rd + 1]);
2075 }
2076 } else {
2077 env->regwptr[rd] = cpu_ldq_nucleus(env, addr);
2078 env->regwptr[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2079 if (asi == 0x2c) {
2080 bswap64s(&env->regwptr[rd]);
2081 bswap64s(&env->regwptr[rd + 1]);
2082 }
2083 }
2084 break;
2085 #endif
2086 default:
2087 helper_check_align(env, addr, 0x3);
2088 if (rd == 0) {
2089 env->gregs[1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2090 } else if (rd < 8) {
2091 env->gregs[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2092 env->gregs[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2093 } else {
2094 env->regwptr[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2095 env->regwptr[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2096 }
2097 break;
2098 }
2099 }
2100
2101 void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2102 int rd)
2103 {
2104 unsigned int i;
2105 target_ulong val;
2106
2107 helper_check_align(env, addr, 3);
2108 addr = asi_address_mask(env, asi, addr);
2109
2110 switch (asi) {
2111 case 0xf0: /* UA2007/JPS1 Block load primary */
2112 case 0xf1: /* UA2007/JPS1 Block load secondary */
2113 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2114 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2115 if (rd & 7) {
2116 helper_raise_exception(env, TT_ILL_INSN);
2117 return;
2118 }
2119 helper_check_align(env, addr, 0x3f);
2120 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2121 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0);
2122 }
2123 return;
2124
2125 case 0x16: /* UA2007 Block load primary, user privilege */
2126 case 0x17: /* UA2007 Block load secondary, user privilege */
2127 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2128 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2129 case 0x70: /* JPS1 Block load primary, user privilege */
2130 case 0x71: /* JPS1 Block load secondary, user privilege */
2131 case 0x78: /* JPS1 Block load primary LE, user privilege */
2132 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2133 if (rd & 7) {
2134 helper_raise_exception(env, TT_ILL_INSN);
2135 return;
2136 }
2137 helper_check_align(env, addr, 0x3f);
2138 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2139 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
2140 }
2141 return;
2142
2143 default:
2144 break;
2145 }
2146
2147 switch (size) {
2148 default:
2149 case 4:
2150 val = helper_ld_asi(env, addr, asi, size, 0);
2151 if (rd & 1) {
2152 env->fpr[rd / 2].l.lower = val;
2153 } else {
2154 env->fpr[rd / 2].l.upper = val;
2155 }
2156 break;
2157 case 8:
2158 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0);
2159 break;
2160 case 16:
2161 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0);
2162 env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0);
2163 break;
2164 }
2165 }
2166
2167 void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2168 int rd)
2169 {
2170 unsigned int i;
2171 target_ulong val;
2172
2173 helper_check_align(env, addr, 3);
2174 addr = asi_address_mask(env, asi, addr);
2175
2176 switch (asi) {
2177 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2178 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2179 case 0xf0: /* UA2007/JPS1 Block store primary */
2180 case 0xf1: /* UA2007/JPS1 Block store secondary */
2181 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2182 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2183 if (rd & 7) {
2184 helper_raise_exception(env, TT_ILL_INSN);
2185 return;
2186 }
2187 helper_check_align(env, addr, 0x3f);
2188 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2189 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8);
2190 }
2191
2192 return;
2193 case 0x16: /* UA2007 Block load primary, user privilege */
2194 case 0x17: /* UA2007 Block load secondary, user privilege */
2195 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2196 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2197 case 0x70: /* JPS1 Block store primary, user privilege */
2198 case 0x71: /* JPS1 Block store secondary, user privilege */
2199 case 0x78: /* JPS1 Block load primary LE, user privilege */
2200 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2201 if (rd & 7) {
2202 helper_raise_exception(env, TT_ILL_INSN);
2203 return;
2204 }
2205 helper_check_align(env, addr, 0x3f);
2206 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2207 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
2208 }
2209
2210 return;
2211 default:
2212 break;
2213 }
2214
2215 switch (size) {
2216 default:
2217 case 4:
2218 if (rd & 1) {
2219 val = env->fpr[rd / 2].l.lower;
2220 } else {
2221 val = env->fpr[rd / 2].l.upper;
2222 }
2223 helper_st_asi(env, addr, val, asi, size);
2224 break;
2225 case 8:
2226 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size);
2227 break;
2228 case 16:
2229 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8);
2230 helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8);
2231 break;
2232 }
2233 }
2234
2235 target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
2236 target_ulong val1, target_ulong val2, uint32_t asi)
2237 {
2238 target_ulong ret;
2239
2240 val2 &= 0xffffffffUL;
2241 ret = helper_ld_asi(env, addr, asi, 4, 0);
2242 ret &= 0xffffffffUL;
2243 if (val2 == ret) {
2244 helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
2245 }
2246 return ret;
2247 }
2248
2249 target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
2250 target_ulong val1, target_ulong val2,
2251 uint32_t asi)
2252 {
2253 target_ulong ret;
2254
2255 ret = helper_ld_asi(env, addr, asi, 8, 0);
2256 if (val2 == ret) {
2257 helper_st_asi(env, addr, val1, asi, 8);
2258 }
2259 return ret;
2260 }
2261 #endif /* TARGET_SPARC64 */
2262
2263 void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2264 {
2265 /* XXX add 128 bit load */
2266 CPU_QuadU u;
2267
2268 helper_check_align(env, addr, 7);
2269 #if !defined(CONFIG_USER_ONLY)
2270 switch (mem_idx) {
2271 case MMU_USER_IDX:
2272 u.ll.upper = cpu_ldq_user(env, addr);
2273 u.ll.lower = cpu_ldq_user(env, addr + 8);
2274 QT0 = u.q;
2275 break;
2276 case MMU_KERNEL_IDX:
2277 u.ll.upper = cpu_ldq_kernel(env, addr);
2278 u.ll.lower = cpu_ldq_kernel(env, addr + 8);
2279 QT0 = u.q;
2280 break;
2281 #ifdef TARGET_SPARC64
2282 case MMU_HYPV_IDX:
2283 u.ll.upper = cpu_ldq_hypv(env, addr);
2284 u.ll.lower = cpu_ldq_hypv(env, addr + 8);
2285 QT0 = u.q;
2286 break;
2287 #endif
2288 default:
2289 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2290 break;
2291 }
2292 #else
2293 u.ll.upper = ldq_raw(address_mask(env, addr));
2294 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
2295 QT0 = u.q;
2296 #endif
2297 }
2298
2299 void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2300 {
2301 /* XXX add 128 bit store */
2302 CPU_QuadU u;
2303
2304 helper_check_align(env, addr, 7);
2305 #if !defined(CONFIG_USER_ONLY)
2306 switch (mem_idx) {
2307 case MMU_USER_IDX:
2308 u.q = QT0;
2309 cpu_stq_user(env, addr, u.ll.upper);
2310 cpu_stq_user(env, addr + 8, u.ll.lower);
2311 break;
2312 case MMU_KERNEL_IDX:
2313 u.q = QT0;
2314 cpu_stq_kernel(env, addr, u.ll.upper);
2315 cpu_stq_kernel(env, addr + 8, u.ll.lower);
2316 break;
2317 #ifdef TARGET_SPARC64
2318 case MMU_HYPV_IDX:
2319 u.q = QT0;
2320 cpu_stq_hypv(env, addr, u.ll.upper);
2321 cpu_stq_hypv(env, addr + 8, u.ll.lower);
2322 break;
2323 #endif
2324 default:
2325 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2326 break;
2327 }
2328 #else
2329 u.q = QT0;
2330 stq_raw(address_mask(env, addr), u.ll.upper);
2331 stq_raw(address_mask(env, addr + 8), u.ll.lower);
2332 #endif
2333 }
2334
2335 #if !defined(CONFIG_USER_ONLY)
2336 #ifndef TARGET_SPARC64
2337 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2338 bool is_write, bool is_exec, int is_asi,
2339 unsigned size)
2340 {
2341 SPARCCPU *cpu = SPARC_CPU(cs);
2342 CPUSPARCState *env = &cpu->env;
2343 int fault_type;
2344
2345 #ifdef DEBUG_UNASSIGNED
2346 if (is_asi) {
2347 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2348 " asi 0x%02x from " TARGET_FMT_lx "\n",
2349 is_exec ? "exec" : is_write ? "write" : "read", size,
2350 size == 1 ? "" : "s", addr, is_asi, env->pc);
2351 } else {
2352 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2353 " from " TARGET_FMT_lx "\n",
2354 is_exec ? "exec" : is_write ? "write" : "read", size,
2355 size == 1 ? "" : "s", addr, env->pc);
2356 }
2357 #endif
2358 /* Don't overwrite translation and access faults */
2359 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2360 if ((fault_type > 4) || (fault_type == 0)) {
2361 env->mmuregs[3] = 0; /* Fault status register */
2362 if (is_asi) {
2363 env->mmuregs[3] |= 1 << 16;
2364 }
2365 if (env->psrs) {
2366 env->mmuregs[3] |= 1 << 5;
2367 }
2368 if (is_exec) {
2369 env->mmuregs[3] |= 1 << 6;
2370 }
2371 if (is_write) {
2372 env->mmuregs[3] |= 1 << 7;
2373 }
2374 env->mmuregs[3] |= (5 << 2) | 2;
2375 /* SuperSPARC will never place instruction fault addresses in the FAR */
2376 if (!is_exec) {
2377 env->mmuregs[4] = addr; /* Fault address register */
2378 }
2379 }
2380 /* overflow (same type fault was not read before another fault) */
2381 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2382 env->mmuregs[3] |= 1;
2383 }
2384
2385 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2386 if (is_exec) {
2387 helper_raise_exception(env, TT_CODE_ACCESS);
2388 } else {
2389 helper_raise_exception(env, TT_DATA_ACCESS);
2390 }
2391 }
2392
2393 /* flush neverland mappings created during no-fault mode,
2394 so the sequential MMU faults report proper fault types */
2395 if (env->mmuregs[0] & MMU_NF) {
2396 tlb_flush(env, 1);
2397 }
2398 }
2399 #else
2400 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2401 bool is_write, bool is_exec, int is_asi,
2402 unsigned size)
2403 {
2404 SPARCCPU *cpu = SPARC_CPU(cs);
2405 CPUSPARCState *env = &cpu->env;
2406
2407 #ifdef DEBUG_UNASSIGNED
2408 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2409 "\n", addr, env->pc);
2410 #endif
2411
2412 if (is_exec) {
2413 helper_raise_exception(env, TT_CODE_ACCESS);
2414 } else {
2415 helper_raise_exception(env, TT_DATA_ACCESS);
2416 }
2417 }
2418 #endif
2419 #endif
2420
2421 #if !defined(CONFIG_USER_ONLY)
2422 static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
2423 target_ulong addr, int is_write,
2424 int is_user, uintptr_t retaddr)
2425 {
2426 #ifdef DEBUG_UNALIGNED
2427 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2428 "\n", addr, env->pc);
2429 #endif
2430 if (retaddr) {
2431 cpu_restore_state(env, retaddr);
2432 }
2433 helper_raise_exception(env, TT_UNALIGNED);
2434 }
2435
2436 /* try to fill the TLB and return an exception if error. If retaddr is
2437 NULL, it means that the function was called in C code (i.e. not
2438 from generated code or from helper.c) */
2439 /* XXX: fix it to restore all registers */
2440 void tlb_fill(CPUSPARCState *env, target_ulong addr, int is_write, int mmu_idx,
2441 uintptr_t retaddr)
2442 {
2443 int ret;
2444
2445 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx);
2446 if (ret) {
2447 if (retaddr) {
2448 cpu_restore_state(env, retaddr);
2449 }
2450 cpu_loop_exit(env);
2451 }
2452 }
2453 #endif
AR7 emulation for QEMU