hw/riscv/sifive_u.c

   1 /*
   2  * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017 SiFive, Inc.
   6  *
   7  * Provides a board compatible with the SiFive Freedom U SDK:
   8  *
   9  * 0) UART
  10  * 1) CLINT (Core Level Interruptor)
  11  * 2) PLIC (Platform Level Interrupt Controller)
  12  *
  13  * This board currently uses a hardcoded devicetree that indicates one hart.
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms and conditions of the GNU General Public License,
  17  * version 2 or later, as published by the Free Software Foundation.
  18  *
  19  * This program is distributed in the hope it will be useful, but WITHOUT
  20  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  21  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  22  * more details.
  23  *
  24  * You should have received a copy of the GNU General Public License along with
  25  * this program.  If not, see <http://www.gnu.org/licenses/>.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qemu/log.h"
  30 #include "qemu/error-report.h"
  31 #include "qapi/error.h"
  32 #include "hw/hw.h"
  33 #include "hw/boards.h"
  34 #include "hw/loader.h"
  35 #include "hw/sysbus.h"
  36 #include "hw/char/serial.h"
  37 #include "target/riscv/cpu.h"
  38 #include "hw/riscv/riscv_hart.h"
  39 #include "hw/riscv/sifive_plic.h"
  40 #include "hw/riscv/sifive_clint.h"
  41 #include "hw/riscv/sifive_uart.h"
  42 #include "hw/riscv/sifive_prci.h"
  43 #include "hw/riscv/sifive_u.h"
  44 #include "chardev/char.h"
  45 #include "sysemu/arch_init.h"
  46 #include "sysemu/device_tree.h"
  47 #include "exec/address-spaces.h"
  48 #include "elf.h"
  49
  50 #include <libfdt.h>
  51
  52 static const struct MemmapEntry {
  53     hwaddr base;
  54     hwaddr size;
  55 } sifive_u_memmap[] = {
  56     [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
  57     [SIFIVE_U_MROM] =     {     0x1000,    0x11000 },
  58     [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
  59     [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
  60     [SIFIVE_U_UART0] =    { 0x10013000,     0x1000 },
  61     [SIFIVE_U_UART1] =    { 0x10023000,     0x1000 },
  62     [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
  63     [SIFIVE_U_GEM] =      { 0x100900FC,     0x2000 },
  64 };
  65
  66 #define GEM_REVISION        0x10070109
  67
  68 static uint64_t load_kernel(const char *kernel_filename)
  69 {
  70     uint64_t kernel_entry, kernel_high;
  71
  72     if (load_elf(kernel_filename, NULL, NULL,
  73                  &kernel_entry, NULL, &kernel_high,
  74                  0, EM_RISCV, 1, 0) < 0) {
  75         error_report("could not load kernel '%s'", kernel_filename);
  76         exit(1);
  77     }
  78     return kernel_entry;
  79 }
  80
  81 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
  82     uint64_t mem_size, const char *cmdline)
  83 {
  84     void *fdt;
  85     int cpu;
  86     uint32_t *cells;
  87     char *nodename;
  88     uint32_t plic_phandle;
  89
  90     fdt = s->fdt = create_device_tree(&s->fdt_size);
  91     if (!fdt) {
  92         error_report("create_device_tree() failed");
  93         exit(1);
  94     }
  95
  96     qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
  97     qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
  98     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
  99     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 100
 101     qemu_fdt_add_subnode(fdt, "/soc");
 102     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 103     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
 104     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 105     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 106
 107     nodename = g_strdup_printf("/memory@%lx",
 108         (long)memmap[SIFIVE_U_DRAM].base);
 109     qemu_fdt_add_subnode(fdt, nodename);
 110     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 111         memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
 112         mem_size >> 32, mem_size);
 113     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 114     g_free(nodename);
 115
 116     qemu_fdt_add_subnode(fdt, "/cpus");
 117     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 118         SIFIVE_CLINT_TIMEBASE_FREQ);
 119     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 120     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 121
 122     for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) {
 123         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 124         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 125         char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]);
 126         qemu_fdt_add_subnode(fdt, nodename);
 127         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 128                               SIFIVE_U_CLOCK_FREQ);
 129         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 130         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 131         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 132         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 133         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 134         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 135         qemu_fdt_add_subnode(fdt, intc);
 136         qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
 137         qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
 138         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 139         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 140         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 141         g_free(isa);
 142         g_free(intc);
 143         g_free(nodename);
 144     }
 145
 146     cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4);
 147     for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
 148         nodename =
 149             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 150         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 151         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 152         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 153         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 154         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 155         g_free(nodename);
 156     }
 157     nodename = g_strdup_printf("/soc/clint@%lx",
 158         (long)memmap[SIFIVE_U_CLINT].base);
 159     qemu_fdt_add_subnode(fdt, nodename);
 160     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 161     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 162         0x0, memmap[SIFIVE_U_CLINT].base,
 163         0x0, memmap[SIFIVE_U_CLINT].size);
 164     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 165         cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
 166     g_free(cells);
 167     g_free(nodename);
 168
 169     cells =  g_new0(uint32_t, s->soc.cpus.num_harts * 4);
 170     for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
 171         nodename =
 172             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 173         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 174         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 175         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 176         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 177         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 178         g_free(nodename);
 179     }
 180     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 181         (long)memmap[SIFIVE_U_PLIC].base);
 182     qemu_fdt_add_subnode(fdt, nodename);
 183     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 184     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 185     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 186     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 187         cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
 188     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 189         0x0, memmap[SIFIVE_U_PLIC].base,
 190         0x0, memmap[SIFIVE_U_PLIC].size);
 191     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 192     qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 193     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
 194     qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
 195     qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
 196     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 197     g_free(cells);
 198     g_free(nodename);
 199
 200     nodename = g_strdup_printf("/soc/ethernet@%lx",
 201         (long)memmap[SIFIVE_U_GEM].base);
 202     qemu_fdt_add_subnode(fdt, nodename);
 203     qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
 204     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 205         0x0, memmap[SIFIVE_U_GEM].base,
 206         0x0, memmap[SIFIVE_U_GEM].size);
 207     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 208     qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
 209     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
 210     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
 211     qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
 212     qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
 213     g_free(nodename);
 214
 215     nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
 216         (long)memmap[SIFIVE_U_GEM].base);
 217     qemu_fdt_add_subnode(fdt, nodename);
 218     qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
 219     g_free(nodename);
 220
 221     nodename = g_strdup_printf("/soc/uart@%lx",
 222         (long)memmap[SIFIVE_U_UART0].base);
 223     qemu_fdt_add_subnode(fdt, nodename);
 224     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
 225     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 226         0x0, memmap[SIFIVE_U_UART0].base,
 227         0x0, memmap[SIFIVE_U_UART0].size);
 228     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
 229     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);
 230
 231     qemu_fdt_add_subnode(fdt, "/chosen");
 232     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 233     qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 234     g_free(nodename);
 235 }
 236
 237 static void riscv_sifive_u_init(MachineState *machine)
 238 {
 239     const struct MemmapEntry *memmap = sifive_u_memmap;
 240
 241     SiFiveUState *s = g_new0(SiFiveUState, 1);
 242     MemoryRegion *system_memory = get_system_memory();
 243     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 244     int i;
 245
 246     /* Initialize SoC */
 247     object_initialize_child(OBJECT(machine), "soc", &s->soc,
 248                             sizeof(s->soc), TYPE_RISCV_U_SOC,
 249                             &error_abort, NULL);
 250     object_property_set_bool(OBJECT(&s->soc), true, "realized",
 251                             &error_abort);
 252
 253     /* register RAM */
 254     memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
 255                            machine->ram_size, &error_fatal);
 256     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
 257                                 main_mem);
 258
 259     /* create device tree */
 260     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 261
 262     if (machine->kernel_filename) {
 263         load_kernel(machine->kernel_filename);
 264     }
 265
 266     /* reset vector */
 267     uint32_t reset_vec[8] = {
 268         0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
 269         0x02028593,                    /*     addi   a1, t0, %pcrel_lo(1b) */
 270         0xf1402573,                    /*     csrr   a0, mhartid  */
 271 #if defined(TARGET_RISCV32)
 272         0x0182a283,                    /*     lw     t0, 24(t0) */
 273 #elif defined(TARGET_RISCV64)
 274         0x0182b283,                    /*     ld     t0, 24(t0) */
 275 #endif
 276         0x00028067,                    /*     jr     t0 */
 277         0x00000000,
 278         memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
 279         0x00000000,
 280                                        /* dtb: */
 281     };
 282
 283     /* copy in the reset vector in little_endian byte order */
 284     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 285         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 286     }
 287     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 288                           memmap[SIFIVE_U_MROM].base, &address_space_memory);
 289
 290     /* copy in the device tree */
 291     if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
 292             memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
 293         error_report("not enough space to store device-tree");
 294         exit(1);
 295     }
 296     qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
 297     rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
 298                           memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
 299                           &address_space_memory);
 300 }
 301
 302 static void riscv_sifive_u_soc_init(Object *obj)
 303 {
 304     SiFiveUSoCState *s = RISCV_U_SOC(obj);
 305
 306     object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
 307                             TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
 308     object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
 309                             &error_abort);
 310     object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
 311                             &error_abort);
 312
 313     sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
 314                           TYPE_CADENCE_GEM);
 315 }
 316
 317 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
 318 {
 319     SiFiveUSoCState *s = RISCV_U_SOC(dev);
 320     const struct MemmapEntry *memmap = sifive_u_memmap;
 321     MemoryRegion *system_memory = get_system_memory();
 322     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 323     qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
 324     int i;
 325     Error *err = NULL;
 326     NICInfo *nd = &nd_table[0];
 327
 328     object_property_set_bool(OBJECT(&s->cpus), true, "realized",
 329                              &error_abort);
 330
 331     /* boot rom */
 332     memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
 333                            memmap[SIFIVE_U_MROM].size, &error_fatal);
 334     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
 335                                 mask_rom);
 336
 337     /* MMIO */
 338     s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
 339         (char *)SIFIVE_U_PLIC_HART_CONFIG,
 340         SIFIVE_U_PLIC_NUM_SOURCES,
 341         SIFIVE_U_PLIC_NUM_PRIORITIES,
 342         SIFIVE_U_PLIC_PRIORITY_BASE,
 343         SIFIVE_U_PLIC_PENDING_BASE,
 344         SIFIVE_U_PLIC_ENABLE_BASE,
 345         SIFIVE_U_PLIC_ENABLE_STRIDE,
 346         SIFIVE_U_PLIC_CONTEXT_BASE,
 347         SIFIVE_U_PLIC_CONTEXT_STRIDE,
 348         memmap[SIFIVE_U_PLIC].size);
 349     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
 350         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
 351     /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
 352         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic),
 353                                        SIFIVE_U_UART1_IRQ)); */
 354     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
 355         memmap[SIFIVE_U_CLINT].size, smp_cpus,
 356         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 357
 358     for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
 359         plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
 360     }
 361
 362     if (nd->used) {
 363         qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 364         qdev_set_nic_properties(DEVICE(&s->gem), nd);
 365     }
 366     object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
 367                             &error_abort);
 368     object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
 369     if (err) {
 370         error_propagate(errp, err);
 371         return;
 372     }
 373     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
 374     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
 375                        plic_gpios[SIFIVE_U_GEM_IRQ]);
 376 }
 377
 378 static void riscv_sifive_u_machine_init(MachineClass *mc)
 379 {
 380     mc->desc = "RISC-V Board compatible with SiFive U SDK";
 381     mc->init = riscv_sifive_u_init;
 382     mc->max_cpus = 1;
 383 }
 384
 385 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
 386
 387 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
 388 {
 389     DeviceClass *dc = DEVICE_CLASS(oc);
 390
 391     dc->realize = riscv_sifive_u_soc_realize;
 392     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 393     dc->user_creatable = false;
 394 }
 395
 396 static const TypeInfo riscv_sifive_u_soc_type_info = {
 397     .name = TYPE_RISCV_U_SOC,
 398     .parent = TYPE_DEVICE,
 399     .instance_size = sizeof(SiFiveUSoCState),
 400     .instance_init = riscv_sifive_u_soc_init,
 401     .class_init = riscv_sifive_u_soc_class_init,
 402 };
 403
 404 static void riscv_sifive_u_soc_register_types(void)
 405 {
 406     type_register_static(&riscv_sifive_u_soc_type_info);
 407 }
 408
 409 type_init(riscv_sifive_u_soc_register_types)