4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>
26 #include "hw/isa/isa.h"
27 #include "hw/sysbus.h"
28 #include "hw/i386/pc.h"
29 #include "hw/isa/apm.h"
30 #include "hw/pci/pci.h"
31 #include "hw/pci/pcie_host.h"
32 #include "hw/acpi/acpi.h"
33 #include "hw/acpi/ich9.h"
34 #include "hw/pci-host/pam.h"
35 #include "hw/i386/intel_iommu.h"
37 #define TYPE_Q35_HOST_DEVICE "q35-pcihost"
38 #define Q35_HOST_DEVICE(obj) \
39 OBJECT_CHECK(Q35PCIHost, (obj), TYPE_Q35_HOST_DEVICE)
41 #define TYPE_MCH_PCI_DEVICE "mch"
42 #define MCH_PCI_DEVICE(obj) \
43 OBJECT_CHECK(MCHPCIState, (obj), TYPE_MCH_PCI_DEVICE)
45 typedef struct MCHPCIState
{
50 MemoryRegion
*ram_memory
;
51 MemoryRegion
*pci_address_space
;
52 MemoryRegion
*system_memory
;
53 MemoryRegion
*address_space_io
;
54 PAMMemoryRegion pam_regions
[13];
55 MemoryRegion smram_region
, open_high_smram
;
56 MemoryRegion smram
, low_smram
, high_smram
;
57 MemoryRegion tseg_blackhole
, tseg_window
;
59 uint64_t below_4g_mem_size
;
60 uint64_t above_4g_mem_size
;
61 uint64_t pci_hole64_size
;
62 uint32_t short_root_bus
;
63 uint16_t ext_tseg_mbytes
;
66 typedef struct Q35PCIHost
{
68 PCIExpressHost parent_obj
;
74 #define Q35_MASK(bit, ms_bit, ls_bit) \
75 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
81 #define MCH_HOST_PROP_RAM_MEM "ram-mem"
82 #define MCH_HOST_PROP_PCI_MEM "pci-mem"
83 #define MCH_HOST_PROP_SYSTEM_MEM "system-mem"
84 #define MCH_HOST_PROP_IO_MEM "io-mem"
86 /* PCI configuration */
87 #define MCH_HOST_BRIDGE "MCH"
89 #define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
90 #define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
92 /* D0:F0 configuration space */
93 #define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0
95 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES 0x50
96 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE 2
97 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff
98 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff
100 #define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */
101 #define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */
102 #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000
103 #define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */
104 #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28)
105 #define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26))
106 #define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25))
107 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1))
108 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1))
109 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1))
110 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1))
111 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1))
112 #define MCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
114 #define MCH_HOST_BRIDGE_PAM_NB 7
115 #define MCH_HOST_BRIDGE_PAM_SIZE 7
116 #define MCH_HOST_BRIDGE_PAM0 0x90
117 #define MCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000
118 #define MCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */
119 #define MCH_HOST_BRIDGE_PAM1 0x91
120 #define MCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000
121 #define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000
122 #define MCH_HOST_BRIDGE_PAM2 0x92
123 #define MCH_HOST_BRIDGE_PAM3 0x93
124 #define MCH_HOST_BRIDGE_PAM4 0x94
125 #define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000
126 #define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000
127 #define MCH_HOST_BRIDGE_PAM5 0x95
128 #define MCH_HOST_BRIDGE_PAM6 0x96
129 #define MCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4))
130 #define MCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4))
131 #define MCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4))
132 #define MCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2)
133 #define MCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1)
134 #define MCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3)
135 #define MCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2)
136 #define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
137 #define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
139 #define MCH_HOST_BRIDGE_SMRAM 0x9d
140 #define MCH_HOST_BRIDGE_SMRAM_SIZE 2
141 #define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
142 #define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
143 #define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4))
144 #define MCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3))
145 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
146 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
147 #define MCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000
148 #define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000
149 #define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000
150 #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
151 #define MCH_HOST_BRIDGE_SMRAM_DEFAULT \
152 MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG
153 #define MCH_HOST_BRIDGE_SMRAM_WMASK \
154 (MCH_HOST_BRIDGE_SMRAM_D_OPEN | \
155 MCH_HOST_BRIDGE_SMRAM_D_CLS | \
156 MCH_HOST_BRIDGE_SMRAM_D_LCK | \
157 MCH_HOST_BRIDGE_SMRAM_G_SMRAME)
158 #define MCH_HOST_BRIDGE_SMRAM_WMASK_LCK \
159 MCH_HOST_BRIDGE_SMRAM_D_CLS
161 #define MCH_HOST_BRIDGE_ESMRAMC 0x9e
162 #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7))
163 #define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 6))
164 #define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 5))
165 #define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 4))
166 #define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 3))
167 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
168 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
169 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
170 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
171 #define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1)
172 #define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \
173 (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \
174 MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \
175 MCH_HOST_BRIDGE_ESMRAMC_SM_L2)
176 #define MCH_HOST_BRIDGE_ESMRAMC_WMASK \
177 (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \
178 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \
179 MCH_HOST_BRIDGE_ESMRAMC_T_EN)
180 #define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK 0
182 /* D1:F0 PCIE* port*/
183 #define MCH_PCIE_DEV 1
184 #define MCH_PCIE_FUNC 0
186 uint64_t mch_mcfg_base(void);
189 * Arbitrary but unique BNF number for IOAPIC device.
191 * TODO: make sure there would have no conflict with real PCI bus
193 #define Q35_PSEUDO_BUS_PLATFORM (0xff)
194 #define Q35_PSEUDO_DEVFN_IOAPIC (0x00)
196 #endif /* HW_Q35_H */