4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
29 #include "libqos/libqos-pc.h"
30 #include "libqos/ahci.h"
31 #include "libqos/pci-pc.h"
33 #include "qemu-common.h"
34 #include "qemu/host-utils.h"
36 #include "hw/pci/pci_ids.h"
37 #include "hw/pci/pci_regs.h"
39 /* Test images sizes in MB */
40 #define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024)
41 #define TEST_IMAGE_SIZE_MB_SMALL 64
44 static char tmp_path
[] = "/tmp/qtest.XXXXXX";
45 static char debug_path
[] = "/tmp/qtest-blkdebug.XXXXXX";
46 static char mig_socket
[] = "/tmp/qtest-migration.XXXXXX";
47 static bool ahci_pedantic
;
48 static const char *imgfmt
;
49 static unsigned test_image_size_mb
;
51 /*** Function Declarations ***/
52 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
);
53 static void ahci_test_pci_spec(AHCIQState
*ahci
);
54 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
56 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
);
57 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
);
58 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
);
62 static uint64_t mb_to_sectors(uint64_t image_size_mb
)
64 return (image_size_mb
* 1024 * 1024) / AHCI_SECTOR_SIZE
;
67 static void string_bswap16(uint16_t *s
, size_t bytes
)
69 g_assert_cmphex((bytes
& 1), ==, 0);
79 * Verify that the transfer did not corrupt our state at all.
81 static void verify_state(AHCIQState
*ahci
, uint64_t hba_old
)
84 uint32_t ahci_fingerprint
;
86 AHCICommandHeader cmd
;
88 ahci_fingerprint
= qpci_config_readl(ahci
->dev
, PCI_VENDOR_ID
);
89 g_assert_cmphex(ahci_fingerprint
, ==, ahci
->fingerprint
);
91 /* If we haven't initialized, this is as much as can be validated. */
96 hba_base
= (uint64_t)qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
97 g_assert_cmphex(hba_base
, ==, hba_old
);
99 g_assert_cmphex(ahci_rreg(ahci
, AHCI_CAP
), ==, ahci
->cap
);
100 g_assert_cmphex(ahci_rreg(ahci
, AHCI_CAP2
), ==, ahci
->cap2
);
102 for (i
= 0; i
< 32; i
++) {
103 g_assert_cmphex(ahci_px_rreg(ahci
, i
, AHCI_PX_FB
), ==,
105 g_assert_cmphex(ahci_px_rreg(ahci
, i
, AHCI_PX_CLB
), ==,
107 for (j
= 0; j
< 32; j
++) {
108 ahci_get_command_header(ahci
, i
, j
, &cmd
);
109 g_assert_cmphex(cmd
.prdtl
, ==, ahci
->port
[i
].prdtl
[j
]);
110 g_assert_cmphex(cmd
.ctba
, ==, ahci
->port
[i
].ctba
[j
]);
115 static void ahci_migrate(AHCIQState
*from
, AHCIQState
*to
, const char *uri
)
117 QOSState
*tmp
= to
->parent
;
118 QPCIDevice
*dev
= to
->dev
;
119 char *uri_local
= NULL
;
123 uri_local
= g_strdup_printf("%s%s", "unix:", mig_socket
);
127 hba_old
= (uint64_t)qpci_config_readl(from
->dev
, PCI_BASE_ADDRESS_5
);
129 /* context will be 'to' after completion. */
130 migrate(from
->parent
, to
->parent
, uri
);
132 /* We'd like for the AHCIState objects to still point
133 * to information specific to its specific parent
134 * instance, but otherwise just inherit the new data. */
135 memcpy(to
, from
, sizeof(AHCIQState
));
141 memset(from
, 0x00, sizeof(AHCIQState
));
145 verify_state(to
, hba_old
);
149 /*** Test Setup & Teardown ***/
152 * Start a Q35 machine and bookmark a handle to the AHCI device.
154 static GCC_FMT_ATTR(1, 0)
155 AHCIQState
*ahci_vboot(const char *cli
, va_list ap
)
159 s
= g_malloc0(sizeof(AHCIQState
));
160 s
->parent
= qtest_pc_vboot(cli
, ap
);
161 alloc_set_flags(s
->parent
->alloc
, ALLOC_LEAK_ASSERT
);
163 /* Verify that we have an AHCI device present. */
164 s
->dev
= get_ahci_device(&s
->fingerprint
);
170 * Start a Q35 machine and bookmark a handle to the AHCI device.
172 static GCC_FMT_ATTR(1, 0)
173 AHCIQState
*ahci_boot(const char *cli
, ...)
180 s
= ahci_vboot(cli
, ap
);
183 cli
= "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
186 "-device ide-hd,drive=drive0 "
187 "-global ide-hd.ver=%s";
188 s
= ahci_boot(cli
, tmp_path
, "testdisk", imgfmt
, "version");
195 * Clean up the PCI device, then terminate the QEMU instance.
197 static void ahci_shutdown(AHCIQState
*ahci
)
199 QOSState
*qs
= ahci
->parent
;
202 ahci_clean_mem(ahci
);
203 free_ahci_device(ahci
->dev
);
209 * Boot and fully enable the HBA device.
210 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
212 static GCC_FMT_ATTR(1, 0)
213 AHCIQState
*ahci_boot_and_enable(const char *cli
, ...)
223 ahci
= ahci_vboot(cli
, ap
);
226 ahci
= ahci_boot(NULL
);
229 ahci_pci_enable(ahci
);
230 ahci_hba_enable(ahci
);
231 /* Initialize test device */
232 port
= ahci_port_select(ahci
);
233 ahci_port_clear(ahci
, port
);
234 if (is_atapi(ahci
, port
)) {
235 hello
= CMD_PACKET_ID
;
237 hello
= CMD_IDENTIFY
;
239 ahci_io(ahci
, port
, hello
, &buff
, sizeof(buff
), 0);
244 /*** Specification Adherence Tests ***/
247 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
249 static void ahci_test_pci_spec(AHCIQState
*ahci
)
255 /* Most of these bits should start cleared until we turn them on. */
256 data
= qpci_config_readw(ahci
->dev
, PCI_COMMAND
);
257 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MEMORY
);
258 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MASTER
);
259 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SPECIAL
); /* Reserved */
260 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_VGA_PALETTE
); /* Reserved */
261 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_PARITY
);
262 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_WAIT
); /* Reserved */
263 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SERR
);
264 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_FAST_BACK
);
265 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_INTX_DISABLE
);
266 ASSERT_BIT_CLEAR(data
, 0xF800); /* Reserved */
268 data
= qpci_config_readw(ahci
->dev
, PCI_STATUS
);
269 ASSERT_BIT_CLEAR(data
, 0x01 | 0x02 | 0x04); /* Reserved */
270 ASSERT_BIT_CLEAR(data
, PCI_STATUS_INTERRUPT
);
271 ASSERT_BIT_SET(data
, PCI_STATUS_CAP_LIST
); /* must be set */
272 ASSERT_BIT_CLEAR(data
, PCI_STATUS_UDF
); /* Reserved */
273 ASSERT_BIT_CLEAR(data
, PCI_STATUS_PARITY
);
274 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_TARGET_ABORT
);
275 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_TARGET_ABORT
);
276 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_MASTER_ABORT
);
277 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_SYSTEM_ERROR
);
278 ASSERT_BIT_CLEAR(data
, PCI_STATUS_DETECTED_PARITY
);
280 /* RID occupies the low byte, CCs occupy the high three. */
281 datal
= qpci_config_readl(ahci
->dev
, PCI_CLASS_REVISION
);
283 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
284 * Though in practice this is likely seldom true. */
285 ASSERT_BIT_CLEAR(datal
, 0xFF);
288 /* BCC *must* equal 0x01. */
289 g_assert_cmphex(PCI_BCC(datal
), ==, 0x01);
290 if (PCI_SCC(datal
) == 0x01) {
292 ASSERT_BIT_SET(0x80000000, datal
);
293 ASSERT_BIT_CLEAR(0x60000000, datal
);
294 } else if (PCI_SCC(datal
) == 0x04) {
296 g_assert_cmphex(PCI_PI(datal
), ==, 0);
297 } else if (PCI_SCC(datal
) == 0x06) {
299 g_assert_cmphex(PCI_PI(datal
), ==, 0x01);
301 g_assert_not_reached();
304 datab
= qpci_config_readb(ahci
->dev
, PCI_CACHE_LINE_SIZE
);
305 g_assert_cmphex(datab
, ==, 0);
307 datab
= qpci_config_readb(ahci
->dev
, PCI_LATENCY_TIMER
);
308 g_assert_cmphex(datab
, ==, 0);
310 /* Only the bottom 7 bits must be off. */
311 datab
= qpci_config_readb(ahci
->dev
, PCI_HEADER_TYPE
);
312 ASSERT_BIT_CLEAR(datab
, 0x7F);
314 /* BIST is optional, but the low 7 bits must always start off regardless. */
315 datab
= qpci_config_readb(ahci
->dev
, PCI_BIST
);
316 ASSERT_BIT_CLEAR(datab
, 0x7F);
318 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
319 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
320 g_assert_cmphex(datal
, ==, 0);
322 qpci_config_writel(ahci
->dev
, PCI_BASE_ADDRESS_5
, 0xFFFFFFFF);
323 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
324 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
325 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
326 ASSERT_BIT_CLEAR(datal
, 0xFF);
328 /* Capability list MUST be present, */
329 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
);
330 /* But these bits are reserved. */
331 ASSERT_BIT_CLEAR(datal
, ~0xFF);
332 g_assert_cmphex(datal
, !=, 0);
334 /* Check specification adherence for capability extenstions. */
335 data
= qpci_config_readw(ahci
->dev
, datal
);
337 switch (ahci
->fingerprint
) {
338 case AHCI_INTEL_ICH9
:
339 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
340 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_MSI
);
343 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
344 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_PM
);
347 ahci_test_pci_caps(ahci
, data
, (uint8_t)datal
);
350 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
+ 4);
351 g_assert_cmphex(datal
, ==, 0);
353 /* IPIN might vary, but ILINE must be off. */
354 datab
= qpci_config_readb(ahci
->dev
, PCI_INTERRUPT_LINE
);
355 g_assert_cmphex(datab
, ==, 0);
359 * Test PCI capabilities for AHCI specification adherence.
361 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
364 uint8_t cid
= header
& 0xFF;
365 uint8_t next
= header
>> 8;
367 g_test_message("CID: %02x; next: %02x", cid
, next
);
371 ahci_test_pmcap(ahci
, offset
);
374 ahci_test_msicap(ahci
, offset
);
376 case PCI_CAP_ID_SATA
:
377 ahci_test_satacap(ahci
, offset
);
381 g_test_message("Unknown CAP 0x%02x", cid
);
385 ahci_test_pci_caps(ahci
, qpci_config_readw(ahci
->dev
, next
), next
);
390 * Test SATA PCI capabilitity for AHCI specification adherence.
392 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
)
397 g_test_message("Verifying SATACAP");
399 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
400 dataw
= qpci_config_readw(ahci
->dev
, offset
+ 2);
401 g_assert_cmphex(dataw
, ==, 0x10);
403 /* Grab the SATACR1 register. */
404 datal
= qpci_config_readw(ahci
->dev
, offset
+ 4);
406 switch (datal
& 0x0F) {
407 case 0x04: /* BAR0 */
408 case 0x05: /* BAR1 */
412 case 0x09: /* BAR5 */
413 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
416 /* Invalid BARLOC for the Index Data Pair. */
417 g_assert_not_reached();
421 g_assert_cmphex((datal
>> 24), ==, 0x00);
425 * Test MSI PCI capability for AHCI specification adherence.
427 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
)
432 g_test_message("Verifying MSICAP");
434 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_FLAGS
);
435 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_ENABLE
);
436 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_QSIZE
);
437 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_RESERVED
);
439 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_LO
);
440 g_assert_cmphex(datal
, ==, 0);
442 if (dataw
& PCI_MSI_FLAGS_64BIT
) {
443 g_test_message("MSICAP is 64bit");
444 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_HI
);
445 g_assert_cmphex(datal
, ==, 0);
446 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_64
);
447 g_assert_cmphex(dataw
, ==, 0);
449 g_test_message("MSICAP is 32bit");
450 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_32
);
451 g_assert_cmphex(dataw
, ==, 0);
456 * Test Power Management PCI capability for AHCI specification adherence.
458 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
)
462 g_test_message("Verifying PMCAP");
464 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_PMC
);
465 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_PME_CLOCK
);
466 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_RESERVED
);
467 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D1
);
468 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D2
);
470 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_CTRL
);
471 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_STATE_MASK
);
472 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_RESERVED
);
473 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SEL_MASK
);
474 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SCALE_MASK
);
477 static void ahci_test_hba_spec(AHCIQState
*ahci
)
485 g_assert(ahci
!= NULL
);
488 * Note that the AHCI spec does expect the BIOS to set up a few things:
489 * CAP.SSS - Support for staggered spin-up (t/f)
490 * CAP.SMPS - Support for mechanical presence switches (t/f)
491 * PI - Ports Implemented (1-32)
492 * PxCMD.HPCP - Hot Plug Capable Port
493 * PxCMD.MPSP - Mechanical Presence Switch Present
494 * PxCMD.CPD - Cold Presence Detection support
496 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
497 * Foreach Port Implemented:
498 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
499 * -PxCLB/U and PxFB/U are set to valid regions in memory
500 * -PxSUD is set to 1.
501 * -PxSSTS.DET is polled for presence; if detected, we continue:
502 * -PxSERR is cleared with 1's.
503 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
504 * the device is ready.
507 /* 1 CAP - Capabilities Register */
508 ahci
->cap
= ahci_rreg(ahci
, AHCI_CAP
);
509 ASSERT_BIT_CLEAR(ahci
->cap
, AHCI_CAP_RESERVED
);
511 /* 2 GHC - Global Host Control */
512 reg
= ahci_rreg(ahci
, AHCI_GHC
);
513 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_HR
);
514 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_IE
);
515 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_MRSM
);
516 if (BITSET(ahci
->cap
, AHCI_CAP_SAM
)) {
517 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
518 ASSERT_BIT_SET(reg
, AHCI_GHC_AE
);
520 g_test_message("Supports AHCI/Legacy mix.");
521 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_AE
);
524 /* 3 IS - Interrupt Status */
525 reg
= ahci_rreg(ahci
, AHCI_IS
);
526 g_assert_cmphex(reg
, ==, 0);
528 /* 4 PI - Ports Implemented */
529 ports
= ahci_rreg(ahci
, AHCI_PI
);
530 /* Ports Implemented must be non-zero. */
531 g_assert_cmphex(ports
, !=, 0);
532 /* Ports Implemented must be <= Number of Ports. */
533 nports_impl
= ctpopl(ports
);
534 g_assert_cmpuint(((AHCI_CAP_NP
& ahci
->cap
) + 1), >=, nports_impl
);
536 /* Ports must be within the proper range. Given a mapping of SIZE,
537 * 256 bytes are used for global HBA control, and the rest is used
538 * for ports data, at 0x80 bytes each. */
539 g_assert_cmphex(ahci
->barsize
, >, 0);
540 maxports
= (ahci
->barsize
- HBA_DATA_REGION_SIZE
) / HBA_PORT_DATA_SIZE
;
541 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
542 g_assert_cmphex((reg
>> maxports
), ==, 0);
545 reg
= ahci_rreg(ahci
, AHCI_VS
);
547 case AHCI_VERSION_0_95
:
548 case AHCI_VERSION_1_0
:
549 case AHCI_VERSION_1_1
:
550 case AHCI_VERSION_1_2
:
551 case AHCI_VERSION_1_3
:
554 g_assert_not_reached();
557 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
558 reg
= ahci_rreg(ahci
, AHCI_CCCCTL
);
559 if (BITSET(ahci
->cap
, AHCI_CAP_CCCS
)) {
560 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_EN
);
561 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_RESERVED
);
562 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_CC
);
563 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_TV
);
565 g_assert_cmphex(reg
, ==, 0);
569 reg
= ahci_rreg(ahci
, AHCI_CCCPORTS
);
570 /* Must be zeroes initially regardless of CAP.CCCS */
571 g_assert_cmphex(reg
, ==, 0);
574 reg
= ahci_rreg(ahci
, AHCI_EMLOC
);
575 if (BITCLR(ahci
->cap
, AHCI_CAP_EMS
)) {
576 g_assert_cmphex(reg
, ==, 0);
580 reg
= ahci_rreg(ahci
, AHCI_EMCTL
);
581 if (BITSET(ahci
->cap
, AHCI_CAP_EMS
)) {
582 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_STSMR
);
583 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLTM
);
584 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLRST
);
585 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_RESERVED
);
587 g_assert_cmphex(reg
, ==, 0);
590 /* 10 CAP2 -- Capabilities Extended */
591 ahci
->cap2
= ahci_rreg(ahci
, AHCI_CAP2
);
592 ASSERT_BIT_CLEAR(ahci
->cap2
, AHCI_CAP2_RESERVED
);
594 /* 11 BOHC -- Bios/OS Handoff Control */
595 reg
= ahci_rreg(ahci
, AHCI_BOHC
);
596 g_assert_cmphex(reg
, ==, 0);
598 /* 12 -- 23: Reserved */
599 g_test_message("Verifying HBA reserved area is empty.");
600 for (i
= AHCI_RESERVED
; i
< AHCI_NVMHCI
; ++i
) {
601 reg
= ahci_rreg(ahci
, i
);
602 g_assert_cmphex(reg
, ==, 0);
605 /* 24 -- 39: NVMHCI */
606 if (BITCLR(ahci
->cap2
, AHCI_CAP2_NVMP
)) {
607 g_test_message("Verifying HBA/NVMHCI area is empty.");
608 for (i
= AHCI_NVMHCI
; i
< AHCI_VENDOR
; ++i
) {
609 reg
= ahci_rreg(ahci
, i
);
610 g_assert_cmphex(reg
, ==, 0);
614 /* 40 -- 63: Vendor */
615 g_test_message("Verifying HBA/Vendor area is empty.");
616 for (i
= AHCI_VENDOR
; i
< AHCI_PORTS
; ++i
) {
617 reg
= ahci_rreg(ahci
, i
);
618 g_assert_cmphex(reg
, ==, 0);
621 /* 64 -- XX: Port Space */
622 for (i
= 0; ports
|| (i
< maxports
); ports
>>= 1, ++i
) {
623 if (BITSET(ports
, 0x1)) {
624 g_test_message("Testing port %u for spec", i
);
625 ahci_test_port_spec(ahci
, i
);
628 uint16_t low
= AHCI_PORTS
+ (32 * i
);
629 uint16_t high
= AHCI_PORTS
+ (32 * (i
+ 1));
630 g_test_message("Asserting unimplemented port %u "
631 "(reg [%u-%u]) is empty.",
633 for (j
= low
; j
< high
; ++j
) {
634 reg
= ahci_rreg(ahci
, j
);
635 g_assert_cmphex(reg
, ==, 0);
642 * Test the memory space for one port for specification adherence.
644 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
)
650 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLB
);
651 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CLB_RESERVED
);
654 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
655 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLBU
);
656 g_assert_cmphex(reg
, ==, 0);
660 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FB
);
661 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FB_RESERVED
);
664 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
665 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBU
);
666 g_assert_cmphex(reg
, ==, 0);
670 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IS
);
671 g_assert_cmphex(reg
, ==, 0);
674 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IE
);
675 g_assert_cmphex(reg
, ==, 0);
678 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CMD
);
679 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FRE
);
680 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_RESERVED
);
681 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CCS
);
682 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FR
);
683 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CR
);
684 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_PMA
); /* And RW only if CAP.SPM */
685 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_APSTE
); /* RW only if CAP2.APST */
686 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ATAPI
);
687 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_DLAE
);
688 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ALPE
); /* RW only if CAP.SALP */
689 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ASP
); /* RW only if CAP.SALP */
690 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ICC
);
691 /* If CPDetect support does not exist, CPState must be off. */
692 if (BITCLR(reg
, AHCI_PX_CMD_CPD
)) {
693 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CPS
);
695 /* If MPSPresence is not set, MPSState must be off. */
696 if (BITCLR(reg
, AHCI_PX_CMD_MPSP
)) {
697 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
699 /* If we do not support MPS, MPSS and MPSP must be off. */
700 if (BITCLR(ahci
->cap
, AHCI_CAP_SMPS
)) {
701 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
702 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSP
);
704 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
705 if (BITANY(reg
, AHCI_PX_CMD_CPD
| AHCI_PX_CMD_MPSP
)) {
706 ASSERT_BIT_SET(reg
, AHCI_PX_CMD_HPCP
);
708 /* HPCP and ESP cannot both be active. */
709 g_assert(!BITSET(reg
, AHCI_PX_CMD_HPCP
| AHCI_PX_CMD_ESP
));
710 /* If CAP.FBSS is not set, FBSCP must not be set. */
711 if (BITCLR(ahci
->cap
, AHCI_CAP_FBSS
)) {
712 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FBSCP
);
716 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_RES1
);
717 g_assert_cmphex(reg
, ==, 0);
720 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_TFD
);
721 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
722 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
723 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_ERR
);
724 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS1
);
725 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_DRQ
);
726 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS2
);
727 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_BSY
);
728 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_ERR
);
729 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_RESERVED
);
732 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
733 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
734 * D2H register FIS and update the signature asynchronously,
735 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
737 /* (10) SSTS / SCR0: SStatus */
738 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SSTS
);
739 ASSERT_BIT_CLEAR(reg
, AHCI_PX_SSTS_RESERVED
);
740 /* Even though the register should be 0 at boot, it is asynchronous and
741 * prone to change, so we cannot test any well known value. */
743 /* (11) SCTL / SCR2: SControl */
744 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SCTL
);
745 g_assert_cmphex(reg
, ==, 0);
747 /* (12) SERR / SCR1: SError */
748 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SERR
);
749 g_assert_cmphex(reg
, ==, 0);
751 /* (13) SACT / SCR3: SActive */
752 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SACT
);
753 g_assert_cmphex(reg
, ==, 0);
756 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CI
);
757 g_assert_cmphex(reg
, ==, 0);
760 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SNTF
);
761 g_assert_cmphex(reg
, ==, 0);
764 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBS
);
765 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_EN
);
766 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEC
);
767 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_SDE
);
768 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEV
);
769 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DWE
);
770 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_RESERVED
);
771 if (BITSET(ahci
->cap
, AHCI_CAP_FBSS
)) {
772 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
773 g_assert((reg
& AHCI_PX_FBS_ADO
) >> ctzl(AHCI_PX_FBS_ADO
) >= 2);
776 /* [17 -- 27] RESERVED */
777 for (i
= AHCI_PX_RES2
; i
< AHCI_PX_VS
; ++i
) {
778 reg
= ahci_px_rreg(ahci
, port
, i
);
779 g_assert_cmphex(reg
, ==, 0);
782 /* [28 -- 31] Vendor-Specific */
783 for (i
= AHCI_PX_VS
; i
< 32; ++i
) {
784 reg
= ahci_px_rreg(ahci
, port
, i
);
786 g_test_message("INFO: Vendor register %u non-empty", i
);
792 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
793 * device we see, then read and check the response.
795 static void ahci_test_identify(AHCIQState
*ahci
)
801 const size_t buffsize
= 512;
803 g_assert(ahci
!= NULL
);
806 * This serves as a bit of a tutorial on AHCI device programming:
808 * (1) Create a data buffer for the IDENTIFY response to be sent to
809 * (2) Create a Command Table buffer, where we will store the
810 * command and PRDT (Physical Region Descriptor Table)
811 * (3) Construct an FIS host-to-device command structure, and write it to
812 * the top of the Command Table buffer.
813 * (4) Create one or more Physical Region Descriptors (PRDs) that describe
814 * a location in memory where data may be stored/retrieved.
815 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
816 * (6) Each AHCI port has up to 32 command slots. Each slot contains a
817 * header that points to a Command Table buffer. Pick an unused slot
818 * and update it to point to the Command Table we have built.
819 * (7) Now: Command #n points to our Command Table, and our Command Table
820 * contains the FIS (that describes our command) and the PRDTL, which
821 * describes our buffer.
822 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
823 * #n is ready for processing.
826 /* Pick the first implemented and running port */
827 px
= ahci_port_select(ahci
);
828 g_test_message("Selected port %u for test", px
);
830 /* Clear out the FIS Receive area and any pending interrupts. */
831 ahci_port_clear(ahci
, px
);
833 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
834 ahci_io(ahci
, px
, CMD_IDENTIFY
, &buff
, buffsize
, 0);
836 /* Check serial number/version in the buffer */
837 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
838 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
839 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
840 * as a consequence, only needs to unchunk the data on LE machines. */
841 string_bswap16(&buff
[10], 20);
842 rc
= memcmp(&buff
[10], "testdisk ", 20);
843 g_assert_cmphex(rc
, ==, 0);
845 string_bswap16(&buff
[23], 8);
846 rc
= memcmp(&buff
[23], "version ", 8);
847 g_assert_cmphex(rc
, ==, 0);
849 sect_size
= le16_to_cpu(*((uint16_t *)(&buff
[5])));
850 g_assert_cmphex(sect_size
, ==, AHCI_SECTOR_SIZE
);
853 static void ahci_test_io_rw_simple(AHCIQState
*ahci
, unsigned bufsize
,
854 uint64_t sector
, uint8_t read_cmd
,
859 unsigned char *tx
= g_malloc(bufsize
);
860 unsigned char *rx
= g_malloc0(bufsize
);
862 g_assert(ahci
!= NULL
);
864 /* Pick the first running port and clear it. */
865 port
= ahci_port_select(ahci
);
866 ahci_port_clear(ahci
, port
);
868 /*** Create pattern and transfer to guest ***/
869 /* Data buffer in the guest */
870 ptr
= ahci_alloc(ahci
, bufsize
);
873 /* Write some indicative pattern to our buffer. */
874 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
875 bufwrite(ptr
, tx
, bufsize
);
877 /* Write this buffer to disk, then read it back to the DMA buffer. */
878 ahci_guest_io(ahci
, port
, write_cmd
, ptr
, bufsize
, sector
);
879 qmemset(ptr
, 0x00, bufsize
);
880 ahci_guest_io(ahci
, port
, read_cmd
, ptr
, bufsize
, sector
);
882 /*** Read back the Data ***/
883 bufread(ptr
, rx
, bufsize
);
884 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
886 ahci_free(ahci
, ptr
);
891 static uint8_t ahci_test_nondata(AHCIQState
*ahci
, uint8_t ide_cmd
)
896 port
= ahci_port_select(ahci
);
897 ahci_port_clear(ahci
, port
);
899 ahci_io(ahci
, port
, ide_cmd
, NULL
, 0, 0);
904 static void ahci_test_flush(AHCIQState
*ahci
)
906 ahci_test_nondata(ahci
, CMD_FLUSH_CACHE
);
909 static void ahci_test_max(AHCIQState
*ahci
)
911 RegD2HFIS
*d2h
= g_malloc0(0x20);
915 uint64_t config_sect
= mb_to_sectors(test_image_size_mb
) - 1;
917 if (config_sect
> 0xFFFFFF) {
918 cmd
= CMD_READ_MAX_EXT
;
923 port
= ahci_test_nondata(ahci
, cmd
);
924 memread(ahci
->port
[port
].fb
+ 0x40, d2h
, 0x20);
925 nsect
= (uint64_t)d2h
->lba_hi
[2] << 40 |
926 (uint64_t)d2h
->lba_hi
[1] << 32 |
927 (uint64_t)d2h
->lba_hi
[0] << 24 |
928 (uint64_t)d2h
->lba_lo
[2] << 16 |
929 (uint64_t)d2h
->lba_lo
[1] << 8 |
930 (uint64_t)d2h
->lba_lo
[0];
932 g_assert_cmphex(nsect
, ==, config_sect
);
937 /******************************************************************************/
938 /* Test Interfaces */
939 /******************************************************************************/
942 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
944 static void test_sanity(void)
947 ahci
= ahci_boot(NULL
);
952 * Ensure that the PCI configuration space for the AHCI device is in-line with
953 * the AHCI 1.3 specification for initial values.
955 static void test_pci_spec(void)
958 ahci
= ahci_boot(NULL
);
959 ahci_test_pci_spec(ahci
);
964 * Engage the PCI AHCI device and sanity check the response.
965 * Perform additional PCI config space bringup for the HBA.
967 static void test_pci_enable(void)
970 ahci
= ahci_boot(NULL
);
971 ahci_pci_enable(ahci
);
976 * Investigate the memory mapped regions of the HBA,
977 * and test them for AHCI specification adherence.
979 static void test_hba_spec(void)
983 ahci
= ahci_boot(NULL
);
984 ahci_pci_enable(ahci
);
985 ahci_test_hba_spec(ahci
);
990 * Engage the HBA functionality of the AHCI PCI device,
991 * and bring it into a functional idle state.
993 static void test_hba_enable(void)
997 ahci
= ahci_boot(NULL
);
998 ahci_pci_enable(ahci
);
999 ahci_hba_enable(ahci
);
1000 ahci_shutdown(ahci
);
1004 * Bring up the device and issue an IDENTIFY command.
1005 * Inspect the state of the HBA device and the data returned.
1007 static void test_identify(void)
1011 ahci
= ahci_boot_and_enable(NULL
);
1012 ahci_test_identify(ahci
);
1013 ahci_shutdown(ahci
);
1017 * Fragmented DMA test: Perform a standard 4K DMA read/write
1018 * test, but make sure the physical regions are fragmented to
1019 * be very small, each just 32 bytes, to see how AHCI performs
1020 * with chunks defined to be much less than a sector.
1022 static void test_dma_fragmented(void)
1027 size_t bufsize
= 4096;
1028 unsigned char *tx
= g_malloc(bufsize
);
1029 unsigned char *rx
= g_malloc0(bufsize
);
1032 ahci
= ahci_boot_and_enable(NULL
);
1033 px
= ahci_port_select(ahci
);
1034 ahci_port_clear(ahci
, px
);
1036 /* create pattern */
1037 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1039 /* Create a DMA buffer in guest memory, and write our pattern to it. */
1040 ptr
= guest_alloc(ahci
->parent
->alloc
, bufsize
);
1042 bufwrite(ptr
, tx
, bufsize
);
1044 cmd
= ahci_command_create(CMD_WRITE_DMA
);
1045 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
1046 ahci_command_commit(ahci
, cmd
, px
);
1047 ahci_command_issue(ahci
, cmd
);
1048 ahci_command_verify(ahci
, cmd
);
1049 ahci_command_free(cmd
);
1051 cmd
= ahci_command_create(CMD_READ_DMA
);
1052 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
1053 ahci_command_commit(ahci
, cmd
, px
);
1054 ahci_command_issue(ahci
, cmd
);
1055 ahci_command_verify(ahci
, cmd
);
1056 ahci_command_free(cmd
);
1058 /* Read back the guest's receive buffer into local memory */
1059 bufread(ptr
, rx
, bufsize
);
1060 guest_free(ahci
->parent
->alloc
, ptr
);
1062 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1064 ahci_shutdown(ahci
);
1071 * Write sector 1 with random data to make AHCI storage dirty
1072 * Needed for flush tests so that flushes actually go though the block layer
1074 static void make_dirty(AHCIQState
* ahci
, uint8_t port
)
1077 unsigned bufsize
= 512;
1079 ptr
= ahci_alloc(ahci
, bufsize
);
1082 ahci_guest_io(ahci
, port
, CMD_WRITE_DMA
, ptr
, bufsize
, 1);
1083 ahci_free(ahci
, ptr
);
1086 static void test_flush(void)
1091 ahci
= ahci_boot_and_enable(NULL
);
1093 port
= ahci_port_select(ahci
);
1094 ahci_port_clear(ahci
, port
);
1096 make_dirty(ahci
, port
);
1098 ahci_test_flush(ahci
);
1099 ahci_shutdown(ahci
);
1102 static void test_flush_retry(void)
1108 prepare_blkdebug_script(debug_path
, "flush_to_disk");
1109 ahci
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1110 "format=%s,cache=writeback,"
1111 "rerror=stop,werror=stop "
1113 "-device ide-hd,drive=drive0 ",
1117 port
= ahci_port_select(ahci
);
1118 ahci_port_clear(ahci
, port
);
1120 /* Issue write so that flush actually goes to disk */
1121 make_dirty(ahci
, port
);
1123 /* Issue Flush Command and wait for error */
1124 cmd
= ahci_guest_io_halt(ahci
, port
, CMD_FLUSH_CACHE
, 0, 0, 0);
1125 ahci_guest_io_resume(ahci
, cmd
);
1127 ahci_shutdown(ahci
);
1131 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1133 static void test_migrate_sanity(void)
1135 AHCIQState
*src
, *dst
;
1136 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1138 src
= ahci_boot("-m 1024 -M q35 "
1139 "-drive if=ide,file=%s,format=%s ", tmp_path
, imgfmt
);
1140 dst
= ahci_boot("-m 1024 -M q35 "
1141 "-drive if=ide,file=%s,format=%s "
1142 "-incoming %s", tmp_path
, imgfmt
, uri
);
1144 ahci_migrate(src
, dst
, uri
);
1152 * Simple migration test: Write a pattern, migrate, then read.
1154 static void ahci_migrate_simple(uint8_t cmd_read
, uint8_t cmd_write
)
1156 AHCIQState
*src
, *dst
;
1158 size_t bufsize
= 4096;
1159 unsigned char *tx
= g_malloc(bufsize
);
1160 unsigned char *rx
= g_malloc0(bufsize
);
1161 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1163 src
= ahci_boot_and_enable("-m 1024 -M q35 "
1164 "-drive if=ide,format=%s,file=%s ",
1166 dst
= ahci_boot("-m 1024 -M q35 "
1167 "-drive if=ide,format=%s,file=%s "
1168 "-incoming %s", imgfmt
, tmp_path
, uri
);
1170 set_context(src
->parent
);
1173 px
= ahci_port_select(src
);
1174 ahci_port_clear(src
, px
);
1176 /* create pattern */
1177 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1179 /* Write, migrate, then read. */
1180 ahci_io(src
, px
, cmd_write
, tx
, bufsize
, 0);
1181 ahci_migrate(src
, dst
, uri
);
1182 ahci_io(dst
, px
, cmd_read
, rx
, bufsize
, 0);
1184 /* Verify pattern */
1185 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1194 static void test_migrate_dma(void)
1196 ahci_migrate_simple(CMD_READ_DMA
, CMD_WRITE_DMA
);
1199 static void test_migrate_ncq(void)
1201 ahci_migrate_simple(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1205 * Halted IO Error Test
1207 * Simulate an error on first write, Try to write a pattern,
1208 * Confirm the VM has stopped, resume the VM, verify command
1209 * has completed, then read back the data and verify.
1211 static void ahci_halted_io_test(uint8_t cmd_read
, uint8_t cmd_write
)
1215 size_t bufsize
= 4096;
1216 unsigned char *tx
= g_malloc(bufsize
);
1217 unsigned char *rx
= g_malloc0(bufsize
);
1221 prepare_blkdebug_script(debug_path
, "write_aio");
1223 ahci
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1224 "format=%s,cache=writeback,"
1225 "rerror=stop,werror=stop "
1227 "-device ide-hd,drive=drive0 ",
1231 /* Initialize and prepare */
1232 port
= ahci_port_select(ahci
);
1233 ahci_port_clear(ahci
, port
);
1235 /* create DMA source buffer and write pattern */
1236 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1237 ptr
= ahci_alloc(ahci
, bufsize
);
1239 memwrite(ptr
, tx
, bufsize
);
1241 /* Attempt to write (and fail) */
1242 cmd
= ahci_guest_io_halt(ahci
, port
, cmd_write
,
1245 /* Attempt to resume the command */
1246 ahci_guest_io_resume(ahci
, cmd
);
1247 ahci_free(ahci
, ptr
);
1249 /* Read back and verify */
1250 ahci_io(ahci
, port
, cmd_read
, rx
, bufsize
, 0);
1251 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1253 /* Cleanup and go home */
1254 ahci_shutdown(ahci
);
1259 static void test_halted_dma(void)
1261 ahci_halted_io_test(CMD_READ_DMA
, CMD_WRITE_DMA
);
1264 static void test_halted_ncq(void)
1266 ahci_halted_io_test(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1270 * IO Error Migration Test
1272 * Simulate an error on first write, Try to write a pattern,
1273 * Confirm the VM has stopped, migrate, resume the VM,
1274 * verify command has completed, then read back the data and verify.
1276 static void ahci_migrate_halted_io(uint8_t cmd_read
, uint8_t cmd_write
)
1278 AHCIQState
*src
, *dst
;
1280 size_t bufsize
= 4096;
1281 unsigned char *tx
= g_malloc(bufsize
);
1282 unsigned char *rx
= g_malloc0(bufsize
);
1285 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1287 prepare_blkdebug_script(debug_path
, "write_aio");
1289 src
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1290 "format=%s,cache=writeback,"
1291 "rerror=stop,werror=stop "
1293 "-device ide-hd,drive=drive0 ",
1297 dst
= ahci_boot("-drive file=%s,if=none,id=drive0,"
1298 "format=%s,cache=writeback,"
1299 "rerror=stop,werror=stop "
1301 "-device ide-hd,drive=drive0 "
1303 tmp_path
, imgfmt
, uri
);
1305 set_context(src
->parent
);
1307 /* Initialize and prepare */
1308 port
= ahci_port_select(src
);
1309 ahci_port_clear(src
, port
);
1310 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1312 /* create DMA source buffer and write pattern */
1313 ptr
= ahci_alloc(src
, bufsize
);
1315 memwrite(ptr
, tx
, bufsize
);
1317 /* Write, trigger the VM to stop, migrate, then resume. */
1318 cmd
= ahci_guest_io_halt(src
, port
, cmd_write
,
1320 ahci_migrate(src
, dst
, uri
);
1321 ahci_guest_io_resume(dst
, cmd
);
1322 ahci_free(dst
, ptr
);
1325 ahci_io(dst
, port
, cmd_read
, rx
, bufsize
, 0);
1327 /* Verify TX and RX are identical */
1328 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1330 /* Cleanup and go home. */
1338 static void test_migrate_halted_dma(void)
1340 ahci_migrate_halted_io(CMD_READ_DMA
, CMD_WRITE_DMA
);
1343 static void test_migrate_halted_ncq(void)
1345 ahci_migrate_halted_io(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1349 * Migration test: Try to flush, migrate, then resume.
1351 static void test_flush_migrate(void)
1353 AHCIQState
*src
, *dst
;
1357 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1359 prepare_blkdebug_script(debug_path
, "flush_to_disk");
1361 src
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1362 "cache=writeback,rerror=stop,werror=stop,"
1365 "-device ide-hd,drive=drive0 ",
1366 debug_path
, tmp_path
, imgfmt
);
1367 dst
= ahci_boot("-drive file=%s,if=none,id=drive0,"
1368 "cache=writeback,rerror=stop,werror=stop,"
1371 "-device ide-hd,drive=drive0 "
1372 "-incoming %s", tmp_path
, imgfmt
, uri
);
1374 set_context(src
->parent
);
1376 px
= ahci_port_select(src
);
1377 ahci_port_clear(src
, px
);
1379 /* Dirty device so that flush reaches disk */
1380 make_dirty(src
, px
);
1382 /* Issue Flush Command */
1383 cmd
= ahci_command_create(CMD_FLUSH_CACHE
);
1384 ahci_command_commit(src
, cmd
, px
);
1385 ahci_command_issue_async(src
, cmd
);
1386 qmp_eventwait("STOP");
1389 ahci_migrate(src
, dst
, uri
);
1391 /* Complete the command */
1392 s
= "{'execute':'cont' }";
1394 qmp_eventwait("RESUME");
1395 ahci_command_wait(dst
, cmd
);
1396 ahci_command_verify(dst
, cmd
);
1398 ahci_command_free(cmd
);
1404 static void test_max(void)
1408 ahci
= ahci_boot_and_enable(NULL
);
1409 ahci_test_max(ahci
);
1410 ahci_shutdown(ahci
);
1413 static void test_reset(void)
1418 ahci
= ahci_boot(NULL
);
1419 ahci_test_pci_spec(ahci
);
1420 ahci_pci_enable(ahci
);
1422 for (i
= 0; i
< 2; i
++) {
1423 ahci_test_hba_spec(ahci
);
1424 ahci_hba_enable(ahci
);
1425 ahci_test_identify(ahci
);
1426 ahci_test_io_rw_simple(ahci
, 4096, 0,
1429 ahci_set(ahci
, AHCI_GHC
, AHCI_GHC_HR
);
1430 ahci_clean_mem(ahci
);
1433 ahci_shutdown(ahci
);
1436 static void test_ncq_simple(void)
1440 ahci
= ahci_boot_and_enable(NULL
);
1441 ahci_test_io_rw_simple(ahci
, 4096, 0,
1443 WRITE_FPDMA_QUEUED
);
1444 ahci_shutdown(ahci
);
1447 static int prepare_iso(size_t size
, unsigned char **buf
, char **name
)
1449 char cdrom_path
[] = "/tmp/qtest.iso.XXXXXX";
1450 unsigned char *patt
;
1452 int fd
= mkstemp(cdrom_path
);
1456 patt
= g_malloc(size
);
1458 /* Generate a pattern and build a CDROM image to read from */
1459 generate_pattern(patt
, size
, ATAPI_SECTOR_SIZE
);
1460 ret
= write(fd
, patt
, size
);
1461 g_assert(ret
== size
);
1463 *name
= g_strdup(cdrom_path
);
1468 static void remove_iso(int fd
, char *name
)
1475 static int ahci_cb_cmp_buff(AHCIQState
*ahci
, AHCICommand
*cmd
,
1476 const AHCIOpts
*opts
)
1478 unsigned char *tx
= opts
->opaque
;
1485 rx
= g_malloc0(opts
->size
);
1486 bufread(opts
->buffer
, rx
, opts
->size
);
1487 g_assert_cmphex(memcmp(tx
, rx
, opts
->size
), ==, 0);
1493 static void ahci_test_cdrom(int nsectors
, bool dma
, uint8_t cmd
,
1494 bool override_bcl
, uint16_t bcl
)
1501 .size
= (ATAPI_SECTOR_SIZE
* nsectors
),
1504 .post_cb
= ahci_cb_cmp_buff
,
1505 .set_bcl
= override_bcl
,
1508 uint64_t iso_size
= ATAPI_SECTOR_SIZE
* (nsectors
+ 1);
1510 /* Prepare ISO and fill 'tx' buffer */
1511 fd
= prepare_iso(iso_size
, &tx
, &iso
);
1514 /* Standard startup wonkery, but use ide-cd and our special iso file */
1515 ahci
= ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1517 "-device ide-cd,drive=drive0 ", iso
);
1519 /* Build & Send AHCI command */
1520 ahci_exec(ahci
, ahci_port_select(ahci
), cmd
, &opts
);
1524 ahci_shutdown(ahci
);
1525 remove_iso(fd
, iso
);
1528 static void ahci_test_cdrom_read10(int nsectors
, bool dma
)
1530 ahci_test_cdrom(nsectors
, dma
, CMD_ATAPI_READ_10
, false, 0);
1533 static void test_cdrom_dma(void)
1535 ahci_test_cdrom_read10(1, true);
1538 static void test_cdrom_dma_multi(void)
1540 ahci_test_cdrom_read10(3, true);
1543 static void test_cdrom_pio(void)
1545 ahci_test_cdrom_read10(1, false);
1548 static void test_cdrom_pio_multi(void)
1550 ahci_test_cdrom_read10(3, false);
1553 /* Regression test: Test that a READ_CD command with a BCL of 0 but a size of 0
1554 * completes as a NOP instead of erroring out. */
1555 static void test_atapi_bcl(void)
1557 ahci_test_cdrom(0, false, CMD_ATAPI_READ_CD
, true, 0);
1561 static void atapi_wait_tray(bool open
)
1563 QDict
*rsp
= qmp_eventwait_ref("DEVICE_TRAY_MOVED");
1564 QDict
*data
= qdict_get_qdict(rsp
, "data");
1566 g_assert(qdict_get_bool(data
, "tray-open"));
1568 g_assert(!qdict_get_bool(data
, "tray-open"));
1573 static void test_atapi_tray(void)
1579 uint8_t port
, sense
, asc
;
1580 uint64_t iso_size
= ATAPI_SECTOR_SIZE
;
1583 fd
= prepare_iso(iso_size
, &tx
, &iso
);
1584 ahci
= ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1586 "-device ide-cd,drive=drive0 ", iso
);
1587 port
= ahci_port_select(ahci
);
1589 ahci_atapi_eject(ahci
, port
);
1590 atapi_wait_tray(true);
1592 ahci_atapi_load(ahci
, port
);
1593 atapi_wait_tray(false);
1596 qmp_async("{'execute': 'blockdev-open-tray', "
1597 "'arguments': {'device': 'drive0'}}");
1598 atapi_wait_tray(true);
1599 rsp
= qmp_receive();
1602 qmp_discard_response("{'execute': 'x-blockdev-remove-medium', "
1603 "'arguments': {'device': 'drive0'}}");
1605 /* Test the tray without a medium */
1606 ahci_atapi_load(ahci
, port
);
1607 atapi_wait_tray(false);
1609 ahci_atapi_eject(ahci
, port
);
1610 atapi_wait_tray(true);
1612 /* Re-insert media */
1613 qmp_discard_response("{'execute': 'blockdev-add', "
1614 "'arguments': {'node-name': 'node0', "
1616 "'file': { 'driver': 'file', "
1617 "'filename': %s }}}", iso
);
1618 qmp_discard_response("{'execute': 'x-blockdev-insert-medium',"
1619 "'arguments': { 'device': 'drive0', "
1620 "'node-name': 'node0' }}");
1622 /* Again, the event shows up first */
1623 qmp_async("{'execute': 'blockdev-close-tray', "
1624 "'arguments': {'device': 'drive0'}}");
1625 atapi_wait_tray(false);
1626 rsp
= qmp_receive();
1629 /* Now, to convince ATAPI we understand the media has changed... */
1630 ahci_atapi_test_ready(ahci
, port
, false, SENSE_NOT_READY
);
1631 ahci_atapi_get_sense(ahci
, port
, &sense
, &asc
);
1632 g_assert_cmpuint(sense
, ==, SENSE_NOT_READY
);
1633 g_assert_cmpuint(asc
, ==, ASC_MEDIUM_NOT_PRESENT
);
1635 ahci_atapi_test_ready(ahci
, port
, false, SENSE_UNIT_ATTENTION
);
1636 ahci_atapi_get_sense(ahci
, port
, &sense
, &asc
);
1637 g_assert_cmpuint(sense
, ==, SENSE_UNIT_ATTENTION
);
1638 g_assert_cmpuint(asc
, ==, ASC_MEDIUM_MAY_HAVE_CHANGED
);
1640 ahci_atapi_test_ready(ahci
, port
, true, SENSE_NO_SENSE
);
1641 ahci_atapi_get_sense(ahci
, port
, &sense
, &asc
);
1642 g_assert_cmpuint(sense
, ==, SENSE_NO_SENSE
);
1644 /* Final tray test. */
1645 ahci_atapi_eject(ahci
, port
);
1646 atapi_wait_tray(true);
1648 ahci_atapi_load(ahci
, port
);
1649 atapi_wait_tray(false);
1653 ahci_shutdown(ahci
);
1654 remove_iso(fd
, iso
);
1657 /******************************************************************************/
1658 /* AHCI I/O Test Matrix Definitions */
1662 LEN_SIMPLE
= LEN_BEGIN
,
1669 static const char *buff_len_str
[NUM_LENGTHS
] = { "simple", "double",
1673 ADDR_MODE_BEGIN
= 0,
1674 ADDR_MODE_LBA28
= ADDR_MODE_BEGIN
,
1679 static const char *addr_mode_str
[NUM_ADDR_MODES
] = { "lba28", "lba48" };
1683 MODE_PIO
= MODE_BEGIN
,
1688 static const char *io_mode_str
[NUM_MODES
] = { "pio", "dma" };
1699 OFFSET_ZERO
= OFFSET_BEGIN
,
1705 static const char *offset_str
[NUM_OFFSETS
] = { "zero", "low", "high" };
1707 typedef struct AHCIIOTestOptions
{
1708 enum BuffLen length
;
1709 enum AddrMode address_type
;
1710 enum IOMode io_type
;
1711 enum OffsetType offset
;
1712 } AHCIIOTestOptions
;
1714 static uint64_t offset_sector(enum OffsetType ofst
,
1715 enum AddrMode addr_type
,
1727 ceil
= (addr_type
== ADDR_MODE_LBA28
) ? 0xfffffff : 0xffffffffffff;
1728 ceil
= MIN(ceil
, mb_to_sectors(test_image_size_mb
) - 1);
1729 nsectors
= buffsize
/ AHCI_SECTOR_SIZE
;
1730 return ceil
- nsectors
+ 1;
1732 g_assert_not_reached();
1737 * Table of possible I/O ATA commands given a set of enumerations.
1739 static const uint8_t io_cmds
[NUM_MODES
][NUM_ADDR_MODES
][NUM_IO_OPS
] = {
1741 [ADDR_MODE_LBA28
] = {
1742 [IO_READ
] = CMD_READ_PIO
,
1743 [IO_WRITE
] = CMD_WRITE_PIO
},
1744 [ADDR_MODE_LBA48
] = {
1745 [IO_READ
] = CMD_READ_PIO_EXT
,
1746 [IO_WRITE
] = CMD_WRITE_PIO_EXT
}
1749 [ADDR_MODE_LBA28
] = {
1750 [IO_READ
] = CMD_READ_DMA
,
1751 [IO_WRITE
] = CMD_WRITE_DMA
},
1752 [ADDR_MODE_LBA48
] = {
1753 [IO_READ
] = CMD_READ_DMA_EXT
,
1754 [IO_WRITE
] = CMD_WRITE_DMA_EXT
}
1759 * Test a Read/Write pattern using various commands, addressing modes,
1760 * transfer modes, and buffer sizes.
1762 static void test_io_rw_interface(enum AddrMode lba48
, enum IOMode dma
,
1763 unsigned bufsize
, uint64_t sector
)
1767 ahci
= ahci_boot_and_enable(NULL
);
1768 ahci_test_io_rw_simple(ahci
, bufsize
, sector
,
1769 io_cmds
[dma
][lba48
][IO_READ
],
1770 io_cmds
[dma
][lba48
][IO_WRITE
]);
1771 ahci_shutdown(ahci
);
1775 * Demultiplex the test data and invoke the actual test routine.
1777 static void test_io_interface(gconstpointer opaque
)
1779 AHCIIOTestOptions
*opts
= (AHCIIOTestOptions
*)opaque
;
1783 switch (opts
->length
) {
1791 bufsize
= 4096 * 64;
1797 g_assert_not_reached();
1800 sector
= offset_sector(opts
->offset
, opts
->address_type
, bufsize
);
1801 test_io_rw_interface(opts
->address_type
, opts
->io_type
, bufsize
, sector
);
1806 static void create_ahci_io_test(enum IOMode type
, enum AddrMode addr
,
1807 enum BuffLen len
, enum OffsetType offset
)
1810 AHCIIOTestOptions
*opts
;
1812 opts
= g_malloc(sizeof(AHCIIOTestOptions
));
1814 opts
->address_type
= addr
;
1815 opts
->io_type
= type
;
1816 opts
->offset
= offset
;
1818 name
= g_strdup_printf("ahci/io/%s/%s/%s/%s",
1820 addr_mode_str
[addr
],
1822 offset_str
[offset
]);
1824 if ((addr
== ADDR_MODE_LBA48
) && (offset
== OFFSET_HIGH
) &&
1825 (mb_to_sectors(test_image_size_mb
) <= 0xFFFFFFF)) {
1826 g_test_message("%s: skipped; test image too small", name
);
1831 qtest_add_data_func(name
, opts
, test_io_interface
);
1835 /******************************************************************************/
1837 int main(int argc
, char **argv
)
1845 static struct option long_options
[] = {
1846 {"pedantic", no_argument
, 0, 'p' },
1850 /* Should be first to utilize g_test functionality, So we can see errors. */
1851 g_test_init(&argc
, &argv
, NULL
);
1854 c
= getopt_long(argc
, argv
, "", long_options
, NULL
);
1865 fprintf(stderr
, "Unrecognized ahci_test option.\n");
1866 g_assert_not_reached();
1870 /* Check architecture */
1871 arch
= qtest_get_arch();
1872 if (strcmp(arch
, "i386") && strcmp(arch
, "x86_64")) {
1873 g_test_message("Skipping test for non-x86");
1877 /* Create a temporary image */
1878 fd
= mkstemp(tmp_path
);
1880 if (have_qemu_img()) {
1882 test_image_size_mb
= TEST_IMAGE_SIZE_MB_LARGE
;
1883 mkqcow2(tmp_path
, TEST_IMAGE_SIZE_MB_LARGE
);
1885 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; "
1886 "skipping LBA48 high-sector tests");
1888 test_image_size_mb
= TEST_IMAGE_SIZE_MB_SMALL
;
1889 ret
= ftruncate(fd
, test_image_size_mb
* 1024 * 1024);
1894 /* Create temporary blkdebug instructions */
1895 fd
= mkstemp(debug_path
);
1899 /* Reserve a hollow file to use as a socket for migration tests */
1900 fd
= mkstemp(mig_socket
);
1905 qtest_add_func("/ahci/sanity", test_sanity
);
1906 qtest_add_func("/ahci/pci_spec", test_pci_spec
);
1907 qtest_add_func("/ahci/pci_enable", test_pci_enable
);
1908 qtest_add_func("/ahci/hba_spec", test_hba_spec
);
1909 qtest_add_func("/ahci/hba_enable", test_hba_enable
);
1910 qtest_add_func("/ahci/identify", test_identify
);
1912 for (i
= MODE_BEGIN
; i
< NUM_MODES
; i
++) {
1913 for (j
= ADDR_MODE_BEGIN
; j
< NUM_ADDR_MODES
; j
++) {
1914 for (k
= LEN_BEGIN
; k
< NUM_LENGTHS
; k
++) {
1915 for (m
= OFFSET_BEGIN
; m
< NUM_OFFSETS
; m
++) {
1916 create_ahci_io_test(i
, j
, k
, m
);
1922 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented
);
1924 qtest_add_func("/ahci/flush/simple", test_flush
);
1925 qtest_add_func("/ahci/flush/retry", test_flush_retry
);
1926 qtest_add_func("/ahci/flush/migrate", test_flush_migrate
);
1928 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity
);
1929 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma
);
1930 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma
);
1931 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma
);
1933 qtest_add_func("/ahci/max", test_max
);
1934 qtest_add_func("/ahci/reset", test_reset
);
1936 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple
);
1937 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq
);
1938 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq
);
1939 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq
);
1941 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma
);
1942 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi
);
1943 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio
);
1944 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi
);
1946 qtest_add_func("/ahci/cdrom/pio/bcl", test_atapi_bcl
);
1947 qtest_add_func("/ahci/cdrom/eject", test_atapi_tray
);