memory: cpu_physical_memory_set_dirty_tracking() should return void
[qemu/ar7.git] / cputlb.c
blob0ac8d90a487b8cb13d83a801b640a132c1d5f1ca
1 /*
2 * Common CPU TLB handling
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "config.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "exec/memory.h"
24 #include "exec/address-spaces.h"
26 #include "exec/cputlb.h"
28 #include "exec/memory-internal.h"
30 //#define DEBUG_TLB
31 //#define DEBUG_TLB_CHECK
33 /* statistics */
34 int tlb_flush_count;
36 /* NOTE:
37 * If flush_global is true (the usual case), flush all tlb entries.
38 * If flush_global is false, flush (at least) all tlb entries not
39 * marked global.
41 * Since QEMU doesn't currently implement a global/not-global flag
42 * for tlb entries, at the moment tlb_flush() will also flush all
43 * tlb entries in the flush_global == false case. This is OK because
44 * CPU architectures generally permit an implementation to drop
45 * entries from the TLB at any time, so flushing more entries than
46 * required is only an efficiency issue, not a correctness issue.
48 void tlb_flush(CPUArchState *env, int flush_global)
50 CPUState *cpu = ENV_GET_CPU(env);
52 #if defined(DEBUG_TLB)
53 printf("tlb_flush:\n");
54 #endif
55 /* must reset current TB so that interrupts cannot modify the
56 links while we are modifying them */
57 cpu->current_tb = NULL;
59 memset(env->tlb_table, -1, sizeof(env->tlb_table));
60 memset(env->tb_jmp_cache, 0, sizeof(env->tb_jmp_cache));
62 env->tlb_flush_addr = -1;
63 env->tlb_flush_mask = 0;
64 tlb_flush_count++;
67 static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
69 if (addr == (tlb_entry->addr_read &
70 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
71 addr == (tlb_entry->addr_write &
72 (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
73 addr == (tlb_entry->addr_code &
74 (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
75 memset(tlb_entry, -1, sizeof(*tlb_entry));
79 void tlb_flush_page(CPUArchState *env, target_ulong addr)
81 CPUState *cpu = ENV_GET_CPU(env);
82 int i;
83 int mmu_idx;
85 #if defined(DEBUG_TLB)
86 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
87 #endif
88 /* Check if we need to flush due to large pages. */
89 if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
90 #if defined(DEBUG_TLB)
91 printf("tlb_flush_page: forced full flush ("
92 TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
93 env->tlb_flush_addr, env->tlb_flush_mask);
94 #endif
95 tlb_flush(env, 1);
96 return;
98 /* must reset current TB so that interrupts cannot modify the
99 links while we are modifying them */
100 cpu->current_tb = NULL;
102 addr &= TARGET_PAGE_MASK;
103 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
104 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
105 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
108 tb_flush_jmp_cache(env, addr);
111 /* update the TLBs so that writes to code in the virtual page 'addr'
112 can be detected */
113 void tlb_protect_code(ram_addr_t ram_addr)
115 cpu_physical_memory_reset_dirty(ram_addr, TARGET_PAGE_SIZE,
116 DIRTY_MEMORY_CODE);
119 /* update the TLB so that writes in physical page 'phys_addr' are no longer
120 tested for self modifying code */
121 void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
122 target_ulong vaddr)
124 cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE);
127 static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe)
129 return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0;
132 void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
133 uintptr_t length)
135 uintptr_t addr;
137 if (tlb_is_dirty_ram(tlb_entry)) {
138 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
139 if ((addr - start) < length) {
140 tlb_entry->addr_write |= TLB_NOTDIRTY;
145 static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
147 ram_addr_t ram_addr;
149 if (qemu_ram_addr_from_host(ptr, &ram_addr) == NULL) {
150 fprintf(stderr, "Bad ram pointer %p\n", ptr);
151 abort();
153 return ram_addr;
156 void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length)
158 CPUState *cpu;
159 CPUArchState *env;
161 CPU_FOREACH(cpu) {
162 int mmu_idx;
164 env = cpu->env_ptr;
165 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
166 unsigned int i;
168 for (i = 0; i < CPU_TLB_SIZE; i++) {
169 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
170 start1, length);
176 static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
178 if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY)) {
179 tlb_entry->addr_write = vaddr;
183 /* update the TLB corresponding to virtual page vaddr
184 so that it is no longer dirty */
185 void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
187 int i;
188 int mmu_idx;
190 vaddr &= TARGET_PAGE_MASK;
191 i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
192 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
193 tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
197 /* Our TLB does not support large pages, so remember the area covered by
198 large pages and trigger a full TLB flush if these are invalidated. */
199 static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
200 target_ulong size)
202 target_ulong mask = ~(size - 1);
204 if (env->tlb_flush_addr == (target_ulong)-1) {
205 env->tlb_flush_addr = vaddr & mask;
206 env->tlb_flush_mask = mask;
207 return;
209 /* Extend the existing region to include the new page.
210 This is a compromise between unnecessary flushes and the cost
211 of maintaining a full variable size TLB. */
212 mask &= env->tlb_flush_mask;
213 while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
214 mask <<= 1;
216 env->tlb_flush_addr &= mask;
217 env->tlb_flush_mask = mask;
220 /* Add a new TLB entry. At most one entry for a given virtual address
221 is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
222 supplied size is only used by tlb_flush_page. */
223 void tlb_set_page(CPUArchState *env, target_ulong vaddr,
224 hwaddr paddr, int prot,
225 int mmu_idx, target_ulong size)
227 MemoryRegionSection *section;
228 unsigned int index;
229 target_ulong address;
230 target_ulong code_address;
231 uintptr_t addend;
232 CPUTLBEntry *te;
233 hwaddr iotlb, xlat, sz;
235 assert(size >= TARGET_PAGE_SIZE);
236 if (size != TARGET_PAGE_SIZE) {
237 tlb_add_large_page(env, vaddr, size);
240 sz = size;
241 section = address_space_translate_for_iotlb(&address_space_memory, paddr,
242 &xlat, &sz);
243 assert(sz >= TARGET_PAGE_SIZE);
245 #if defined(DEBUG_TLB)
246 printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
247 " prot=%x idx=%d\n",
248 vaddr, paddr, prot, mmu_idx);
249 #endif
251 address = vaddr;
252 if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) {
253 /* IO memory case */
254 address |= TLB_MMIO;
255 addend = 0;
256 } else {
257 /* TLB_MMIO for rom/romd handled below */
258 addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat;
261 code_address = address;
262 iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, xlat,
263 prot, &address);
265 index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
266 env->iotlb[mmu_idx][index] = iotlb - vaddr;
267 te = &env->tlb_table[mmu_idx][index];
268 te->addend = addend - vaddr;
269 if (prot & PAGE_READ) {
270 te->addr_read = address;
271 } else {
272 te->addr_read = -1;
275 if (prot & PAGE_EXEC) {
276 te->addr_code = code_address;
277 } else {
278 te->addr_code = -1;
280 if (prot & PAGE_WRITE) {
281 if ((memory_region_is_ram(section->mr) && section->readonly)
282 || memory_region_is_romd(section->mr)) {
283 /* Write access calls the I/O callback. */
284 te->addr_write = address | TLB_MMIO;
285 } else if (memory_region_is_ram(section->mr)
286 && cpu_physical_memory_is_clean(section->mr->ram_addr
287 + xlat)) {
288 te->addr_write = address | TLB_NOTDIRTY;
289 } else {
290 te->addr_write = address;
292 } else {
293 te->addr_write = -1;
297 /* NOTE: this function can trigger an exception */
298 /* NOTE2: the returned address is not exactly the physical address: it
299 * is actually a ram_addr_t (in system mode; the user mode emulation
300 * version of this function returns a guest virtual address).
302 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
304 int mmu_idx, page_index, pd;
305 void *p;
306 MemoryRegion *mr;
308 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
309 mmu_idx = cpu_mmu_index(env1);
310 if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
311 (addr & TARGET_PAGE_MASK))) {
312 cpu_ldub_code(env1, addr);
314 pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
315 mr = iotlb_to_region(pd);
316 if (memory_region_is_unassigned(mr)) {
317 CPUState *cpu = ENV_GET_CPU(env1);
318 CPUClass *cc = CPU_GET_CLASS(cpu);
320 if (cc->do_unassigned_access) {
321 cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
322 } else {
323 cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
324 TARGET_FMT_lx "\n", addr);
327 p = (void *)((uintptr_t)addr + env1->tlb_table[mmu_idx][page_index].addend);
328 return qemu_ram_addr_from_host_nofail(p);
331 #define MMUSUFFIX _cmmu
332 #undef GETPC
333 #define GETPC() ((uintptr_t)0)
334 #define SOFTMMU_CODE_ACCESS
336 #define SHIFT 0
337 #include "exec/softmmu_template.h"
339 #define SHIFT 1
340 #include "exec/softmmu_template.h"
342 #define SHIFT 2
343 #include "exec/softmmu_template.h"
345 #define SHIFT 3
346 #include "exec/softmmu_template.h"
348 #undef env