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qdev: Convert to qdev_unrealize() with Coccinelle
[qemu/ar7.git] / hw / i386 / pc.c
bloba5dd6252fa7da66502e9df8558c0cdc0d050b0a8
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "hw/i386/vmport.h"
35 #include "sysemu/cpus.h"
36 #include "hw/block/fdc.h"
37 #include "hw/ide.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/nvram/fw_cfg.h"
41 #include "hw/timer/hpet.h"
42 #include "hw/firmware/smbios.h"
43 #include "hw/loader.h"
44 #include "elf.h"
45 #include "migration/vmstate.h"
46 #include "multiboot.h"
47 #include "hw/rtc/mc146818rtc.h"
48 #include "hw/intc/i8259.h"
49 #include "hw/dma/i8257.h"
50 #include "hw/timer/i8254.h"
51 #include "hw/input/i8042.h"
52 #include "hw/irq.h"
53 #include "hw/audio/pcspk.h"
54 #include "hw/pci/msi.h"
55 #include "hw/sysbus.h"
56 #include "sysemu/sysemu.h"
57 #include "sysemu/tcg.h"
58 #include "sysemu/numa.h"
59 #include "sysemu/kvm.h"
60 #include "sysemu/xen.h"
61 #include "sysemu/qtest.h"
62 #include "sysemu/reset.h"
63 #include "sysemu/runstate.h"
64 #include "kvm_i386.h"
65 #include "hw/xen/xen.h"
66 #include "hw/xen/start_info.h"
67 #include "ui/qemu-spice.h"
68 #include "exec/memory.h"
69 #include "exec/address-spaces.h"
70 #include "sysemu/arch_init.h"
71 #include "qemu/bitmap.h"
72 #include "qemu/config-file.h"
73 #include "qemu/error-report.h"
74 #include "qemu/option.h"
75 #include "qemu/cutils.h"
76 #include "hw/acpi/acpi.h"
77 #include "hw/acpi/cpu_hotplug.h"
78 #include "hw/boards.h"
79 #include "acpi-build.h"
80 #include "hw/mem/pc-dimm.h"
81 #include "hw/mem/nvdimm.h"
82 #include "qapi/error.h"
83 #include "qapi/qapi-visit-common.h"
84 #include "qapi/visitor.h"
85 #include "hw/core/cpu.h"
86 #include "hw/usb.h"
87 #include "hw/i386/intel_iommu.h"
88 #include "hw/net/ne2000-isa.h"
89 #include "standard-headers/asm-x86/bootparam.h"
90 #include "hw/virtio/virtio-pmem-pci.h"
91 #include "hw/mem/memory-device.h"
92 #include "sysemu/replay.h"
93 #include "qapi/qmp/qerror.h"
94 #include "config-devices.h"
95 #include "e820_memory_layout.h"
96 #include "fw_cfg.h"
97 #include "trace.h"
98
99 GlobalProperty pc_compat_5_0[] = {};
100 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
101
102 GlobalProperty pc_compat_4_2[] = {
103 { "mch", "smbase-smram", "off" },
104 };
105 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
106
107 GlobalProperty pc_compat_4_1[] = {};
108 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
109
110 GlobalProperty pc_compat_4_0[] = {};
111 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
112
113 GlobalProperty pc_compat_3_1[] = {
114 { "intel-iommu", "dma-drain", "off" },
115 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
116 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
117 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
118 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
119 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
120 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
121 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
122 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
123 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
124 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
125 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
126 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
127 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
128 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
129 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
130 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
131 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
132 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
133 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
134 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
135 };
136 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
137
138 GlobalProperty pc_compat_3_0[] = {
139 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
140 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
141 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
142 };
143 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
144
145 GlobalProperty pc_compat_2_12[] = {
146 { TYPE_X86_CPU, "legacy-cache", "on" },
147 { TYPE_X86_CPU, "topoext", "off" },
148 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
149 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
150 };
151 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
152
153 GlobalProperty pc_compat_2_11[] = {
154 { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
155 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
156 };
157 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
158
159 GlobalProperty pc_compat_2_10[] = {
160 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
161 { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
162 { "q35-pcihost", "x-pci-hole64-fix", "off" },
163 };
164 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
165
166 GlobalProperty pc_compat_2_9[] = {
167 { "mch", "extended-tseg-mbytes", "0" },
168 };
169 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
170
171 GlobalProperty pc_compat_2_8[] = {
172 { TYPE_X86_CPU, "tcg-cpuid", "off" },
173 { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
174 { "ICH9-LPC", "x-smi-broadcast", "off" },
175 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
176 { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
177 };
178 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
179
180 GlobalProperty pc_compat_2_7[] = {
181 { TYPE_X86_CPU, "l3-cache", "off" },
182 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
183 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
184 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
185 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
186 { "isa-pcspk", "migrate", "off" },
187 };
188 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
189
190 GlobalProperty pc_compat_2_6[] = {
191 { TYPE_X86_CPU, "cpuid-0xb", "off" },
192 { "vmxnet3", "romfile", "" },
193 { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
194 { "apic-common", "legacy-instance-id", "on", }
195 };
196 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
197
198 GlobalProperty pc_compat_2_5[] = {};
199 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
200
201 GlobalProperty pc_compat_2_4[] = {
202 PC_CPU_MODEL_IDS("2.4.0")
203 { "Haswell-" TYPE_X86_CPU, "abm", "off" },
204 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
205 { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
206 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
207 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
208 { TYPE_X86_CPU, "check", "off" },
209 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
210 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
211 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
212 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
213 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
214 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
215 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
216 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
217 };
218 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
219
220 GlobalProperty pc_compat_2_3[] = {
221 PC_CPU_MODEL_IDS("2.3.0")
222 { TYPE_X86_CPU, "arat", "off" },
223 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
224 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
225 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
226 { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
227 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
228 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
229 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
230 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
231 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
232 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
233 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
234 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
235 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
236 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
237 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
238 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
239 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
240 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
241 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
242 };
243 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
244
245 GlobalProperty pc_compat_2_2[] = {
246 PC_CPU_MODEL_IDS("2.2.0")
247 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
248 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
249 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
250 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
251 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
252 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
253 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
254 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
255 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
256 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
257 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
258 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
259 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
260 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
261 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
262 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
263 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
264 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
265 };
266 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
267
268 GlobalProperty pc_compat_2_1[] = {
269 PC_CPU_MODEL_IDS("2.1.0")
270 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
271 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
272 };
273 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
274
275 GlobalProperty pc_compat_2_0[] = {
276 PC_CPU_MODEL_IDS("2.0.0")
277 { "virtio-scsi-pci", "any_layout", "off" },
278 { "PIIX4_PM", "memory-hotplug-support", "off" },
279 { "apic", "version", "0x11" },
280 { "nec-usb-xhci", "superspeed-ports-first", "off" },
281 { "nec-usb-xhci", "force-pcie-endcap", "on" },
282 { "pci-serial", "prog_if", "0" },
283 { "pci-serial-2x", "prog_if", "0" },
284 { "pci-serial-4x", "prog_if", "0" },
285 { "virtio-net-pci", "guest_announce", "off" },
286 { "ICH9-LPC", "memory-hotplug-support", "off" },
287 { "xio3130-downstream", COMPAT_PROP_PCP, "off" },
288 { "ioh3420", COMPAT_PROP_PCP, "off" },
289 };
290 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
291
292 GlobalProperty pc_compat_1_7[] = {
293 PC_CPU_MODEL_IDS("1.7.0")
294 { TYPE_USB_DEVICE, "msos-desc", "no" },
295 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
296 { "hpet", HPET_INTCAP, "4" },
297 };
298 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
299
300 GlobalProperty pc_compat_1_6[] = {
301 PC_CPU_MODEL_IDS("1.6.0")
302 { "e1000", "mitigation", "off" },
303 { "qemu64-" TYPE_X86_CPU, "model", "2" },
304 { "qemu32-" TYPE_X86_CPU, "model", "3" },
305 { "i440FX-pcihost", "short_root_bus", "1" },
306 { "q35-pcihost", "short_root_bus", "1" },
307 };
308 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
309
310 GlobalProperty pc_compat_1_5[] = {
311 PC_CPU_MODEL_IDS("1.5.0")
312 { "Conroe-" TYPE_X86_CPU, "model", "2" },
313 { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
314 { "Penryn-" TYPE_X86_CPU, "model", "2" },
315 { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
316 { "Nehalem-" TYPE_X86_CPU, "model", "2" },
317 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
318 { "virtio-net-pci", "any_layout", "off" },
319 { TYPE_X86_CPU, "pmu", "on" },
320 { "i440FX-pcihost", "short_root_bus", "0" },
321 { "q35-pcihost", "short_root_bus", "0" },
322 };
323 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
324
325 GlobalProperty pc_compat_1_4[] = {
326 PC_CPU_MODEL_IDS("1.4.0")
327 { "scsi-hd", "discard_granularity", "0" },
328 { "scsi-cd", "discard_granularity", "0" },
329 { "scsi-disk", "discard_granularity", "0" },
330 { "ide-hd", "discard_granularity", "0" },
331 { "ide-cd", "discard_granularity", "0" },
332 { "ide-drive", "discard_granularity", "0" },
333 { "virtio-blk-pci", "discard_granularity", "0" },
334 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
335 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
336 { "virtio-net-pci", "ctrl_guest_offloads", "off" },
337 { "e1000", "romfile", "pxe-e1000.rom" },
338 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
339 { "pcnet", "romfile", "pxe-pcnet.rom" },
340 { "rtl8139", "romfile", "pxe-rtl8139.rom" },
341 { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
342 { "486-" TYPE_X86_CPU, "model", "0" },
343 { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
344 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
345 };
346 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
347
348 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
349 {
350 GSIState *s;
351
352 s = g_new0(GSIState, 1);
353 if (kvm_ioapic_in_kernel()) {
354 kvm_pc_setup_irq_routing(pci_enabled);
355 }
356 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
357
358 return s;
359 }
360
361 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
362 unsigned size)
363 {
364 }
365
366 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
367 {
368 return 0xffffffffffffffffULL;
369 }
370
371 /* MSDOS compatibility mode FPU exception support */
372 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
373 unsigned size)
374 {
375 if (tcg_enabled()) {
376 cpu_set_ignne();
377 }
378 }
379
380 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
381 {
382 return 0xffffffffffffffffULL;
383 }
384
385 /* PC cmos mappings */
386
387 #define REG_EQUIPMENT_BYTE 0x14
388
389 int cmos_get_fd_drive_type(FloppyDriveType fd0)
390 {
391 int val;
392
393 switch (fd0) {
394 case FLOPPY_DRIVE_TYPE_144:
395 /* 1.44 Mb 3"5 drive */
396 val = 4;
397 break;
398 case FLOPPY_DRIVE_TYPE_288:
399 /* 2.88 Mb 3"5 drive */
400 val = 5;
401 break;
402 case FLOPPY_DRIVE_TYPE_120:
403 /* 1.2 Mb 5"5 drive */
404 val = 2;
405 break;
406 case FLOPPY_DRIVE_TYPE_NONE:
407 default:
408 val = 0;
409 break;
410 }
411 return val;
412 }
413
414 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
415 int16_t cylinders, int8_t heads, int8_t sectors)
416 {
417 rtc_set_memory(s, type_ofs, 47);
418 rtc_set_memory(s, info_ofs, cylinders);
419 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
420 rtc_set_memory(s, info_ofs + 2, heads);
421 rtc_set_memory(s, info_ofs + 3, 0xff);
422 rtc_set_memory(s, info_ofs + 4, 0xff);
423 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
424 rtc_set_memory(s, info_ofs + 6, cylinders);
425 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
426 rtc_set_memory(s, info_ofs + 8, sectors);
427 }
428
429 /* convert boot_device letter to something recognizable by the bios */
430 static int boot_device2nibble(char boot_device)
431 {
432 switch(boot_device) {
433 case 'a':
434 case 'b':
435 return 0x01; /* floppy boot */
436 case 'c':
437 return 0x02; /* hard drive boot */
438 case 'd':
439 return 0x03; /* CD-ROM boot */
440 case 'n':
441 return 0x04; /* Network boot */
442 }
443 return 0;
444 }
445
446 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
447 {
448 #define PC_MAX_BOOT_DEVICES 3
449 int nbds, bds[3] = { 0, };
450 int i;
451
452 nbds = strlen(boot_device);
453 if (nbds > PC_MAX_BOOT_DEVICES) {
454 error_setg(errp, "Too many boot devices for PC");
455 return;
456 }
457 for (i = 0; i < nbds; i++) {
458 bds[i] = boot_device2nibble(boot_device[i]);
459 if (bds[i] == 0) {
460 error_setg(errp, "Invalid boot device for PC: '%c'",
461 boot_device[i]);
462 return;
463 }
464 }
465 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
466 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
467 }
468
469 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
470 {
471 set_boot_dev(opaque, boot_device, errp);
472 }
473
474 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
475 {
476 int val, nb, i;
477 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
478 FLOPPY_DRIVE_TYPE_NONE };
479
480 /* floppy type */
481 if (floppy) {
482 for (i = 0; i < 2; i++) {
483 fd_type[i] = isa_fdc_get_drive_type(floppy, i);
484 }
485 }
486 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
487 cmos_get_fd_drive_type(fd_type[1]);
488 rtc_set_memory(rtc_state, 0x10, val);
489
490 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
491 nb = 0;
492 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
493 nb++;
494 }
495 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
496 nb++;
497 }
498 switch (nb) {
499 case 0:
500 break;
501 case 1:
502 val |= 0x01; /* 1 drive, ready for boot */
503 break;
504 case 2:
505 val |= 0x41; /* 2 drives, ready for boot */
506 break;
507 }
508 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
509 }
510
511 typedef struct pc_cmos_init_late_arg {
512 ISADevice *rtc_state;
513 BusState *idebus[2];
514 } pc_cmos_init_late_arg;
515
516 typedef struct check_fdc_state {
517 ISADevice *floppy;
518 bool multiple;
519 } CheckFdcState;
520
521 static int check_fdc(Object *obj, void *opaque)
522 {
523 CheckFdcState *state = opaque;
524 Object *fdc;
525 uint32_t iobase;
526 Error *local_err = NULL;
527
528 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
529 if (!fdc) {
530 return 0;
531 }
532
533 iobase = object_property_get_uint(obj, "iobase", &local_err);
534 if (local_err || iobase != 0x3f0) {
535 error_free(local_err);
536 return 0;
537 }
538
539 if (state->floppy) {
540 state->multiple = true;
541 } else {
542 state->floppy = ISA_DEVICE(obj);
543 }
544 return 0;
545 }
546
547 static const char * const fdc_container_path[] = {
548 "/unattached", "/peripheral", "/peripheral-anon"
549 };
550
551 /*
552 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
553 * and ACPI objects.
554 */
555 ISADevice *pc_find_fdc0(void)
556 {
557 int i;
558 Object *container;
559 CheckFdcState state = { 0 };
560
561 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
562 container = container_get(qdev_get_machine(), fdc_container_path[i]);
563 object_child_foreach(container, check_fdc, &state);
564 }
565
566 if (state.multiple) {
567 warn_report("multiple floppy disk controllers with "
568 "iobase=0x3f0 have been found");
569 error_printf("the one being picked for CMOS setup might not reflect "
570 "your intent");
571 }
572
573 return state.floppy;
574 }
575
576 static void pc_cmos_init_late(void *opaque)
577 {
578 pc_cmos_init_late_arg *arg = opaque;
579 ISADevice *s = arg->rtc_state;
580 int16_t cylinders;
581 int8_t heads, sectors;
582 int val;
583 int i, trans;
584
585 val = 0;
586 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
587 &cylinders, &heads, &sectors) >= 0) {
588 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
589 val |= 0xf0;
590 }
591 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
592 &cylinders, &heads, &sectors) >= 0) {
593 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
594 val |= 0x0f;
595 }
596 rtc_set_memory(s, 0x12, val);
597
598 val = 0;
599 for (i = 0; i < 4; i++) {
600 /* NOTE: ide_get_geometry() returns the physical
601 geometry. It is always such that: 1 <= sects <= 63, 1
602 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
603 geometry can be different if a translation is done. */
604 if (arg->idebus[i / 2] &&
605 ide_get_geometry(arg->idebus[i / 2], i % 2,
606 &cylinders, &heads, &sectors) >= 0) {
607 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
608 assert((trans & ~3) == 0);
609 val |= trans << (i * 2);
610 }
611 }
612 rtc_set_memory(s, 0x39, val);
613
614 pc_cmos_init_floppy(s, pc_find_fdc0());
615
616 qemu_unregister_reset(pc_cmos_init_late, opaque);
617 }
618
619 void pc_cmos_init(PCMachineState *pcms,
620 BusState *idebus0, BusState *idebus1,
621 ISADevice *s)
622 {
623 int val;
624 static pc_cmos_init_late_arg arg;
625 X86MachineState *x86ms = X86_MACHINE(pcms);
626
627 /* various important CMOS locations needed by PC/Bochs bios */
628
629 /* memory size */
630 /* base memory (first MiB) */
631 val = MIN(x86ms->below_4g_mem_size / KiB, 640);
632 rtc_set_memory(s, 0x15, val);
633 rtc_set_memory(s, 0x16, val >> 8);
634 /* extended memory (next 64MiB) */
635 if (x86ms->below_4g_mem_size > 1 * MiB) {
636 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
637 } else {
638 val = 0;
639 }
640 if (val > 65535)
641 val = 65535;
642 rtc_set_memory(s, 0x17, val);
643 rtc_set_memory(s, 0x18, val >> 8);
644 rtc_set_memory(s, 0x30, val);
645 rtc_set_memory(s, 0x31, val >> 8);
646 /* memory between 16MiB and 4GiB */
647 if (x86ms->below_4g_mem_size > 16 * MiB) {
648 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
649 } else {
650 val = 0;
651 }
652 if (val > 65535)
653 val = 65535;
654 rtc_set_memory(s, 0x34, val);
655 rtc_set_memory(s, 0x35, val >> 8);
656 /* memory above 4GiB */
657 val = x86ms->above_4g_mem_size / 65536;
658 rtc_set_memory(s, 0x5b, val);
659 rtc_set_memory(s, 0x5c, val >> 8);
660 rtc_set_memory(s, 0x5d, val >> 16);
661
662 object_property_add_link(OBJECT(pcms), "rtc_state",
663 TYPE_ISA_DEVICE,
664 (Object **)&x86ms->rtc,
665 object_property_allow_set_link,
666 OBJ_PROP_LINK_STRONG);
667 object_property_set_link(OBJECT(pcms), OBJECT(s),
668 "rtc_state", &error_abort);
669
670 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
671
672 val = 0;
673 val |= 0x02; /* FPU is there */
674 val |= 0x04; /* PS/2 mouse installed */
675 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
676
677 /* hard drives and FDC */
678 arg.rtc_state = s;
679 arg.idebus[0] = idebus0;
680 arg.idebus[1] = idebus1;
681 qemu_register_reset(pc_cmos_init_late, &arg);
682 }
683
684 static void handle_a20_line_change(void *opaque, int irq, int level)
685 {
686 X86CPU *cpu = opaque;
687
688 /* XXX: send to all CPUs ? */
689 /* XXX: add logic to handle multiple A20 line sources */
690 x86_cpu_set_a20(cpu, level);
691 }
692
693 #define NE2000_NB_MAX 6
694
695 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
696 0x280, 0x380 };
697 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
698
699 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
700 {
701 static int nb_ne2k = 0;
702
703 if (nb_ne2k == NE2000_NB_MAX)
704 return;
705 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
706 ne2000_irq[nb_ne2k], nd);
707 nb_ne2k++;
708 }
709
710 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
711 {
712 X86CPU *cpu = opaque;
713
714 if (level) {
715 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
716 }
717 }
718
719 /*
720 * This function is very similar to smp_parse()
721 * in hw/core/machine.c but includes CPU die support.
722 */
723 void pc_smp_parse(MachineState *ms, QemuOpts *opts)
724 {
725 X86MachineState *x86ms = X86_MACHINE(ms);
726
727 if (opts) {
728 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0);
729 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0);
730 unsigned dies = qemu_opt_get_number(opts, "dies", 1);
731 unsigned cores = qemu_opt_get_number(opts, "cores", 0);
732 unsigned threads = qemu_opt_get_number(opts, "threads", 0);
733
734 /* compute missing values, prefer sockets over cores over threads */
735 if (cpus == 0 || sockets == 0) {
736 cores = cores > 0 ? cores : 1;
737 threads = threads > 0 ? threads : 1;
738 if (cpus == 0) {
739 sockets = sockets > 0 ? sockets : 1;
740 cpus = cores * threads * dies * sockets;
741 } else {
742 ms->smp.max_cpus =
743 qemu_opt_get_number(opts, "maxcpus", cpus);
744 sockets = ms->smp.max_cpus / (cores * threads * dies);
745 }
746 } else if (cores == 0) {
747 threads = threads > 0 ? threads : 1;
748 cores = cpus / (sockets * dies * threads);
749 cores = cores > 0 ? cores : 1;
750 } else if (threads == 0) {
751 threads = cpus / (cores * dies * sockets);
752 threads = threads > 0 ? threads : 1;
753 } else if (sockets * dies * cores * threads < cpus) {
754 error_report("cpu topology: "
755 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < "
756 "smp_cpus (%u)",
757 sockets, dies, cores, threads, cpus);
758 exit(1);
759 }
760
761 ms->smp.max_cpus =
762 qemu_opt_get_number(opts, "maxcpus", cpus);
763
764 if (ms->smp.max_cpus < cpus) {
765 error_report("maxcpus must be equal to or greater than smp");
766 exit(1);
767 }
768
769 if (sockets * dies * cores * threads > ms->smp.max_cpus) {
770 error_report("cpu topology: "
771 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > "
772 "maxcpus (%u)",
773 sockets, dies, cores, threads,
774 ms->smp.max_cpus);
775 exit(1);
776 }
777
778 if (sockets * dies * cores * threads != ms->smp.max_cpus) {
779 warn_report("Invalid CPU topology deprecated: "
780 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) "
781 "!= maxcpus (%u)",
782 sockets, dies, cores, threads,
783 ms->smp.max_cpus);
784 }
785
786 ms->smp.cpus = cpus;
787 ms->smp.cores = cores;
788 ms->smp.threads = threads;
789 ms->smp.sockets = sockets;
790 x86ms->smp_dies = dies;
791 }
792
793 if (ms->smp.cpus > 1) {
794 Error *blocker = NULL;
795 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp");
796 replay_add_blocker(blocker);
797 }
798 }
799
800 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp)
801 {
802 X86MachineState *x86ms = X86_MACHINE(ms);
803 int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id);
804 Error *local_err = NULL;
805
806 if (id < 0) {
807 error_setg(errp, "Invalid CPU id: %" PRIi64, id);
808 return;
809 }
810
811 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) {
812 error_setg(errp, "Unable to add CPU: %" PRIi64
813 ", resulting APIC ID (%" PRIi64 ") is too large",
814 id, apic_id);
815 return;
816 }
817
818
819 x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err);
820 if (local_err) {
821 error_propagate(errp, local_err);
822 return;
823 }
824 }
825
826 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count)
827 {
828 if (cpus_count > 0xff) {
829 /* If the number of CPUs can't be represented in 8 bits, the
830 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just
831 * to make old BIOSes fail more predictably.
832 */
833 rtc_set_memory(rtc, 0x5f, 0);
834 } else {
835 rtc_set_memory(rtc, 0x5f, cpus_count - 1);
836 }
837 }
838
839 static
840 void pc_machine_done(Notifier *notifier, void *data)
841 {
842 PCMachineState *pcms = container_of(notifier,
843 PCMachineState, machine_done);
844 X86MachineState *x86ms = X86_MACHINE(pcms);
845 PCIBus *bus = pcms->bus;
846
847 /* set the number of CPUs */
848 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
849
850 if (bus) {
851 int extra_hosts = 0;
852
853 QLIST_FOREACH(bus, &bus->child, sibling) {
854 /* look for expander root buses */
855 if (pci_bus_is_root(bus)) {
856 extra_hosts++;
857 }
858 }
859 if (extra_hosts && x86ms->fw_cfg) {
860 uint64_t *val = g_malloc(sizeof(*val));
861 *val = cpu_to_le64(extra_hosts);
862 fw_cfg_add_file(x86ms->fw_cfg,
863 "etc/extra-pci-roots", val, sizeof(*val));
864 }
865 }
866
867 acpi_setup();
868 if (x86ms->fw_cfg) {
869 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
870 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
871 /* update FW_CFG_NB_CPUS to account for -device added CPUs */
872 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
873 }
874
875 if (x86ms->apic_id_limit > 255 && !xen_enabled()) {
876 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default());
877
878 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) ||
879 iommu->intr_eim != ON_OFF_AUTO_ON) {
880 error_report("current -smp configuration requires "
881 "Extended Interrupt Mode enabled. "
882 "You can add an IOMMU using: "
883 "-device intel-iommu,intremap=on,eim=on");
884 exit(EXIT_FAILURE);
885 }
886 }
887 }
888
889 void pc_guest_info_init(PCMachineState *pcms)
890 {
891 int i;
892 MachineState *ms = MACHINE(pcms);
893 X86MachineState *x86ms = X86_MACHINE(pcms);
894
895 x86ms->apic_xrupt_override = kvm_allows_irq0_override();
896 pcms->numa_nodes = ms->numa_state->num_nodes;
897 pcms->node_mem = g_malloc0(pcms->numa_nodes *
898 sizeof *pcms->node_mem);
899 for (i = 0; i < ms->numa_state->num_nodes; i++) {
900 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem;
901 }
902
903 pcms->machine_done.notify = pc_machine_done;
904 qemu_add_machine_init_done_notifier(&pcms->machine_done);
905 }
906
907 /* setup pci memory address space mapping into system address space */
908 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
909 MemoryRegion *pci_address_space)
910 {
911 /* Set to lower priority than RAM */
912 memory_region_add_subregion_overlap(system_memory, 0x0,
913 pci_address_space, -1);
914 }
915
916 void xen_load_linux(PCMachineState *pcms)
917 {
918 int i;
919 FWCfgState *fw_cfg;
920 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
921 X86MachineState *x86ms = X86_MACHINE(pcms);
922
923 assert(MACHINE(pcms)->kernel_filename != NULL);
924
925 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
926 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
927 rom_set_fw(fw_cfg);
928
929 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
930 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
931 for (i = 0; i < nb_option_roms; i++) {
932 assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
933 !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
934 !strcmp(option_rom[i].name, "pvh.bin") ||
935 !strcmp(option_rom[i].name, "multiboot.bin"));
936 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
937 }
938 x86ms->fw_cfg = fw_cfg;
939 }
940
941 void pc_memory_init(PCMachineState *pcms,
942 MemoryRegion *system_memory,
943 MemoryRegion *rom_memory,
944 MemoryRegion **ram_memory)
945 {
946 int linux_boot, i;
947 MemoryRegion *option_rom_mr;
948 MemoryRegion *ram_below_4g, *ram_above_4g;
949 FWCfgState *fw_cfg;
950 MachineState *machine = MACHINE(pcms);
951 MachineClass *mc = MACHINE_GET_CLASS(machine);
952 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
953 X86MachineState *x86ms = X86_MACHINE(pcms);
954
955 assert(machine->ram_size == x86ms->below_4g_mem_size +
956 x86ms->above_4g_mem_size);
957
958 linux_boot = (machine->kernel_filename != NULL);
959
960 /*
961 * Split single memory region and use aliases to address portions of it,
962 * done for backwards compatibility with older qemus.
963 */
964 *ram_memory = machine->ram;
965 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
966 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
967 0, x86ms->below_4g_mem_size);
968 memory_region_add_subregion(system_memory, 0, ram_below_4g);
969 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
970 if (x86ms->above_4g_mem_size > 0) {
971 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
972 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
973 machine->ram,
974 x86ms->below_4g_mem_size,
975 x86ms->above_4g_mem_size);
976 memory_region_add_subregion(system_memory, 0x100000000ULL,
977 ram_above_4g);
978 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM);
979 }
980
981 if (!pcmc->has_reserved_memory &&
982 (machine->ram_slots ||
983 (machine->maxram_size > machine->ram_size))) {
984
985 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
986 mc->name);
987 exit(EXIT_FAILURE);
988 }
989
990 /* always allocate the device memory information */
991 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
992
993 /* initialize device memory address space */
994 if (pcmc->has_reserved_memory &&
995 (machine->ram_size < machine->maxram_size)) {
996 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
997
998 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
999 error_report("unsupported amount of memory slots: %"PRIu64,
1000 machine->ram_slots);
1001 exit(EXIT_FAILURE);
1002 }
1003
1004 if (QEMU_ALIGN_UP(machine->maxram_size,
1005 TARGET_PAGE_SIZE) != machine->maxram_size) {
1006 error_report("maximum memory size must by aligned to multiple of "
1007 "%d bytes", TARGET_PAGE_SIZE);
1008 exit(EXIT_FAILURE);
1009 }
1010
1011 machine->device_memory->base =
1012 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB);
1013
1014 if (pcmc->enforce_aligned_dimm) {
1015 /* size device region assuming 1G page max alignment per slot */
1016 device_mem_size += (1 * GiB) * machine->ram_slots;
1017 }
1018
1019 if ((machine->device_memory->base + device_mem_size) <
1020 device_mem_size) {
1021 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1022 machine->maxram_size);
1023 exit(EXIT_FAILURE);
1024 }
1025
1026 memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1027 "device-memory", device_mem_size);
1028 memory_region_add_subregion(system_memory, machine->device_memory->base,
1029 &machine->device_memory->mr);
1030 }
1031
1032 /* Initialize PC system firmware */
1033 pc_system_firmware_init(pcms, rom_memory);
1034
1035 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1036 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1037 &error_fatal);
1038 if (pcmc->pci_enabled) {
1039 memory_region_set_readonly(option_rom_mr, true);
1040 }
1041 memory_region_add_subregion_overlap(rom_memory,
1042 PC_ROM_MIN_VGA,
1043 option_rom_mr,
1044 1);
1045
1046 fw_cfg = fw_cfg_arch_create(machine,
1047 x86ms->boot_cpus, x86ms->apic_id_limit);
1048
1049 rom_set_fw(fw_cfg);
1050
1051 if (pcmc->has_reserved_memory && machine->device_memory->base) {
1052 uint64_t *val = g_malloc(sizeof(*val));
1053 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1054 uint64_t res_mem_end = machine->device_memory->base;
1055
1056 if (!pcmc->broken_reserved_end) {
1057 res_mem_end += memory_region_size(&machine->device_memory->mr);
1058 }
1059 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1060 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1061 }
1062
1063 if (linux_boot) {
1064 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1065 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled);
1066 }
1067
1068 for (i = 0; i < nb_option_roms; i++) {
1069 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1070 }
1071 x86ms->fw_cfg = fw_cfg;
1072
1073 /* Init default IOAPIC address space */
1074 x86ms->ioapic_as = &address_space_memory;
1075
1076 /* Init ACPI memory hotplug IO base address */
1077 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1078 }
1079
1080 /*
1081 * The 64bit pci hole starts after "above 4G RAM" and
1082 * potentially the space reserved for memory hotplug.
1083 */
1084 uint64_t pc_pci_hole64_start(void)
1085 {
1086 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1087 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1088 MachineState *ms = MACHINE(pcms);
1089 X86MachineState *x86ms = X86_MACHINE(pcms);
1090 uint64_t hole64_start = 0;
1091
1092 if (pcmc->has_reserved_memory && ms->device_memory->base) {
1093 hole64_start = ms->device_memory->base;
1094 if (!pcmc->broken_reserved_end) {
1095 hole64_start += memory_region_size(&ms->device_memory->mr);
1096 }
1097 } else {
1098 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size;
1099 }
1100
1101 return ROUND_UP(hole64_start, 1 * GiB);
1102 }
1103
1104 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1105 {
1106 DeviceState *dev = NULL;
1107
1108 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1109 if (pci_bus) {
1110 PCIDevice *pcidev = pci_vga_init(pci_bus);
1111 dev = pcidev ? &pcidev->qdev : NULL;
1112 } else if (isa_bus) {
1113 ISADevice *isadev = isa_vga_init(isa_bus);
1114 dev = isadev ? DEVICE(isadev) : NULL;
1115 }
1116 rom_reset_order_override();
1117 return dev;
1118 }
1119
1120 static const MemoryRegionOps ioport80_io_ops = {
1121 .write = ioport80_write,
1122 .read = ioport80_read,
1123 .endianness = DEVICE_NATIVE_ENDIAN,
1124 .impl = {
1125 .min_access_size = 1,
1126 .max_access_size = 1,
1127 },
1128 };
1129
1130 static const MemoryRegionOps ioportF0_io_ops = {
1131 .write = ioportF0_write,
1132 .read = ioportF0_read,
1133 .endianness = DEVICE_NATIVE_ENDIAN,
1134 .impl = {
1135 .min_access_size = 1,
1136 .max_access_size = 1,
1137 },
1138 };
1139
1140 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport)
1141 {
1142 int i;
1143 DriveInfo *fd[MAX_FD];
1144 qemu_irq *a20_line;
1145 ISADevice *i8042, *port92, *vmmouse;
1146
1147 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1148 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1149
1150 for (i = 0; i < MAX_FD; i++) {
1151 fd[i] = drive_get(IF_FLOPPY, 0, i);
1152 create_fdctrl |= !!fd[i];
1153 }
1154 if (create_fdctrl) {
1155 fdctrl_init_isa(isa_bus, fd);
1156 }
1157
1158 i8042 = isa_create_simple(isa_bus, "i8042");
1159 if (!no_vmport) {
1160 isa_create_simple(isa_bus, TYPE_VMPORT);
1161 vmmouse = isa_try_create(isa_bus, "vmmouse");
1162 } else {
1163 vmmouse = NULL;
1164 }
1165 if (vmmouse) {
1166 object_property_set_link(OBJECT(vmmouse), OBJECT(i8042),
1167 "i8042", &error_abort);
1168 qdev_init_nofail(DEVICE(vmmouse));
1169 }
1170 port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1171
1172 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1173 i8042_setup_a20_line(i8042, a20_line[0]);
1174 qdev_connect_gpio_out_named(DEVICE(port92),
1175 PORT92_A20_LINE, 0, a20_line[1]);
1176 g_free(a20_line);
1177 }
1178
1179 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1180 ISADevice **rtc_state,
1181 bool create_fdctrl,
1182 bool no_vmport,
1183 bool has_pit,
1184 uint32_t hpet_irqs)
1185 {
1186 int i;
1187 DeviceState *hpet = NULL;
1188 int pit_isa_irq = 0;
1189 qemu_irq pit_alt_irq = NULL;
1190 qemu_irq rtc_irq = NULL;
1191 ISADevice *pit = NULL;
1192 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1193 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1194
1195 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1196 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1197
1198 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1199 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1200
1201 /*
1202 * Check if an HPET shall be created.
1203 *
1204 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1205 * when the HPET wants to take over. Thus we have to disable the latter.
1206 */
1207 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1208 hpet = qdev_try_create(NULL, TYPE_HPET);
1209 if (hpet) {
1210 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7
1211 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23,
1212 * IRQ8 and IRQ2.
1213 */
1214 uint8_t compat = object_property_get_uint(OBJECT(hpet),
1215 HPET_INTCAP, NULL);
1216 if (!compat) {
1217 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1218 }
1219 qdev_init_nofail(hpet);
1220 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1221
1222 for (i = 0; i < GSI_NUM_PINS; i++) {
1223 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1224 }
1225 pit_isa_irq = -1;
1226 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1227 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1228 }
1229 }
1230 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1231
1232 qemu_register_boot_set(pc_boot_set, *rtc_state);
1233
1234 if (!xen_enabled() && has_pit) {
1235 if (kvm_pit_in_kernel()) {
1236 pit = kvm_pit_init(isa_bus, 0x40);
1237 } else {
1238 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1239 }
1240 if (hpet) {
1241 /* connect PIT to output control line of the HPET */
1242 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1243 }
1244 pcspk_init(isa_bus, pit);
1245 }
1246
1247 i8257_dma_init(isa_bus, 0);
1248
1249 /* Super I/O */
1250 pc_superio_init(isa_bus, create_fdctrl, no_vmport);
1251 }
1252
1253 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1254 {
1255 int i;
1256
1257 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1258 for (i = 0; i < nb_nics; i++) {
1259 NICInfo *nd = &nd_table[i];
1260 const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1261
1262 if (g_str_equal(model, "ne2k_isa")) {
1263 pc_init_ne2k_isa(isa_bus, nd);
1264 } else {
1265 pci_nic_init_nofail(nd, pci_bus, model, NULL);
1266 }
1267 }
1268 rom_reset_order_override();
1269 }
1270
1271 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1272 {
1273 qemu_irq *i8259;
1274
1275 if (kvm_pic_in_kernel()) {
1276 i8259 = kvm_i8259_init(isa_bus);
1277 } else if (xen_enabled()) {
1278 i8259 = xen_interrupt_controller_init();
1279 } else {
1280 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1281 }
1282
1283 for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1284 i8259_irqs[i] = i8259[i];
1285 }
1286
1287 g_free(i8259);
1288 }
1289
1290 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1291 Error **errp)
1292 {
1293 const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1294 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1295 const MachineState *ms = MACHINE(hotplug_dev);
1296 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1297 const uint64_t legacy_align = TARGET_PAGE_SIZE;
1298 Error *local_err = NULL;
1299
1300 /*
1301 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1302 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1303 * addition to cover this case.
1304 */
1305 if (!pcms->acpi_dev || !x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
1306 error_setg(errp,
1307 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1308 return;
1309 }
1310
1311 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1312 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1313 return;
1314 }
1315
1316 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err);
1317 if (local_err) {
1318 error_propagate(errp, local_err);
1319 return;
1320 }
1321
1322 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1323 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1324 }
1325
1326 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1327 DeviceState *dev, Error **errp)
1328 {
1329 Error *local_err = NULL;
1330 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1331 MachineState *ms = MACHINE(hotplug_dev);
1332 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1333
1334 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err);
1335 if (local_err) {
1336 goto out;
1337 }
1338
1339 if (is_nvdimm) {
1340 nvdimm_plug(ms->nvdimms_state);
1341 }
1342
1343 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort);
1344 out:
1345 error_propagate(errp, local_err);
1346 }
1347
1348 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1349 DeviceState *dev, Error **errp)
1350 {
1351 Error *local_err = NULL;
1352 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1353
1354 /*
1355 * When -no-acpi is used with Q35 machine type, no ACPI is built,
1356 * but pcms->acpi_dev is still created. Check !acpi_enabled in
1357 * addition to cover this case.
1358 */
1359 if (!pcms->acpi_dev || !x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
1360 error_setg(&local_err,
1361 "memory hotplug is not enabled: missing acpi device or acpi disabled");
1362 goto out;
1363 }
1364
1365 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1366 error_setg(&local_err,
1367 "nvdimm device hot unplug is not supported yet.");
1368 goto out;
1369 }
1370
1371 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1372 &local_err);
1373 out:
1374 error_propagate(errp, local_err);
1375 }
1376
1377 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1378 DeviceState *dev, Error **errp)
1379 {
1380 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1381 Error *local_err = NULL;
1382
1383 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1384 if (local_err) {
1385 goto out;
1386 }
1387
1388 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1389 qdev_unrealize(dev);
1390 out:
1391 error_propagate(errp, local_err);
1392 }
1393
1394 static int pc_apic_cmp(const void *a, const void *b)
1395 {
1396 CPUArchId *apic_a = (CPUArchId *)a;
1397 CPUArchId *apic_b = (CPUArchId *)b;
1398
1399 return apic_a->arch_id - apic_b->arch_id;
1400 }
1401
1402 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id
1403 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no
1404 * entry corresponding to CPU's apic_id returns NULL.
1405 */
1406 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
1407 {
1408 CPUArchId apic_id, *found_cpu;
1409
1410 apic_id.arch_id = id;
1411 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus,
1412 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus),
1413 pc_apic_cmp);
1414 if (found_cpu && idx) {
1415 *idx = found_cpu - ms->possible_cpus->cpus;
1416 }
1417 return found_cpu;
1418 }
1419
1420 static void pc_cpu_plug(HotplugHandler *hotplug_dev,
1421 DeviceState *dev, Error **errp)
1422 {
1423 CPUArchId *found_cpu;
1424 Error *local_err = NULL;
1425 X86CPU *cpu = X86_CPU(dev);
1426 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1427 X86MachineState *x86ms = X86_MACHINE(pcms);
1428
1429 if (pcms->acpi_dev) {
1430 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1431 if (local_err) {
1432 goto out;
1433 }
1434 }
1435
1436 /* increment the number of CPUs */
1437 x86ms->boot_cpus++;
1438 if (x86ms->rtc) {
1439 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1440 }
1441 if (x86ms->fw_cfg) {
1442 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1443 }
1444
1445 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1446 found_cpu->cpu = OBJECT(dev);
1447 out:
1448 error_propagate(errp, local_err);
1449 }
1450 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
1451 DeviceState *dev, Error **errp)
1452 {
1453 int idx = -1;
1454 Error *local_err = NULL;
1455 X86CPU *cpu = X86_CPU(dev);
1456 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1457
1458 if (!pcms->acpi_dev) {
1459 error_setg(&local_err, "CPU hot unplug not supported without ACPI");
1460 goto out;
1461 }
1462
1463 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1464 assert(idx != -1);
1465 if (idx == 0) {
1466 error_setg(&local_err, "Boot CPU is unpluggable");
1467 goto out;
1468 }
1469
1470 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev,
1471 &local_err);
1472 if (local_err) {
1473 goto out;
1474 }
1475
1476 out:
1477 error_propagate(errp, local_err);
1478
1479 }
1480
1481 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev,
1482 DeviceState *dev, Error **errp)
1483 {
1484 CPUArchId *found_cpu;
1485 Error *local_err = NULL;
1486 X86CPU *cpu = X86_CPU(dev);
1487 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1488 X86MachineState *x86ms = X86_MACHINE(pcms);
1489
1490 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err);
1491 if (local_err) {
1492 goto out;
1493 }
1494
1495 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL);
1496 found_cpu->cpu = NULL;
1497 qdev_unrealize(dev);
1498
1499 /* decrement the number of CPUs */
1500 x86ms->boot_cpus--;
1501 /* Update the number of CPUs in CMOS */
1502 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
1503 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
1504 out:
1505 error_propagate(errp, local_err);
1506 }
1507
1508 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
1509 DeviceState *dev, Error **errp)
1510 {
1511 int idx;
1512 CPUState *cs;
1513 CPUArchId *cpu_slot;
1514 X86CPUTopoIDs topo_ids;
1515 X86CPU *cpu = X86_CPU(dev);
1516 CPUX86State *env = &cpu->env;
1517 MachineState *ms = MACHINE(hotplug_dev);
1518 PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1519 X86MachineState *x86ms = X86_MACHINE(pcms);
1520 unsigned int smp_cores = ms->smp.cores;
1521 unsigned int smp_threads = ms->smp.threads;
1522 X86CPUTopoInfo topo_info;
1523
1524 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) {
1525 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'",
1526 ms->cpu_type);
1527 return;
1528 }
1529
1530 init_topo_info(&topo_info, x86ms);
1531
1532 env->nr_dies = x86ms->smp_dies;
1533 env->nr_nodes = topo_info.nodes_per_pkg;
1534 env->pkg_offset = x86ms->apicid_pkg_offset(&topo_info);
1535
1536 /*
1537 * If APIC ID is not set,
1538 * set it based on socket/die/core/thread properties.
1539 */
1540 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
1541 int max_socket = (ms->smp.max_cpus - 1) /
1542 smp_threads / smp_cores / x86ms->smp_dies;
1543
1544 /*
1545 * die-id was optional in QEMU 4.0 and older, so keep it optional
1546 * if there's only one die per socket.
1547 */
1548 if (cpu->die_id < 0 && x86ms->smp_dies == 1) {
1549 cpu->die_id = 0;
1550 }
1551
1552 if (cpu->socket_id < 0) {
1553 error_setg(errp, "CPU socket-id is not set");
1554 return;
1555 } else if (cpu->socket_id > max_socket) {
1556 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u",
1557 cpu->socket_id, max_socket);
1558 return;
1559 }
1560 if (cpu->die_id < 0) {
1561 error_setg(errp, "CPU die-id is not set");
1562 return;
1563 } else if (cpu->die_id > x86ms->smp_dies - 1) {
1564 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u",
1565 cpu->die_id, x86ms->smp_dies - 1);
1566 return;
1567 }
1568 if (cpu->core_id < 0) {
1569 error_setg(errp, "CPU core-id is not set");
1570 return;
1571 } else if (cpu->core_id > (smp_cores - 1)) {
1572 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u",
1573 cpu->core_id, smp_cores - 1);
1574 return;
1575 }
1576 if (cpu->thread_id < 0) {
1577 error_setg(errp, "CPU thread-id is not set");
1578 return;
1579 } else if (cpu->thread_id > (smp_threads - 1)) {
1580 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u",
1581 cpu->thread_id, smp_threads - 1);
1582 return;
1583 }
1584
1585 topo_ids.pkg_id = cpu->socket_id;
1586 topo_ids.die_id = cpu->die_id;
1587 topo_ids.core_id = cpu->core_id;
1588 topo_ids.smt_id = cpu->thread_id;
1589 cpu->apic_id = x86ms->apicid_from_topo_ids(&topo_info, &topo_ids);
1590 }
1591
1592 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx);
1593 if (!cpu_slot) {
1594 MachineState *ms = MACHINE(pcms);
1595
1596 x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
1597 error_setg(errp,
1598 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with"
1599 " APIC ID %" PRIu32 ", valid index range 0:%d",
1600 topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.smt_id,
1601 cpu->apic_id, ms->possible_cpus->len - 1);
1602 return;
1603 }
1604
1605 if (cpu_slot->cpu) {
1606 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists",
1607 idx, cpu->apic_id);
1608 return;
1609 }
1610
1611 /* if 'address' properties socket-id/core-id/thread-id are not set, set them
1612 * so that machine_query_hotpluggable_cpus would show correct values
1613 */
1614 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn()
1615 * once -smp refactoring is complete and there will be CPU private
1616 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */
1617 x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids);
1618 if (cpu->socket_id != -1 && cpu->socket_id != topo_ids.pkg_id) {
1619 error_setg(errp, "property socket-id: %u doesn't match set apic-id:"
1620 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id,
1621 topo_ids.pkg_id);
1622 return;
1623 }
1624 cpu->socket_id = topo_ids.pkg_id;
1625
1626 if (cpu->die_id != -1 && cpu->die_id != topo_ids.die_id) {
1627 error_setg(errp, "property die-id: %u doesn't match set apic-id:"
1628 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_id);
1629 return;
1630 }
1631 cpu->die_id = topo_ids.die_id;
1632
1633 if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
1634 error_setg(errp, "property core-id: %u doesn't match set apic-id:"
1635 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id,
1636 topo_ids.core_id);
1637 return;
1638 }
1639 cpu->core_id = topo_ids.core_id;
1640
1641 if (cpu->thread_id != -1 && cpu->thread_id != topo_ids.smt_id) {
1642 error_setg(errp, "property thread-id: %u doesn't match set apic-id:"
1643 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id,
1644 topo_ids.smt_id);
1645 return;
1646 }
1647 cpu->thread_id = topo_ids.smt_id;
1648
1649 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) &&
1650 !kvm_hv_vpindex_settable()) {
1651 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX");
1652 return;
1653 }
1654
1655 cs = CPU(cpu);
1656 cs->cpu_index = idx;
1657
1658 numa_cpu_pre_plug(cpu_slot, dev, errp);
1659 }
1660
1661 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev,
1662 DeviceState *dev, Error **errp)
1663 {
1664 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1665 Error *local_err = NULL;
1666
1667 if (!hotplug_dev2) {
1668 /*
1669 * Without a bus hotplug handler, we cannot control the plug/unplug
1670 * order. This should never be the case on x86, however better add
1671 * a safety net.
1672 */
1673 error_setg(errp, "virtio-pmem-pci not supported on this bus.");
1674 return;
1675 }
1676 /*
1677 * First, see if we can plug this memory device at all. If that
1678 * succeeds, branch of to the actual hotplug handler.
1679 */
1680 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1681 &local_err);
1682 if (!local_err) {
1683 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1684 }
1685 error_propagate(errp, local_err);
1686 }
1687
1688 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev,
1689 DeviceState *dev, Error **errp)
1690 {
1691 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1692 Error *local_err = NULL;
1693
1694 /*
1695 * Plug the memory device first and then branch off to the actual
1696 * hotplug handler. If that one fails, we can easily undo the memory
1697 * device bits.
1698 */
1699 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1700 hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1701 if (local_err) {
1702 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1703 }
1704 error_propagate(errp, local_err);
1705 }
1706
1707 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev,
1708 DeviceState *dev, Error **errp)
1709 {
1710 /* We don't support virtio pmem hot unplug */
1711 error_setg(errp, "virtio pmem device unplug not supported.");
1712 }
1713
1714 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev,
1715 DeviceState *dev, Error **errp)
1716 {
1717 /* We don't support virtio pmem hot unplug */
1718 }
1719
1720 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1721 DeviceState *dev, Error **errp)
1722 {
1723 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1724 pc_memory_pre_plug(hotplug_dev, dev, errp);
1725 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1726 pc_cpu_pre_plug(hotplug_dev, dev, errp);
1727 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1728 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp);
1729 }
1730 }
1731
1732 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1733 DeviceState *dev, Error **errp)
1734 {
1735 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1736 pc_memory_plug(hotplug_dev, dev, errp);
1737 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1738 pc_cpu_plug(hotplug_dev, dev, errp);
1739 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1740 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp);
1741 }
1742 }
1743
1744 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1745 DeviceState *dev, Error **errp)
1746 {
1747 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1748 pc_memory_unplug_request(hotplug_dev, dev, errp);
1749 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1750 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1751 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1752 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp);
1753 } else {
1754 error_setg(errp, "acpi: device unplug request for not supported device"
1755 " type: %s", object_get_typename(OBJECT(dev)));
1756 }
1757 }
1758
1759 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1760 DeviceState *dev, Error **errp)
1761 {
1762 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1763 pc_memory_unplug(hotplug_dev, dev, errp);
1764 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1765 pc_cpu_unplug_cb(hotplug_dev, dev, errp);
1766 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1767 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp);
1768 } else {
1769 error_setg(errp, "acpi: device unplug for not supported device"
1770 " type: %s", object_get_typename(OBJECT(dev)));
1771 }
1772 }
1773
1774 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1775 DeviceState *dev)
1776 {
1777 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1778 object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1779 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) {
1780 return HOTPLUG_HANDLER(machine);
1781 }
1782
1783 return NULL;
1784 }
1785
1786 static void
1787 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1788 const char *name, void *opaque,
1789 Error **errp)
1790 {
1791 MachineState *ms = MACHINE(obj);
1792 int64_t value = 0;
1793
1794 if (ms->device_memory) {
1795 value = memory_region_size(&ms->device_memory->mr);
1796 }
1797
1798 visit_type_int(v, name, &value, errp);
1799 }
1800
1801 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1802 void *opaque, Error **errp)
1803 {
1804 PCMachineState *pcms = PC_MACHINE(obj);
1805 OnOffAuto vmport = pcms->vmport;
1806
1807 visit_type_OnOffAuto(v, name, &vmport, errp);
1808 }
1809
1810 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1811 void *opaque, Error **errp)
1812 {
1813 PCMachineState *pcms = PC_MACHINE(obj);
1814
1815 visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1816 }
1817
1818 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1819 {
1820 PCMachineState *pcms = PC_MACHINE(obj);
1821
1822 return pcms->smbus_enabled;
1823 }
1824
1825 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1826 {
1827 PCMachineState *pcms = PC_MACHINE(obj);
1828
1829 pcms->smbus_enabled = value;
1830 }
1831
1832 static bool pc_machine_get_sata(Object *obj, Error **errp)
1833 {
1834 PCMachineState *pcms = PC_MACHINE(obj);
1835
1836 return pcms->sata_enabled;
1837 }
1838
1839 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1840 {
1841 PCMachineState *pcms = PC_MACHINE(obj);
1842
1843 pcms->sata_enabled = value;
1844 }
1845
1846 static bool pc_machine_get_pit(Object *obj, Error **errp)
1847 {
1848 PCMachineState *pcms = PC_MACHINE(obj);
1849
1850 return pcms->pit_enabled;
1851 }
1852
1853 static void pc_machine_set_pit(Object *obj, bool value, Error **errp)
1854 {
1855 PCMachineState *pcms = PC_MACHINE(obj);
1856
1857 pcms->pit_enabled = value;
1858 }
1859
1860 static void pc_machine_initfn(Object *obj)
1861 {
1862 PCMachineState *pcms = PC_MACHINE(obj);
1863
1864 #ifdef CONFIG_VMPORT
1865 pcms->vmport = ON_OFF_AUTO_AUTO;
1866 #else
1867 pcms->vmport = ON_OFF_AUTO_OFF;
1868 #endif /* CONFIG_VMPORT */
1869 /* acpi build is enabled by default if machine supports it */
1870 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1871 pcms->smbus_enabled = true;
1872 pcms->sata_enabled = true;
1873 pcms->pit_enabled = true;
1874
1875 pc_system_flash_create(pcms);
1876 }
1877
1878 static void pc_machine_reset(MachineState *machine)
1879 {
1880 CPUState *cs;
1881 X86CPU *cpu;
1882
1883 qemu_devices_reset();
1884
1885 /* Reset APIC after devices have been reset to cancel
1886 * any changes that qemu_devices_reset() might have done.
1887 */
1888 CPU_FOREACH(cs) {
1889 cpu = X86_CPU(cs);
1890
1891 if (cpu->apic_state) {
1892 device_legacy_reset(cpu->apic_state);
1893 }
1894 }
1895 }
1896
1897 static void pc_machine_wakeup(MachineState *machine)
1898 {
1899 cpu_synchronize_all_states();
1900 pc_machine_reset(machine);
1901 cpu_synchronize_all_post_reset();
1902 }
1903
1904 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1905 {
1906 X86IOMMUState *iommu = x86_iommu_get_default();
1907 IntelIOMMUState *intel_iommu;
1908
1909 if (iommu &&
1910 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1911 object_dynamic_cast((Object *)dev, "vfio-pci")) {
1912 intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1913 if (!intel_iommu->caching_mode) {
1914 error_setg(errp, "Device assignment is not allowed without "
1915 "enabling caching-mode=on for Intel IOMMU.");
1916 return false;
1917 }
1918 }
1919
1920 return true;
1921 }
1922
1923 static void pc_machine_class_init(ObjectClass *oc, void *data)
1924 {
1925 MachineClass *mc = MACHINE_CLASS(oc);
1926 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1927 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1928
1929 pcmc->pci_enabled = true;
1930 pcmc->has_acpi_build = true;
1931 pcmc->rsdp_in_ram = true;
1932 pcmc->smbios_defaults = true;
1933 pcmc->smbios_uuid_encoded = true;
1934 pcmc->gigabyte_align = true;
1935 pcmc->has_reserved_memory = true;
1936 pcmc->kvmclock_enabled = true;
1937 pcmc->enforce_aligned_dimm = true;
1938 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1939 * to be used at the moment, 32K should be enough for a while. */
1940 pcmc->acpi_data_size = 0x20000 + 0x8000;
1941 pcmc->linuxboot_dma_enabled = true;
1942 pcmc->pvh_enabled = true;
1943 assert(!mc->get_hotplug_handler);
1944 mc->get_hotplug_handler = pc_get_hotplug_handler;
1945 mc->hotplug_allowed = pc_hotplug_allowed;
1946 mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1947 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1948 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1949 mc->auto_enable_numa_with_memhp = true;
1950 mc->has_hotpluggable_cpus = true;
1951 mc->default_boot_order = "cad";
1952 mc->hot_add_cpu = pc_hot_add_cpu;
1953 mc->smp_parse = pc_smp_parse;
1954 mc->block_default_type = IF_IDE;
1955 mc->max_cpus = 255;
1956 mc->reset = pc_machine_reset;
1957 mc->wakeup = pc_machine_wakeup;
1958 hc->pre_plug = pc_machine_device_pre_plug_cb;
1959 hc->plug = pc_machine_device_plug_cb;
1960 hc->unplug_request = pc_machine_device_unplug_request_cb;
1961 hc->unplug = pc_machine_device_unplug_cb;
1962 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1963 mc->nvdimm_supported = true;
1964 mc->numa_mem_supported = true;
1965 mc->default_ram_id = "pc.ram";
1966
1967 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1968 pc_machine_get_device_memory_region_size, NULL,
1969 NULL, NULL);
1970
1971 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1972 pc_machine_get_vmport, pc_machine_set_vmport,
1973 NULL, NULL);
1974 object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1975 "Enable vmport (pc & q35)");
1976
1977 object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1978 pc_machine_get_smbus, pc_machine_set_smbus);
1979
1980 object_class_property_add_bool(oc, PC_MACHINE_SATA,
1981 pc_machine_get_sata, pc_machine_set_sata);
1982
1983 object_class_property_add_bool(oc, PC_MACHINE_PIT,
1984 pc_machine_get_pit, pc_machine_set_pit);
1985 }
1986
1987 static const TypeInfo pc_machine_info = {
1988 .name = TYPE_PC_MACHINE,
1989 .parent = TYPE_X86_MACHINE,
1990 .abstract = true,
1991 .instance_size = sizeof(PCMachineState),
1992 .instance_init = pc_machine_initfn,
1993 .class_size = sizeof(PCMachineClass),
1994 .class_init = pc_machine_class_init,
1995 .interfaces = (InterfaceInfo[]) {
1996 { TYPE_HOTPLUG_HANDLER },
1997 { }
1998 },
1999 };
2000
2001 static void pc_machine_register_types(void)
2002 {
2003 type_register_static(&pc_machine_info);
2004 }
2005
2006 type_init(pc_machine_register_types)
AR7 emulation for QEMU