hw/timer/sh_timer.c

   1 /*
   2  * SuperH Timer modules.
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Based on arm_timer.c by Paul Brook
   6  * Copyright (c) 2005-2006 CodeSourcery.
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "exec/memory.h"
  13 #include "hw/hw.h"
  14 #include "hw/irq.h"
  15 #include "hw/sh4/sh.h"
  16 #include "hw/timer/tmu012.h"
  17 #include "hw/ptimer.h"
  18
  19 //#define DEBUG_TIMER
  20
  21 #define TIMER_TCR_TPSC          (7 << 0)
  22 #define TIMER_TCR_CKEG          (3 << 3)
  23 #define TIMER_TCR_UNIE          (1 << 5)
  24 #define TIMER_TCR_ICPE          (3 << 6)
  25 #define TIMER_TCR_UNF           (1 << 8)
  26 #define TIMER_TCR_ICPF          (1 << 9)
  27 #define TIMER_TCR_RESERVED      (0x3f << 10)
  28
  29 #define TIMER_FEAT_CAPT   (1 << 0)
  30 #define TIMER_FEAT_EXTCLK (1 << 1)
  31
  32 #define OFFSET_TCOR   0
  33 #define OFFSET_TCNT   1
  34 #define OFFSET_TCR    2
  35 #define OFFSET_TCPR   3
  36
  37 typedef struct {
  38     ptimer_state *timer;
  39     uint32_t tcnt;
  40     uint32_t tcor;
  41     uint32_t tcr;
  42     uint32_t tcpr;
  43     int freq;
  44     int int_level;
  45     int old_level;
  46     int feat;
  47     int enabled;
  48     qemu_irq irq;
  49 } sh_timer_state;
  50
  51 /* Check all active timers, and schedule the next timer interrupt. */
  52
  53 static void sh_timer_update(sh_timer_state *s)
  54 {
  55     int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
  56
  57     if (new_level != s->old_level)
  58       qemu_set_irq (s->irq, new_level);
  59
  60     s->old_level = s->int_level;
  61     s->int_level = new_level;
  62 }
  63
  64 static uint32_t sh_timer_read(void *opaque, hwaddr offset)
  65 {
  66     sh_timer_state *s = (sh_timer_state *)opaque;
  67
  68     switch (offset >> 2) {
  69     case OFFSET_TCOR:
  70         return s->tcor;
  71     case OFFSET_TCNT:
  72         return ptimer_get_count(s->timer);
  73     case OFFSET_TCR:
  74         return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
  75     case OFFSET_TCPR:
  76         if (s->feat & TIMER_FEAT_CAPT)
  77             return s->tcpr;
  78         /* fall through */
  79     default:
  80         hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
  81         return 0;
  82     }
  83 }
  84
  85 static void sh_timer_write(void *opaque, hwaddr offset,
  86                             uint32_t value)
  87 {
  88     sh_timer_state *s = (sh_timer_state *)opaque;
  89     int freq;
  90
  91     switch (offset >> 2) {
  92     case OFFSET_TCOR:
  93         s->tcor = value;
  94         ptimer_transaction_begin(s->timer);
  95         ptimer_set_limit(s->timer, s->tcor, 0);
  96         ptimer_transaction_commit(s->timer);
  97         break;
  98     case OFFSET_TCNT:
  99         s->tcnt = value;
 100         ptimer_transaction_begin(s->timer);
 101         ptimer_set_count(s->timer, s->tcnt);
 102         ptimer_transaction_commit(s->timer);
 103         break;
 104     case OFFSET_TCR:
 105         ptimer_transaction_begin(s->timer);
 106         if (s->enabled) {
 107             /* Pause the timer if it is running.  This may cause some
 108                inaccuracy dure to rounding, but avoids a whole lot of other
 109                messyness.  */
 110             ptimer_stop(s->timer);
 111         }
 112         freq = s->freq;
 113         /* ??? Need to recalculate expiry time after changing divisor.  */
 114         switch (value & TIMER_TCR_TPSC) {
 115         case 0: freq >>= 2; break;
 116         case 1: freq >>= 4; break;
 117         case 2: freq >>= 6; break;
 118         case 3: freq >>= 8; break;
 119         case 4: freq >>= 10; break;
 120         case 6:
 121         case 7:
 122             if (s->feat & TIMER_FEAT_EXTCLK) {
 123                 break;
 124             }
 125             /* fallthrough */
 126         default:
 127             hw_error("sh_timer_write: Reserved TPSC value\n");
 128             break;
 129         }
 130         switch ((value & TIMER_TCR_CKEG) >> 3) {
 131         case 0:
 132             break;
 133         case 1:
 134         case 2:
 135         case 3:
 136             if (s->feat & TIMER_FEAT_EXTCLK) {
 137                 break;
 138             }
 139             /* fallthrough */
 140         default:
 141             hw_error("sh_timer_write: Reserved CKEG value\n");
 142             break;
 143         }
 144         switch ((value & TIMER_TCR_ICPE) >> 6) {
 145         case 0:
 146             break;
 147         case 2:
 148         case 3:
 149             if (s->feat & TIMER_FEAT_CAPT) {
 150                 break;
 151             }
 152             /* fallthrough */
 153         default:
 154             hw_error("sh_timer_write: Reserved ICPE value\n");
 155             break;
 156         }
 157         if ((value & TIMER_TCR_UNF) == 0) {
 158             s->int_level = 0;
 159         }
 160
 161         value &= ~TIMER_TCR_UNF;
 162
 163         if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) {
 164             hw_error("sh_timer_write: Reserved ICPF value\n");
 165         }
 166
 167         value &= ~TIMER_TCR_ICPF; /* capture not supported */
 168
 169         if (value & TIMER_TCR_RESERVED) {
 170             hw_error("sh_timer_write: Reserved TCR bits set\n");
 171         }
 172         s->tcr = value;
 173         ptimer_set_limit(s->timer, s->tcor, 0);
 174         ptimer_set_freq(s->timer, freq);
 175         if (s->enabled) {
 176             /* Restart the timer if still enabled.  */
 177             ptimer_run(s->timer, 0);
 178         }
 179         ptimer_transaction_commit(s->timer);
 180         break;
 181     case OFFSET_TCPR:
 182         if (s->feat & TIMER_FEAT_CAPT) {
 183             s->tcpr = value;
 184             break;
 185         }
 186         /* fallthrough */
 187     default:
 188         hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
 189     }
 190     sh_timer_update(s);
 191 }
 192
 193 static void sh_timer_start_stop(void *opaque, int enable)
 194 {
 195     sh_timer_state *s = (sh_timer_state *)opaque;
 196
 197 #ifdef DEBUG_TIMER
 198     printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
 199 #endif
 200
 201     ptimer_transaction_begin(s->timer);
 202     if (s->enabled && !enable) {
 203         ptimer_stop(s->timer);
 204     }
 205     if (!s->enabled && enable) {
 206         ptimer_run(s->timer, 0);
 207     }
 208     ptimer_transaction_commit(s->timer);
 209     s->enabled = !!enable;
 210
 211 #ifdef DEBUG_TIMER
 212     printf("sh_timer_start_stop done %d\n", s->enabled);
 213 #endif
 214 }
 215
 216 static void sh_timer_tick(void *opaque)
 217 {
 218     sh_timer_state *s = (sh_timer_state *)opaque;
 219     s->int_level = s->enabled;
 220     sh_timer_update(s);
 221 }
 222
 223 static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
 224 {
 225     sh_timer_state *s;
 226
 227     s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
 228     s->freq = freq;
 229     s->feat = feat;
 230     s->tcor = 0xffffffff;
 231     s->tcnt = 0xffffffff;
 232     s->tcpr = 0xdeadbeef;
 233     s->tcr = 0;
 234     s->enabled = 0;
 235     s->irq = irq;
 236
 237     s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT);
 238
 239     sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
 240     sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
 241     sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
 242     sh_timer_write(s, OFFSET_TCR  >> 2, s->tcpr);
 243     /* ??? Save/restore.  */
 244     return s;
 245 }
 246
 247 typedef struct {
 248     MemoryRegion iomem;
 249     MemoryRegion iomem_p4;
 250     MemoryRegion iomem_a7;
 251     void *timer[3];
 252     int level[3];
 253     uint32_t tocr;
 254     uint32_t tstr;
 255     int feat;
 256 } tmu012_state;
 257
 258 static uint64_t tmu012_read(void *opaque, hwaddr offset,
 259                             unsigned size)
 260 {
 261     tmu012_state *s = (tmu012_state *)opaque;
 262
 263 #ifdef DEBUG_TIMER
 264     printf("tmu012_read 0x%lx\n", (unsigned long) offset);
 265 #endif
 266
 267     if (offset >= 0x20) {
 268         if (!(s->feat & TMU012_FEAT_3CHAN)) {
 269             hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
 270         }
 271         return sh_timer_read(s->timer[2], offset - 0x20);
 272     }
 273
 274     if (offset >= 0x14)
 275         return sh_timer_read(s->timer[1], offset - 0x14);
 276
 277     if (offset >= 0x08)
 278         return sh_timer_read(s->timer[0], offset - 0x08);
 279
 280     if (offset == 4)
 281         return s->tstr;
 282
 283     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
 284         return s->tocr;
 285
 286     hw_error("tmu012_write: Bad offset %x\n", (int)offset);
 287     return 0;
 288 }
 289
 290 static void tmu012_write(void *opaque, hwaddr offset,
 291                         uint64_t value, unsigned size)
 292 {
 293     tmu012_state *s = (tmu012_state *)opaque;
 294
 295 #ifdef DEBUG_TIMER
 296     printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
 297 #endif
 298
 299     if (offset >= 0x20) {
 300         if (!(s->feat & TMU012_FEAT_3CHAN)) {
 301             hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
 302         }
 303         sh_timer_write(s->timer[2], offset - 0x20, value);
 304         return;
 305     }
 306
 307     if (offset >= 0x14) {
 308         sh_timer_write(s->timer[1], offset - 0x14, value);
 309         return;
 310     }
 311
 312     if (offset >= 0x08) {
 313         sh_timer_write(s->timer[0], offset - 0x08, value);
 314         return;
 315     }
 316
 317     if (offset == 4) {
 318         sh_timer_start_stop(s->timer[0], value & (1 << 0));
 319         sh_timer_start_stop(s->timer[1], value & (1 << 1));
 320         if (s->feat & TMU012_FEAT_3CHAN) {
 321             sh_timer_start_stop(s->timer[2], value & (1 << 2));
 322         } else {
 323             if (value & (1 << 2)) {
 324                 hw_error("tmu012_write: Bad channel\n");
 325             }
 326         }
 327
 328         s->tstr = value;
 329         return;
 330     }
 331
 332     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
 333         s->tocr = value & (1 << 0);
 334     }
 335 }
 336
 337 static const MemoryRegionOps tmu012_ops = {
 338     .read = tmu012_read,
 339     .write = tmu012_write,
 340     .endianness = DEVICE_NATIVE_ENDIAN,
 341 };
 342
 343 void tmu012_init(MemoryRegion *sysmem, hwaddr base,
 344                  int feat, uint32_t freq,
 345                  qemu_irq ch0_irq, qemu_irq ch1_irq,
 346                  qemu_irq ch2_irq0, qemu_irq ch2_irq1)
 347 {
 348     tmu012_state *s;
 349     int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
 350
 351     s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
 352     s->feat = feat;
 353     s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
 354     s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
 355     if (feat & TMU012_FEAT_3CHAN) {
 356         s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
 357                                     ch2_irq0); /* ch2_irq1 not supported */
 358     }
 359
 360     memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
 361                           "timer", 0x100000000ULL);
 362
 363     memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4",
 364                              &s->iomem, 0, 0x1000);
 365     memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
 366
 367     memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7",
 368                              &s->iomem, 0, 0x1000);
 369     memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
 370     /* ??? Save/restore.  */
 371 }