2 * SuperH Timer modules.
4 * Copyright (c) 2007 Magnus Damm
5 * Based on arm_timer.c by Paul Brook
6 * Copyright (c) 2005-2006 CodeSourcery.
8 * This code is licensed under the GPL.
11 #include "qemu/osdep.h"
12 #include "exec/memory.h"
15 #include "hw/sh4/sh.h"
16 #include "hw/timer/tmu012.h"
17 #include "hw/ptimer.h"
21 #define TIMER_TCR_TPSC (7 << 0)
22 #define TIMER_TCR_CKEG (3 << 3)
23 #define TIMER_TCR_UNIE (1 << 5)
24 #define TIMER_TCR_ICPE (3 << 6)
25 #define TIMER_TCR_UNF (1 << 8)
26 #define TIMER_TCR_ICPF (1 << 9)
27 #define TIMER_TCR_RESERVED (0x3f << 10)
29 #define TIMER_FEAT_CAPT (1 << 0)
30 #define TIMER_FEAT_EXTCLK (1 << 1)
51 /* Check all active timers, and schedule the next timer interrupt. */
53 static void sh_timer_update(sh_timer_state
*s
)
55 int new_level
= s
->int_level
&& (s
->tcr
& TIMER_TCR_UNIE
);
57 if (new_level
!= s
->old_level
)
58 qemu_set_irq (s
->irq
, new_level
);
60 s
->old_level
= s
->int_level
;
61 s
->int_level
= new_level
;
64 static uint32_t sh_timer_read(void *opaque
, hwaddr offset
)
66 sh_timer_state
*s
= (sh_timer_state
*)opaque
;
68 switch (offset
>> 2) {
72 return ptimer_get_count(s
->timer
);
74 return s
->tcr
| (s
->int_level
? TIMER_TCR_UNF
: 0);
76 if (s
->feat
& TIMER_FEAT_CAPT
)
80 hw_error("sh_timer_read: Bad offset %x\n", (int)offset
);
85 static void sh_timer_write(void *opaque
, hwaddr offset
,
88 sh_timer_state
*s
= (sh_timer_state
*)opaque
;
91 switch (offset
>> 2) {
94 ptimer_transaction_begin(s
->timer
);
95 ptimer_set_limit(s
->timer
, s
->tcor
, 0);
96 ptimer_transaction_commit(s
->timer
);
100 ptimer_transaction_begin(s
->timer
);
101 ptimer_set_count(s
->timer
, s
->tcnt
);
102 ptimer_transaction_commit(s
->timer
);
105 ptimer_transaction_begin(s
->timer
);
107 /* Pause the timer if it is running. This may cause some
108 inaccuracy dure to rounding, but avoids a whole lot of other
110 ptimer_stop(s
->timer
);
113 /* ??? Need to recalculate expiry time after changing divisor. */
114 switch (value
& TIMER_TCR_TPSC
) {
115 case 0: freq
>>= 2; break;
116 case 1: freq
>>= 4; break;
117 case 2: freq
>>= 6; break;
118 case 3: freq
>>= 8; break;
119 case 4: freq
>>= 10; break;
122 if (s
->feat
& TIMER_FEAT_EXTCLK
) {
127 hw_error("sh_timer_write: Reserved TPSC value\n");
130 switch ((value
& TIMER_TCR_CKEG
) >> 3) {
136 if (s
->feat
& TIMER_FEAT_EXTCLK
) {
141 hw_error("sh_timer_write: Reserved CKEG value\n");
144 switch ((value
& TIMER_TCR_ICPE
) >> 6) {
149 if (s
->feat
& TIMER_FEAT_CAPT
) {
154 hw_error("sh_timer_write: Reserved ICPE value\n");
157 if ((value
& TIMER_TCR_UNF
) == 0) {
161 value
&= ~TIMER_TCR_UNF
;
163 if ((value
& TIMER_TCR_ICPF
) && (!(s
->feat
& TIMER_FEAT_CAPT
))) {
164 hw_error("sh_timer_write: Reserved ICPF value\n");
167 value
&= ~TIMER_TCR_ICPF
; /* capture not supported */
169 if (value
& TIMER_TCR_RESERVED
) {
170 hw_error("sh_timer_write: Reserved TCR bits set\n");
173 ptimer_set_limit(s
->timer
, s
->tcor
, 0);
174 ptimer_set_freq(s
->timer
, freq
);
176 /* Restart the timer if still enabled. */
177 ptimer_run(s
->timer
, 0);
179 ptimer_transaction_commit(s
->timer
);
182 if (s
->feat
& TIMER_FEAT_CAPT
) {
188 hw_error("sh_timer_write: Bad offset %x\n", (int)offset
);
193 static void sh_timer_start_stop(void *opaque
, int enable
)
195 sh_timer_state
*s
= (sh_timer_state
*)opaque
;
198 printf("sh_timer_start_stop %d (%d)\n", enable
, s
->enabled
);
201 ptimer_transaction_begin(s
->timer
);
202 if (s
->enabled
&& !enable
) {
203 ptimer_stop(s
->timer
);
205 if (!s
->enabled
&& enable
) {
206 ptimer_run(s
->timer
, 0);
208 ptimer_transaction_commit(s
->timer
);
209 s
->enabled
= !!enable
;
212 printf("sh_timer_start_stop done %d\n", s
->enabled
);
216 static void sh_timer_tick(void *opaque
)
218 sh_timer_state
*s
= (sh_timer_state
*)opaque
;
219 s
->int_level
= s
->enabled
;
223 static void *sh_timer_init(uint32_t freq
, int feat
, qemu_irq irq
)
227 s
= (sh_timer_state
*)g_malloc0(sizeof(sh_timer_state
));
230 s
->tcor
= 0xffffffff;
231 s
->tcnt
= 0xffffffff;
232 s
->tcpr
= 0xdeadbeef;
237 s
->timer
= ptimer_init(sh_timer_tick
, s
, PTIMER_POLICY_DEFAULT
);
239 sh_timer_write(s
, OFFSET_TCOR
>> 2, s
->tcor
);
240 sh_timer_write(s
, OFFSET_TCNT
>> 2, s
->tcnt
);
241 sh_timer_write(s
, OFFSET_TCPR
>> 2, s
->tcpr
);
242 sh_timer_write(s
, OFFSET_TCR
>> 2, s
->tcpr
);
243 /* ??? Save/restore. */
249 MemoryRegion iomem_p4
;
250 MemoryRegion iomem_a7
;
258 static uint64_t tmu012_read(void *opaque
, hwaddr offset
,
261 tmu012_state
*s
= (tmu012_state
*)opaque
;
264 printf("tmu012_read 0x%lx\n", (unsigned long) offset
);
267 if (offset
>= 0x20) {
268 if (!(s
->feat
& TMU012_FEAT_3CHAN
)) {
269 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset
);
271 return sh_timer_read(s
->timer
[2], offset
- 0x20);
275 return sh_timer_read(s
->timer
[1], offset
- 0x14);
278 return sh_timer_read(s
->timer
[0], offset
- 0x08);
283 if ((s
->feat
& TMU012_FEAT_TOCR
) && offset
== 0)
286 hw_error("tmu012_write: Bad offset %x\n", (int)offset
);
290 static void tmu012_write(void *opaque
, hwaddr offset
,
291 uint64_t value
, unsigned size
)
293 tmu012_state
*s
= (tmu012_state
*)opaque
;
296 printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset
, value
);
299 if (offset
>= 0x20) {
300 if (!(s
->feat
& TMU012_FEAT_3CHAN
)) {
301 hw_error("tmu012_write: Bad channel offset %x\n", (int)offset
);
303 sh_timer_write(s
->timer
[2], offset
- 0x20, value
);
307 if (offset
>= 0x14) {
308 sh_timer_write(s
->timer
[1], offset
- 0x14, value
);
312 if (offset
>= 0x08) {
313 sh_timer_write(s
->timer
[0], offset
- 0x08, value
);
318 sh_timer_start_stop(s
->timer
[0], value
& (1 << 0));
319 sh_timer_start_stop(s
->timer
[1], value
& (1 << 1));
320 if (s
->feat
& TMU012_FEAT_3CHAN
) {
321 sh_timer_start_stop(s
->timer
[2], value
& (1 << 2));
323 if (value
& (1 << 2)) {
324 hw_error("tmu012_write: Bad channel\n");
332 if ((s
->feat
& TMU012_FEAT_TOCR
) && offset
== 0) {
333 s
->tocr
= value
& (1 << 0);
337 static const MemoryRegionOps tmu012_ops
= {
339 .write
= tmu012_write
,
340 .endianness
= DEVICE_NATIVE_ENDIAN
,
343 void tmu012_init(MemoryRegion
*sysmem
, hwaddr base
,
344 int feat
, uint32_t freq
,
345 qemu_irq ch0_irq
, qemu_irq ch1_irq
,
346 qemu_irq ch2_irq0
, qemu_irq ch2_irq1
)
349 int timer_feat
= (feat
& TMU012_FEAT_EXTCLK
) ? TIMER_FEAT_EXTCLK
: 0;
351 s
= (tmu012_state
*)g_malloc0(sizeof(tmu012_state
));
353 s
->timer
[0] = sh_timer_init(freq
, timer_feat
, ch0_irq
);
354 s
->timer
[1] = sh_timer_init(freq
, timer_feat
, ch1_irq
);
355 if (feat
& TMU012_FEAT_3CHAN
) {
356 s
->timer
[2] = sh_timer_init(freq
, timer_feat
| TIMER_FEAT_CAPT
,
357 ch2_irq0
); /* ch2_irq1 not supported */
360 memory_region_init_io(&s
->iomem
, NULL
, &tmu012_ops
, s
,
361 "timer", 0x100000000ULL
);
363 memory_region_init_alias(&s
->iomem_p4
, NULL
, "timer-p4",
364 &s
->iomem
, 0, 0x1000);
365 memory_region_add_subregion(sysmem
, P4ADDR(base
), &s
->iomem_p4
);
367 memory_region_init_alias(&s
->iomem_a7
, NULL
, "timer-a7",
368 &s
->iomem
, 0, 0x1000);
369 memory_region_add_subregion(sysmem
, A7ADDR(base
), &s
->iomem_a7
);
370 /* ??? Save/restore. */