ppc4xx: Export ECB and PLB emulation
[qemu/ar7.git] / hw / sparc64 / niagara.c
blob9a8d6109d497a3a129f5d974eb6fe9125a3911ce
1 /*
2 * QEMU Sun4v/Niagara System Emulator
4 * Copyright (c) 2016 Artyom Tarasenko
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include "hw/hw.h"
30 #include "hw/boards.h"
31 #include "hw/char/serial.h"
32 #include "hw/empty_slot.h"
33 #include "hw/loader.h"
34 #include "hw/sparc/sparc64.h"
35 #include "hw/timer/sun4v-rtc.h"
36 #include "exec/address-spaces.h"
37 #include "sysemu/block-backend.h"
38 #include "qemu/error-report.h"
39 #include "sysemu/qtest.h"
42 typedef struct NiagaraBoardState {
43 MemoryRegion hv_ram;
44 MemoryRegion partition_ram;
45 MemoryRegion nvram;
46 MemoryRegion md_rom;
47 MemoryRegion hv_rom;
48 MemoryRegion vdisk_ram;
49 MemoryRegion prom;
50 } NiagaraBoardState;
52 #define NIAGARA_HV_RAM_BASE 0x100000ULL
53 #define NIAGARA_HV_RAM_SIZE 0x3f00000ULL /* 63 MiB */
55 #define NIAGARA_PARTITION_RAM_BASE 0x80000000ULL
57 #define NIAGARA_UART_BASE 0x1f10000000ULL
59 #define NIAGARA_NVRAM_BASE 0x1f11000000ULL
60 #define NIAGARA_NVRAM_SIZE 0x2000
62 #define NIAGARA_MD_ROM_BASE 0x1f12000000ULL
63 #define NIAGARA_MD_ROM_SIZE 0x2000
65 #define NIAGARA_HV_ROM_BASE 0x1f12080000ULL
66 #define NIAGARA_HV_ROM_SIZE 0x2000
68 #define NIAGARA_IOBBASE 0x9800000000ULL
69 #define NIAGARA_IOBSIZE 0x0100000000ULL
71 #define NIAGARA_VDISK_BASE 0x1f40000000ULL
72 #define NIAGARA_RTC_BASE 0xfff0c1fff8ULL
73 #define NIAGARA_UART_BASE 0x1f10000000ULL
75 /* Firmware layout
77 * |------------------|
78 * | openboot.bin |
79 * |------------------| PROM_ADDR + OBP_OFFSET
80 * | q.bin |
81 * |------------------| PROM_ADDR + Q_OFFSET
82 * | reset.bin |
83 * |------------------| PROM_ADDR
85 #define NIAGARA_PROM_BASE 0xfff0000000ULL
86 #define NIAGARA_Q_OFFSET 0x10000ULL
87 #define NIAGARA_OBP_OFFSET 0x80000ULL
88 #define PROM_SIZE_MAX (4 * 1024 * 1024)
90 static void add_rom_or_fail(const char *file, const hwaddr addr)
92 /* XXX remove qtest_enabled() check once firmware files are
93 * in the qemu tree
95 if (!qtest_enabled() && rom_add_file_fixed(file, addr, -1)) {
96 error_report("Unable to load a firmware for -M niagara");
97 exit(1);
101 /* Niagara hardware initialisation */
102 static void niagara_init(MachineState *machine)
104 NiagaraBoardState *s = g_new(NiagaraBoardState, 1);
105 DriveInfo *dinfo = drive_get_next(IF_PFLASH);
106 MemoryRegion *sysmem = get_system_memory();
108 /* init CPUs */
109 sparc64_cpu_devinit(machine->cpu_model, "Sun UltraSparc T1",
110 NIAGARA_PROM_BASE);
111 /* set up devices */
112 memory_region_allocate_system_memory(&s->hv_ram, NULL, "sun4v-hv.ram",
113 NIAGARA_HV_RAM_SIZE);
114 memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram);
116 memory_region_allocate_system_memory(&s->partition_ram, NULL,
117 "sun4v-partition.ram",
118 machine->ram_size);
119 memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE,
120 &s->partition_ram);
122 memory_region_allocate_system_memory(&s->nvram, NULL,
123 "sun4v.nvram", NIAGARA_NVRAM_SIZE);
124 memory_region_add_subregion(sysmem, NIAGARA_NVRAM_BASE, &s->nvram);
125 memory_region_allocate_system_memory(&s->md_rom, NULL,
126 "sun4v-md.rom", NIAGARA_MD_ROM_SIZE);
127 memory_region_add_subregion(sysmem, NIAGARA_MD_ROM_BASE, &s->md_rom);
128 memory_region_allocate_system_memory(&s->hv_rom, NULL,
129 "sun4v-hv.rom", NIAGARA_HV_ROM_SIZE);
130 memory_region_add_subregion(sysmem, NIAGARA_HV_ROM_BASE, &s->hv_rom);
131 memory_region_allocate_system_memory(&s->prom, NULL,
132 "sun4v.prom", PROM_SIZE_MAX);
133 memory_region_add_subregion(sysmem, NIAGARA_PROM_BASE, &s->prom);
135 add_rom_or_fail("nvram1", NIAGARA_NVRAM_BASE);
136 add_rom_or_fail("1up-md.bin", NIAGARA_MD_ROM_BASE);
137 add_rom_or_fail("1up-hv.bin", NIAGARA_HV_ROM_BASE);
139 add_rom_or_fail("reset.bin", NIAGARA_PROM_BASE);
140 add_rom_or_fail("q.bin", NIAGARA_PROM_BASE + NIAGARA_Q_OFFSET);
141 add_rom_or_fail("openboot.bin", NIAGARA_PROM_BASE + NIAGARA_OBP_OFFSET);
143 /* the virtual ramdisk is kind of initrd, but it resides
144 outside of the partition RAM */
145 if (dinfo) {
146 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
147 int size = blk_getlength(blk);
148 if (size > 0) {
149 memory_region_allocate_system_memory(&s->vdisk_ram, NULL,
150 "sun4v_vdisk.ram", size);
151 memory_region_add_subregion(get_system_memory(),
152 NIAGARA_VDISK_BASE, &s->vdisk_ram);
153 dinfo->is_default = 1;
154 rom_add_file_fixed(blk_bs(blk)->filename, NIAGARA_VDISK_BASE, -1);
155 } else {
156 fprintf(stderr, "qemu: could not load ram disk '%s'\n",
157 blk_bs(blk)->filename);
158 exit(1);
161 if (serial_hds[0]) {
162 serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 115200,
163 serial_hds[0], DEVICE_BIG_ENDIAN);
165 empty_slot_init(NIAGARA_IOBBASE, NIAGARA_IOBSIZE);
166 sun4v_rtc_init(NIAGARA_RTC_BASE);
169 static void niagara_class_init(ObjectClass *oc, void *data)
171 MachineClass *mc = MACHINE_CLASS(oc);
173 mc->desc = "Sun4v platform, Niagara";
174 mc->init = niagara_init;
175 mc->max_cpus = 1; /* XXX for now */
176 mc->default_boot_order = "c";
179 static const TypeInfo niagara_type = {
180 .name = MACHINE_TYPE_NAME("niagara"),
181 .parent = TYPE_MACHINE,
182 .class_init = niagara_class_init,
185 static void niagara_register_types(void)
187 type_register_static(&niagara_type);
190 type_init(niagara_register_types)