hw/gpio/zaurus.c

   1 /*
   2  * Copyright (c) 2006-2008 Openedhand Ltd.
   3  * Written by Andrzej Zaborowski <balrog@zabor.org>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 or
   8  * (at your option) version 3 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #include "qemu/osdep.h"
  19 #include "hw/hw.h"
  20 #include "hw/arm/sharpsl.h"
  21 #include "hw/sysbus.h"
  22
  23 #undef REG_FMT
  24 #define REG_FMT                 "0x%02lx"
  25
  26 /* SCOOP devices */
  27
  28 #define TYPE_SCOOP "scoop"
  29 #define SCOOP(obj) OBJECT_CHECK(ScoopInfo, (obj), TYPE_SCOOP)
  30
  31 typedef struct ScoopInfo ScoopInfo;
  32 struct ScoopInfo {
  33     SysBusDevice parent_obj;
  34
  35     qemu_irq handler[16];
  36     MemoryRegion iomem;
  37     uint16_t status;
  38     uint16_t power;
  39     uint32_t gpio_level;
  40     uint32_t gpio_dir;
  41     uint32_t prev_level;
  42
  43     uint16_t mcr;
  44     uint16_t cdr;
  45     uint16_t ccr;
  46     uint16_t irr;
  47     uint16_t imr;
  48     uint16_t isr;
  49 };
  50
  51 #define SCOOP_MCR       0x00
  52 #define SCOOP_CDR       0x04
  53 #define SCOOP_CSR       0x08
  54 #define SCOOP_CPR       0x0c
  55 #define SCOOP_CCR       0x10
  56 #define SCOOP_IRR_IRM   0x14
  57 #define SCOOP_IMR       0x18
  58 #define SCOOP_ISR       0x1c
  59 #define SCOOP_GPCR      0x20
  60 #define SCOOP_GPWR      0x24
  61 #define SCOOP_GPRR      0x28
  62
  63 static inline void scoop_gpio_handler_update(ScoopInfo *s) {
  64     uint32_t level, diff;
  65     int bit;
  66     level = s->gpio_level & s->gpio_dir;
  67
  68     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
  69         bit = ctz32(diff);
  70         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
  71     }
  72
  73     s->prev_level = level;
  74 }
  75
  76 static uint64_t scoop_read(void *opaque, hwaddr addr,
  77                            unsigned size)
  78 {
  79     ScoopInfo *s = (ScoopInfo *) opaque;
  80
  81     switch (addr & 0x3f) {
  82     case SCOOP_MCR:
  83         return s->mcr;
  84     case SCOOP_CDR:
  85         return s->cdr;
  86     case SCOOP_CSR:
  87         return s->status;
  88     case SCOOP_CPR:
  89         return s->power;
  90     case SCOOP_CCR:
  91         return s->ccr;
  92     case SCOOP_IRR_IRM:
  93         return s->irr;
  94     case SCOOP_IMR:
  95         return s->imr;
  96     case SCOOP_ISR:
  97         return s->isr;
  98     case SCOOP_GPCR:
  99         return s->gpio_dir;
 100     case SCOOP_GPWR:
 101     case SCOOP_GPRR:
 102         return s->gpio_level;
 103     default:
 104         zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
 105     }
 106
 107     return 0;
 108 }
 109
 110 static void scoop_write(void *opaque, hwaddr addr,
 111                         uint64_t value, unsigned size)
 112 {
 113     ScoopInfo *s = (ScoopInfo *) opaque;
 114     value &= 0xffff;
 115
 116     switch (addr & 0x3f) {
 117     case SCOOP_MCR:
 118         s->mcr = value;
 119         break;
 120     case SCOOP_CDR:
 121         s->cdr = value;
 122         break;
 123     case SCOOP_CPR:
 124         s->power = value;
 125         if (value & 0x80)
 126             s->power |= 0x8040;
 127         break;
 128     case SCOOP_CCR:
 129         s->ccr = value;
 130         break;
 131     case SCOOP_IRR_IRM:
 132         s->irr = value;
 133         break;
 134     case SCOOP_IMR:
 135         s->imr = value;
 136         break;
 137     case SCOOP_ISR:
 138         s->isr = value;
 139         break;
 140     case SCOOP_GPCR:
 141         s->gpio_dir = value;
 142         scoop_gpio_handler_update(s);
 143         break;
 144     case SCOOP_GPWR:
 145     case SCOOP_GPRR:    /* GPRR is probably R/O in real HW */
 146         s->gpio_level = value & s->gpio_dir;
 147         scoop_gpio_handler_update(s);
 148         break;
 149     default:
 150         zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
 151     }
 152 }
 153
 154 static const MemoryRegionOps scoop_ops = {
 155     .read = scoop_read,
 156     .write = scoop_write,
 157     .endianness = DEVICE_NATIVE_ENDIAN,
 158 };
 159
 160 static void scoop_gpio_set(void *opaque, int line, int level)
 161 {
 162     ScoopInfo *s = (ScoopInfo *) opaque;
 163
 164     if (level)
 165         s->gpio_level |= (1 << line);
 166     else
 167         s->gpio_level &= ~(1 << line);
 168 }
 169
 170 static void scoop_init(Object *obj)
 171 {
 172     DeviceState *dev = DEVICE(obj);
 173     ScoopInfo *s = SCOOP(obj);
 174     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 175
 176     s->status = 0x02;
 177     qdev_init_gpio_out(dev, s->handler, 16);
 178     qdev_init_gpio_in(dev, scoop_gpio_set, 16);
 179     memory_region_init_io(&s->iomem, obj, &scoop_ops, s, "scoop", 0x1000);
 180
 181     sysbus_init_mmio(sbd, &s->iomem);
 182 }
 183
 184 static int scoop_post_load(void *opaque, int version_id)
 185 {
 186     ScoopInfo *s = (ScoopInfo *) opaque;
 187     int i;
 188     uint32_t level;
 189
 190     level = s->gpio_level & s->gpio_dir;
 191
 192     for (i = 0; i < 16; i++) {
 193         qemu_set_irq(s->handler[i], (level >> i) & 1);
 194     }
 195
 196     s->prev_level = level;
 197
 198     return 0;
 199 }
 200
 201 static bool is_version_0 (void *opaque, int version_id)
 202 {
 203     return version_id == 0;
 204 }
 205
 206 static bool vmstate_scoop_validate(void *opaque, int version_id)
 207 {
 208     ScoopInfo *s = opaque;
 209
 210     return !(s->prev_level & 0xffff0000) &&
 211         !(s->gpio_level & 0xffff0000) &&
 212         !(s->gpio_dir & 0xffff0000);
 213 }
 214
 215 static const VMStateDescription vmstate_scoop_regs = {
 216     .name = "scoop",
 217     .version_id = 1,
 218     .minimum_version_id = 0,
 219     .post_load = scoop_post_load,
 220     .fields = (VMStateField[]) {
 221         VMSTATE_UINT16(status, ScoopInfo),
 222         VMSTATE_UINT16(power, ScoopInfo),
 223         VMSTATE_UINT32(gpio_level, ScoopInfo),
 224         VMSTATE_UINT32(gpio_dir, ScoopInfo),
 225         VMSTATE_UINT32(prev_level, ScoopInfo),
 226         VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate),
 227         VMSTATE_UINT16(mcr, ScoopInfo),
 228         VMSTATE_UINT16(cdr, ScoopInfo),
 229         VMSTATE_UINT16(ccr, ScoopInfo),
 230         VMSTATE_UINT16(irr, ScoopInfo),
 231         VMSTATE_UINT16(imr, ScoopInfo),
 232         VMSTATE_UINT16(isr, ScoopInfo),
 233         VMSTATE_UNUSED_TEST(is_version_0, 2),
 234         VMSTATE_END_OF_LIST(),
 235     },
 236 };
 237
 238 static void scoop_sysbus_class_init(ObjectClass *klass, void *data)
 239 {
 240     DeviceClass *dc = DEVICE_CLASS(klass);
 241
 242     dc->desc = "Scoop2 Sharp custom ASIC";
 243     dc->vmsd = &vmstate_scoop_regs;
 244 }
 245
 246 static const TypeInfo scoop_sysbus_info = {
 247     .name          = TYPE_SCOOP,
 248     .parent        = TYPE_SYS_BUS_DEVICE,
 249     .instance_size = sizeof(ScoopInfo),
 250     .instance_init = scoop_init,
 251     .class_init    = scoop_sysbus_class_init,
 252 };
 253
 254 static void scoop_register_types(void)
 255 {
 256     type_register_static(&scoop_sysbus_info);
 257 }
 258
 259 type_init(scoop_register_types)
 260
 261 /* Write the bootloader parameters memory area.  */
 262
 263 #define MAGIC_CHG(a, b, c, d)   ((d << 24) | (c << 16) | (b << 8) | a)
 264
 265 static struct QEMU_PACKED sl_param_info {
 266     uint32_t comadj_keyword;
 267     int32_t comadj;
 268
 269     uint32_t uuid_keyword;
 270     char uuid[16];
 271
 272     uint32_t touch_keyword;
 273     int32_t touch_xp;
 274     int32_t touch_yp;
 275     int32_t touch_xd;
 276     int32_t touch_yd;
 277
 278     uint32_t adadj_keyword;
 279     int32_t adadj;
 280
 281     uint32_t phad_keyword;
 282     int32_t phadadj;
 283 } zaurus_bootparam = {
 284     .comadj_keyword     = MAGIC_CHG('C', 'M', 'A', 'D'),
 285     .comadj             = 125,
 286     .uuid_keyword       = MAGIC_CHG('U', 'U', 'I', 'D'),
 287     .uuid               = { -1 },
 288     .touch_keyword      = MAGIC_CHG('T', 'U', 'C', 'H'),
 289     .touch_xp           = -1,
 290     .adadj_keyword      = MAGIC_CHG('B', 'V', 'A', 'D'),
 291     .adadj              = -1,
 292     .phad_keyword       = MAGIC_CHG('P', 'H', 'A', 'D'),
 293     .phadadj            = 0x01,
 294 };
 295
 296 void sl_bootparam_write(hwaddr ptr)
 297 {
 298     cpu_physical_memory_write(ptr, &zaurus_bootparam,
 299                               sizeof(struct sl_param_info));
 300 }