2 * ARM VFP floating-point operations
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/helper-proto.h"
23 #include "internals.h"
26 #include "fpu/softfloat.h"
29 /* VFP support. We follow the convention used for VFP instructions:
30 Single precision routines have a "s" suffix, double precision a
35 /* Convert host exception flags to vfp form. */
36 static inline int vfp_exceptbits_from_host(int host_bits
)
40 if (host_bits
& float_flag_invalid
) {
43 if (host_bits
& float_flag_divbyzero
) {
46 if (host_bits
& float_flag_overflow
) {
49 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
)) {
52 if (host_bits
& float_flag_inexact
) {
55 if (host_bits
& float_flag_input_denormal
) {
61 /* Convert vfp exception flags to target form. */
62 static inline int vfp_exceptbits_to_host(int target_bits
)
66 if (target_bits
& 1) {
67 host_bits
|= float_flag_invalid
;
69 if (target_bits
& 2) {
70 host_bits
|= float_flag_divbyzero
;
72 if (target_bits
& 4) {
73 host_bits
|= float_flag_overflow
;
75 if (target_bits
& 8) {
76 host_bits
|= float_flag_underflow
;
78 if (target_bits
& 0x10) {
79 host_bits
|= float_flag_inexact
;
81 if (target_bits
& 0x80) {
82 host_bits
|= float_flag_input_denormal
;
87 static uint32_t vfp_get_fpscr_from_host(CPUARMState
*env
)
91 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
92 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
93 /* FZ16 does not generate an input denormal exception. */
94 i
|= (get_float_exception_flags(&env
->vfp
.fp_status_f16
)
95 & ~float_flag_input_denormal
);
96 i
|= (get_float_exception_flags(&env
->vfp
.standard_fp_status_f16
)
97 & ~float_flag_input_denormal
);
98 return vfp_exceptbits_from_host(i
);
101 static void vfp_set_fpscr_to_host(CPUARMState
*env
, uint32_t val
)
104 uint32_t changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
107 if (changed
& (3 << 22)) {
110 case FPROUNDING_TIEEVEN
:
111 i
= float_round_nearest_even
;
113 case FPROUNDING_POSINF
:
116 case FPROUNDING_NEGINF
:
117 i
= float_round_down
;
119 case FPROUNDING_ZERO
:
120 i
= float_round_to_zero
;
123 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
124 set_float_rounding_mode(i
, &env
->vfp
.fp_status_f16
);
126 if (changed
& FPCR_FZ16
) {
127 bool ftz_enabled
= val
& FPCR_FZ16
;
128 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
129 set_flush_to_zero(ftz_enabled
, &env
->vfp
.standard_fp_status_f16
);
130 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
131 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.standard_fp_status_f16
);
133 if (changed
& FPCR_FZ
) {
134 bool ftz_enabled
= val
& FPCR_FZ
;
135 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
136 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
138 if (changed
& FPCR_DN
) {
139 bool dnan_enabled
= val
& FPCR_DN
;
140 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status
);
141 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status_f16
);
145 * The exception flags are ORed together when we read fpscr so we
146 * only need to preserve the current state in one of our
147 * float_status values.
149 i
= vfp_exceptbits_to_host(val
);
150 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
151 set_float_exception_flags(0, &env
->vfp
.fp_status_f16
);
152 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
153 set_float_exception_flags(0, &env
->vfp
.standard_fp_status_f16
);
158 static uint32_t vfp_get_fpscr_from_host(CPUARMState
*env
)
163 static void vfp_set_fpscr_to_host(CPUARMState
*env
, uint32_t val
)
169 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
173 fpscr
= env
->vfp
.xregs
[ARM_VFP_FPSCR
]
174 | (env
->vfp
.vec_len
<< 16)
175 | (env
->vfp
.vec_stride
<< 20);
177 fpscr
|= vfp_get_fpscr_from_host(env
);
179 i
= env
->vfp
.qc
[0] | env
->vfp
.qc
[1] | env
->vfp
.qc
[2] | env
->vfp
.qc
[3];
180 fpscr
|= i
? FPCR_QC
: 0;
185 uint32_t vfp_get_fpscr(CPUARMState
*env
)
187 return HELPER(vfp_get_fpscr
)(env
);
190 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
192 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
193 if (!cpu_isar_feature(any_fp16
, env_archcpu(env
))) {
197 if (arm_feature(env
, ARM_FEATURE_M
)) {
199 * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
200 * and also for the trapped-exception-handling bits IxE.
205 vfp_set_fpscr_to_host(env
, val
);
208 * We don't implement trapped exception handling, so the
209 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
211 * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
212 * (which are stored in fp_status), and the other RES0 bits
213 * in between, then we clear all of the low 16 bits.
215 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = val
& 0xf7c80000;
216 env
->vfp
.vec_len
= (val
>> 16) & 7;
217 env
->vfp
.vec_stride
= (val
>> 20) & 3;
220 * The bit we set within fpscr_q is arbitrary; the register as a
221 * whole being zero/non-zero is what counts.
223 env
->vfp
.qc
[0] = val
& FPCR_QC
;
229 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
231 HELPER(vfp_set_fpscr
)(env
, val
);
236 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
238 #define VFP_BINOP(name) \
239 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \
241 float_status *fpst = fpstp; \
242 return float16_ ## name(a, b, fpst); \
244 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
246 float_status *fpst = fpstp; \
247 return float32_ ## name(a, b, fpst); \
249 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
251 float_status *fpst = fpstp; \
252 return float64_ ## name(a, b, fpst); \
264 dh_ctype_f16
VFP_HELPER(neg
, h
)(dh_ctype_f16 a
)
266 return float16_chs(a
);
269 float32
VFP_HELPER(neg
, s
)(float32 a
)
271 return float32_chs(a
);
274 float64
VFP_HELPER(neg
, d
)(float64 a
)
276 return float64_chs(a
);
279 dh_ctype_f16
VFP_HELPER(abs
, h
)(dh_ctype_f16 a
)
281 return float16_abs(a
);
284 float32
VFP_HELPER(abs
, s
)(float32 a
)
286 return float32_abs(a
);
289 float64
VFP_HELPER(abs
, d
)(float64 a
)
291 return float64_abs(a
);
294 dh_ctype_f16
VFP_HELPER(sqrt
, h
)(dh_ctype_f16 a
, CPUARMState
*env
)
296 return float16_sqrt(a
, &env
->vfp
.fp_status_f16
);
299 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
301 return float32_sqrt(a
, &env
->vfp
.fp_status
);
304 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
306 return float64_sqrt(a
, &env
->vfp
.fp_status
);
309 static void softfloat_to_vfp_compare(CPUARMState
*env
, FloatRelation cmp
)
313 case float_relation_equal
:
316 case float_relation_less
:
319 case float_relation_greater
:
322 case float_relation_unordered
:
326 g_assert_not_reached();
328 env
->vfp
.xregs
[ARM_VFP_FPSCR
] =
329 deposit32(env
->vfp
.xregs
[ARM_VFP_FPSCR
], 28, 4, flags
);
332 /* XXX: check quiet/signaling case */
333 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \
334 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
336 softfloat_to_vfp_compare(env, \
337 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \
339 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
341 softfloat_to_vfp_compare(env, \
342 FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \
344 DO_VFP_cmp(h
, float16
, dh_ctype_f16
, fp_status_f16
)
345 DO_VFP_cmp(s
, float32
, float32
, fp_status
)
346 DO_VFP_cmp(d
, float64
, float64
, fp_status
)
349 /* Integer to float and float to integer conversions */
351 #define CONV_ITOF(name, ftype, fsz, sign) \
352 ftype HELPER(name)(uint32_t x, void *fpstp) \
354 float_status *fpst = fpstp; \
355 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
358 #define CONV_FTOI(name, ftype, fsz, sign, round) \
359 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
361 float_status *fpst = fpstp; \
362 if (float##fsz##_is_any_nan(x)) { \
363 float_raise(float_flag_invalid, fpst); \
366 return float##fsz##_to_##sign##int32##round(x, fpst); \
369 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
370 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
371 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
372 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
374 FLOAT_CONVS(si
, h
, uint32_t, 16, )
375 FLOAT_CONVS(si
, s
, float32
, 32, )
376 FLOAT_CONVS(si
, d
, float64
, 64, )
377 FLOAT_CONVS(ui
, h
, uint32_t, 16, u
)
378 FLOAT_CONVS(ui
, s
, float32
, 32, u
)
379 FLOAT_CONVS(ui
, d
, float64
, 64, u
)
385 /* floating point conversion */
386 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
388 return float32_to_float64(x
, &env
->vfp
.fp_status
);
391 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
393 return float64_to_float32(x
, &env
->vfp
.fp_status
);
396 /* VFP3 fixed point conversion. */
397 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
398 ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
400 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
402 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
403 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
406 if (unlikely(float##fsz##_is_any_nan(x))) { \
407 float_raise(float_flag_invalid, fpst); \
410 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
413 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \
414 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
415 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
416 float_round_to_zero, _round_to_zero) \
417 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
418 get_float_rounding_mode(fpst), )
420 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \
421 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
422 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
423 get_float_rounding_mode(fpst), )
425 VFP_CONV_FIX(sh
, d
, 64, float64
, 64, int16
)
426 VFP_CONV_FIX(sl
, d
, 64, float64
, 64, int32
)
427 VFP_CONV_FIX_A64(sq
, d
, 64, float64
, 64, int64
)
428 VFP_CONV_FIX(uh
, d
, 64, float64
, 64, uint16
)
429 VFP_CONV_FIX(ul
, d
, 64, float64
, 64, uint32
)
430 VFP_CONV_FIX_A64(uq
, d
, 64, float64
, 64, uint64
)
431 VFP_CONV_FIX(sh
, s
, 32, float32
, 32, int16
)
432 VFP_CONV_FIX(sl
, s
, 32, float32
, 32, int32
)
433 VFP_CONV_FIX_A64(sq
, s
, 32, float32
, 64, int64
)
434 VFP_CONV_FIX(uh
, s
, 32, float32
, 32, uint16
)
435 VFP_CONV_FIX(ul
, s
, 32, float32
, 32, uint32
)
436 VFP_CONV_FIX_A64(uq
, s
, 32, float32
, 64, uint64
)
437 VFP_CONV_FIX(sh
, h
, 16, dh_ctype_f16
, 32, int16
)
438 VFP_CONV_FIX(sl
, h
, 16, dh_ctype_f16
, 32, int32
)
439 VFP_CONV_FIX_A64(sq
, h
, 16, dh_ctype_f16
, 64, int64
)
440 VFP_CONV_FIX(uh
, h
, 16, dh_ctype_f16
, 32, uint16
)
441 VFP_CONV_FIX(ul
, h
, 16, dh_ctype_f16
, 32, uint32
)
442 VFP_CONV_FIX_A64(uq
, h
, 16, dh_ctype_f16
, 64, uint64
)
445 #undef VFP_CONV_FIX_FLOAT
446 #undef VFP_CONV_FLOAT_FIX_ROUND
447 #undef VFP_CONV_FIX_A64
449 /* Set the current fp rounding mode and return the old one.
450 * The argument is a softfloat float_round_ value.
452 uint32_t HELPER(set_rmode
)(uint32_t rmode
, void *fpstp
)
454 float_status
*fp_status
= fpstp
;
456 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
457 set_float_rounding_mode(rmode
, fp_status
);
462 /* Half precision conversions. */
463 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
465 /* Squash FZ16 to 0 for the duration of conversion. In this case,
466 * it would affect flushing input denormals.
468 float_status
*fpst
= fpstp
;
469 bool save
= get_flush_inputs_to_zero(fpst
);
470 set_flush_inputs_to_zero(false, fpst
);
471 float32 r
= float16_to_float32(a
, !ahp_mode
, fpst
);
472 set_flush_inputs_to_zero(save
, fpst
);
476 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, void *fpstp
, uint32_t ahp_mode
)
478 /* Squash FZ16 to 0 for the duration of conversion. In this case,
479 * it would affect flushing output denormals.
481 float_status
*fpst
= fpstp
;
482 bool save
= get_flush_to_zero(fpst
);
483 set_flush_to_zero(false, fpst
);
484 float16 r
= float32_to_float16(a
, !ahp_mode
, fpst
);
485 set_flush_to_zero(save
, fpst
);
489 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
491 /* Squash FZ16 to 0 for the duration of conversion. In this case,
492 * it would affect flushing input denormals.
494 float_status
*fpst
= fpstp
;
495 bool save
= get_flush_inputs_to_zero(fpst
);
496 set_flush_inputs_to_zero(false, fpst
);
497 float64 r
= float16_to_float64(a
, !ahp_mode
, fpst
);
498 set_flush_inputs_to_zero(save
, fpst
);
502 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, void *fpstp
, uint32_t ahp_mode
)
504 /* Squash FZ16 to 0 for the duration of conversion. In this case,
505 * it would affect flushing output denormals.
507 float_status
*fpst
= fpstp
;
508 bool save
= get_flush_to_zero(fpst
);
509 set_flush_to_zero(false, fpst
);
510 float16 r
= float64_to_float16(a
, !ahp_mode
, fpst
);
511 set_flush_to_zero(save
, fpst
);
517 /* Constants 256 and 512 are used in some helpers; we avoid relying on
518 * int->float conversions at run-time. */
519 #define float64_256 make_float64(0x4070000000000000LL)
520 #define float64_512 make_float64(0x4080000000000000LL)
521 #define float16_maxnorm make_float16(0x7bff)
522 #define float32_maxnorm make_float32(0x7f7fffff)
523 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
525 /* Reciprocal functions
527 * The algorithm that must be used to calculate the estimate
528 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
531 /* See RecipEstimate()
533 * input is a 9 bit fixed point number
534 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
535 * result range 256 .. 511 for a number from 1.0 to 511/256.
538 static int recip_estimate(int input
)
541 assert(256 <= input
&& input
< 512);
545 assert(256 <= r
&& r
< 512);
550 * Common wrapper to call recip_estimate
552 * The parameters are exponent and 64 bit fraction (without implicit
553 * bit) where the binary point is nominally at bit 52. Returns a
554 * float64 which can then be rounded to the appropriate size by the
558 static uint64_t call_recip_estimate(int *exp
, int exp_off
, uint64_t frac
)
560 uint32_t scaled
, estimate
;
561 uint64_t result_frac
;
564 /* Handle sub-normals */
566 if (extract64(frac
, 51, 1) == 0) {
574 /* scaled = UInt('1':fraction<51:44>) */
575 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
576 estimate
= recip_estimate(scaled
);
578 result_exp
= exp_off
- *exp
;
579 result_frac
= deposit64(0, 44, 8, estimate
);
580 if (result_exp
== 0) {
581 result_frac
= deposit64(result_frac
>> 1, 51, 1, 1);
582 } else if (result_exp
== -1) {
583 result_frac
= deposit64(result_frac
>> 2, 50, 2, 1);
592 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
594 switch (fpst
->float_rounding_mode
) {
595 case float_round_nearest_even
: /* Round to Nearest */
597 case float_round_up
: /* Round to +Inf */
599 case float_round_down
: /* Round to -Inf */
601 case float_round_to_zero
: /* Round to Zero */
604 g_assert_not_reached();
608 uint32_t HELPER(recpe_f16
)(uint32_t input
, void *fpstp
)
610 float_status
*fpst
= fpstp
;
611 float16 f16
= float16_squash_input_denormal(input
, fpst
);
612 uint32_t f16_val
= float16_val(f16
);
613 uint32_t f16_sign
= float16_is_neg(f16
);
614 int f16_exp
= extract32(f16_val
, 10, 5);
615 uint32_t f16_frac
= extract32(f16_val
, 0, 10);
618 if (float16_is_any_nan(f16
)) {
620 if (float16_is_signaling_nan(f16
, fpst
)) {
621 float_raise(float_flag_invalid
, fpst
);
622 nan
= float16_silence_nan(f16
, fpst
);
624 if (fpst
->default_nan_mode
) {
625 nan
= float16_default_nan(fpst
);
628 } else if (float16_is_infinity(f16
)) {
629 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
630 } else if (float16_is_zero(f16
)) {
631 float_raise(float_flag_divbyzero
, fpst
);
632 return float16_set_sign(float16_infinity
, float16_is_neg(f16
));
633 } else if (float16_abs(f16
) < (1 << 8)) {
634 /* Abs(value) < 2.0^-16 */
635 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
636 if (round_to_inf(fpst
, f16_sign
)) {
637 return float16_set_sign(float16_infinity
, f16_sign
);
639 return float16_set_sign(float16_maxnorm
, f16_sign
);
641 } else if (f16_exp
>= 29 && fpst
->flush_to_zero
) {
642 float_raise(float_flag_underflow
, fpst
);
643 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
646 f64_frac
= call_recip_estimate(&f16_exp
, 29,
647 ((uint64_t) f16_frac
) << (52 - 10));
649 /* result = sign : result_exp<4:0> : fraction<51:42> */
650 f16_val
= deposit32(0, 15, 1, f16_sign
);
651 f16_val
= deposit32(f16_val
, 10, 5, f16_exp
);
652 f16_val
= deposit32(f16_val
, 0, 10, extract64(f64_frac
, 52 - 10, 10));
653 return make_float16(f16_val
);
656 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
658 float_status
*fpst
= fpstp
;
659 float32 f32
= float32_squash_input_denormal(input
, fpst
);
660 uint32_t f32_val
= float32_val(f32
);
661 bool f32_sign
= float32_is_neg(f32
);
662 int f32_exp
= extract32(f32_val
, 23, 8);
663 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
666 if (float32_is_any_nan(f32
)) {
668 if (float32_is_signaling_nan(f32
, fpst
)) {
669 float_raise(float_flag_invalid
, fpst
);
670 nan
= float32_silence_nan(f32
, fpst
);
672 if (fpst
->default_nan_mode
) {
673 nan
= float32_default_nan(fpst
);
676 } else if (float32_is_infinity(f32
)) {
677 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
678 } else if (float32_is_zero(f32
)) {
679 float_raise(float_flag_divbyzero
, fpst
);
680 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
681 } else if (float32_abs(f32
) < (1ULL << 21)) {
682 /* Abs(value) < 2.0^-128 */
683 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
684 if (round_to_inf(fpst
, f32_sign
)) {
685 return float32_set_sign(float32_infinity
, f32_sign
);
687 return float32_set_sign(float32_maxnorm
, f32_sign
);
689 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
690 float_raise(float_flag_underflow
, fpst
);
691 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
694 f64_frac
= call_recip_estimate(&f32_exp
, 253,
695 ((uint64_t) f32_frac
) << (52 - 23));
697 /* result = sign : result_exp<7:0> : fraction<51:29> */
698 f32_val
= deposit32(0, 31, 1, f32_sign
);
699 f32_val
= deposit32(f32_val
, 23, 8, f32_exp
);
700 f32_val
= deposit32(f32_val
, 0, 23, extract64(f64_frac
, 52 - 23, 23));
701 return make_float32(f32_val
);
704 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
706 float_status
*fpst
= fpstp
;
707 float64 f64
= float64_squash_input_denormal(input
, fpst
);
708 uint64_t f64_val
= float64_val(f64
);
709 bool f64_sign
= float64_is_neg(f64
);
710 int f64_exp
= extract64(f64_val
, 52, 11);
711 uint64_t f64_frac
= extract64(f64_val
, 0, 52);
713 /* Deal with any special cases */
714 if (float64_is_any_nan(f64
)) {
716 if (float64_is_signaling_nan(f64
, fpst
)) {
717 float_raise(float_flag_invalid
, fpst
);
718 nan
= float64_silence_nan(f64
, fpst
);
720 if (fpst
->default_nan_mode
) {
721 nan
= float64_default_nan(fpst
);
724 } else if (float64_is_infinity(f64
)) {
725 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
726 } else if (float64_is_zero(f64
)) {
727 float_raise(float_flag_divbyzero
, fpst
);
728 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
729 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
730 /* Abs(value) < 2.0^-1024 */
731 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
732 if (round_to_inf(fpst
, f64_sign
)) {
733 return float64_set_sign(float64_infinity
, f64_sign
);
735 return float64_set_sign(float64_maxnorm
, f64_sign
);
737 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
738 float_raise(float_flag_underflow
, fpst
);
739 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
742 f64_frac
= call_recip_estimate(&f64_exp
, 2045, f64_frac
);
744 /* result = sign : result_exp<10:0> : fraction<51:0>; */
745 f64_val
= deposit64(0, 63, 1, f64_sign
);
746 f64_val
= deposit64(f64_val
, 52, 11, f64_exp
);
747 f64_val
= deposit64(f64_val
, 0, 52, f64_frac
);
748 return make_float64(f64_val
);
751 /* The algorithm that must be used to calculate the estimate
752 * is specified by the ARM ARM.
755 static int do_recip_sqrt_estimate(int a
)
759 assert(128 <= a
&& a
< 512);
767 while (a
* (b
+ 1) * (b
+ 1) < (1 << 28)) {
770 estimate
= (b
+ 1) / 2;
771 assert(256 <= estimate
&& estimate
< 512);
777 static uint64_t recip_sqrt_estimate(int *exp
, int exp_off
, uint64_t frac
)
783 while (extract64(frac
, 51, 1) == 0) {
787 frac
= extract64(frac
, 0, 51) << 1;
791 /* scaled = UInt('01':fraction<51:45>) */
792 scaled
= deposit32(1 << 7, 0, 7, extract64(frac
, 45, 7));
794 /* scaled = UInt('1':fraction<51:44>) */
795 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
797 estimate
= do_recip_sqrt_estimate(scaled
);
799 *exp
= (exp_off
- *exp
) / 2;
800 return extract64(estimate
, 0, 8) << 44;
803 uint32_t HELPER(rsqrte_f16
)(uint32_t input
, void *fpstp
)
805 float_status
*s
= fpstp
;
806 float16 f16
= float16_squash_input_denormal(input
, s
);
807 uint16_t val
= float16_val(f16
);
808 bool f16_sign
= float16_is_neg(f16
);
809 int f16_exp
= extract32(val
, 10, 5);
810 uint16_t f16_frac
= extract32(val
, 0, 10);
813 if (float16_is_any_nan(f16
)) {
815 if (float16_is_signaling_nan(f16
, s
)) {
816 float_raise(float_flag_invalid
, s
);
817 nan
= float16_silence_nan(f16
, s
);
819 if (s
->default_nan_mode
) {
820 nan
= float16_default_nan(s
);
823 } else if (float16_is_zero(f16
)) {
824 float_raise(float_flag_divbyzero
, s
);
825 return float16_set_sign(float16_infinity
, f16_sign
);
826 } else if (f16_sign
) {
827 float_raise(float_flag_invalid
, s
);
828 return float16_default_nan(s
);
829 } else if (float16_is_infinity(f16
)) {
833 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
834 * preserving the parity of the exponent. */
836 f64_frac
= ((uint64_t) f16_frac
) << (52 - 10);
838 f64_frac
= recip_sqrt_estimate(&f16_exp
, 44, f64_frac
);
840 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
841 val
= deposit32(0, 15, 1, f16_sign
);
842 val
= deposit32(val
, 10, 5, f16_exp
);
843 val
= deposit32(val
, 2, 8, extract64(f64_frac
, 52 - 8, 8));
844 return make_float16(val
);
847 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
849 float_status
*s
= fpstp
;
850 float32 f32
= float32_squash_input_denormal(input
, s
);
851 uint32_t val
= float32_val(f32
);
852 uint32_t f32_sign
= float32_is_neg(f32
);
853 int f32_exp
= extract32(val
, 23, 8);
854 uint32_t f32_frac
= extract32(val
, 0, 23);
857 if (float32_is_any_nan(f32
)) {
859 if (float32_is_signaling_nan(f32
, s
)) {
860 float_raise(float_flag_invalid
, s
);
861 nan
= float32_silence_nan(f32
, s
);
863 if (s
->default_nan_mode
) {
864 nan
= float32_default_nan(s
);
867 } else if (float32_is_zero(f32
)) {
868 float_raise(float_flag_divbyzero
, s
);
869 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
870 } else if (float32_is_neg(f32
)) {
871 float_raise(float_flag_invalid
, s
);
872 return float32_default_nan(s
);
873 } else if (float32_is_infinity(f32
)) {
877 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
878 * preserving the parity of the exponent. */
880 f64_frac
= ((uint64_t) f32_frac
) << 29;
882 f64_frac
= recip_sqrt_estimate(&f32_exp
, 380, f64_frac
);
884 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
885 val
= deposit32(0, 31, 1, f32_sign
);
886 val
= deposit32(val
, 23, 8, f32_exp
);
887 val
= deposit32(val
, 15, 8, extract64(f64_frac
, 52 - 8, 8));
888 return make_float32(val
);
891 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
893 float_status
*s
= fpstp
;
894 float64 f64
= float64_squash_input_denormal(input
, s
);
895 uint64_t val
= float64_val(f64
);
896 bool f64_sign
= float64_is_neg(f64
);
897 int f64_exp
= extract64(val
, 52, 11);
898 uint64_t f64_frac
= extract64(val
, 0, 52);
900 if (float64_is_any_nan(f64
)) {
902 if (float64_is_signaling_nan(f64
, s
)) {
903 float_raise(float_flag_invalid
, s
);
904 nan
= float64_silence_nan(f64
, s
);
906 if (s
->default_nan_mode
) {
907 nan
= float64_default_nan(s
);
910 } else if (float64_is_zero(f64
)) {
911 float_raise(float_flag_divbyzero
, s
);
912 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
913 } else if (float64_is_neg(f64
)) {
914 float_raise(float_flag_invalid
, s
);
915 return float64_default_nan(s
);
916 } else if (float64_is_infinity(f64
)) {
920 f64_frac
= recip_sqrt_estimate(&f64_exp
, 3068, f64_frac
);
922 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
923 val
= deposit64(0, 61, 1, f64_sign
);
924 val
= deposit64(val
, 52, 11, f64_exp
);
925 val
= deposit64(val
, 44, 8, extract64(f64_frac
, 52 - 8, 8));
926 return make_float64(val
);
929 uint32_t HELPER(recpe_u32
)(uint32_t a
)
933 if ((a
& 0x80000000) == 0) {
937 input
= extract32(a
, 23, 9);
938 estimate
= recip_estimate(input
);
940 return deposit32(0, (32 - 9), 9, estimate
);
943 uint32_t HELPER(rsqrte_u32
)(uint32_t a
)
947 if ((a
& 0xc0000000) == 0) {
951 estimate
= do_recip_sqrt_estimate(extract32(a
, 23, 9));
953 return deposit32(0, 23, 9, estimate
);
956 /* VFPv4 fused multiply-accumulate */
957 dh_ctype_f16
VFP_HELPER(muladd
, h
)(dh_ctype_f16 a
, dh_ctype_f16 b
,
958 dh_ctype_f16 c
, void *fpstp
)
960 float_status
*fpst
= fpstp
;
961 return float16_muladd(a
, b
, c
, 0, fpst
);
964 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
966 float_status
*fpst
= fpstp
;
967 return float32_muladd(a
, b
, c
, 0, fpst
);
970 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
972 float_status
*fpst
= fpstp
;
973 return float64_muladd(a
, b
, c
, 0, fpst
);
976 /* ARMv8 round to integral */
977 dh_ctype_f16
HELPER(rinth_exact
)(dh_ctype_f16 x
, void *fp_status
)
979 return float16_round_to_int(x
, fp_status
);
982 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
984 return float32_round_to_int(x
, fp_status
);
987 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
989 return float64_round_to_int(x
, fp_status
);
992 dh_ctype_f16
HELPER(rinth
)(dh_ctype_f16 x
, void *fp_status
)
994 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
997 ret
= float16_round_to_int(x
, fp_status
);
999 /* Suppress any inexact exceptions the conversion produced */
1000 if (!(old_flags
& float_flag_inexact
)) {
1001 new_flags
= get_float_exception_flags(fp_status
);
1002 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1008 float32
HELPER(rints
)(float32 x
, void *fp_status
)
1010 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1013 ret
= float32_round_to_int(x
, fp_status
);
1015 /* Suppress any inexact exceptions the conversion produced */
1016 if (!(old_flags
& float_flag_inexact
)) {
1017 new_flags
= get_float_exception_flags(fp_status
);
1018 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1024 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
1026 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1029 ret
= float64_round_to_int(x
, fp_status
);
1031 new_flags
= get_float_exception_flags(fp_status
);
1033 /* Suppress any inexact exceptions the conversion produced */
1034 if (!(old_flags
& float_flag_inexact
)) {
1035 new_flags
= get_float_exception_flags(fp_status
);
1036 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1042 /* Convert ARM rounding mode to softfloat */
1043 int arm_rmode_to_sf(int rmode
)
1046 case FPROUNDING_TIEAWAY
:
1047 rmode
= float_round_ties_away
;
1049 case FPROUNDING_ODD
:
1050 /* FIXME: add support for TIEAWAY and ODD */
1051 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
1053 /* fall through for now */
1054 case FPROUNDING_TIEEVEN
:
1056 rmode
= float_round_nearest_even
;
1058 case FPROUNDING_POSINF
:
1059 rmode
= float_round_up
;
1061 case FPROUNDING_NEGINF
:
1062 rmode
= float_round_down
;
1064 case FPROUNDING_ZERO
:
1065 rmode
= float_round_to_zero
;
1072 * Implement float64 to int32_t conversion without saturation;
1073 * the result is supplied modulo 2^32.
1075 uint64_t HELPER(fjcvtzs
)(float64 value
, void *vstatus
)
1077 float_status
*status
= vstatus
;
1080 uint32_t inexact
= 1; /* !Z */
1082 sign
= extract64(value
, 63, 1);
1083 exp
= extract64(value
, 52, 11);
1084 frac
= extract64(value
, 0, 52);
1087 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
1090 if (status
->flush_inputs_to_zero
) {
1091 float_raise(float_flag_input_denormal
, status
);
1093 float_raise(float_flag_inexact
, status
);
1098 } else if (exp
== 0x7ff) {
1099 /* This operation raises Invalid for both NaN and overflow (Inf). */
1100 float_raise(float_flag_invalid
, status
);
1103 int true_exp
= exp
- 1023;
1104 int shift
= true_exp
- 52;
1106 /* Restore implicit bit. */
1109 /* Shift the fraction into place. */
1111 /* The number is so large we must shift the fraction left. */
1113 /* The fraction is shifted out entirely. */
1118 } else if (shift
> -64) {
1119 /* Normal case -- shift right and notice if bits shift out. */
1120 inexact
= (frac
<< (64 + shift
)) != 0;
1123 /* The fraction is shifted out entirely. */
1127 /* Notice overflow or inexact exceptions. */
1128 if (true_exp
> 31 || frac
> (sign
? 0x80000000ull
: 0x7fffffff)) {
1129 /* Overflow, for which this operation raises invalid. */
1130 float_raise(float_flag_invalid
, status
);
1132 } else if (inexact
) {
1133 float_raise(float_flag_inexact
, status
);
1136 /* Honor the sign. */
1142 /* Pack the result and the env->ZF representation of Z together. */
1143 return deposit64(frac
, 32, 32, inexact
);
1146 uint32_t HELPER(vjcvt
)(float64 value
, CPUARMState
*env
)
1148 uint64_t pair
= HELPER(fjcvtzs
)(value
, &env
->vfp
.fp_status
);
1149 uint32_t result
= pair
;
1150 uint32_t z
= (pair
>> 32) == 0;
1152 /* Store Z, clear NCV, in FPSCR.NZCV. */
1153 env
->vfp
.xregs
[ARM_VFP_FPSCR
]
1154 = (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & ~CPSR_NZCV
) | (z
* CPSR_Z
);
1159 /* Round a float32 to an integer that fits in int32_t or int64_t. */
1160 static float32
frint_s(float32 f
, float_status
*fpst
, int intsize
)
1162 int old_flags
= get_float_exception_flags(fpst
);
1163 uint32_t exp
= extract32(f
, 23, 8);
1165 if (unlikely(exp
== 0xff)) {
1170 /* Round and re-extract the exponent. */
1171 f
= float32_round_to_int(f
, fpst
);
1172 exp
= extract32(f
, 23, 8);
1174 /* Validate the range of the result. */
1175 if (exp
< 126 + intsize
) {
1176 /* abs(F) <= INT{N}_MAX */
1179 if (exp
== 126 + intsize
) {
1180 uint32_t sign
= extract32(f
, 31, 1);
1181 uint32_t frac
= extract32(f
, 0, 23);
1182 if (sign
&& frac
== 0) {
1183 /* F == INT{N}_MIN */
1190 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1191 * inexact exception float32_round_to_int may have raised.
1193 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1194 return (0x100u
+ 126u + intsize
) << 23;
1197 float32
HELPER(frint32_s
)(float32 f
, void *fpst
)
1199 return frint_s(f
, fpst
, 32);
1202 float32
HELPER(frint64_s
)(float32 f
, void *fpst
)
1204 return frint_s(f
, fpst
, 64);
1207 /* Round a float64 to an integer that fits in int32_t or int64_t. */
1208 static float64
frint_d(float64 f
, float_status
*fpst
, int intsize
)
1210 int old_flags
= get_float_exception_flags(fpst
);
1211 uint32_t exp
= extract64(f
, 52, 11);
1213 if (unlikely(exp
== 0x7ff)) {
1218 /* Round and re-extract the exponent. */
1219 f
= float64_round_to_int(f
, fpst
);
1220 exp
= extract64(f
, 52, 11);
1222 /* Validate the range of the result. */
1223 if (exp
< 1022 + intsize
) {
1224 /* abs(F) <= INT{N}_MAX */
1227 if (exp
== 1022 + intsize
) {
1228 uint64_t sign
= extract64(f
, 63, 1);
1229 uint64_t frac
= extract64(f
, 0, 52);
1230 if (sign
&& frac
== 0) {
1231 /* F == INT{N}_MIN */
1238 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1239 * inexact exception float64_round_to_int may have raised.
1241 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1242 return (uint64_t)(0x800 + 1022 + intsize
) << 52;
1245 float64
HELPER(frint32_d
)(float64 f
, void *fpst
)
1247 return frint_d(f
, fpst
, 32);
1250 float64
HELPER(frint64_d
)(float64 f
, void *fpst
)
1252 return frint_d(f
, fpst
, 64);
1255 void HELPER(check_hcr_el2_trap
)(CPUARMState
*env
, uint32_t rt
, uint32_t reg
)
1263 if (!(arm_hcr_el2_eff(env
) & HCR_TID3
)) {
1268 if (!(arm_hcr_el2_eff(env
) & HCR_TID0
)) {
1273 g_assert_not_reached();
1276 syndrome
= ((EC_FPIDTRAP
<< ARM_EL_EC_SHIFT
)
1278 | (1 << 24) | (0xe << 20) | (7 << 14)
1279 | (reg
<< 10) | (rt
<< 5) | 1);
1281 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);