hw/dma: Add SiFive platform DMA controller emulation
[qemu/ar7.git] / hw / display / ssd0323.c
blob32d27f008aefe0032987106b81ffb6ae017f75e9
1 /*
2 * SSD0323 OLED controller with OSRAM Pictiva 128x64 display.
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
8 */
10 /* The controller can support a variety of different displays, but we only
11 implement one. Most of the commends relating to brightness and geometry
12 setup are ignored. */
14 #include "qemu/osdep.h"
15 #include "hw/ssi/ssi.h"
16 #include "migration/vmstate.h"
17 #include "qemu/module.h"
18 #include "ui/console.h"
20 //#define DEBUG_SSD0323 1
22 #ifdef DEBUG_SSD0323
23 #define DPRINTF(fmt, ...) \
24 do { printf("ssd0323: " fmt , ## __VA_ARGS__); } while (0)
25 #define BADF(fmt, ...) \
26 do { \
27 fprintf(stderr, "ssd0323: error: " fmt , ## __VA_ARGS__); abort(); \
28 } while (0)
29 #else
30 #define DPRINTF(fmt, ...) do {} while(0)
31 #define BADF(fmt, ...) \
32 do { fprintf(stderr, "ssd0323: error: " fmt , ## __VA_ARGS__);} while (0)
33 #endif
35 /* Scaling factor for pixels. */
36 #define MAGNIFY 4
38 #define REMAP_SWAP_COLUMN 0x01
39 #define REMAP_SWAP_NYBBLE 0x02
40 #define REMAP_VERTICAL 0x04
41 #define REMAP_SWAP_COM 0x10
42 #define REMAP_SPLIT_COM 0x40
44 enum ssd0323_mode
46 SSD0323_CMD,
47 SSD0323_DATA
50 typedef struct {
51 SSISlave ssidev;
52 QemuConsole *con;
54 uint32_t cmd_len;
55 int32_t cmd;
56 int32_t cmd_data[8];
57 int32_t row;
58 int32_t row_start;
59 int32_t row_end;
60 int32_t col;
61 int32_t col_start;
62 int32_t col_end;
63 int32_t redraw;
64 int32_t remap;
65 uint32_t mode;
66 uint8_t framebuffer[128 * 80 / 2];
67 } ssd0323_state;
69 #define TYPE_SSD0323 "ssd0323"
70 #define SSD0323(obj) OBJECT_CHECK(ssd0323_state, (obj), TYPE_SSD0323)
73 static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
75 ssd0323_state *s = SSD0323(dev);
77 switch (s->mode) {
78 case SSD0323_DATA:
79 DPRINTF("data 0x%02x\n", data);
80 s->framebuffer[s->col + s->row * 64] = data;
81 if (s->remap & REMAP_VERTICAL) {
82 s->row++;
83 if (s->row > s->row_end) {
84 s->row = s->row_start;
85 s->col++;
87 if (s->col > s->col_end) {
88 s->col = s->col_start;
90 } else {
91 s->col++;
92 if (s->col > s->col_end) {
93 s->row++;
94 s->col = s->col_start;
96 if (s->row > s->row_end) {
97 s->row = s->row_start;
100 s->redraw = 1;
101 break;
102 case SSD0323_CMD:
103 DPRINTF("cmd 0x%02x\n", data);
104 if (s->cmd_len == 0) {
105 s->cmd = data;
106 } else {
107 s->cmd_data[s->cmd_len - 1] = data;
109 s->cmd_len++;
110 switch (s->cmd) {
111 #define DATA(x) if (s->cmd_len <= (x)) return 0
112 case 0x15: /* Set column. */
113 DATA(2);
114 s->col = s->col_start = s->cmd_data[0] % 64;
115 s->col_end = s->cmd_data[1] % 64;
116 break;
117 case 0x75: /* Set row. */
118 DATA(2);
119 s->row = s->row_start = s->cmd_data[0] % 80;
120 s->row_end = s->cmd_data[1] % 80;
121 break;
122 case 0x81: /* Set contrast */
123 DATA(1);
124 break;
125 case 0x84: case 0x85: case 0x86: /* Max current. */
126 DATA(0);
127 break;
128 case 0xa0: /* Set remapping. */
129 /* FIXME: Implement this. */
130 DATA(1);
131 s->remap = s->cmd_data[0];
132 break;
133 case 0xa1: /* Set display start line. */
134 case 0xa2: /* Set display offset. */
135 /* FIXME: Implement these. */
136 DATA(1);
137 break;
138 case 0xa4: /* Normal mode. */
139 case 0xa5: /* All on. */
140 case 0xa6: /* All off. */
141 case 0xa7: /* Inverse. */
142 /* FIXME: Implement these. */
143 DATA(0);
144 break;
145 case 0xa8: /* Set multiplex ratio. */
146 case 0xad: /* Set DC-DC converter. */
147 DATA(1);
148 /* Ignored. Don't care. */
149 break;
150 case 0xae: /* Display off. */
151 case 0xaf: /* Display on. */
152 DATA(0);
153 /* TODO: Implement power control. */
154 break;
155 case 0xb1: /* Set phase length. */
156 case 0xb2: /* Set row period. */
157 case 0xb3: /* Set clock rate. */
158 case 0xbc: /* Set precharge. */
159 case 0xbe: /* Set VCOMH. */
160 case 0xbf: /* Set segment low. */
161 DATA(1);
162 /* Ignored. Don't care. */
163 break;
164 case 0xb8: /* Set grey scale table. */
165 /* FIXME: Implement this. */
166 DATA(8);
167 break;
168 case 0xe3: /* NOP. */
169 DATA(0);
170 break;
171 case 0xff: /* Nasty hack because we don't handle chip selects
172 properly. */
173 break;
174 default:
175 BADF("Unknown command: 0x%x\n", data);
177 s->cmd_len = 0;
178 return 0;
180 return 0;
183 static void ssd0323_update_display(void *opaque)
185 ssd0323_state *s = (ssd0323_state *)opaque;
186 DisplaySurface *surface = qemu_console_surface(s->con);
187 uint8_t *dest;
188 uint8_t *src;
189 int x;
190 int y;
191 int i;
192 int line;
193 char *colors[16];
194 char colortab[MAGNIFY * 64];
195 char *p;
196 int dest_width;
198 if (!s->redraw)
199 return;
201 switch (surface_bits_per_pixel(surface)) {
202 case 0:
203 return;
204 case 15:
205 dest_width = 2;
206 break;
207 case 16:
208 dest_width = 2;
209 break;
210 case 24:
211 dest_width = 3;
212 break;
213 case 32:
214 dest_width = 4;
215 break;
216 default:
217 BADF("Bad color depth\n");
218 return;
220 p = colortab;
221 for (i = 0; i < 16; i++) {
222 int n;
223 colors[i] = p;
224 switch (surface_bits_per_pixel(surface)) {
225 case 15:
226 n = i * 2 + (i >> 3);
227 p[0] = n | (n << 5);
228 p[1] = (n << 2) | (n >> 3);
229 break;
230 case 16:
231 n = i * 2 + (i >> 3);
232 p[0] = n | (n << 6) | ((n << 1) & 0x20);
233 p[1] = (n << 3) | (n >> 2);
234 break;
235 case 24:
236 case 32:
237 n = (i << 4) | i;
238 p[0] = p[1] = p[2] = n;
239 break;
240 default:
241 BADF("Bad color depth\n");
242 return;
244 p += dest_width;
246 /* TODO: Implement row/column remapping. */
247 dest = surface_data(surface);
248 for (y = 0; y < 64; y++) {
249 line = y;
250 src = s->framebuffer + 64 * line;
251 for (x = 0; x < 64; x++) {
252 int val;
253 val = *src >> 4;
254 for (i = 0; i < MAGNIFY; i++) {
255 memcpy(dest, colors[val], dest_width);
256 dest += dest_width;
258 val = *src & 0xf;
259 for (i = 0; i < MAGNIFY; i++) {
260 memcpy(dest, colors[val], dest_width);
261 dest += dest_width;
263 src++;
265 for (i = 1; i < MAGNIFY; i++) {
266 memcpy(dest, dest - dest_width * MAGNIFY * 128,
267 dest_width * 128 * MAGNIFY);
268 dest += dest_width * 128 * MAGNIFY;
271 s->redraw = 0;
272 dpy_gfx_update(s->con, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY);
275 static void ssd0323_invalidate_display(void * opaque)
277 ssd0323_state *s = (ssd0323_state *)opaque;
278 s->redraw = 1;
281 /* Command/data input. */
282 static void ssd0323_cd(void *opaque, int n, int level)
284 ssd0323_state *s = (ssd0323_state *)opaque;
285 DPRINTF("%s mode\n", level ? "Data" : "Command");
286 s->mode = level ? SSD0323_DATA : SSD0323_CMD;
289 static int ssd0323_post_load(void *opaque, int version_id)
291 ssd0323_state *s = (ssd0323_state *)opaque;
293 if (s->cmd_len > ARRAY_SIZE(s->cmd_data)) {
294 return -EINVAL;
296 if (s->row < 0 || s->row >= 80) {
297 return -EINVAL;
299 if (s->row_start < 0 || s->row_start >= 80) {
300 return -EINVAL;
302 if (s->row_end < 0 || s->row_end >= 80) {
303 return -EINVAL;
305 if (s->col < 0 || s->col >= 64) {
306 return -EINVAL;
308 if (s->col_start < 0 || s->col_start >= 64) {
309 return -EINVAL;
311 if (s->col_end < 0 || s->col_end >= 64) {
312 return -EINVAL;
314 if (s->mode != SSD0323_CMD && s->mode != SSD0323_DATA) {
315 return -EINVAL;
318 return 0;
321 static const VMStateDescription vmstate_ssd0323 = {
322 .name = "ssd0323_oled",
323 .version_id = 2,
324 .minimum_version_id = 2,
325 .post_load = ssd0323_post_load,
326 .fields = (VMStateField []) {
327 VMSTATE_UINT32(cmd_len, ssd0323_state),
328 VMSTATE_INT32(cmd, ssd0323_state),
329 VMSTATE_INT32_ARRAY(cmd_data, ssd0323_state, 8),
330 VMSTATE_INT32(row, ssd0323_state),
331 VMSTATE_INT32(row_start, ssd0323_state),
332 VMSTATE_INT32(row_end, ssd0323_state),
333 VMSTATE_INT32(col, ssd0323_state),
334 VMSTATE_INT32(col_start, ssd0323_state),
335 VMSTATE_INT32(col_end, ssd0323_state),
336 VMSTATE_INT32(redraw, ssd0323_state),
337 VMSTATE_INT32(remap, ssd0323_state),
338 VMSTATE_UINT32(mode, ssd0323_state),
339 VMSTATE_BUFFER(framebuffer, ssd0323_state),
340 VMSTATE_SSI_SLAVE(ssidev, ssd0323_state),
341 VMSTATE_END_OF_LIST()
345 static const GraphicHwOps ssd0323_ops = {
346 .invalidate = ssd0323_invalidate_display,
347 .gfx_update = ssd0323_update_display,
350 static void ssd0323_realize(SSISlave *d, Error **errp)
352 DeviceState *dev = DEVICE(d);
353 ssd0323_state *s = SSD0323(d);
355 s->col_end = 63;
356 s->row_end = 79;
357 s->con = graphic_console_init(dev, 0, &ssd0323_ops, s);
358 qemu_console_resize(s->con, 128 * MAGNIFY, 64 * MAGNIFY);
360 qdev_init_gpio_in(dev, ssd0323_cd, 1);
363 static void ssd0323_class_init(ObjectClass *klass, void *data)
365 DeviceClass *dc = DEVICE_CLASS(klass);
366 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
368 k->realize = ssd0323_realize;
369 k->transfer = ssd0323_transfer;
370 k->cs_polarity = SSI_CS_HIGH;
371 dc->vmsd = &vmstate_ssd0323;
374 static const TypeInfo ssd0323_info = {
375 .name = TYPE_SSD0323,
376 .parent = TYPE_SSI_SLAVE,
377 .instance_size = sizeof(ssd0323_state),
378 .class_init = ssd0323_class_init,
381 static void ssd03232_register_types(void)
383 type_register_static(&ssd0323_info);
386 type_init(ssd03232_register_types)