4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu-common.h"
23 #include "target/arm/idau.h"
24 #include "qemu/module.h"
25 #include "qapi/error.h"
26 #include "qapi/visitor.h"
28 #include "internals.h"
29 #include "exec/exec-all.h"
30 #include "hw/qdev-properties.h"
31 #if !defined(CONFIG_USER_ONLY)
32 #include "hw/loader.h"
34 #include "sysemu/sysemu.h"
35 #include "sysemu/tcg.h"
36 #include "sysemu/hw_accel.h"
38 #include "disas/capstone.h"
39 #include "fpu/softfloat.h"
41 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
43 ARMCPU
*cpu
= ARM_CPU(cs
);
44 CPUARMState
*env
= &cpu
->env
;
50 env
->regs
[15] = value
& ~1;
51 env
->thumb
= value
& 1;
55 static void arm_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
57 ARMCPU
*cpu
= ARM_CPU(cs
);
58 CPUARMState
*env
= &cpu
->env
;
61 * It's OK to look at env for the current mode here, because it's
62 * never possible for an AArch64 TB to chain to an AArch32 TB.
67 env
->regs
[15] = tb
->pc
;
71 static bool arm_cpu_has_work(CPUState
*cs
)
73 ARMCPU
*cpu
= ARM_CPU(cs
);
75 return (cpu
->power_state
!= PSCI_OFF
)
76 && cs
->interrupt_request
&
77 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
78 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
79 | CPU_INTERRUPT_EXITTB
);
82 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
85 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
88 entry
->opaque
= opaque
;
90 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
93 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
96 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
99 entry
->opaque
= opaque
;
101 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
104 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
106 /* Reset a single ARMCPRegInfo register */
107 ARMCPRegInfo
*ri
= value
;
108 ARMCPU
*cpu
= opaque
;
110 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
115 ri
->resetfn(&cpu
->env
, ri
);
119 /* A zero offset is never possible as it would be regs[0]
120 * so we use it to indicate that reset is being handled elsewhere.
121 * This is basically only used for fields in non-core coprocessors
122 * (like the pxa2xx ones).
124 if (!ri
->fieldoffset
) {
128 if (cpreg_field_is_64bit(ri
)) {
129 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
131 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
135 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
137 /* Purely an assertion check: we've already done reset once,
138 * so now check that running the reset for the cpreg doesn't
139 * change its value. This traps bugs where two different cpregs
140 * both try to reset the same state field but to different values.
142 ARMCPRegInfo
*ri
= value
;
143 ARMCPU
*cpu
= opaque
;
144 uint64_t oldvalue
, newvalue
;
146 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
150 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
151 cp_reg_reset(key
, value
, opaque
);
152 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
153 assert(oldvalue
== newvalue
);
156 /* CPUClass::reset() */
157 static void arm_cpu_reset(CPUState
*s
)
159 ARMCPU
*cpu
= ARM_CPU(s
);
160 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
161 CPUARMState
*env
= &cpu
->env
;
163 acc
->parent_reset(s
);
165 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
167 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
168 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
170 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
171 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
172 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
173 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
175 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
176 s
->halted
= cpu
->start_powered_off
;
178 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
179 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
182 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
183 /* 64 bit CPUs always start in 64 bit mode */
185 #if defined(CONFIG_USER_ONLY)
186 env
->pstate
= PSTATE_MODE_EL0t
;
187 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
188 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
189 /* Enable all PAC keys. */
190 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
191 SCTLR_EnDA
| SCTLR_EnDB
);
192 /* Enable all PAC instructions */
193 env
->cp15
.hcr_el2
|= HCR_API
;
194 env
->cp15
.scr_el3
|= SCR_API
;
195 /* and to the FP/Neon instructions */
196 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
197 /* and to the SVE instructions */
198 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
199 env
->cp15
.cptr_el
[3] |= CPTR_EZ
;
200 /* with maximum vector length */
201 env
->vfp
.zcr_el
[1] = cpu
->sve_max_vq
- 1;
202 env
->vfp
.zcr_el
[2] = env
->vfp
.zcr_el
[1];
203 env
->vfp
.zcr_el
[3] = env
->vfp
.zcr_el
[1];
205 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
206 * turning on both here will produce smaller code and otherwise
207 * make no difference to the user-level emulation.
209 env
->cp15
.tcr_el
[1].raw_tcr
= (3ULL << 37);
211 /* Reset into the highest available EL */
212 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
213 env
->pstate
= PSTATE_MODE_EL3h
;
214 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
215 env
->pstate
= PSTATE_MODE_EL2h
;
217 env
->pstate
= PSTATE_MODE_EL1h
;
219 env
->pc
= cpu
->rvbar
;
222 #if defined(CONFIG_USER_ONLY)
223 /* Userspace expects access to cp10 and cp11 for FP/Neon */
224 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
228 #if defined(CONFIG_USER_ONLY)
229 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
230 /* For user mode we must enable access to coprocessors */
231 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
232 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
233 env
->cp15
.c15_cpar
= 3;
234 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
235 env
->cp15
.c15_cpar
= 1;
240 * If the highest available EL is EL2, AArch32 will start in Hyp
241 * mode; otherwise it starts in SVC. Note that if we start in
242 * AArch64 then these values in the uncached_cpsr will be ignored.
244 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
245 !arm_feature(env
, ARM_FEATURE_EL3
)) {
246 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
248 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
250 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
252 if (arm_feature(env
, ARM_FEATURE_M
)) {
253 uint32_t initial_msp
; /* Loaded from 0x0 */
254 uint32_t initial_pc
; /* Loaded from 0x4 */
258 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
259 env
->v7m
.secure
= true;
261 /* This bit resets to 0 if security is supported, but 1 if
262 * it is not. The bit is not present in v7M, but we set it
263 * here so we can avoid having to make checks on it conditional
264 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
266 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
269 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
270 * that it resets to 1, so QEMU always does that rather than making
271 * it dependent on CPU model. In v8M it is RES1.
273 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
274 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
275 if (arm_feature(env
, ARM_FEATURE_V8
)) {
276 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
277 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
278 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
280 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
281 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
282 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
285 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
286 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
287 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
288 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
290 /* Unlike A/R profile, M profile defines the reset LR value */
291 env
->regs
[14] = 0xffffffff;
293 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
295 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
296 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
297 rom
= rom_ptr(vecbase
, 8);
299 /* Address zero is covered by ROM which hasn't yet been
300 * copied into physical memory.
302 initial_msp
= ldl_p(rom
);
303 initial_pc
= ldl_p(rom
+ 4);
305 /* Address zero not covered by a ROM blob, or the ROM blob
306 * is in non-modifiable memory and this is a second reset after
307 * it got copied into memory. In the latter case, rom_ptr
308 * will return a NULL pointer and we should use ldl_phys instead.
310 initial_msp
= ldl_phys(s
->as
, vecbase
);
311 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
314 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
315 env
->regs
[15] = initial_pc
& ~1;
316 env
->thumb
= initial_pc
& 1;
319 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
320 * executing as AArch32 then check if highvecs are enabled and
321 * adjust the PC accordingly.
323 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
324 env
->regs
[15] = 0xFFFF0000;
327 /* M profile requires that reset clears the exclusive monitor;
328 * A profile does not, but clearing it makes more sense than having it
329 * set with an exclusive access on address zero.
331 arm_clear_exclusive(env
);
333 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
336 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
337 if (cpu
->pmsav7_dregion
> 0) {
338 if (arm_feature(env
, ARM_FEATURE_V8
)) {
339 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
340 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
341 * cpu
->pmsav7_dregion
);
342 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
343 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
344 * cpu
->pmsav7_dregion
);
345 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
346 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
347 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
348 * cpu
->pmsav7_dregion
);
349 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
350 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
351 * cpu
->pmsav7_dregion
);
353 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
354 memset(env
->pmsav7
.drbar
, 0,
355 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
356 memset(env
->pmsav7
.drsr
, 0,
357 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
358 memset(env
->pmsav7
.dracr
, 0,
359 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
362 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
363 env
->pmsav7
.rnr
[M_REG_S
] = 0;
364 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
365 env
->pmsav8
.mair0
[M_REG_S
] = 0;
366 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
367 env
->pmsav8
.mair1
[M_REG_S
] = 0;
370 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
371 if (cpu
->sau_sregion
> 0) {
372 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
373 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
376 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
377 * the Cortex-M33 does.
382 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
383 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
384 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
385 set_float_detect_tininess(float_tininess_before_rounding
,
386 &env
->vfp
.fp_status
);
387 set_float_detect_tininess(float_tininess_before_rounding
,
388 &env
->vfp
.standard_fp_status
);
389 set_float_detect_tininess(float_tininess_before_rounding
,
390 &env
->vfp
.fp_status_f16
);
391 #ifndef CONFIG_USER_ONLY
393 kvm_arm_reset_vcpu(cpu
);
397 hw_breakpoint_update_all(cpu
);
398 hw_watchpoint_update_all(cpu
);
401 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
403 CPUClass
*cc
= CPU_GET_CLASS(cs
);
404 CPUARMState
*env
= cs
->env_ptr
;
405 uint32_t cur_el
= arm_current_el(env
);
406 bool secure
= arm_is_secure(env
);
411 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
413 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
414 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
415 cs
->exception_index
= excp_idx
;
416 env
->exception
.target_el
= target_el
;
417 cc
->do_interrupt(cs
);
421 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
423 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
424 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
425 cs
->exception_index
= excp_idx
;
426 env
->exception
.target_el
= target_el
;
427 cc
->do_interrupt(cs
);
431 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
432 excp_idx
= EXCP_VIRQ
;
434 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
435 cs
->exception_index
= excp_idx
;
436 env
->exception
.target_el
= target_el
;
437 cc
->do_interrupt(cs
);
441 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
442 excp_idx
= EXCP_VFIQ
;
444 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
445 cs
->exception_index
= excp_idx
;
446 env
->exception
.target_el
= target_el
;
447 cc
->do_interrupt(cs
);
455 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
456 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
458 CPUClass
*cc
= CPU_GET_CLASS(cs
);
459 ARMCPU
*cpu
= ARM_CPU(cs
);
460 CPUARMState
*env
= &cpu
->env
;
463 /* ARMv7-M interrupt masking works differently than -A or -R.
464 * There is no FIQ/IRQ distinction. Instead of I and F bits
465 * masking FIQ and IRQ interrupts, an exception is taken only
466 * if it is higher priority than the current execution priority
467 * (which depends on state like BASEPRI, FAULTMASK and the
468 * currently active exception).
470 if (interrupt_request
& CPU_INTERRUPT_HARD
471 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
472 cs
->exception_index
= EXCP_IRQ
;
473 cc
->do_interrupt(cs
);
480 void arm_cpu_update_virq(ARMCPU
*cpu
)
483 * Update the interrupt level for VIRQ, which is the logical OR of
484 * the HCR_EL2.VI bit and the input line level from the GIC.
486 CPUARMState
*env
= &cpu
->env
;
487 CPUState
*cs
= CPU(cpu
);
489 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
490 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
492 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
494 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
496 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
501 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
504 * Update the interrupt level for VFIQ, which is the logical OR of
505 * the HCR_EL2.VF bit and the input line level from the GIC.
507 CPUARMState
*env
= &cpu
->env
;
508 CPUState
*cs
= CPU(cpu
);
510 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
511 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
513 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
515 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
517 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
522 #ifndef CONFIG_USER_ONLY
523 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
525 ARMCPU
*cpu
= opaque
;
526 CPUARMState
*env
= &cpu
->env
;
527 CPUState
*cs
= CPU(cpu
);
528 static const int mask
[] = {
529 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
530 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
531 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
532 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
536 env
->irq_line_state
|= mask
[irq
];
538 env
->irq_line_state
&= ~mask
[irq
];
543 assert(arm_feature(env
, ARM_FEATURE_EL2
));
544 arm_cpu_update_virq(cpu
);
547 assert(arm_feature(env
, ARM_FEATURE_EL2
));
548 arm_cpu_update_vfiq(cpu
);
553 cpu_interrupt(cs
, mask
[irq
]);
555 cpu_reset_interrupt(cs
, mask
[irq
]);
559 g_assert_not_reached();
563 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
566 ARMCPU
*cpu
= opaque
;
567 CPUARMState
*env
= &cpu
->env
;
568 CPUState
*cs
= CPU(cpu
);
569 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
570 uint32_t linestate_bit
;
574 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
575 linestate_bit
= CPU_INTERRUPT_HARD
;
578 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
579 linestate_bit
= CPU_INTERRUPT_FIQ
;
582 g_assert_not_reached();
586 env
->irq_line_state
|= linestate_bit
;
588 env
->irq_line_state
&= ~linestate_bit
;
591 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
592 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
596 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
598 ARMCPU
*cpu
= ARM_CPU(cs
);
599 CPUARMState
*env
= &cpu
->env
;
601 cpu_synchronize_state(cs
);
602 return arm_cpu_data_is_big_endian(env
);
607 static inline void set_feature(CPUARMState
*env
, int feature
)
609 env
->features
|= 1ULL << feature
;
612 static inline void unset_feature(CPUARMState
*env
, int feature
)
614 env
->features
&= ~(1ULL << feature
);
618 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
620 return print_insn_arm(pc
| 1, info
);
623 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
625 ARMCPU
*ac
= ARM_CPU(cpu
);
626 CPUARMState
*env
= &ac
->env
;
630 /* We might not be compiled with the A64 disassembler
631 * because it needs a C++ compiler. Leave print_insn
632 * unset in this case to use the caller default behaviour.
634 #if defined(CONFIG_ARM_A64_DIS)
635 info
->print_insn
= print_insn_arm_a64
;
637 info
->cap_arch
= CS_ARCH_ARM64
;
638 info
->cap_insn_unit
= 4;
639 info
->cap_insn_split
= 4;
643 info
->print_insn
= print_insn_thumb1
;
644 info
->cap_insn_unit
= 2;
645 info
->cap_insn_split
= 4;
646 cap_mode
= CS_MODE_THUMB
;
648 info
->print_insn
= print_insn_arm
;
649 info
->cap_insn_unit
= 4;
650 info
->cap_insn_split
= 4;
651 cap_mode
= CS_MODE_ARM
;
653 if (arm_feature(env
, ARM_FEATURE_V8
)) {
654 cap_mode
|= CS_MODE_V8
;
656 if (arm_feature(env
, ARM_FEATURE_M
)) {
657 cap_mode
|= CS_MODE_MCLASS
;
659 info
->cap_arch
= CS_ARCH_ARM
;
660 info
->cap_mode
= cap_mode
;
663 sctlr_b
= arm_sctlr_b(env
);
664 if (bswap_code(sctlr_b
)) {
665 #ifdef TARGET_WORDS_BIGENDIAN
666 info
->endian
= BFD_ENDIAN_LITTLE
;
668 info
->endian
= BFD_ENDIAN_BIG
;
671 info
->flags
&= ~INSN_ARM_BE32
;
672 #ifndef CONFIG_USER_ONLY
674 info
->flags
|= INSN_ARM_BE32
;
679 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
681 uint32_t Aff1
= idx
/ clustersz
;
682 uint32_t Aff0
= idx
% clustersz
;
683 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
686 static void cpreg_hashtable_data_destroy(gpointer data
)
689 * Destroy function for cpu->cp_regs hashtable data entries.
690 * We must free the name string because it was g_strdup()ed in
691 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
692 * from r->name because we know we definitely allocated it.
694 ARMCPRegInfo
*r
= data
;
696 g_free((void *)r
->name
);
700 static void arm_cpu_initfn(Object
*obj
)
702 ARMCPU
*cpu
= ARM_CPU(obj
);
704 cpu_set_cpustate_pointers(cpu
);
705 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
706 g_free
, cpreg_hashtable_data_destroy
);
708 QLIST_INIT(&cpu
->pre_el_change_hooks
);
709 QLIST_INIT(&cpu
->el_change_hooks
);
711 #ifndef CONFIG_USER_ONLY
712 /* Our inbound IRQ and FIQ lines */
714 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
715 * the same interface as non-KVM CPUs.
717 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
719 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
722 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
723 ARRAY_SIZE(cpu
->gt_timer_outputs
));
725 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
726 "gicv3-maintenance-interrupt", 1);
727 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
731 /* DTB consumers generally don't in fact care what the 'compatible'
732 * string is, so always provide some string and trust that a hypothetical
733 * picky DTB consumer will also provide a helpful error message.
735 cpu
->dtb_compatible
= "qemu,unknown";
736 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
737 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
740 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
744 static Property arm_cpu_reset_cbar_property
=
745 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
747 static Property arm_cpu_reset_hivecs_property
=
748 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
750 static Property arm_cpu_rvbar_property
=
751 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
753 static Property arm_cpu_has_el2_property
=
754 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
756 static Property arm_cpu_has_el3_property
=
757 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
759 static Property arm_cpu_cfgend_property
=
760 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
762 /* use property name "pmu" to match other archs and virt tools */
763 static Property arm_cpu_has_pmu_property
=
764 DEFINE_PROP_BOOL("pmu", ARMCPU
, has_pmu
, true);
766 static Property arm_cpu_has_vfp_property
=
767 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
769 static Property arm_cpu_has_neon_property
=
770 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
772 static Property arm_cpu_has_mpu_property
=
773 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
775 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
776 * because the CPU initfn will have already set cpu->pmsav7_dregion to
777 * the right value for that particular CPU type, and we don't want
778 * to override that with an incorrect constant value.
780 static Property arm_cpu_pmsav7_dregion_property
=
781 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
783 qdev_prop_uint32
, uint32_t);
785 static void arm_get_init_svtor(Object
*obj
, Visitor
*v
, const char *name
,
786 void *opaque
, Error
**errp
)
788 ARMCPU
*cpu
= ARM_CPU(obj
);
790 visit_type_uint32(v
, name
, &cpu
->init_svtor
, errp
);
793 static void arm_set_init_svtor(Object
*obj
, Visitor
*v
, const char *name
,
794 void *opaque
, Error
**errp
)
796 ARMCPU
*cpu
= ARM_CPU(obj
);
798 visit_type_uint32(v
, name
, &cpu
->init_svtor
, errp
);
801 void arm_cpu_post_init(Object
*obj
)
803 ARMCPU
*cpu
= ARM_CPU(obj
);
805 /* M profile implies PMSA. We have to do this here rather than
806 * in realize with the other feature-implication checks because
807 * we look at the PMSA bit to see if we should add some properties.
809 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
810 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
812 /* Similarly for the VFP feature bits */
813 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP4
)) {
814 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
816 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP3
)) {
817 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
820 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
821 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
822 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
826 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
827 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
831 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
832 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
836 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
837 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
838 * prevent "has_el3" from existing on CPUs which cannot support EL3.
840 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
843 #ifndef CONFIG_USER_ONLY
844 object_property_add_link(obj
, "secure-memory",
846 (Object
**)&cpu
->secure_memory
,
847 qdev_prop_allow_set_link_before_realize
,
848 OBJ_PROP_LINK_STRONG
,
853 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
854 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
,
858 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
859 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_pmu_property
,
864 * Allow user to turn off VFP and Neon support, but only for TCG --
865 * KVM does not currently allow us to lie to the guest about its
866 * ID/feature registers, so the guest always sees what the host has.
868 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
870 if (!kvm_enabled()) {
871 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
,
876 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
877 cpu
->has_neon
= true;
878 if (!kvm_enabled()) {
879 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
,
884 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
885 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
887 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
888 qdev_property_add_static(DEVICE(obj
),
889 &arm_cpu_pmsav7_dregion_property
,
894 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
895 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
896 qdev_prop_allow_set_link_before_realize
,
897 OBJ_PROP_LINK_STRONG
,
900 * M profile: initial value of the Secure VTOR. We can't just use
901 * a simple DEFINE_PROP_UINT32 for this because we want to permit
902 * the property to be set after realize.
904 object_property_add(obj
, "init-svtor", "uint32",
905 arm_get_init_svtor
, arm_set_init_svtor
,
906 NULL
, NULL
, &error_abort
);
909 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
,
913 static void arm_cpu_finalizefn(Object
*obj
)
915 ARMCPU
*cpu
= ARM_CPU(obj
);
916 ARMELChangeHook
*hook
, *next
;
918 g_hash_table_destroy(cpu
->cp_regs
);
920 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
921 QLIST_REMOVE(hook
, node
);
924 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
925 QLIST_REMOVE(hook
, node
);
928 #ifndef CONFIG_USER_ONLY
929 if (cpu
->pmu_timer
) {
930 timer_del(cpu
->pmu_timer
);
931 timer_deinit(cpu
->pmu_timer
);
932 timer_free(cpu
->pmu_timer
);
937 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
939 CPUState
*cs
= CPU(dev
);
940 ARMCPU
*cpu
= ARM_CPU(dev
);
941 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
942 CPUARMState
*env
= &cpu
->env
;
944 Error
*local_err
= NULL
;
945 bool no_aa32
= false;
947 /* If we needed to query the host kernel for the CPU features
948 * then it's possible that might have failed in the initfn, but
949 * this is the first point where we can report it.
951 if (cpu
->host_cpu_probe_failed
) {
952 if (!kvm_enabled()) {
953 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
955 error_setg(errp
, "Failed to retrieve host CPU features");
960 #ifndef CONFIG_USER_ONLY
961 /* The NVIC and M-profile CPU are two halves of a single piece of
962 * hardware; trying to use one without the other is a command line
963 * error and will result in segfaults if not caught here.
965 if (arm_feature(env
, ARM_FEATURE_M
)) {
967 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
972 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
977 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
978 arm_gt_ptimer_cb
, cpu
);
979 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
980 arm_gt_vtimer_cb
, cpu
);
981 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
982 arm_gt_htimer_cb
, cpu
);
983 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
984 arm_gt_stimer_cb
, cpu
);
987 cpu_exec_realizefn(cs
, &local_err
);
988 if (local_err
!= NULL
) {
989 error_propagate(errp
, local_err
);
993 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
994 cpu
->has_vfp
!= cpu
->has_neon
) {
996 * This is an architectural requirement for AArch64; AArch32 is
997 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1000 "AArch64 CPUs must have both VFP and Neon or neither");
1004 if (!cpu
->has_vfp
) {
1008 unset_feature(env
, ARM_FEATURE_VFP
);
1009 unset_feature(env
, ARM_FEATURE_VFP3
);
1010 unset_feature(env
, ARM_FEATURE_VFP4
);
1012 t
= cpu
->isar
.id_aa64isar1
;
1013 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1014 cpu
->isar
.id_aa64isar1
= t
;
1016 t
= cpu
->isar
.id_aa64pfr0
;
1017 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1018 cpu
->isar
.id_aa64pfr0
= t
;
1020 u
= cpu
->isar
.id_isar6
;
1021 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1022 cpu
->isar
.id_isar6
= u
;
1024 u
= cpu
->isar
.mvfr0
;
1025 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1026 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1027 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1028 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1029 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1030 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1031 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1032 cpu
->isar
.mvfr0
= u
;
1034 u
= cpu
->isar
.mvfr1
;
1035 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1036 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1037 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1038 cpu
->isar
.mvfr1
= u
;
1040 u
= cpu
->isar
.mvfr2
;
1041 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1042 cpu
->isar
.mvfr2
= u
;
1045 if (!cpu
->has_neon
) {
1049 unset_feature(env
, ARM_FEATURE_NEON
);
1051 t
= cpu
->isar
.id_aa64isar0
;
1052 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1053 cpu
->isar
.id_aa64isar0
= t
;
1055 t
= cpu
->isar
.id_aa64isar1
;
1056 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1057 cpu
->isar
.id_aa64isar1
= t
;
1059 t
= cpu
->isar
.id_aa64pfr0
;
1060 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1061 cpu
->isar
.id_aa64pfr0
= t
;
1063 u
= cpu
->isar
.id_isar5
;
1064 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1065 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1066 cpu
->isar
.id_isar5
= u
;
1068 u
= cpu
->isar
.id_isar6
;
1069 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1070 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1071 cpu
->isar
.id_isar6
= u
;
1073 u
= cpu
->isar
.mvfr1
;
1074 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1075 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1076 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1077 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1078 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1079 cpu
->isar
.mvfr1
= u
;
1081 u
= cpu
->isar
.mvfr2
;
1082 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1083 cpu
->isar
.mvfr2
= u
;
1086 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1090 t
= cpu
->isar
.id_aa64isar0
;
1091 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1092 cpu
->isar
.id_aa64isar0
= t
;
1094 t
= cpu
->isar
.id_aa64isar1
;
1095 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1096 cpu
->isar
.id_aa64isar1
= t
;
1098 u
= cpu
->isar
.mvfr0
;
1099 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1100 cpu
->isar
.mvfr0
= u
;
1103 /* Some features automatically imply others: */
1104 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1105 if (arm_feature(env
, ARM_FEATURE_M
)) {
1106 set_feature(env
, ARM_FEATURE_V7
);
1108 set_feature(env
, ARM_FEATURE_V7VE
);
1113 * There exist AArch64 cpus without AArch32 support. When KVM
1114 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1115 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1117 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1118 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1121 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1122 /* v7 Virtualization Extensions. In real hardware this implies
1123 * EL2 and also the presence of the Security Extensions.
1124 * For QEMU, for backwards-compatibility we implement some
1125 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1126 * include the various other features that V7VE implies.
1127 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1128 * Security Extensions is ARM_FEATURE_EL3.
1130 assert(no_aa32
|| cpu_isar_feature(arm_div
, cpu
));
1131 set_feature(env
, ARM_FEATURE_LPAE
);
1132 set_feature(env
, ARM_FEATURE_V7
);
1134 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1135 set_feature(env
, ARM_FEATURE_VAPA
);
1136 set_feature(env
, ARM_FEATURE_THUMB2
);
1137 set_feature(env
, ARM_FEATURE_MPIDR
);
1138 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1139 set_feature(env
, ARM_FEATURE_V6K
);
1141 set_feature(env
, ARM_FEATURE_V6
);
1144 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1145 * non-EL3 configs. This is needed by some legacy boards.
1147 set_feature(env
, ARM_FEATURE_VBAR
);
1149 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1150 set_feature(env
, ARM_FEATURE_V6
);
1151 set_feature(env
, ARM_FEATURE_MVFR
);
1153 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1154 set_feature(env
, ARM_FEATURE_V5
);
1155 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1156 assert(no_aa32
|| cpu_isar_feature(jazelle
, cpu
));
1157 set_feature(env
, ARM_FEATURE_AUXCR
);
1160 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1161 set_feature(env
, ARM_FEATURE_V4T
);
1163 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1164 set_feature(env
, ARM_FEATURE_V7MP
);
1165 set_feature(env
, ARM_FEATURE_PXN
);
1167 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1168 set_feature(env
, ARM_FEATURE_CBAR
);
1170 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1171 !arm_feature(env
, ARM_FEATURE_M
)) {
1172 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1176 * We rely on no XScale CPU having VFP so we can use the same bits in the
1177 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1179 assert(!(arm_feature(env
, ARM_FEATURE_VFP
) &&
1180 arm_feature(env
, ARM_FEATURE_XSCALE
)));
1182 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1183 !arm_feature(env
, ARM_FEATURE_M
) &&
1184 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1185 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1190 /* For CPUs which might have tiny 1K pages, or which have an
1191 * MPU and might have small region sizes, stick with 1K pages.
1195 if (!set_preferred_target_page_bits(pagebits
)) {
1196 /* This can only ever happen for hotplugging a CPU, or if
1197 * the board code incorrectly creates a CPU which it has
1198 * promised via minimum_page_size that it will not.
1200 error_setg(errp
, "This CPU requires a smaller page size than the "
1205 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1206 * We don't support setting cluster ID ([16..23]) (known as Aff2
1207 * in later ARM ARM versions), or any of the higher affinity level fields,
1208 * so these bits always RAZ.
1210 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1211 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1212 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1215 if (cpu
->reset_hivecs
) {
1216 cpu
->reset_sctlr
|= (1 << 13);
1220 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1221 cpu
->reset_sctlr
|= SCTLR_EE
;
1223 cpu
->reset_sctlr
|= SCTLR_B
;
1227 if (!cpu
->has_el3
) {
1228 /* If the has_el3 CPU property is disabled then we need to disable the
1231 unset_feature(env
, ARM_FEATURE_EL3
);
1233 /* Disable the security extension feature bits in the processor feature
1234 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1236 cpu
->id_pfr1
&= ~0xf0;
1237 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1240 if (!cpu
->has_el2
) {
1241 unset_feature(env
, ARM_FEATURE_EL2
);
1244 if (!cpu
->has_pmu
) {
1245 unset_feature(env
, ARM_FEATURE_PMU
);
1247 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1250 if (!kvm_enabled()) {
1251 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1252 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1255 #ifndef CONFIG_USER_ONLY
1256 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1260 cpu
->id_aa64dfr0
&= ~0xf00;
1261 cpu
->id_dfr0
&= ~(0xf << 24);
1266 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1267 /* Disable the hypervisor feature bits in the processor feature
1268 * registers if we don't have EL2. These are id_pfr1[15:12] and
1269 * id_aa64pfr0_el1[11:8].
1271 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1272 cpu
->id_pfr1
&= ~0xf000;
1275 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1276 * to false or by setting pmsav7-dregion to 0.
1278 if (!cpu
->has_mpu
) {
1279 cpu
->pmsav7_dregion
= 0;
1281 if (cpu
->pmsav7_dregion
== 0) {
1282 cpu
->has_mpu
= false;
1285 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1286 arm_feature(env
, ARM_FEATURE_V7
)) {
1287 uint32_t nr
= cpu
->pmsav7_dregion
;
1290 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1295 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1297 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1298 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1299 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1300 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1301 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1304 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1305 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1306 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1311 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1312 uint32_t nr
= cpu
->sau_sregion
;
1315 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1320 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1321 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1325 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1326 set_feature(env
, ARM_FEATURE_VBAR
);
1329 register_cp_regs_for_features(cpu
);
1330 arm_cpu_register_gdb_regs_for_features(cpu
);
1332 init_cpreg_list(cpu
);
1334 #ifndef CONFIG_USER_ONLY
1335 if (cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1338 if (!cpu
->secure_memory
) {
1339 cpu
->secure_memory
= cs
->memory
;
1341 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1342 cpu
->secure_memory
);
1346 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1348 /* No core_count specified, default to smp_cpus. */
1349 if (cpu
->core_count
== -1) {
1350 cpu
->core_count
= smp_cpus
;
1357 acc
->parent_realize(dev
, errp
);
1360 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1365 const char *cpunamestr
;
1367 cpuname
= g_strsplit(cpu_model
, ",", 1);
1368 cpunamestr
= cpuname
[0];
1369 #ifdef CONFIG_USER_ONLY
1370 /* For backwards compatibility usermode emulation allows "-cpu any",
1371 * which has the same semantics as "-cpu max".
1373 if (!strcmp(cpunamestr
, "any")) {
1377 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1378 oc
= object_class_by_name(typename
);
1379 g_strfreev(cpuname
);
1381 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1382 object_class_is_abstract(oc
)) {
1388 /* CPU models. These are not needed for the AArch64 linux-user build. */
1389 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1391 static void arm926_initfn(Object
*obj
)
1393 ARMCPU
*cpu
= ARM_CPU(obj
);
1395 cpu
->dtb_compatible
= "arm,arm926";
1396 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1397 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1398 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1399 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1400 cpu
->midr
= 0x41069265;
1401 cpu
->reset_fpsid
= 0x41011090;
1402 cpu
->ctr
= 0x1dd20d2;
1403 cpu
->reset_sctlr
= 0x00090078;
1406 * ARMv5 does not have the ID_ISAR registers, but we can still
1407 * set the field to indicate Jazelle support within QEMU.
1409 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1412 static void arm946_initfn(Object
*obj
)
1414 ARMCPU
*cpu
= ARM_CPU(obj
);
1416 cpu
->dtb_compatible
= "arm,arm946";
1417 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1418 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1419 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1420 cpu
->midr
= 0x41059461;
1421 cpu
->ctr
= 0x0f004006;
1422 cpu
->reset_sctlr
= 0x00000078;
1425 static void arm1026_initfn(Object
*obj
)
1427 ARMCPU
*cpu
= ARM_CPU(obj
);
1429 cpu
->dtb_compatible
= "arm,arm1026";
1430 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1431 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1432 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
1433 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1434 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1435 cpu
->midr
= 0x4106a262;
1436 cpu
->reset_fpsid
= 0x410110a0;
1437 cpu
->ctr
= 0x1dd20d2;
1438 cpu
->reset_sctlr
= 0x00090078;
1439 cpu
->reset_auxcr
= 1;
1442 * ARMv5 does not have the ID_ISAR registers, but we can still
1443 * set the field to indicate Jazelle support within QEMU.
1445 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1448 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1449 ARMCPRegInfo ifar
= {
1450 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1452 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
1455 define_one_arm_cp_reg(cpu
, &ifar
);
1459 static void arm1136_r2_initfn(Object
*obj
)
1461 ARMCPU
*cpu
= ARM_CPU(obj
);
1462 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1463 * older core than plain "arm1136". In particular this does not
1464 * have the v6K features.
1465 * These ID register values are correct for 1136 but may be wrong
1466 * for 1136_r2 (in particular r0p2 does not actually implement most
1467 * of the ID registers).
1470 cpu
->dtb_compatible
= "arm,arm1136";
1471 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1472 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1473 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1474 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1475 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1476 cpu
->midr
= 0x4107b362;
1477 cpu
->reset_fpsid
= 0x410120b4;
1478 cpu
->isar
.mvfr0
= 0x11111111;
1479 cpu
->isar
.mvfr1
= 0x00000000;
1480 cpu
->ctr
= 0x1dd20d2;
1481 cpu
->reset_sctlr
= 0x00050078;
1482 cpu
->id_pfr0
= 0x111;
1486 cpu
->id_mmfr0
= 0x01130003;
1487 cpu
->id_mmfr1
= 0x10030302;
1488 cpu
->id_mmfr2
= 0x01222110;
1489 cpu
->isar
.id_isar0
= 0x00140011;
1490 cpu
->isar
.id_isar1
= 0x12002111;
1491 cpu
->isar
.id_isar2
= 0x11231111;
1492 cpu
->isar
.id_isar3
= 0x01102131;
1493 cpu
->isar
.id_isar4
= 0x141;
1494 cpu
->reset_auxcr
= 7;
1497 static void arm1136_initfn(Object
*obj
)
1499 ARMCPU
*cpu
= ARM_CPU(obj
);
1501 cpu
->dtb_compatible
= "arm,arm1136";
1502 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1503 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1504 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1505 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1506 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1507 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1508 cpu
->midr
= 0x4117b363;
1509 cpu
->reset_fpsid
= 0x410120b4;
1510 cpu
->isar
.mvfr0
= 0x11111111;
1511 cpu
->isar
.mvfr1
= 0x00000000;
1512 cpu
->ctr
= 0x1dd20d2;
1513 cpu
->reset_sctlr
= 0x00050078;
1514 cpu
->id_pfr0
= 0x111;
1518 cpu
->id_mmfr0
= 0x01130003;
1519 cpu
->id_mmfr1
= 0x10030302;
1520 cpu
->id_mmfr2
= 0x01222110;
1521 cpu
->isar
.id_isar0
= 0x00140011;
1522 cpu
->isar
.id_isar1
= 0x12002111;
1523 cpu
->isar
.id_isar2
= 0x11231111;
1524 cpu
->isar
.id_isar3
= 0x01102131;
1525 cpu
->isar
.id_isar4
= 0x141;
1526 cpu
->reset_auxcr
= 7;
1529 static void arm1176_initfn(Object
*obj
)
1531 ARMCPU
*cpu
= ARM_CPU(obj
);
1533 cpu
->dtb_compatible
= "arm,arm1176";
1534 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1535 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1536 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1537 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1538 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1539 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1540 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1541 cpu
->midr
= 0x410fb767;
1542 cpu
->reset_fpsid
= 0x410120b5;
1543 cpu
->isar
.mvfr0
= 0x11111111;
1544 cpu
->isar
.mvfr1
= 0x00000000;
1545 cpu
->ctr
= 0x1dd20d2;
1546 cpu
->reset_sctlr
= 0x00050078;
1547 cpu
->id_pfr0
= 0x111;
1548 cpu
->id_pfr1
= 0x11;
1549 cpu
->id_dfr0
= 0x33;
1551 cpu
->id_mmfr0
= 0x01130003;
1552 cpu
->id_mmfr1
= 0x10030302;
1553 cpu
->id_mmfr2
= 0x01222100;
1554 cpu
->isar
.id_isar0
= 0x0140011;
1555 cpu
->isar
.id_isar1
= 0x12002111;
1556 cpu
->isar
.id_isar2
= 0x11231121;
1557 cpu
->isar
.id_isar3
= 0x01102131;
1558 cpu
->isar
.id_isar4
= 0x01141;
1559 cpu
->reset_auxcr
= 7;
1562 static void arm11mpcore_initfn(Object
*obj
)
1564 ARMCPU
*cpu
= ARM_CPU(obj
);
1566 cpu
->dtb_compatible
= "arm,arm11mpcore";
1567 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1568 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1569 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1570 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
1571 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1572 cpu
->midr
= 0x410fb022;
1573 cpu
->reset_fpsid
= 0x410120b4;
1574 cpu
->isar
.mvfr0
= 0x11111111;
1575 cpu
->isar
.mvfr1
= 0x00000000;
1576 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
1577 cpu
->id_pfr0
= 0x111;
1581 cpu
->id_mmfr0
= 0x01100103;
1582 cpu
->id_mmfr1
= 0x10020302;
1583 cpu
->id_mmfr2
= 0x01222000;
1584 cpu
->isar
.id_isar0
= 0x00100011;
1585 cpu
->isar
.id_isar1
= 0x12002111;
1586 cpu
->isar
.id_isar2
= 0x11221011;
1587 cpu
->isar
.id_isar3
= 0x01102131;
1588 cpu
->isar
.id_isar4
= 0x141;
1589 cpu
->reset_auxcr
= 1;
1592 static void cortex_m0_initfn(Object
*obj
)
1594 ARMCPU
*cpu
= ARM_CPU(obj
);
1595 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1596 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1598 cpu
->midr
= 0x410cc200;
1601 static void cortex_m3_initfn(Object
*obj
)
1603 ARMCPU
*cpu
= ARM_CPU(obj
);
1604 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1605 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1606 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1607 cpu
->midr
= 0x410fc231;
1608 cpu
->pmsav7_dregion
= 8;
1609 cpu
->id_pfr0
= 0x00000030;
1610 cpu
->id_pfr1
= 0x00000200;
1611 cpu
->id_dfr0
= 0x00100000;
1612 cpu
->id_afr0
= 0x00000000;
1613 cpu
->id_mmfr0
= 0x00000030;
1614 cpu
->id_mmfr1
= 0x00000000;
1615 cpu
->id_mmfr2
= 0x00000000;
1616 cpu
->id_mmfr3
= 0x00000000;
1617 cpu
->isar
.id_isar0
= 0x01141110;
1618 cpu
->isar
.id_isar1
= 0x02111000;
1619 cpu
->isar
.id_isar2
= 0x21112231;
1620 cpu
->isar
.id_isar3
= 0x01111110;
1621 cpu
->isar
.id_isar4
= 0x01310102;
1622 cpu
->isar
.id_isar5
= 0x00000000;
1623 cpu
->isar
.id_isar6
= 0x00000000;
1626 static void cortex_m4_initfn(Object
*obj
)
1628 ARMCPU
*cpu
= ARM_CPU(obj
);
1630 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1631 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1632 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1633 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1634 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1635 cpu
->midr
= 0x410fc240; /* r0p0 */
1636 cpu
->pmsav7_dregion
= 8;
1637 cpu
->isar
.mvfr0
= 0x10110021;
1638 cpu
->isar
.mvfr1
= 0x11000011;
1639 cpu
->isar
.mvfr2
= 0x00000000;
1640 cpu
->id_pfr0
= 0x00000030;
1641 cpu
->id_pfr1
= 0x00000200;
1642 cpu
->id_dfr0
= 0x00100000;
1643 cpu
->id_afr0
= 0x00000000;
1644 cpu
->id_mmfr0
= 0x00000030;
1645 cpu
->id_mmfr1
= 0x00000000;
1646 cpu
->id_mmfr2
= 0x00000000;
1647 cpu
->id_mmfr3
= 0x00000000;
1648 cpu
->isar
.id_isar0
= 0x01141110;
1649 cpu
->isar
.id_isar1
= 0x02111000;
1650 cpu
->isar
.id_isar2
= 0x21112231;
1651 cpu
->isar
.id_isar3
= 0x01111110;
1652 cpu
->isar
.id_isar4
= 0x01310102;
1653 cpu
->isar
.id_isar5
= 0x00000000;
1654 cpu
->isar
.id_isar6
= 0x00000000;
1657 static void cortex_m33_initfn(Object
*obj
)
1659 ARMCPU
*cpu
= ARM_CPU(obj
);
1661 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1662 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1663 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1664 set_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
);
1665 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1666 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1667 cpu
->midr
= 0x410fd213; /* r0p3 */
1668 cpu
->pmsav7_dregion
= 16;
1669 cpu
->sau_sregion
= 8;
1670 cpu
->isar
.mvfr0
= 0x10110021;
1671 cpu
->isar
.mvfr1
= 0x11000011;
1672 cpu
->isar
.mvfr2
= 0x00000040;
1673 cpu
->id_pfr0
= 0x00000030;
1674 cpu
->id_pfr1
= 0x00000210;
1675 cpu
->id_dfr0
= 0x00200000;
1676 cpu
->id_afr0
= 0x00000000;
1677 cpu
->id_mmfr0
= 0x00101F40;
1678 cpu
->id_mmfr1
= 0x00000000;
1679 cpu
->id_mmfr2
= 0x01000000;
1680 cpu
->id_mmfr3
= 0x00000000;
1681 cpu
->isar
.id_isar0
= 0x01101110;
1682 cpu
->isar
.id_isar1
= 0x02212000;
1683 cpu
->isar
.id_isar2
= 0x20232232;
1684 cpu
->isar
.id_isar3
= 0x01111131;
1685 cpu
->isar
.id_isar4
= 0x01310132;
1686 cpu
->isar
.id_isar5
= 0x00000000;
1687 cpu
->isar
.id_isar6
= 0x00000000;
1688 cpu
->clidr
= 0x00000000;
1689 cpu
->ctr
= 0x8000c000;
1692 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
1694 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1695 CPUClass
*cc
= CPU_CLASS(oc
);
1698 #ifndef CONFIG_USER_ONLY
1699 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
1702 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
1705 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
1706 /* Dummy the TCM region regs for the moment */
1707 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
1708 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1709 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
1710 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1711 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
1712 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
1716 static void cortex_r5_initfn(Object
*obj
)
1718 ARMCPU
*cpu
= ARM_CPU(obj
);
1720 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1721 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1722 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1723 cpu
->midr
= 0x411fc153; /* r1p3 */
1724 cpu
->id_pfr0
= 0x0131;
1725 cpu
->id_pfr1
= 0x001;
1726 cpu
->id_dfr0
= 0x010400;
1728 cpu
->id_mmfr0
= 0x0210030;
1729 cpu
->id_mmfr1
= 0x00000000;
1730 cpu
->id_mmfr2
= 0x01200000;
1731 cpu
->id_mmfr3
= 0x0211;
1732 cpu
->isar
.id_isar0
= 0x02101111;
1733 cpu
->isar
.id_isar1
= 0x13112111;
1734 cpu
->isar
.id_isar2
= 0x21232141;
1735 cpu
->isar
.id_isar3
= 0x01112131;
1736 cpu
->isar
.id_isar4
= 0x0010142;
1737 cpu
->isar
.id_isar5
= 0x0;
1738 cpu
->isar
.id_isar6
= 0x0;
1739 cpu
->mp_is_up
= true;
1740 cpu
->pmsav7_dregion
= 16;
1741 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
1744 static void cortex_r5f_initfn(Object
*obj
)
1746 ARMCPU
*cpu
= ARM_CPU(obj
);
1748 cortex_r5_initfn(obj
);
1749 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1750 cpu
->isar
.mvfr0
= 0x10110221;
1751 cpu
->isar
.mvfr1
= 0x00000011;
1754 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
1755 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
1756 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1757 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1758 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1762 static void cortex_a8_initfn(Object
*obj
)
1764 ARMCPU
*cpu
= ARM_CPU(obj
);
1766 cpu
->dtb_compatible
= "arm,cortex-a8";
1767 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1768 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1769 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1770 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1771 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1772 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1773 cpu
->midr
= 0x410fc080;
1774 cpu
->reset_fpsid
= 0x410330c0;
1775 cpu
->isar
.mvfr0
= 0x11110222;
1776 cpu
->isar
.mvfr1
= 0x00011111;
1777 cpu
->ctr
= 0x82048004;
1778 cpu
->reset_sctlr
= 0x00c50078;
1779 cpu
->id_pfr0
= 0x1031;
1780 cpu
->id_pfr1
= 0x11;
1781 cpu
->id_dfr0
= 0x400;
1783 cpu
->id_mmfr0
= 0x31100003;
1784 cpu
->id_mmfr1
= 0x20000000;
1785 cpu
->id_mmfr2
= 0x01202000;
1786 cpu
->id_mmfr3
= 0x11;
1787 cpu
->isar
.id_isar0
= 0x00101111;
1788 cpu
->isar
.id_isar1
= 0x12112111;
1789 cpu
->isar
.id_isar2
= 0x21232031;
1790 cpu
->isar
.id_isar3
= 0x11112131;
1791 cpu
->isar
.id_isar4
= 0x00111142;
1792 cpu
->dbgdidr
= 0x15141000;
1793 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1794 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1795 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1796 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1797 cpu
->reset_auxcr
= 2;
1798 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1801 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1802 /* power_control should be set to maximum latency. Again,
1803 * default to 0 and set by private hook
1805 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1806 .access
= PL1_RW
, .resetvalue
= 0,
1807 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1808 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1809 .access
= PL1_RW
, .resetvalue
= 0,
1810 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1811 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1812 .access
= PL1_RW
, .resetvalue
= 0,
1813 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1814 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1815 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1816 /* TLB lockdown control */
1817 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1818 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1819 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1820 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1821 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1822 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1823 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1824 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1825 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1826 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1830 static void cortex_a9_initfn(Object
*obj
)
1832 ARMCPU
*cpu
= ARM_CPU(obj
);
1834 cpu
->dtb_compatible
= "arm,cortex-a9";
1835 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1836 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1837 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1838 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1839 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1840 /* Note that A9 supports the MP extensions even for
1841 * A9UP and single-core A9MP (which are both different
1842 * and valid configurations; we don't model A9UP).
1844 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1845 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1846 cpu
->midr
= 0x410fc090;
1847 cpu
->reset_fpsid
= 0x41033090;
1848 cpu
->isar
.mvfr0
= 0x11110222;
1849 cpu
->isar
.mvfr1
= 0x01111111;
1850 cpu
->ctr
= 0x80038003;
1851 cpu
->reset_sctlr
= 0x00c50078;
1852 cpu
->id_pfr0
= 0x1031;
1853 cpu
->id_pfr1
= 0x11;
1854 cpu
->id_dfr0
= 0x000;
1856 cpu
->id_mmfr0
= 0x00100103;
1857 cpu
->id_mmfr1
= 0x20000000;
1858 cpu
->id_mmfr2
= 0x01230000;
1859 cpu
->id_mmfr3
= 0x00002111;
1860 cpu
->isar
.id_isar0
= 0x00101111;
1861 cpu
->isar
.id_isar1
= 0x13112111;
1862 cpu
->isar
.id_isar2
= 0x21232041;
1863 cpu
->isar
.id_isar3
= 0x11112131;
1864 cpu
->isar
.id_isar4
= 0x00111142;
1865 cpu
->dbgdidr
= 0x35141000;
1866 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1867 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1868 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1869 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1872 #ifndef CONFIG_USER_ONLY
1873 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1875 /* Linux wants the number of processors from here.
1876 * Might as well set the interrupt-controller bit too.
1878 return ((smp_cpus
- 1) << 24) | (1 << 23);
1882 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
1883 #ifndef CONFIG_USER_ONLY
1884 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1885 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
1886 .writefn
= arm_cp_write_ignore
, },
1888 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
1889 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1893 static void cortex_a7_initfn(Object
*obj
)
1895 ARMCPU
*cpu
= ARM_CPU(obj
);
1897 cpu
->dtb_compatible
= "arm,cortex-a7";
1898 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
1899 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1900 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1901 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1902 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1903 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1904 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1905 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
1906 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1907 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1908 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
1909 cpu
->midr
= 0x410fc075;
1910 cpu
->reset_fpsid
= 0x41023075;
1911 cpu
->isar
.mvfr0
= 0x10110222;
1912 cpu
->isar
.mvfr1
= 0x11111111;
1913 cpu
->ctr
= 0x84448003;
1914 cpu
->reset_sctlr
= 0x00c50078;
1915 cpu
->id_pfr0
= 0x00001131;
1916 cpu
->id_pfr1
= 0x00011011;
1917 cpu
->id_dfr0
= 0x02010555;
1918 cpu
->id_afr0
= 0x00000000;
1919 cpu
->id_mmfr0
= 0x10101105;
1920 cpu
->id_mmfr1
= 0x40000000;
1921 cpu
->id_mmfr2
= 0x01240000;
1922 cpu
->id_mmfr3
= 0x02102211;
1923 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
1924 * table 4-41 gives 0x02101110, which includes the arm div insns.
1926 cpu
->isar
.id_isar0
= 0x02101110;
1927 cpu
->isar
.id_isar1
= 0x13112111;
1928 cpu
->isar
.id_isar2
= 0x21232041;
1929 cpu
->isar
.id_isar3
= 0x11112131;
1930 cpu
->isar
.id_isar4
= 0x10011142;
1931 cpu
->dbgdidr
= 0x3515f005;
1932 cpu
->clidr
= 0x0a200023;
1933 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1934 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1935 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1936 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
1939 static void cortex_a15_initfn(Object
*obj
)
1941 ARMCPU
*cpu
= ARM_CPU(obj
);
1943 cpu
->dtb_compatible
= "arm,cortex-a15";
1944 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
1945 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1946 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1947 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1948 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1949 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1950 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1951 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
1952 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1953 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1954 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1955 cpu
->midr
= 0x412fc0f1;
1956 cpu
->reset_fpsid
= 0x410430f0;
1957 cpu
->isar
.mvfr0
= 0x10110222;
1958 cpu
->isar
.mvfr1
= 0x11111111;
1959 cpu
->ctr
= 0x8444c004;
1960 cpu
->reset_sctlr
= 0x00c50078;
1961 cpu
->id_pfr0
= 0x00001131;
1962 cpu
->id_pfr1
= 0x00011011;
1963 cpu
->id_dfr0
= 0x02010555;
1964 cpu
->id_afr0
= 0x00000000;
1965 cpu
->id_mmfr0
= 0x10201105;
1966 cpu
->id_mmfr1
= 0x20000000;
1967 cpu
->id_mmfr2
= 0x01240000;
1968 cpu
->id_mmfr3
= 0x02102211;
1969 cpu
->isar
.id_isar0
= 0x02101110;
1970 cpu
->isar
.id_isar1
= 0x13112111;
1971 cpu
->isar
.id_isar2
= 0x21232041;
1972 cpu
->isar
.id_isar3
= 0x11112131;
1973 cpu
->isar
.id_isar4
= 0x10011142;
1974 cpu
->dbgdidr
= 0x3515f021;
1975 cpu
->clidr
= 0x0a200023;
1976 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1977 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1978 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1979 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1982 static void ti925t_initfn(Object
*obj
)
1984 ARMCPU
*cpu
= ARM_CPU(obj
);
1985 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1986 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1987 cpu
->midr
= ARM_CPUID_TI925T
;
1988 cpu
->ctr
= 0x5109149;
1989 cpu
->reset_sctlr
= 0x00000070;
1992 static void sa1100_initfn(Object
*obj
)
1994 ARMCPU
*cpu
= ARM_CPU(obj
);
1996 cpu
->dtb_compatible
= "intel,sa1100";
1997 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1998 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1999 cpu
->midr
= 0x4401A11B;
2000 cpu
->reset_sctlr
= 0x00000070;
2003 static void sa1110_initfn(Object
*obj
)
2005 ARMCPU
*cpu
= ARM_CPU(obj
);
2006 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
2007 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2008 cpu
->midr
= 0x6901B119;
2009 cpu
->reset_sctlr
= 0x00000070;
2012 static void pxa250_initfn(Object
*obj
)
2014 ARMCPU
*cpu
= ARM_CPU(obj
);
2016 cpu
->dtb_compatible
= "marvell,xscale";
2017 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2018 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2019 cpu
->midr
= 0x69052100;
2020 cpu
->ctr
= 0xd172172;
2021 cpu
->reset_sctlr
= 0x00000078;
2024 static void pxa255_initfn(Object
*obj
)
2026 ARMCPU
*cpu
= ARM_CPU(obj
);
2028 cpu
->dtb_compatible
= "marvell,xscale";
2029 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2030 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2031 cpu
->midr
= 0x69052d00;
2032 cpu
->ctr
= 0xd172172;
2033 cpu
->reset_sctlr
= 0x00000078;
2036 static void pxa260_initfn(Object
*obj
)
2038 ARMCPU
*cpu
= ARM_CPU(obj
);
2040 cpu
->dtb_compatible
= "marvell,xscale";
2041 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2042 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2043 cpu
->midr
= 0x69052903;
2044 cpu
->ctr
= 0xd172172;
2045 cpu
->reset_sctlr
= 0x00000078;
2048 static void pxa261_initfn(Object
*obj
)
2050 ARMCPU
*cpu
= ARM_CPU(obj
);
2052 cpu
->dtb_compatible
= "marvell,xscale";
2053 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2054 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2055 cpu
->midr
= 0x69052d05;
2056 cpu
->ctr
= 0xd172172;
2057 cpu
->reset_sctlr
= 0x00000078;
2060 static void pxa262_initfn(Object
*obj
)
2062 ARMCPU
*cpu
= ARM_CPU(obj
);
2064 cpu
->dtb_compatible
= "marvell,xscale";
2065 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2066 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2067 cpu
->midr
= 0x69052d06;
2068 cpu
->ctr
= 0xd172172;
2069 cpu
->reset_sctlr
= 0x00000078;
2072 static void pxa270a0_initfn(Object
*obj
)
2074 ARMCPU
*cpu
= ARM_CPU(obj
);
2076 cpu
->dtb_compatible
= "marvell,xscale";
2077 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2078 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2079 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2080 cpu
->midr
= 0x69054110;
2081 cpu
->ctr
= 0xd172172;
2082 cpu
->reset_sctlr
= 0x00000078;
2085 static void pxa270a1_initfn(Object
*obj
)
2087 ARMCPU
*cpu
= ARM_CPU(obj
);
2089 cpu
->dtb_compatible
= "marvell,xscale";
2090 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2091 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2092 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2093 cpu
->midr
= 0x69054111;
2094 cpu
->ctr
= 0xd172172;
2095 cpu
->reset_sctlr
= 0x00000078;
2098 static void pxa270b0_initfn(Object
*obj
)
2100 ARMCPU
*cpu
= ARM_CPU(obj
);
2102 cpu
->dtb_compatible
= "marvell,xscale";
2103 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2104 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2105 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2106 cpu
->midr
= 0x69054112;
2107 cpu
->ctr
= 0xd172172;
2108 cpu
->reset_sctlr
= 0x00000078;
2111 static void pxa270b1_initfn(Object
*obj
)
2113 ARMCPU
*cpu
= ARM_CPU(obj
);
2115 cpu
->dtb_compatible
= "marvell,xscale";
2116 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2117 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2118 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2119 cpu
->midr
= 0x69054113;
2120 cpu
->ctr
= 0xd172172;
2121 cpu
->reset_sctlr
= 0x00000078;
2124 static void pxa270c0_initfn(Object
*obj
)
2126 ARMCPU
*cpu
= ARM_CPU(obj
);
2128 cpu
->dtb_compatible
= "marvell,xscale";
2129 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2130 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2131 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2132 cpu
->midr
= 0x69054114;
2133 cpu
->ctr
= 0xd172172;
2134 cpu
->reset_sctlr
= 0x00000078;
2137 static void pxa270c5_initfn(Object
*obj
)
2139 ARMCPU
*cpu
= ARM_CPU(obj
);
2141 cpu
->dtb_compatible
= "marvell,xscale";
2142 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2143 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2144 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2145 cpu
->midr
= 0x69054117;
2146 cpu
->ctr
= 0xd172172;
2147 cpu
->reset_sctlr
= 0x00000078;
2150 #ifndef TARGET_AARCH64
2151 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2152 * otherwise, a CPU with as many features enabled as our emulation supports.
2153 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2154 * this only needs to handle 32 bits.
2156 static void arm_max_initfn(Object
*obj
)
2158 ARMCPU
*cpu
= ARM_CPU(obj
);
2160 if (kvm_enabled()) {
2161 kvm_arm_set_cpu_features_from_host(cpu
);
2163 cortex_a15_initfn(obj
);
2165 /* old-style VFP short-vector support */
2166 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
2168 #ifdef CONFIG_USER_ONLY
2169 /* We don't set these in system emulation mode for the moment,
2170 * since we don't correctly set (all of) the ID registers to
2173 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2177 t
= cpu
->isar
.id_isar5
;
2178 t
= FIELD_DP32(t
, ID_ISAR5
, AES
, 2);
2179 t
= FIELD_DP32(t
, ID_ISAR5
, SHA1
, 1);
2180 t
= FIELD_DP32(t
, ID_ISAR5
, SHA2
, 1);
2181 t
= FIELD_DP32(t
, ID_ISAR5
, CRC32
, 1);
2182 t
= FIELD_DP32(t
, ID_ISAR5
, RDM
, 1);
2183 t
= FIELD_DP32(t
, ID_ISAR5
, VCMA
, 1);
2184 cpu
->isar
.id_isar5
= t
;
2186 t
= cpu
->isar
.id_isar6
;
2187 t
= FIELD_DP32(t
, ID_ISAR6
, JSCVT
, 1);
2188 t
= FIELD_DP32(t
, ID_ISAR6
, DP
, 1);
2189 t
= FIELD_DP32(t
, ID_ISAR6
, FHM
, 1);
2190 t
= FIELD_DP32(t
, ID_ISAR6
, SB
, 1);
2191 t
= FIELD_DP32(t
, ID_ISAR6
, SPECRES
, 1);
2192 cpu
->isar
.id_isar6
= t
;
2194 t
= cpu
->isar
.mvfr2
;
2195 t
= FIELD_DP32(t
, MVFR2
, SIMDMISC
, 3); /* SIMD MaxNum */
2196 t
= FIELD_DP32(t
, MVFR2
, FPMISC
, 4); /* FP MaxNum */
2197 cpu
->isar
.mvfr2
= t
;
2200 t
= FIELD_DP32(t
, ID_MMFR4
, HPDS
, 1); /* AA32HPD */
2208 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2212 void (*initfn
)(Object
*obj
);
2213 void (*class_init
)(ObjectClass
*oc
, void *data
);
2216 static const ARMCPUInfo arm_cpus
[] = {
2217 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2218 { .name
= "arm926", .initfn
= arm926_initfn
},
2219 { .name
= "arm946", .initfn
= arm946_initfn
},
2220 { .name
= "arm1026", .initfn
= arm1026_initfn
},
2221 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2222 * older core than plain "arm1136". In particular this does not
2223 * have the v6K features.
2225 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
2226 { .name
= "arm1136", .initfn
= arm1136_initfn
},
2227 { .name
= "arm1176", .initfn
= arm1176_initfn
},
2228 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
2229 { .name
= "cortex-m0", .initfn
= cortex_m0_initfn
,
2230 .class_init
= arm_v7m_class_init
},
2231 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
2232 .class_init
= arm_v7m_class_init
},
2233 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
2234 .class_init
= arm_v7m_class_init
},
2235 { .name
= "cortex-m33", .initfn
= cortex_m33_initfn
,
2236 .class_init
= arm_v7m_class_init
},
2237 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
2238 { .name
= "cortex-r5f", .initfn
= cortex_r5f_initfn
},
2239 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
2240 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
2241 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
2242 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
2243 { .name
= "ti925t", .initfn
= ti925t_initfn
},
2244 { .name
= "sa1100", .initfn
= sa1100_initfn
},
2245 { .name
= "sa1110", .initfn
= sa1110_initfn
},
2246 { .name
= "pxa250", .initfn
= pxa250_initfn
},
2247 { .name
= "pxa255", .initfn
= pxa255_initfn
},
2248 { .name
= "pxa260", .initfn
= pxa260_initfn
},
2249 { .name
= "pxa261", .initfn
= pxa261_initfn
},
2250 { .name
= "pxa262", .initfn
= pxa262_initfn
},
2251 /* "pxa270" is an alias for "pxa270-a0" */
2252 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
2253 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
2254 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
2255 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
2256 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
2257 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
2258 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
2259 #ifndef TARGET_AARCH64
2260 { .name
= "max", .initfn
= arm_max_initfn
},
2262 #ifdef CONFIG_USER_ONLY
2263 { .name
= "any", .initfn
= arm_max_initfn
},
2269 static Property arm_cpu_properties
[] = {
2270 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
2271 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
2272 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
2273 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2274 mp_affinity
, ARM64_AFFINITY_INVALID
),
2275 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2276 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2277 DEFINE_PROP_END_OF_LIST()
2280 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2282 ARMCPU
*cpu
= ARM_CPU(cs
);
2283 CPUARMState
*env
= &cpu
->env
;
2285 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2286 return g_strdup("iwmmxt");
2288 return g_strdup("arm");
2291 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2293 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2294 CPUClass
*cc
= CPU_CLASS(acc
);
2295 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2297 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2298 &acc
->parent_realize
);
2299 dc
->props
= arm_cpu_properties
;
2301 acc
->parent_reset
= cc
->reset
;
2302 cc
->reset
= arm_cpu_reset
;
2304 cc
->class_by_name
= arm_cpu_class_by_name
;
2305 cc
->has_work
= arm_cpu_has_work
;
2306 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
2307 cc
->dump_state
= arm_cpu_dump_state
;
2308 cc
->set_pc
= arm_cpu_set_pc
;
2309 cc
->synchronize_from_tb
= arm_cpu_synchronize_from_tb
;
2310 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2311 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2312 #ifndef CONFIG_USER_ONLY
2313 cc
->do_interrupt
= arm_cpu_do_interrupt
;
2314 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
2315 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
2316 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
2317 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
2318 cc
->vmsd
= &vmstate_arm_cpu
;
2319 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
2320 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
2321 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
2323 cc
->gdb_num_core_regs
= 26;
2324 cc
->gdb_core_xml_file
= "arm-core.xml";
2325 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2326 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2327 cc
->gdb_stop_before_watchpoint
= true;
2328 cc
->debug_excp_handler
= arm_debug_excp_handler
;
2329 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
2330 #if !defined(CONFIG_USER_ONLY)
2331 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
2334 cc
->disas_set_info
= arm_disas_set_info
;
2336 cc
->tcg_initialize
= arm_translate_init
;
2337 cc
->tlb_fill
= arm_cpu_tlb_fill
;
2342 static void arm_host_initfn(Object
*obj
)
2344 ARMCPU
*cpu
= ARM_CPU(obj
);
2346 kvm_arm_set_cpu_features_from_host(cpu
);
2347 arm_cpu_post_init(obj
);
2350 static const TypeInfo host_arm_cpu_type_info
= {
2351 .name
= TYPE_ARM_HOST_CPU
,
2352 #ifdef TARGET_AARCH64
2353 .parent
= TYPE_AARCH64_CPU
,
2355 .parent
= TYPE_ARM_CPU
,
2357 .instance_init
= arm_host_initfn
,
2362 static void arm_cpu_instance_init(Object
*obj
)
2364 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2366 acc
->info
->initfn(obj
);
2367 arm_cpu_post_init(obj
);
2370 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2372 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2377 static void cpu_register(const ARMCPUInfo
*info
)
2379 TypeInfo type_info
= {
2380 .parent
= TYPE_ARM_CPU
,
2381 .instance_size
= sizeof(ARMCPU
),
2382 .instance_init
= arm_cpu_instance_init
,
2383 .class_size
= sizeof(ARMCPUClass
),
2384 .class_init
= info
->class_init
?: cpu_register_class_init
,
2385 .class_data
= (void *)info
,
2388 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2389 type_register(&type_info
);
2390 g_free((void *)type_info
.name
);
2393 static const TypeInfo arm_cpu_type_info
= {
2394 .name
= TYPE_ARM_CPU
,
2396 .instance_size
= sizeof(ARMCPU
),
2397 .instance_init
= arm_cpu_initfn
,
2398 .instance_finalize
= arm_cpu_finalizefn
,
2400 .class_size
= sizeof(ARMCPUClass
),
2401 .class_init
= arm_cpu_class_init
,
2404 static const TypeInfo idau_interface_type_info
= {
2405 .name
= TYPE_IDAU_INTERFACE
,
2406 .parent
= TYPE_INTERFACE
,
2407 .class_size
= sizeof(IDAUInterfaceClass
),
2410 static void arm_cpu_register_types(void)
2412 const ARMCPUInfo
*info
= arm_cpus
;
2414 type_register_static(&arm_cpu_type_info
);
2415 type_register_static(&idau_interface_type_info
);
2417 while (info
->name
) {
2423 type_register_static(&host_arm_cpu_type_info
);
2427 type_init(arm_cpu_register_types
)