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tpm: apci: cleanup TCPA table initialization
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob1e8364a3d4ffe3ad3ceb0a4d958ce9e25f3b79bf
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include <glib.h>
27 #include "qemu-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "qom/cpu.h"
32 #include "hw/i386/pc.h"
33 #include "target-i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47
48 /* Supported chipsets: */
49 #include "hw/acpi/piix4.h"
50 #include "hw/acpi/pcihp.h"
51 #include "hw/i386/ich9.h"
52 #include "hw/pci/pci_bus.h"
53 #include "hw/pci-host/q35.h"
54 #include "hw/i386/intel_iommu.h"
55 #include "hw/timer/hpet.h"
56
57 #include "hw/acpi/aml-build.h"
58
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61
62 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
63 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
64 * a little bit, there should be plenty of free space since the DSDT
65 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
66 */
67 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
68 #define ACPI_BUILD_ALIGN_SIZE 0x1000
69
70 #define ACPI_BUILD_TABLE_SIZE 0x20000
71
72 /* #define DEBUG_ACPI_BUILD */
73 #ifdef DEBUG_ACPI_BUILD
74 #define ACPI_BUILD_DPRINTF(fmt, ...) \
75 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
76 #else
77 #define ACPI_BUILD_DPRINTF(fmt, ...)
78 #endif
79
80 typedef struct AcpiMcfgInfo {
81 uint64_t mcfg_base;
82 uint32_t mcfg_size;
83 } AcpiMcfgInfo;
84
85 typedef struct AcpiPmInfo {
86 bool s3_disabled;
87 bool s4_disabled;
88 bool pcihp_bridge_en;
89 uint8_t s4_val;
90 uint16_t sci_int;
91 uint8_t acpi_enable_cmd;
92 uint8_t acpi_disable_cmd;
93 uint32_t gpe0_blk;
94 uint32_t gpe0_blk_len;
95 uint32_t io_base;
96 uint16_t cpu_hp_io_base;
97 uint16_t mem_hp_io_base;
98 uint16_t mem_hp_io_len;
99 uint16_t pcihp_io_base;
100 uint16_t pcihp_io_len;
101 } AcpiPmInfo;
102
103 typedef struct AcpiMiscInfo {
104 bool is_piix4;
105 bool has_hpet;
106 TPMVersion tpm_version;
107 const unsigned char *dsdt_code;
108 unsigned dsdt_size;
109 uint16_t pvpanic_port;
110 uint16_t applesmc_io_base;
111 } AcpiMiscInfo;
112
113 typedef struct AcpiBuildPciBusHotplugState {
114 GArray *device_table;
115 GArray *notify_table;
116 struct AcpiBuildPciBusHotplugState *parent;
117 bool pcihp_bridge_en;
118 } AcpiBuildPciBusHotplugState;
119
120 static void acpi_get_pm_info(AcpiPmInfo *pm)
121 {
122 Object *piix = piix4_pm_find();
123 Object *lpc = ich9_lpc_find();
124 Object *obj = NULL;
125 QObject *o;
126
127 pm->cpu_hp_io_base = 0;
128 pm->pcihp_io_base = 0;
129 pm->pcihp_io_len = 0;
130 if (piix) {
131 obj = piix;
132 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
133 pm->pcihp_io_base =
134 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
135 pm->pcihp_io_len =
136 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
137 }
138 if (lpc) {
139 obj = lpc;
140 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
141 }
142 assert(obj);
143
144 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
145 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
146
147 /* Fill in optional s3/s4 related properties */
148 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
149 if (o) {
150 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
151 } else {
152 pm->s3_disabled = false;
153 }
154 qobject_decref(o);
155 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
156 if (o) {
157 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
158 } else {
159 pm->s4_disabled = false;
160 }
161 qobject_decref(o);
162 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
163 if (o) {
164 pm->s4_val = qint_get_int(qobject_to_qint(o));
165 } else {
166 pm->s4_val = false;
167 }
168 qobject_decref(o);
169
170 /* Fill in mandatory properties */
171 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
172
173 pm->acpi_enable_cmd = object_property_get_int(obj,
174 ACPI_PM_PROP_ACPI_ENABLE_CMD,
175 NULL);
176 pm->acpi_disable_cmd = object_property_get_int(obj,
177 ACPI_PM_PROP_ACPI_DISABLE_CMD,
178 NULL);
179 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
180 NULL);
181 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
182 NULL);
183 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
184 NULL);
185 pm->pcihp_bridge_en =
186 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
187 NULL);
188 }
189
190 static void acpi_get_misc_info(AcpiMiscInfo *info)
191 {
192 Object *piix = piix4_pm_find();
193 Object *lpc = ich9_lpc_find();
194 assert(!!piix != !!lpc);
195
196 if (piix) {
197 info->is_piix4 = true;
198 }
199 if (lpc) {
200 info->is_piix4 = false;
201 }
202
203 info->has_hpet = hpet_find();
204 info->tpm_version = tpm_get_version();
205 info->pvpanic_port = pvpanic_port();
206 info->applesmc_io_base = applesmc_port();
207 }
208
209 /*
210 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
211 * On i386 arch we only have two pci hosts, so we can look only for them.
212 */
213 static Object *acpi_get_i386_pci_host(void)
214 {
215 PCIHostState *host;
216
217 host = OBJECT_CHECK(PCIHostState,
218 object_resolve_path("/machine/i440fx", NULL),
219 TYPE_PCI_HOST_BRIDGE);
220 if (!host) {
221 host = OBJECT_CHECK(PCIHostState,
222 object_resolve_path("/machine/q35", NULL),
223 TYPE_PCI_HOST_BRIDGE);
224 }
225
226 return OBJECT(host);
227 }
228
229 static void acpi_get_pci_info(PcPciInfo *info)
230 {
231 Object *pci_host;
232
233
234 pci_host = acpi_get_i386_pci_host();
235 g_assert(pci_host);
236
237 info->w32.begin = object_property_get_int(pci_host,
238 PCI_HOST_PROP_PCI_HOLE_START,
239 NULL);
240 info->w32.end = object_property_get_int(pci_host,
241 PCI_HOST_PROP_PCI_HOLE_END,
242 NULL);
243 info->w64.begin = object_property_get_int(pci_host,
244 PCI_HOST_PROP_PCI_HOLE64_START,
245 NULL);
246 info->w64.end = object_property_get_int(pci_host,
247 PCI_HOST_PROP_PCI_HOLE64_END,
248 NULL);
249 }
250
251 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
252
253 static void acpi_align_size(GArray *blob, unsigned align)
254 {
255 /* Align size to multiple of given size. This reduces the chance
256 * we need to change size in the future (breaking cross version migration).
257 */
258 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
259 }
260
261 /* FACS */
262 static void
263 build_facs(GArray *table_data, BIOSLinker *linker)
264 {
265 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
266 memcpy(&facs->signature, "FACS", 4);
267 facs->length = cpu_to_le32(sizeof(*facs));
268 }
269
270 /* Load chipset information in FADT */
271 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
272 {
273 fadt->model = 1;
274 fadt->reserved1 = 0;
275 fadt->sci_int = cpu_to_le16(pm->sci_int);
276 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
277 fadt->acpi_enable = pm->acpi_enable_cmd;
278 fadt->acpi_disable = pm->acpi_disable_cmd;
279 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
280 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
281 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
282 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
283 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
284 /* EVT, CNT, TMR length matches hw/acpi/core.c */
285 fadt->pm1_evt_len = 4;
286 fadt->pm1_cnt_len = 2;
287 fadt->pm_tmr_len = 4;
288 fadt->gpe0_blk_len = pm->gpe0_blk_len;
289 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
290 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
291 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
292 (1 << ACPI_FADT_F_PROC_C1) |
293 (1 << ACPI_FADT_F_SLP_BUTTON) |
294 (1 << ACPI_FADT_F_RTC_S4));
295 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
296 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
297 * For more than 8 CPUs, "Clustered Logical" mode has to be used
298 */
299 if (max_cpus > 8) {
300 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
301 }
302 fadt->century = RTC_CENTURY;
303 }
304
305
306 /* FADT */
307 static void
308 build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
309 unsigned facs, unsigned dsdt,
310 const char *oem_id, const char *oem_table_id)
311 {
312 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
313
314 fadt->firmware_ctrl = cpu_to_le32(facs);
315 /* FACS address to be filled by Guest linker */
316 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
317 ACPI_BUILD_TABLE_FILE,
318 &fadt->firmware_ctrl,
319 sizeof fadt->firmware_ctrl);
320
321 fadt->dsdt = cpu_to_le32(dsdt);
322 /* DSDT address to be filled by Guest linker */
323 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
324 ACPI_BUILD_TABLE_FILE,
325 &fadt->dsdt,
326 sizeof fadt->dsdt);
327
328 fadt_setup(fadt, pm);
329
330 build_header(linker, table_data,
331 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
332 }
333
334 static void
335 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
336 {
337 MachineClass *mc = MACHINE_GET_CLASS(pcms);
338 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
339 int madt_start = table_data->len;
340
341 AcpiMultipleApicTable *madt;
342 AcpiMadtIoApic *io_apic;
343 AcpiMadtIntsrcovr *intsrcovr;
344 AcpiMadtLocalNmi *local_nmi;
345 int i;
346
347 madt = acpi_data_push(table_data, sizeof *madt);
348 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
349 madt->flags = cpu_to_le32(1);
350
351 for (i = 0; i < apic_ids->len; i++) {
352 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
353 int apic_id = apic_ids->cpus[i].arch_id;
354
355 apic->type = ACPI_APIC_PROCESSOR;
356 apic->length = sizeof(*apic);
357 apic->processor_id = i;
358 apic->local_apic_id = apic_id;
359 if (apic_ids->cpus[i].cpu != NULL) {
360 apic->flags = cpu_to_le32(1);
361 } else {
362 /* ACPI spec says that LAPIC entry for non present
363 * CPU may be omitted from MADT or it must be marked
364 * as disabled. However omitting non present CPU from
365 * MADT breaks hotplug on linux. So possible CPUs
366 * should be put in MADT but kept disabled.
367 */
368 apic->flags = cpu_to_le32(0);
369 }
370 }
371 g_free(apic_ids);
372
373 io_apic = acpi_data_push(table_data, sizeof *io_apic);
374 io_apic->type = ACPI_APIC_IO;
375 io_apic->length = sizeof(*io_apic);
376 #define ACPI_BUILD_IOAPIC_ID 0x0
377 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
378 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
379 io_apic->interrupt = cpu_to_le32(0);
380
381 if (pcms->apic_xrupt_override) {
382 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
383 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
384 intsrcovr->length = sizeof(*intsrcovr);
385 intsrcovr->source = 0;
386 intsrcovr->gsi = cpu_to_le32(2);
387 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
388 }
389 for (i = 1; i < 16; i++) {
390 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
391 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
392 /* No need for a INT source override structure. */
393 continue;
394 }
395 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
396 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
397 intsrcovr->length = sizeof(*intsrcovr);
398 intsrcovr->source = i;
399 intsrcovr->gsi = cpu_to_le32(i);
400 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
401 }
402
403 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
404 local_nmi->type = ACPI_APIC_LOCAL_NMI;
405 local_nmi->length = sizeof(*local_nmi);
406 local_nmi->processor_id = 0xff; /* all processors */
407 local_nmi->flags = cpu_to_le16(0);
408 local_nmi->lint = 1; /* ACPI_LINT1 */
409
410 build_header(linker, table_data,
411 (void *)(table_data->data + madt_start), "APIC",
412 table_data->len - madt_start, 1, NULL, NULL);
413 }
414
415 /* Assign BSEL property to all buses. In the future, this can be changed
416 * to only assign to buses that support hotplug.
417 */
418 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
419 {
420 unsigned *bsel_alloc = opaque;
421 unsigned *bus_bsel;
422
423 if (qbus_is_hotpluggable(BUS(bus))) {
424 bus_bsel = g_malloc(sizeof *bus_bsel);
425
426 *bus_bsel = (*bsel_alloc)++;
427 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
428 bus_bsel, NULL);
429 }
430
431 return bsel_alloc;
432 }
433
434 static void acpi_set_pci_info(void)
435 {
436 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
437 unsigned bsel_alloc = 0;
438
439 if (bus) {
440 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
441 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
442 }
443 }
444
445 static void build_append_pcihp_notify_entry(Aml *method, int slot)
446 {
447 Aml *if_ctx;
448 int32_t devfn = PCI_DEVFN(slot, 0);
449
450 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
451 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
452 aml_append(method, if_ctx);
453 }
454
455 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
456 bool pcihp_bridge_en)
457 {
458 Aml *dev, *notify_method, *method;
459 QObject *bsel;
460 PCIBus *sec;
461 int i;
462
463 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
464 if (bsel) {
465 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
466
467 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
468 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
469 }
470
471 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
472 DeviceClass *dc;
473 PCIDeviceClass *pc;
474 PCIDevice *pdev = bus->devices[i];
475 int slot = PCI_SLOT(i);
476 bool hotplug_enabled_dev;
477 bool bridge_in_acpi;
478
479 if (!pdev) {
480 if (bsel) { /* add hotplug slots for non present devices */
481 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
482 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
483 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
484 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
485 aml_append(method,
486 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
487 );
488 aml_append(dev, method);
489 aml_append(parent_scope, dev);
490
491 build_append_pcihp_notify_entry(notify_method, slot);
492 }
493 continue;
494 }
495
496 pc = PCI_DEVICE_GET_CLASS(pdev);
497 dc = DEVICE_GET_CLASS(pdev);
498
499 /* When hotplug for bridges is enabled, bridges are
500 * described in ACPI separately (see build_pci_bus_end).
501 * In this case they aren't themselves hot-pluggable.
502 * Hotplugged bridges *are* hot-pluggable.
503 */
504 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
505 !DEVICE(pdev)->hotplugged;
506
507 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
508
509 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
510 continue;
511 }
512
513 /* start to compose PCI slot descriptor */
514 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
515 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
516
517 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
518 /* add VGA specific AML methods */
519 int s3d;
520
521 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
522 s3d = 3;
523 } else {
524 s3d = 0;
525 }
526
527 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
528 aml_append(method, aml_return(aml_int(0)));
529 aml_append(dev, method);
530
531 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
532 aml_append(method, aml_return(aml_int(0)));
533 aml_append(dev, method);
534
535 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
536 aml_append(method, aml_return(aml_int(s3d)));
537 aml_append(dev, method);
538 } else if (hotplug_enabled_dev) {
539 /* add _SUN/_EJ0 to make slot hotpluggable */
540 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
541
542 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
543 aml_append(method,
544 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
545 );
546 aml_append(dev, method);
547
548 if (bsel) {
549 build_append_pcihp_notify_entry(notify_method, slot);
550 }
551 } else if (bridge_in_acpi) {
552 /*
553 * device is coldplugged bridge,
554 * add child device descriptions into its scope
555 */
556 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
557
558 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
559 }
560 /* slot descriptor has been composed, add it into parent context */
561 aml_append(parent_scope, dev);
562 }
563
564 if (bsel) {
565 aml_append(parent_scope, notify_method);
566 }
567
568 /* Append PCNT method to notify about events on local and child buses.
569 * Add unconditionally for root since DSDT expects it.
570 */
571 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
572
573 /* If bus supports hotplug select it and notify about local events */
574 if (bsel) {
575 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
576 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
577 aml_append(method,
578 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
579 );
580 aml_append(method,
581 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
582 );
583 }
584
585 /* Notify about child bus events in any case */
586 if (pcihp_bridge_en) {
587 QLIST_FOREACH(sec, &bus->child, sibling) {
588 int32_t devfn = sec->parent_dev->devfn;
589
590 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
591 }
592 }
593 aml_append(parent_scope, method);
594 qobject_decref(bsel);
595 }
596
597 /**
598 * build_prt_entry:
599 * @link_name: link name for PCI route entry
600 *
601 * build AML package containing a PCI route entry for @link_name
602 */
603 static Aml *build_prt_entry(const char *link_name)
604 {
605 Aml *a_zero = aml_int(0);
606 Aml *pkg = aml_package(4);
607 aml_append(pkg, a_zero);
608 aml_append(pkg, a_zero);
609 aml_append(pkg, aml_name("%s", link_name));
610 aml_append(pkg, a_zero);
611 return pkg;
612 }
613
614 /*
615 * initialize_route - Initialize the interrupt routing rule
616 * through a specific LINK:
617 * if (lnk_idx == idx)
618 * route using link 'link_name'
619 */
620 static Aml *initialize_route(Aml *route, const char *link_name,
621 Aml *lnk_idx, int idx)
622 {
623 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
624 Aml *pkg = build_prt_entry(link_name);
625
626 aml_append(if_ctx, aml_store(pkg, route));
627
628 return if_ctx;
629 }
630
631 /*
632 * build_prt - Define interrupt rounting rules
633 *
634 * Returns an array of 128 routes, one for each device,
635 * based on device location.
636 * The main goal is to equaly distribute the interrupts
637 * over the 4 existing ACPI links (works only for i440fx).
638 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
639 *
640 */
641 static Aml *build_prt(bool is_pci0_prt)
642 {
643 Aml *method, *while_ctx, *pin, *res;
644
645 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
646 res = aml_local(0);
647 pin = aml_local(1);
648 aml_append(method, aml_store(aml_package(128), res));
649 aml_append(method, aml_store(aml_int(0), pin));
650
651 /* while (pin < 128) */
652 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
653 {
654 Aml *slot = aml_local(2);
655 Aml *lnk_idx = aml_local(3);
656 Aml *route = aml_local(4);
657
658 /* slot = pin >> 2 */
659 aml_append(while_ctx,
660 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
661 /* lnk_idx = (slot + pin) & 3 */
662 aml_append(while_ctx,
663 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
664 lnk_idx));
665
666 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
667 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
668 if (is_pci0_prt) {
669 Aml *if_device_1, *if_pin_4, *else_pin_4;
670
671 /* device 1 is the power-management device, needs SCI */
672 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
673 {
674 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
675 {
676 aml_append(if_pin_4,
677 aml_store(build_prt_entry("LNKS"), route));
678 }
679 aml_append(if_device_1, if_pin_4);
680 else_pin_4 = aml_else();
681 {
682 aml_append(else_pin_4,
683 aml_store(build_prt_entry("LNKA"), route));
684 }
685 aml_append(if_device_1, else_pin_4);
686 }
687 aml_append(while_ctx, if_device_1);
688 } else {
689 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
690 }
691 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
692 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
693
694 /* route[0] = 0x[slot]FFFF */
695 aml_append(while_ctx,
696 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
697 NULL),
698 aml_index(route, aml_int(0))));
699 /* route[1] = pin & 3 */
700 aml_append(while_ctx,
701 aml_store(aml_and(pin, aml_int(3), NULL),
702 aml_index(route, aml_int(1))));
703 /* res[pin] = route */
704 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
705 /* pin++ */
706 aml_append(while_ctx, aml_increment(pin));
707 }
708 aml_append(method, while_ctx);
709 /* return res*/
710 aml_append(method, aml_return(res));
711
712 return method;
713 }
714
715 typedef struct CrsRangeEntry {
716 uint64_t base;
717 uint64_t limit;
718 } CrsRangeEntry;
719
720 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
721 {
722 CrsRangeEntry *entry;
723
724 entry = g_malloc(sizeof(*entry));
725 entry->base = base;
726 entry->limit = limit;
727
728 g_ptr_array_add(ranges, entry);
729 }
730
731 static void crs_range_free(gpointer data)
732 {
733 CrsRangeEntry *entry = (CrsRangeEntry *)data;
734 g_free(entry);
735 }
736
737 static gint crs_range_compare(gconstpointer a, gconstpointer b)
738 {
739 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
740 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
741
742 return (int64_t)entry_a->base - (int64_t)entry_b->base;
743 }
744
745 /*
746 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
747 * interval, computes the 'free' ranges from the same interval.
748 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
749 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
750 */
751 static void crs_replace_with_free_ranges(GPtrArray *ranges,
752 uint64_t start, uint64_t end)
753 {
754 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
755 uint64_t free_base = start;
756 int i;
757
758 g_ptr_array_sort(ranges, crs_range_compare);
759 for (i = 0; i < ranges->len; i++) {
760 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
761
762 if (free_base < used->base) {
763 crs_range_insert(free_ranges, free_base, used->base - 1);
764 }
765
766 free_base = used->limit + 1;
767 }
768
769 if (free_base < end) {
770 crs_range_insert(free_ranges, free_base, end);
771 }
772
773 g_ptr_array_set_size(ranges, 0);
774 for (i = 0; i < free_ranges->len; i++) {
775 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
776 }
777
778 g_ptr_array_free(free_ranges, false);
779 }
780
781 /*
782 * crs_range_merge - merges adjacent ranges in the given array.
783 * Array elements are deleted and replaced with the merged ranges.
784 */
785 static void crs_range_merge(GPtrArray *range)
786 {
787 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
788 CrsRangeEntry *entry;
789 uint64_t range_base, range_limit;
790 int i;
791
792 if (!range->len) {
793 return;
794 }
795
796 g_ptr_array_sort(range, crs_range_compare);
797
798 entry = g_ptr_array_index(range, 0);
799 range_base = entry->base;
800 range_limit = entry->limit;
801 for (i = 1; i < range->len; i++) {
802 entry = g_ptr_array_index(range, i);
803 if (entry->base - 1 == range_limit) {
804 range_limit = entry->limit;
805 } else {
806 crs_range_insert(tmp, range_base, range_limit);
807 range_base = entry->base;
808 range_limit = entry->limit;
809 }
810 }
811 crs_range_insert(tmp, range_base, range_limit);
812
813 g_ptr_array_set_size(range, 0);
814 for (i = 0; i < tmp->len; i++) {
815 entry = g_ptr_array_index(tmp, i);
816 crs_range_insert(range, entry->base, entry->limit);
817 }
818 g_ptr_array_free(tmp, true);
819 }
820
821 static Aml *build_crs(PCIHostState *host,
822 GPtrArray *io_ranges, GPtrArray *mem_ranges)
823 {
824 Aml *crs = aml_resource_template();
825 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
826 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
827 CrsRangeEntry *entry;
828 uint8_t max_bus = pci_bus_num(host->bus);
829 uint8_t type;
830 int devfn;
831 int i;
832
833 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
834 uint64_t range_base, range_limit;
835 PCIDevice *dev = host->bus->devices[devfn];
836
837 if (!dev) {
838 continue;
839 }
840
841 for (i = 0; i < PCI_NUM_REGIONS; i++) {
842 PCIIORegion *r = &dev->io_regions[i];
843
844 range_base = r->addr;
845 range_limit = r->addr + r->size - 1;
846
847 /*
848 * Work-around for old bioses
849 * that do not support multiple root buses
850 */
851 if (!range_base || range_base > range_limit) {
852 continue;
853 }
854
855 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
856 crs_range_insert(host_io_ranges, range_base, range_limit);
857 } else { /* "memory" */
858 crs_range_insert(host_mem_ranges, range_base, range_limit);
859 }
860 }
861
862 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
863 if (type == PCI_HEADER_TYPE_BRIDGE) {
864 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
865 if (subordinate > max_bus) {
866 max_bus = subordinate;
867 }
868
869 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
870 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
871
872 /*
873 * Work-around for old bioses
874 * that do not support multiple root buses
875 */
876 if (range_base && range_base <= range_limit) {
877 crs_range_insert(host_io_ranges, range_base, range_limit);
878 }
879
880 range_base =
881 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
882 range_limit =
883 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
884
885 /*
886 * Work-around for old bioses
887 * that do not support multiple root buses
888 */
889 if (range_base && range_base <= range_limit) {
890 crs_range_insert(host_mem_ranges, range_base, range_limit);
891 }
892
893 range_base =
894 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
895 range_limit =
896 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
897
898 /*
899 * Work-around for old bioses
900 * that do not support multiple root buses
901 */
902 if (range_base && range_base <= range_limit) {
903 crs_range_insert(host_mem_ranges, range_base, range_limit);
904 }
905 }
906 }
907
908 crs_range_merge(host_io_ranges);
909 for (i = 0; i < host_io_ranges->len; i++) {
910 entry = g_ptr_array_index(host_io_ranges, i);
911 aml_append(crs,
912 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
913 AML_POS_DECODE, AML_ENTIRE_RANGE,
914 0, entry->base, entry->limit, 0,
915 entry->limit - entry->base + 1));
916 crs_range_insert(io_ranges, entry->base, entry->limit);
917 }
918 g_ptr_array_free(host_io_ranges, true);
919
920 crs_range_merge(host_mem_ranges);
921 for (i = 0; i < host_mem_ranges->len; i++) {
922 entry = g_ptr_array_index(host_mem_ranges, i);
923 aml_append(crs,
924 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
925 AML_MAX_FIXED, AML_NON_CACHEABLE,
926 AML_READ_WRITE,
927 0, entry->base, entry->limit, 0,
928 entry->limit - entry->base + 1));
929 crs_range_insert(mem_ranges, entry->base, entry->limit);
930 }
931 g_ptr_array_free(host_mem_ranges, true);
932
933 aml_append(crs,
934 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
935 0,
936 pci_bus_num(host->bus),
937 max_bus,
938 0,
939 max_bus - pci_bus_num(host->bus) + 1));
940
941 return crs;
942 }
943
944 static void build_memory_devices(Aml *sb_scope, int nr_mem,
945 uint16_t io_base, uint16_t io_len)
946 {
947 int i;
948 Aml *scope;
949 Aml *crs;
950 Aml *field;
951 Aml *dev;
952 Aml *method;
953 Aml *ifctx;
954
955 /* build memory devices */
956 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
957 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
958 aml_append(scope,
959 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
960 );
961
962 crs = aml_resource_template();
963 aml_append(crs,
964 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
965 );
966 aml_append(scope, aml_name_decl("_CRS", crs));
967
968 aml_append(scope, aml_operation_region(
969 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
970 aml_int(io_base), io_len)
971 );
972
973 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
974 AML_NOLOCK, AML_PRESERVE);
975 aml_append(field, /* read only */
976 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
977 aml_append(field, /* read only */
978 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
979 aml_append(field, /* read only */
980 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
981 aml_append(field, /* read only */
982 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
983 aml_append(field, /* read only */
984 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
985 aml_append(scope, field);
986
987 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
988 AML_NOLOCK, AML_WRITE_AS_ZEROS);
989 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
990 aml_append(field, /* 1 if enabled, read only */
991 aml_named_field(MEMORY_SLOT_ENABLED, 1));
992 aml_append(field,
993 /*(read) 1 if has a insert event. (write) 1 to clear event */
994 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
995 aml_append(field,
996 /* (read) 1 if has a remove event. (write) 1 to clear event */
997 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
998 aml_append(field,
999 /* initiates device eject, write only */
1000 aml_named_field(MEMORY_SLOT_EJECT, 1));
1001 aml_append(scope, field);
1002
1003 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1004 AML_NOLOCK, AML_PRESERVE);
1005 aml_append(field, /* DIMM selector, write only */
1006 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1007 aml_append(field, /* _OST event code, write only */
1008 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1009 aml_append(field, /* _OST status code, write only */
1010 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1011 aml_append(scope, field);
1012 aml_append(sb_scope, scope);
1013
1014 for (i = 0; i < nr_mem; i++) {
1015 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1016 const char *s;
1017
1018 dev = aml_device("MP%02X", i);
1019 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1020 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1021
1022 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1023 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1024 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1025 aml_append(dev, method);
1026
1027 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1028 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1029 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1030 aml_append(dev, method);
1031
1032 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1033 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1034 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1035 aml_append(dev, method);
1036
1037 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1038 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1039
1040 aml_append(method, aml_return(aml_call4(
1041 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1042 )));
1043 aml_append(dev, method);
1044
1045 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1046 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1047 aml_append(method, aml_return(aml_call2(
1048 s, aml_name("_UID"), aml_arg(0))));
1049 aml_append(dev, method);
1050
1051 aml_append(sb_scope, dev);
1052 }
1053
1054 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1055 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1056 */
1057 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1058 for (i = 0; i < nr_mem; i++) {
1059 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1060 aml_append(ifctx,
1061 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1062 );
1063 aml_append(method, ifctx);
1064 }
1065 aml_append(sb_scope, method);
1066 }
1067
1068 static void build_hpet_aml(Aml *table)
1069 {
1070 Aml *crs;
1071 Aml *field;
1072 Aml *method;
1073 Aml *if_ctx;
1074 Aml *scope = aml_scope("_SB");
1075 Aml *dev = aml_device("HPET");
1076 Aml *zero = aml_int(0);
1077 Aml *id = aml_local(0);
1078 Aml *period = aml_local(1);
1079
1080 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1081 aml_append(dev, aml_name_decl("_UID", zero));
1082
1083 aml_append(dev,
1084 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1085 HPET_LEN));
1086 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1087 aml_append(field, aml_named_field("VEND", 32));
1088 aml_append(field, aml_named_field("PRD", 32));
1089 aml_append(dev, field);
1090
1091 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1092 aml_append(method, aml_store(aml_name("VEND"), id));
1093 aml_append(method, aml_store(aml_name("PRD"), period));
1094 aml_append(method, aml_shiftright(id, aml_int(16), id));
1095 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1096 aml_equal(id, aml_int(0xffff))));
1097 {
1098 aml_append(if_ctx, aml_return(zero));
1099 }
1100 aml_append(method, if_ctx);
1101
1102 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1103 aml_lgreater(period, aml_int(100000000))));
1104 {
1105 aml_append(if_ctx, aml_return(zero));
1106 }
1107 aml_append(method, if_ctx);
1108
1109 aml_append(method, aml_return(aml_int(0x0F)));
1110 aml_append(dev, method);
1111
1112 crs = aml_resource_template();
1113 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1114 aml_append(dev, aml_name_decl("_CRS", crs));
1115
1116 aml_append(scope, dev);
1117 aml_append(table, scope);
1118 }
1119
1120 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1121 {
1122 Aml *dev, *fdi;
1123 uint8_t maxc, maxh, maxs;
1124
1125 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1126
1127 dev = aml_device("FLP%c", 'A' + idx);
1128
1129 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1130
1131 fdi = aml_package(16);
1132 aml_append(fdi, aml_int(idx)); /* Drive Number */
1133 aml_append(fdi,
1134 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1135 /*
1136 * the values below are the limits of the drive, and are thus independent
1137 * of the inserted media
1138 */
1139 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1140 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1141 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1142 /*
1143 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1144 * the drive type, so shall we
1145 */
1146 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1147 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1148 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1149 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1150 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1151 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1152 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1153 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1154 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1155 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1156 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1157
1158 aml_append(dev, aml_name_decl("_FDI", fdi));
1159 return dev;
1160 }
1161
1162 static Aml *build_fdc_device_aml(ISADevice *fdc)
1163 {
1164 int i;
1165 Aml *dev;
1166 Aml *crs;
1167
1168 #define ACPI_FDE_MAX_FD 4
1169 uint32_t fde_buf[5] = {
1170 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1171 cpu_to_le32(2) /* tape presence (2 == never present) */
1172 };
1173
1174 dev = aml_device("FDC0");
1175 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1176
1177 crs = aml_resource_template();
1178 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1179 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1180 aml_append(crs, aml_irq_no_flags(6));
1181 aml_append(crs,
1182 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1183 aml_append(dev, aml_name_decl("_CRS", crs));
1184
1185 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1186 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1187
1188 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1189 fde_buf[i] = cpu_to_le32(1); /* drive present */
1190 aml_append(dev, build_fdinfo_aml(i, type));
1191 }
1192 }
1193 aml_append(dev, aml_name_decl("_FDE",
1194 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1195
1196 return dev;
1197 }
1198
1199 static Aml *build_rtc_device_aml(void)
1200 {
1201 Aml *dev;
1202 Aml *crs;
1203
1204 dev = aml_device("RTC");
1205 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1206 crs = aml_resource_template();
1207 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1208 aml_append(crs, aml_irq_no_flags(8));
1209 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1210 aml_append(dev, aml_name_decl("_CRS", crs));
1211
1212 return dev;
1213 }
1214
1215 static Aml *build_kbd_device_aml(void)
1216 {
1217 Aml *dev;
1218 Aml *crs;
1219 Aml *method;
1220
1221 dev = aml_device("KBD");
1222 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1223
1224 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1225 aml_append(method, aml_return(aml_int(0x0f)));
1226 aml_append(dev, method);
1227
1228 crs = aml_resource_template();
1229 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1230 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1231 aml_append(crs, aml_irq_no_flags(1));
1232 aml_append(dev, aml_name_decl("_CRS", crs));
1233
1234 return dev;
1235 }
1236
1237 static Aml *build_mouse_device_aml(void)
1238 {
1239 Aml *dev;
1240 Aml *crs;
1241 Aml *method;
1242
1243 dev = aml_device("MOU");
1244 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1245
1246 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1247 aml_append(method, aml_return(aml_int(0x0f)));
1248 aml_append(dev, method);
1249
1250 crs = aml_resource_template();
1251 aml_append(crs, aml_irq_no_flags(12));
1252 aml_append(dev, aml_name_decl("_CRS", crs));
1253
1254 return dev;
1255 }
1256
1257 static Aml *build_lpt_device_aml(void)
1258 {
1259 Aml *dev;
1260 Aml *crs;
1261 Aml *method;
1262 Aml *if_ctx;
1263 Aml *else_ctx;
1264 Aml *zero = aml_int(0);
1265 Aml *is_present = aml_local(0);
1266
1267 dev = aml_device("LPT");
1268 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1269
1270 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1271 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1272 if_ctx = aml_if(aml_equal(is_present, zero));
1273 {
1274 aml_append(if_ctx, aml_return(aml_int(0x00)));
1275 }
1276 aml_append(method, if_ctx);
1277 else_ctx = aml_else();
1278 {
1279 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1280 }
1281 aml_append(method, else_ctx);
1282 aml_append(dev, method);
1283
1284 crs = aml_resource_template();
1285 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1286 aml_append(crs, aml_irq_no_flags(7));
1287 aml_append(dev, aml_name_decl("_CRS", crs));
1288
1289 return dev;
1290 }
1291
1292 static Aml *build_com_device_aml(uint8_t uid)
1293 {
1294 Aml *dev;
1295 Aml *crs;
1296 Aml *method;
1297 Aml *if_ctx;
1298 Aml *else_ctx;
1299 Aml *zero = aml_int(0);
1300 Aml *is_present = aml_local(0);
1301 const char *enabled_field = "CAEN";
1302 uint8_t irq = 4;
1303 uint16_t io_port = 0x03F8;
1304
1305 assert(uid == 1 || uid == 2);
1306 if (uid == 2) {
1307 enabled_field = "CBEN";
1308 irq = 3;
1309 io_port = 0x02F8;
1310 }
1311
1312 dev = aml_device("COM%d", uid);
1313 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1314 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1315
1316 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1317 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1318 if_ctx = aml_if(aml_equal(is_present, zero));
1319 {
1320 aml_append(if_ctx, aml_return(aml_int(0x00)));
1321 }
1322 aml_append(method, if_ctx);
1323 else_ctx = aml_else();
1324 {
1325 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1326 }
1327 aml_append(method, else_ctx);
1328 aml_append(dev, method);
1329
1330 crs = aml_resource_template();
1331 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1332 aml_append(crs, aml_irq_no_flags(irq));
1333 aml_append(dev, aml_name_decl("_CRS", crs));
1334
1335 return dev;
1336 }
1337
1338 static void build_isa_devices_aml(Aml *table)
1339 {
1340 ISADevice *fdc = pc_find_fdc0();
1341
1342 Aml *scope = aml_scope("_SB.PCI0.ISA");
1343
1344 aml_append(scope, build_rtc_device_aml());
1345 aml_append(scope, build_kbd_device_aml());
1346 aml_append(scope, build_mouse_device_aml());
1347 if (fdc) {
1348 aml_append(scope, build_fdc_device_aml(fdc));
1349 }
1350 aml_append(scope, build_lpt_device_aml());
1351 aml_append(scope, build_com_device_aml(1));
1352 aml_append(scope, build_com_device_aml(2));
1353
1354 aml_append(table, scope);
1355 }
1356
1357 static void build_dbg_aml(Aml *table)
1358 {
1359 Aml *field;
1360 Aml *method;
1361 Aml *while_ctx;
1362 Aml *scope = aml_scope("\\");
1363 Aml *buf = aml_local(0);
1364 Aml *len = aml_local(1);
1365 Aml *idx = aml_local(2);
1366
1367 aml_append(scope,
1368 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1369 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1370 aml_append(field, aml_named_field("DBGB", 8));
1371 aml_append(scope, field);
1372
1373 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1374
1375 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1376 aml_append(method, aml_to_buffer(buf, buf));
1377 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1378 aml_append(method, aml_store(aml_int(0), idx));
1379
1380 while_ctx = aml_while(aml_lless(idx, len));
1381 aml_append(while_ctx,
1382 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1383 aml_append(while_ctx, aml_increment(idx));
1384 aml_append(method, while_ctx);
1385
1386 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1387 aml_append(scope, method);
1388
1389 aml_append(table, scope);
1390 }
1391
1392 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1393 {
1394 Aml *dev;
1395 Aml *crs;
1396 Aml *method;
1397 uint32_t irqs[] = {5, 10, 11};
1398
1399 dev = aml_device("%s", name);
1400 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1401 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1402
1403 crs = aml_resource_template();
1404 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1405 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1406 aml_append(dev, aml_name_decl("_PRS", crs));
1407
1408 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1409 aml_append(method, aml_return(aml_call1("IQST", reg)));
1410 aml_append(dev, method);
1411
1412 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1413 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1414 aml_append(dev, method);
1415
1416 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1417 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1418 aml_append(dev, method);
1419
1420 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1421 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1422 aml_append(method, aml_store(aml_name("PRRI"), reg));
1423 aml_append(dev, method);
1424
1425 return dev;
1426 }
1427
1428 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1429 {
1430 Aml *dev;
1431 Aml *crs;
1432 Aml *method;
1433 uint32_t irqs;
1434
1435 dev = aml_device("%s", name);
1436 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1437 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1438
1439 crs = aml_resource_template();
1440 irqs = gsi;
1441 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1442 AML_SHARED, &irqs, 1));
1443 aml_append(dev, aml_name_decl("_PRS", crs));
1444
1445 aml_append(dev, aml_name_decl("_CRS", crs));
1446
1447 /*
1448 * _DIS can be no-op because the interrupt cannot be disabled.
1449 */
1450 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1451 aml_append(dev, method);
1452
1453 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1454 aml_append(dev, method);
1455
1456 return dev;
1457 }
1458
1459 /* _CRS method - get current settings */
1460 static Aml *build_iqcr_method(bool is_piix4)
1461 {
1462 Aml *if_ctx;
1463 uint32_t irqs;
1464 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1465 Aml *crs = aml_resource_template();
1466
1467 irqs = 0;
1468 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1469 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1470 aml_append(method, aml_name_decl("PRR0", crs));
1471
1472 aml_append(method,
1473 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1474
1475 if (is_piix4) {
1476 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1477 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1478 aml_append(method, if_ctx);
1479 } else {
1480 aml_append(method,
1481 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1482 aml_name("PRRI")));
1483 }
1484
1485 aml_append(method, aml_return(aml_name("PRR0")));
1486 return method;
1487 }
1488
1489 /* _STA method - get status */
1490 static Aml *build_irq_status_method(void)
1491 {
1492 Aml *if_ctx;
1493 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1494
1495 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1496 aml_append(if_ctx, aml_return(aml_int(0x09)));
1497 aml_append(method, if_ctx);
1498 aml_append(method, aml_return(aml_int(0x0B)));
1499 return method;
1500 }
1501
1502 static void build_piix4_pci0_int(Aml *table)
1503 {
1504 Aml *dev;
1505 Aml *crs;
1506 Aml *field;
1507 Aml *method;
1508 uint32_t irqs;
1509 Aml *sb_scope = aml_scope("_SB");
1510 Aml *pci0_scope = aml_scope("PCI0");
1511
1512 aml_append(pci0_scope, build_prt(true));
1513 aml_append(sb_scope, pci0_scope);
1514
1515 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1516 aml_append(field, aml_named_field("PRQ0", 8));
1517 aml_append(field, aml_named_field("PRQ1", 8));
1518 aml_append(field, aml_named_field("PRQ2", 8));
1519 aml_append(field, aml_named_field("PRQ3", 8));
1520 aml_append(sb_scope, field);
1521
1522 aml_append(sb_scope, build_irq_status_method());
1523 aml_append(sb_scope, build_iqcr_method(true));
1524
1525 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1526 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1527 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1528 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1529
1530 dev = aml_device("LNKS");
1531 {
1532 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1533 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1534
1535 crs = aml_resource_template();
1536 irqs = 9;
1537 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1538 AML_ACTIVE_HIGH, AML_SHARED,
1539 &irqs, 1));
1540 aml_append(dev, aml_name_decl("_PRS", crs));
1541
1542 /* The SCI cannot be disabled and is always attached to GSI 9,
1543 * so these are no-ops. We only need this link to override the
1544 * polarity to active high and match the content of the MADT.
1545 */
1546 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1547 aml_append(method, aml_return(aml_int(0x0b)));
1548 aml_append(dev, method);
1549
1550 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1551 aml_append(dev, method);
1552
1553 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1554 aml_append(method, aml_return(aml_name("_PRS")));
1555 aml_append(dev, method);
1556
1557 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1558 aml_append(dev, method);
1559 }
1560 aml_append(sb_scope, dev);
1561
1562 aml_append(table, sb_scope);
1563 }
1564
1565 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1566 {
1567 int i;
1568 int head;
1569 Aml *pkg;
1570 char base = name[3] < 'E' ? 'A' : 'E';
1571 char *s = g_strdup(name);
1572 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1573
1574 assert(strlen(s) == 4);
1575
1576 head = name[3] - base;
1577 for (i = 0; i < 4; i++) {
1578 if (head + i > 3) {
1579 head = i * -1;
1580 }
1581 s[3] = base + head + i;
1582 pkg = aml_package(4);
1583 aml_append(pkg, a_nr);
1584 aml_append(pkg, aml_int(i));
1585 aml_append(pkg, aml_name("%s", s));
1586 aml_append(pkg, aml_int(0));
1587 aml_append(ctx, pkg);
1588 }
1589 g_free(s);
1590 }
1591
1592 static Aml *build_q35_routing_table(const char *str)
1593 {
1594 int i;
1595 Aml *pkg;
1596 char *name = g_strdup_printf("%s ", str);
1597
1598 pkg = aml_package(128);
1599 for (i = 0; i < 0x18; i++) {
1600 name[3] = 'E' + (i & 0x3);
1601 append_q35_prt_entry(pkg, i, name);
1602 }
1603
1604 name[3] = 'E';
1605 append_q35_prt_entry(pkg, 0x18, name);
1606
1607 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1608 for (i = 0x0019; i < 0x1e; i++) {
1609 name[3] = 'A';
1610 append_q35_prt_entry(pkg, i, name);
1611 }
1612
1613 /* PCIe->PCI bridge. use PIRQ[E-H] */
1614 name[3] = 'E';
1615 append_q35_prt_entry(pkg, 0x1e, name);
1616 name[3] = 'A';
1617 append_q35_prt_entry(pkg, 0x1f, name);
1618
1619 g_free(name);
1620 return pkg;
1621 }
1622
1623 static void build_q35_pci0_int(Aml *table)
1624 {
1625 Aml *field;
1626 Aml *method;
1627 Aml *sb_scope = aml_scope("_SB");
1628 Aml *pci0_scope = aml_scope("PCI0");
1629
1630 /* Zero => PIC mode, One => APIC Mode */
1631 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1632 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1633 {
1634 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1635 }
1636 aml_append(table, method);
1637
1638 aml_append(pci0_scope,
1639 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1640 aml_append(pci0_scope,
1641 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1642
1643 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1644 {
1645 Aml *if_ctx;
1646 Aml *else_ctx;
1647
1648 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1649 section 6.2.8.1 */
1650 /* Note: we provide the same info as the PCI routing
1651 table of the Bochs BIOS */
1652 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1653 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1654 aml_append(method, if_ctx);
1655 else_ctx = aml_else();
1656 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1657 aml_append(method, else_ctx);
1658 }
1659 aml_append(pci0_scope, method);
1660 aml_append(sb_scope, pci0_scope);
1661
1662 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1663 aml_append(field, aml_named_field("PRQA", 8));
1664 aml_append(field, aml_named_field("PRQB", 8));
1665 aml_append(field, aml_named_field("PRQC", 8));
1666 aml_append(field, aml_named_field("PRQD", 8));
1667 aml_append(field, aml_reserved_field(0x20));
1668 aml_append(field, aml_named_field("PRQE", 8));
1669 aml_append(field, aml_named_field("PRQF", 8));
1670 aml_append(field, aml_named_field("PRQG", 8));
1671 aml_append(field, aml_named_field("PRQH", 8));
1672 aml_append(sb_scope, field);
1673
1674 aml_append(sb_scope, build_irq_status_method());
1675 aml_append(sb_scope, build_iqcr_method(false));
1676
1677 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1678 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1679 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1680 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1681 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1682 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1683 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1684 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1685
1686 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1687 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1688 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1689 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1690 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1691 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1692 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1693 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1694
1695 aml_append(table, sb_scope);
1696 }
1697
1698 static void build_q35_isa_bridge(Aml *table)
1699 {
1700 Aml *dev;
1701 Aml *scope;
1702 Aml *field;
1703
1704 scope = aml_scope("_SB.PCI0");
1705 dev = aml_device("ISA");
1706 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1707
1708 /* ICH9 PCI to ISA irq remapping */
1709 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1710 aml_int(0x60), 0x0C));
1711
1712 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1713 aml_int(0x80), 0x02));
1714 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1715 aml_append(field, aml_named_field("COMA", 3));
1716 aml_append(field, aml_reserved_field(1));
1717 aml_append(field, aml_named_field("COMB", 3));
1718 aml_append(field, aml_reserved_field(1));
1719 aml_append(field, aml_named_field("LPTD", 2));
1720 aml_append(dev, field);
1721
1722 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1723 aml_int(0x82), 0x02));
1724 /* enable bits */
1725 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1726 aml_append(field, aml_named_field("CAEN", 1));
1727 aml_append(field, aml_named_field("CBEN", 1));
1728 aml_append(field, aml_named_field("LPEN", 1));
1729 aml_append(dev, field);
1730
1731 aml_append(scope, dev);
1732 aml_append(table, scope);
1733 }
1734
1735 static void build_piix4_pm(Aml *table)
1736 {
1737 Aml *dev;
1738 Aml *scope;
1739
1740 scope = aml_scope("_SB.PCI0");
1741 dev = aml_device("PX13");
1742 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1743
1744 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1745 aml_int(0x00), 0xff));
1746 aml_append(scope, dev);
1747 aml_append(table, scope);
1748 }
1749
1750 static void build_piix4_isa_bridge(Aml *table)
1751 {
1752 Aml *dev;
1753 Aml *scope;
1754 Aml *field;
1755
1756 scope = aml_scope("_SB.PCI0");
1757 dev = aml_device("ISA");
1758 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1759
1760 /* PIIX PCI to ISA irq remapping */
1761 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1762 aml_int(0x60), 0x04));
1763 /* enable bits */
1764 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1765 /* Offset(0x5f),, 7, */
1766 aml_append(field, aml_reserved_field(0x2f8));
1767 aml_append(field, aml_reserved_field(7));
1768 aml_append(field, aml_named_field("LPEN", 1));
1769 /* Offset(0x67),, 3, */
1770 aml_append(field, aml_reserved_field(0x38));
1771 aml_append(field, aml_reserved_field(3));
1772 aml_append(field, aml_named_field("CAEN", 1));
1773 aml_append(field, aml_reserved_field(3));
1774 aml_append(field, aml_named_field("CBEN", 1));
1775 aml_append(dev, field);
1776
1777 aml_append(scope, dev);
1778 aml_append(table, scope);
1779 }
1780
1781 static void build_piix4_pci_hotplug(Aml *table)
1782 {
1783 Aml *scope;
1784 Aml *field;
1785 Aml *method;
1786
1787 scope = aml_scope("_SB.PCI0");
1788
1789 aml_append(scope,
1790 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1791 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1792 aml_append(field, aml_named_field("PCIU", 32));
1793 aml_append(field, aml_named_field("PCID", 32));
1794 aml_append(scope, field);
1795
1796 aml_append(scope,
1797 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1798 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1799 aml_append(field, aml_named_field("B0EJ", 32));
1800 aml_append(scope, field);
1801
1802 aml_append(scope,
1803 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1804 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1805 aml_append(field, aml_named_field("BNUM", 32));
1806 aml_append(scope, field);
1807
1808 aml_append(scope, aml_mutex("BLCK", 0));
1809
1810 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1811 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1812 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1813 aml_append(method,
1814 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1815 aml_append(method, aml_release(aml_name("BLCK")));
1816 aml_append(method, aml_return(aml_int(0)));
1817 aml_append(scope, method);
1818
1819 aml_append(table, scope);
1820 }
1821
1822 static Aml *build_q35_osc_method(void)
1823 {
1824 Aml *if_ctx;
1825 Aml *if_ctx2;
1826 Aml *else_ctx;
1827 Aml *method;
1828 Aml *a_cwd1 = aml_name("CDW1");
1829 Aml *a_ctrl = aml_name("CTRL");
1830
1831 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1832 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1833
1834 if_ctx = aml_if(aml_equal(
1835 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1836 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1837 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1838
1839 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1840 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1841
1842 /*
1843 * Always allow native PME, AER (no dependencies)
1844 * Never allow SHPC (no SHPC controller in this system)
1845 */
1846 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1847
1848 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1849 /* Unknown revision */
1850 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1851 aml_append(if_ctx, if_ctx2);
1852
1853 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1854 /* Capabilities bits were masked */
1855 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1856 aml_append(if_ctx, if_ctx2);
1857
1858 /* Update DWORD3 in the buffer */
1859 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1860 aml_append(method, if_ctx);
1861
1862 else_ctx = aml_else();
1863 /* Unrecognized UUID */
1864 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1865 aml_append(method, else_ctx);
1866
1867 aml_append(method, aml_return(aml_arg(3)));
1868 return method;
1869 }
1870
1871 static void
1872 build_dsdt(GArray *table_data, BIOSLinker *linker,
1873 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1874 PcPciInfo *pci, MachineState *machine)
1875 {
1876 CrsRangeEntry *entry;
1877 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1878 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1879 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1880 PCMachineState *pcms = PC_MACHINE(machine);
1881 uint32_t nr_mem = machine->ram_slots;
1882 int root_bus_limit = 0xFF;
1883 PCIBus *bus = NULL;
1884 int i;
1885
1886 dsdt = init_aml_allocator();
1887
1888 /* Reserve space for header */
1889 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1890
1891 build_dbg_aml(dsdt);
1892 if (misc->is_piix4) {
1893 sb_scope = aml_scope("_SB");
1894 dev = aml_device("PCI0");
1895 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1896 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1897 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1898 aml_append(sb_scope, dev);
1899 aml_append(dsdt, sb_scope);
1900
1901 build_hpet_aml(dsdt);
1902 build_piix4_pm(dsdt);
1903 build_piix4_isa_bridge(dsdt);
1904 build_isa_devices_aml(dsdt);
1905 build_piix4_pci_hotplug(dsdt);
1906 build_piix4_pci0_int(dsdt);
1907 } else {
1908 sb_scope = aml_scope("_SB");
1909 aml_append(sb_scope,
1910 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
1911 aml_append(sb_scope,
1912 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
1913 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1914 aml_append(field, aml_named_field("PCIB", 8));
1915 aml_append(sb_scope, field);
1916 aml_append(dsdt, sb_scope);
1917
1918 sb_scope = aml_scope("_SB");
1919 dev = aml_device("PCI0");
1920 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1921 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1922 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1923 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1924 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
1925 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
1926 aml_append(dev, build_q35_osc_method());
1927 aml_append(sb_scope, dev);
1928 aml_append(dsdt, sb_scope);
1929
1930 build_hpet_aml(dsdt);
1931 build_q35_isa_bridge(dsdt);
1932 build_isa_devices_aml(dsdt);
1933 build_q35_pci0_int(dsdt);
1934 }
1935
1936 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1937 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
1938 pm->mem_hp_io_len);
1939
1940 scope = aml_scope("_GPE");
1941 {
1942 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1943
1944 if (misc->is_piix4) {
1945 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1946 aml_append(method,
1947 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1948 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1949 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1950 aml_append(scope, method);
1951 }
1952
1953 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
1954 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
1955 aml_append(scope, method);
1956 }
1957 aml_append(dsdt, scope);
1958
1959 bus = PC_MACHINE(machine)->bus;
1960 if (bus) {
1961 QLIST_FOREACH(bus, &bus->child, sibling) {
1962 uint8_t bus_num = pci_bus_num(bus);
1963 uint8_t numa_node = pci_bus_numa_node(bus);
1964
1965 /* look only for expander root buses */
1966 if (!pci_bus_is_root(bus)) {
1967 continue;
1968 }
1969
1970 if (bus_num < root_bus_limit) {
1971 root_bus_limit = bus_num - 1;
1972 }
1973
1974 scope = aml_scope("\\_SB");
1975 dev = aml_device("PC%.02X", bus_num);
1976 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1977 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1978 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1979
1980 if (numa_node != NUMA_NODE_UNASSIGNED) {
1981 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1982 }
1983
1984 aml_append(dev, build_prt(false));
1985 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
1986 io_ranges, mem_ranges);
1987 aml_append(dev, aml_name_decl("_CRS", crs));
1988 aml_append(scope, dev);
1989 aml_append(dsdt, scope);
1990 }
1991 }
1992
1993 scope = aml_scope("\\_SB.PCI0");
1994 /* build PCI0._CRS */
1995 crs = aml_resource_template();
1996 aml_append(crs,
1997 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1998 0x0000, 0x0, root_bus_limit,
1999 0x0000, root_bus_limit + 1));
2000 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
2001
2002 aml_append(crs,
2003 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2004 AML_POS_DECODE, AML_ENTIRE_RANGE,
2005 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2006
2007 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
2008 for (i = 0; i < io_ranges->len; i++) {
2009 entry = g_ptr_array_index(io_ranges, i);
2010 aml_append(crs,
2011 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2012 AML_POS_DECODE, AML_ENTIRE_RANGE,
2013 0x0000, entry->base, entry->limit,
2014 0x0000, entry->limit - entry->base + 1));
2015 }
2016
2017 aml_append(crs,
2018 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2019 AML_CACHEABLE, AML_READ_WRITE,
2020 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2021
2022 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
2023 for (i = 0; i < mem_ranges->len; i++) {
2024 entry = g_ptr_array_index(mem_ranges, i);
2025 aml_append(crs,
2026 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2027 AML_NON_CACHEABLE, AML_READ_WRITE,
2028 0, entry->base, entry->limit,
2029 0, entry->limit - entry->base + 1));
2030 }
2031
2032 if (pci->w64.begin) {
2033 aml_append(crs,
2034 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2035 AML_CACHEABLE, AML_READ_WRITE,
2036 0, pci->w64.begin, pci->w64.end - 1, 0,
2037 pci->w64.end - pci->w64.begin));
2038 }
2039
2040 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2041 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2042 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2043 }
2044 aml_append(scope, aml_name_decl("_CRS", crs));
2045
2046 /* reserve GPE0 block resources */
2047 dev = aml_device("GPE0");
2048 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2049 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2050 /* device present, functioning, decoding, not shown in UI */
2051 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2052 crs = aml_resource_template();
2053 aml_append(crs,
2054 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2055 );
2056 aml_append(dev, aml_name_decl("_CRS", crs));
2057 aml_append(scope, dev);
2058
2059 g_ptr_array_free(io_ranges, true);
2060 g_ptr_array_free(mem_ranges, true);
2061
2062 /* reserve PCIHP resources */
2063 if (pm->pcihp_io_len) {
2064 dev = aml_device("PHPR");
2065 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2066 aml_append(dev,
2067 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2068 /* device present, functioning, decoding, not shown in UI */
2069 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2070 crs = aml_resource_template();
2071 aml_append(crs,
2072 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2073 pm->pcihp_io_len)
2074 );
2075 aml_append(dev, aml_name_decl("_CRS", crs));
2076 aml_append(scope, dev);
2077 }
2078 aml_append(dsdt, scope);
2079
2080 /* create S3_ / S4_ / S5_ packages if necessary */
2081 scope = aml_scope("\\");
2082 if (!pm->s3_disabled) {
2083 pkg = aml_package(4);
2084 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2085 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2086 aml_append(pkg, aml_int(0)); /* reserved */
2087 aml_append(pkg, aml_int(0)); /* reserved */
2088 aml_append(scope, aml_name_decl("_S3", pkg));
2089 }
2090
2091 if (!pm->s4_disabled) {
2092 pkg = aml_package(4);
2093 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2094 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2095 aml_append(pkg, aml_int(pm->s4_val));
2096 aml_append(pkg, aml_int(0)); /* reserved */
2097 aml_append(pkg, aml_int(0)); /* reserved */
2098 aml_append(scope, aml_name_decl("_S4", pkg));
2099 }
2100
2101 pkg = aml_package(4);
2102 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2103 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2104 aml_append(pkg, aml_int(0)); /* reserved */
2105 aml_append(pkg, aml_int(0)); /* reserved */
2106 aml_append(scope, aml_name_decl("_S5", pkg));
2107 aml_append(dsdt, scope);
2108
2109 /* create fw_cfg node, unconditionally */
2110 {
2111 /* when using port i/o, the 8-bit data register *always* overlaps
2112 * with half of the 16-bit control register. Hence, the total size
2113 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2114 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2115 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2116 "dma_enabled", NULL) ?
2117 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2118 FW_CFG_CTL_SIZE;
2119
2120 scope = aml_scope("\\_SB.PCI0");
2121 dev = aml_device("FWCF");
2122
2123 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2124
2125 /* device present, functioning, decoding, not shown in UI */
2126 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2127
2128 crs = aml_resource_template();
2129 aml_append(crs,
2130 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2131 );
2132 aml_append(dev, aml_name_decl("_CRS", crs));
2133
2134 aml_append(scope, dev);
2135 aml_append(dsdt, scope);
2136 }
2137
2138 if (misc->applesmc_io_base) {
2139 scope = aml_scope("\\_SB.PCI0.ISA");
2140 dev = aml_device("SMC");
2141
2142 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2143 /* device present, functioning, decoding, not shown in UI */
2144 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2145
2146 crs = aml_resource_template();
2147 aml_append(crs,
2148 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2149 0x01, APPLESMC_MAX_DATA_LENGTH)
2150 );
2151 aml_append(crs, aml_irq_no_flags(6));
2152 aml_append(dev, aml_name_decl("_CRS", crs));
2153
2154 aml_append(scope, dev);
2155 aml_append(dsdt, scope);
2156 }
2157
2158 if (misc->pvpanic_port) {
2159 scope = aml_scope("\\_SB.PCI0.ISA");
2160
2161 dev = aml_device("PEVT");
2162 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2163
2164 crs = aml_resource_template();
2165 aml_append(crs,
2166 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2167 );
2168 aml_append(dev, aml_name_decl("_CRS", crs));
2169
2170 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2171 aml_int(misc->pvpanic_port), 1));
2172 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2173 aml_append(field, aml_named_field("PEPT", 8));
2174 aml_append(dev, field);
2175
2176 /* device present, functioning, decoding, shown in UI */
2177 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2178
2179 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2180 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2181 aml_append(method, aml_return(aml_local(0)));
2182 aml_append(dev, method);
2183
2184 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2185 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2186 aml_append(dev, method);
2187
2188 aml_append(scope, dev);
2189 aml_append(dsdt, scope);
2190 }
2191
2192 sb_scope = aml_scope("\\_SB");
2193 {
2194 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2195 pm->mem_hp_io_len);
2196
2197 {
2198 Object *pci_host;
2199 PCIBus *bus = NULL;
2200
2201 pci_host = acpi_get_i386_pci_host();
2202 if (pci_host) {
2203 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2204 }
2205
2206 if (bus) {
2207 Aml *scope = aml_scope("PCI0");
2208 /* Scan all PCI buses. Generate tables to support hotplug. */
2209 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2210
2211 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2212 dev = aml_device("ISA.TPM");
2213 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2214 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2215 crs = aml_resource_template();
2216 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2217 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2218 /*
2219 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2220 Rewrite to take IRQ from TPM device model and
2221 fix default IRQ value there to use some unused IRQ
2222 */
2223 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2224 aml_append(dev, aml_name_decl("_CRS", crs));
2225 aml_append(scope, dev);
2226 }
2227
2228 aml_append(sb_scope, scope);
2229 }
2230 }
2231 aml_append(dsdt, sb_scope);
2232 }
2233
2234 /* copy AML table into ACPI tables blob and patch header there */
2235 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2236 build_header(linker, table_data,
2237 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2238 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2239 free_aml_allocator();
2240 }
2241
2242 static void
2243 build_hpet(GArray *table_data, BIOSLinker *linker)
2244 {
2245 Acpi20Hpet *hpet;
2246
2247 hpet = acpi_data_push(table_data, sizeof(*hpet));
2248 /* Note timer_block_id value must be kept in sync with value advertised by
2249 * emulated hpet
2250 */
2251 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2252 hpet->addr.address = cpu_to_le64(HPET_BASE);
2253 build_header(linker, table_data,
2254 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2255 }
2256
2257 static void
2258 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2259 {
2260 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2261
2262 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2263 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2264 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2265
2266 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2267 false /* high memory */);
2268
2269 /* log area start address to be filled by Guest linker */
2270 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2271 ACPI_BUILD_TPMLOG_FILE,
2272 &tcpa->log_area_start_address,
2273 sizeof(tcpa->log_area_start_address));
2274
2275 build_header(linker, table_data,
2276 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2277 }
2278
2279 static void
2280 build_tpm2(GArray *table_data, BIOSLinker *linker)
2281 {
2282 Acpi20TPM2 *tpm2_ptr;
2283
2284 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2285
2286 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2287 tpm2_ptr->control_area_address = cpu_to_le64(0);
2288 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2289
2290 build_header(linker, table_data,
2291 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2292 }
2293
2294 static void
2295 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2296 {
2297 AcpiSystemResourceAffinityTable *srat;
2298 AcpiSratProcessorAffinity *core;
2299 AcpiSratMemoryAffinity *numamem;
2300
2301 int i;
2302 uint64_t curnode;
2303 int srat_start, numa_start, slots;
2304 uint64_t mem_len, mem_base, next_base;
2305 MachineClass *mc = MACHINE_GET_CLASS(machine);
2306 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2307 PCMachineState *pcms = PC_MACHINE(machine);
2308 ram_addr_t hotplugabble_address_space_size =
2309 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2310 NULL);
2311
2312 srat_start = table_data->len;
2313
2314 srat = acpi_data_push(table_data, sizeof *srat);
2315 srat->reserved1 = cpu_to_le32(1);
2316
2317 for (i = 0; i < apic_ids->len; i++) {
2318 int apic_id = apic_ids->cpus[i].arch_id;
2319
2320 core = acpi_data_push(table_data, sizeof *core);
2321 core->type = ACPI_SRAT_PROCESSOR_APIC;
2322 core->length = sizeof(*core);
2323 core->local_apic_id = apic_id;
2324 curnode = pcms->node_cpu[apic_id];
2325 core->proximity_lo = curnode;
2326 memset(core->proximity_hi, 0, 3);
2327 core->local_sapic_eid = 0;
2328 core->flags = cpu_to_le32(1);
2329 }
2330
2331
2332 /* the memory map is a bit tricky, it contains at least one hole
2333 * from 640k-1M and possibly another one from 3.5G-4G.
2334 */
2335 next_base = 0;
2336 numa_start = table_data->len;
2337
2338 numamem = acpi_data_push(table_data, sizeof *numamem);
2339 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED);
2340 next_base = 1024 * 1024;
2341 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2342 mem_base = next_base;
2343 mem_len = pcms->node_mem[i - 1];
2344 if (i == 1) {
2345 mem_len -= 1024 * 1024;
2346 }
2347 next_base = mem_base + mem_len;
2348
2349 /* Cut out the ACPI_PCI hole */
2350 if (mem_base <= pcms->below_4g_mem_size &&
2351 next_base > pcms->below_4g_mem_size) {
2352 mem_len -= next_base - pcms->below_4g_mem_size;
2353 if (mem_len > 0) {
2354 numamem = acpi_data_push(table_data, sizeof *numamem);
2355 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2356 MEM_AFFINITY_ENABLED);
2357 }
2358 mem_base = 1ULL << 32;
2359 mem_len = next_base - pcms->below_4g_mem_size;
2360 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2361 }
2362 numamem = acpi_data_push(table_data, sizeof *numamem);
2363 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2364 MEM_AFFINITY_ENABLED);
2365 }
2366 slots = (table_data->len - numa_start) / sizeof *numamem;
2367 for (; slots < pcms->numa_nodes + 2; slots++) {
2368 numamem = acpi_data_push(table_data, sizeof *numamem);
2369 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2370 }
2371
2372 /*
2373 * Entry is required for Windows to enable memory hotplug in OS.
2374 * Memory devices may override proximity set by this entry,
2375 * providing _PXM method if necessary.
2376 */
2377 if (hotplugabble_address_space_size) {
2378 numamem = acpi_data_push(table_data, sizeof *numamem);
2379 build_srat_memory(numamem, pcms->hotplug_memory.base,
2380 hotplugabble_address_space_size, 0,
2381 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2382 }
2383
2384 build_header(linker, table_data,
2385 (void *)(table_data->data + srat_start),
2386 "SRAT",
2387 table_data->len - srat_start, 1, NULL, NULL);
2388 g_free(apic_ids);
2389 }
2390
2391 static void
2392 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2393 {
2394 AcpiTableMcfg *mcfg;
2395 const char *sig;
2396 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2397
2398 mcfg = acpi_data_push(table_data, len);
2399 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2400 /* Only a single allocation so no need to play with segments */
2401 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2402 mcfg->allocation[0].start_bus_number = 0;
2403 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2404
2405 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2406 * To avoid table size changes (which create migration issues),
2407 * always create the table even if there are no allocations,
2408 * but set the signature to a reserved value in this case.
2409 * ACPI spec requires OSPMs to ignore such tables.
2410 */
2411 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2412 /* Reserved signature: ignored by OSPM */
2413 sig = "QEMU";
2414 } else {
2415 sig = "MCFG";
2416 }
2417 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2418 }
2419
2420 static void
2421 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2422 {
2423 int dmar_start = table_data->len;
2424
2425 AcpiTableDmar *dmar;
2426 AcpiDmarHardwareUnit *drhd;
2427
2428 dmar = acpi_data_push(table_data, sizeof(*dmar));
2429 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2430 dmar->flags = 0; /* No intr_remap for now */
2431
2432 /* DMAR Remapping Hardware Unit Definition structure */
2433 drhd = acpi_data_push(table_data, sizeof(*drhd));
2434 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2435 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
2436 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2437 drhd->pci_segment = cpu_to_le16(0);
2438 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2439
2440 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2441 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2442 }
2443
2444 static GArray *
2445 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt)
2446 {
2447 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2448
2449 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
2450 true /* fseg memory */);
2451
2452 memcpy(&rsdp->signature, "RSD PTR ", 8);
2453 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2454 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
2455 /* Address to be filled by Guest linker */
2456 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
2457 ACPI_BUILD_TABLE_FILE,
2458 &rsdp->rsdt_physical_address,
2459 sizeof rsdp->rsdt_physical_address);
2460 rsdp->checksum = 0;
2461 /* Checksum to be filled by Guest linker */
2462 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2463 rsdp, sizeof *rsdp,
2464 &rsdp->checksum);
2465
2466 return rsdp_table;
2467 }
2468
2469 typedef
2470 struct AcpiBuildState {
2471 /* Copy of table in RAM (for patching). */
2472 MemoryRegion *table_mr;
2473 /* Is table patched? */
2474 uint8_t patched;
2475 void *rsdp;
2476 MemoryRegion *rsdp_mr;
2477 MemoryRegion *linker_mr;
2478 } AcpiBuildState;
2479
2480 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2481 {
2482 Object *pci_host;
2483 QObject *o;
2484
2485 pci_host = acpi_get_i386_pci_host();
2486 g_assert(pci_host);
2487
2488 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2489 if (!o) {
2490 return false;
2491 }
2492 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2493 qobject_decref(o);
2494
2495 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2496 assert(o);
2497 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2498 qobject_decref(o);
2499 return true;
2500 }
2501
2502 static bool acpi_has_iommu(void)
2503 {
2504 bool ambiguous;
2505 Object *intel_iommu;
2506
2507 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
2508 &ambiguous);
2509 return intel_iommu && !ambiguous;
2510 }
2511
2512 static
2513 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2514 {
2515 PCMachineState *pcms = PC_MACHINE(machine);
2516 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2517 GArray *table_offsets;
2518 unsigned facs, dsdt, rsdt, fadt;
2519 AcpiPmInfo pm;
2520 AcpiMiscInfo misc;
2521 AcpiMcfgInfo mcfg;
2522 PcPciInfo pci;
2523 uint8_t *u;
2524 size_t aml_len = 0;
2525 GArray *tables_blob = tables->table_data;
2526 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2527
2528 acpi_get_pm_info(&pm);
2529 acpi_get_misc_info(&misc);
2530 acpi_get_pci_info(&pci);
2531 acpi_get_slic_oem(&slic_oem);
2532
2533 table_offsets = g_array_new(false, true /* clear */,
2534 sizeof(uint32_t));
2535 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2536
2537 bios_linker_loader_alloc(tables->linker,
2538 ACPI_BUILD_TABLE_FILE, tables_blob,
2539 64 /* Ensure FACS is aligned */,
2540 false /* high memory */);
2541
2542 /*
2543 * FACS is pointed to by FADT.
2544 * We place it first since it's the only table that has alignment
2545 * requirements.
2546 */
2547 facs = tables_blob->len;
2548 build_facs(tables_blob, tables->linker);
2549
2550 /* DSDT is pointed to by FADT */
2551 dsdt = tables_blob->len;
2552 build_dsdt(tables_blob, tables->linker, &pm, &misc, &pci, machine);
2553
2554 /* Count the size of the DSDT and SSDT, we will need it for legacy
2555 * sizing of ACPI tables.
2556 */
2557 aml_len += tables_blob->len - dsdt;
2558
2559 /* ACPI tables pointed to by RSDT */
2560 fadt = tables_blob->len;
2561 acpi_add_table(table_offsets, tables_blob);
2562 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2563 slic_oem.id, slic_oem.table_id);
2564 aml_len += tables_blob->len - fadt;
2565
2566 acpi_add_table(table_offsets, tables_blob);
2567 build_madt(tables_blob, tables->linker, pcms);
2568
2569 if (misc.has_hpet) {
2570 acpi_add_table(table_offsets, tables_blob);
2571 build_hpet(tables_blob, tables->linker);
2572 }
2573 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2574 acpi_add_table(table_offsets, tables_blob);
2575 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2576
2577 if (misc.tpm_version == TPM_VERSION_2_0) {
2578 acpi_add_table(table_offsets, tables_blob);
2579 build_tpm2(tables_blob, tables->linker);
2580 }
2581 }
2582 if (pcms->numa_nodes) {
2583 acpi_add_table(table_offsets, tables_blob);
2584 build_srat(tables_blob, tables->linker, machine);
2585 }
2586 if (acpi_get_mcfg(&mcfg)) {
2587 acpi_add_table(table_offsets, tables_blob);
2588 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2589 }
2590 if (acpi_has_iommu()) {
2591 acpi_add_table(table_offsets, tables_blob);
2592 build_dmar_q35(tables_blob, tables->linker);
2593 }
2594 if (pcms->acpi_nvdimm_state.is_enabled) {
2595 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2596 pcms->acpi_nvdimm_state.dsm_mem);
2597 }
2598
2599 /* Add tables supplied by user (if any) */
2600 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2601 unsigned len = acpi_table_len(u);
2602
2603 acpi_add_table(table_offsets, tables_blob);
2604 g_array_append_vals(tables_blob, u, len);
2605 }
2606
2607 /* RSDT is pointed to by RSDP */
2608 rsdt = tables_blob->len;
2609 build_rsdt(tables_blob, tables->linker, table_offsets,
2610 slic_oem.id, slic_oem.table_id);
2611
2612 /* RSDP is in FSEG memory, so allocate it separately */
2613 build_rsdp(tables->rsdp, tables->linker, rsdt);
2614
2615 /* We'll expose it all to Guest so we want to reduce
2616 * chance of size changes.
2617 *
2618 * We used to align the tables to 4k, but of course this would
2619 * too simple to be enough. 4k turned out to be too small an
2620 * alignment very soon, and in fact it is almost impossible to
2621 * keep the table size stable for all (max_cpus, max_memory_slots)
2622 * combinations. So the table size is always 64k for pc-i440fx-2.1
2623 * and we give an error if the table grows beyond that limit.
2624 *
2625 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2626 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2627 * than 2.0 and we can always pad the smaller tables with zeros. We can
2628 * then use the exact size of the 2.0 tables.
2629 *
2630 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2631 */
2632 if (pcmc->legacy_acpi_table_size) {
2633 /* Subtracting aml_len gives the size of fixed tables. Then add the
2634 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2635 */
2636 int legacy_aml_len =
2637 pcmc->legacy_acpi_table_size +
2638 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2639 int legacy_table_size =
2640 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2641 ACPI_BUILD_ALIGN_SIZE);
2642 if (tables_blob->len > legacy_table_size) {
2643 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2644 error_report("Warning: migration may not work.");
2645 }
2646 g_array_set_size(tables_blob, legacy_table_size);
2647 } else {
2648 /* Make sure we have a buffer in case we need to resize the tables. */
2649 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2650 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2651 error_report("Warning: ACPI tables are larger than 64k.");
2652 error_report("Warning: migration may not work.");
2653 error_report("Warning: please remove CPUs, NUMA nodes, "
2654 "memory slots or PCI bridges.");
2655 }
2656 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2657 }
2658
2659 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2660
2661 /* Cleanup memory that's no longer used. */
2662 g_array_free(table_offsets, true);
2663 }
2664
2665 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2666 {
2667 uint32_t size = acpi_data_len(data);
2668
2669 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2670 memory_region_ram_resize(mr, size, &error_abort);
2671
2672 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2673 memory_region_set_dirty(mr, 0, size);
2674 }
2675
2676 static void acpi_build_update(void *build_opaque)
2677 {
2678 AcpiBuildState *build_state = build_opaque;
2679 AcpiBuildTables tables;
2680
2681 /* No state to update or already patched? Nothing to do. */
2682 if (!build_state || build_state->patched) {
2683 return;
2684 }
2685 build_state->patched = 1;
2686
2687 acpi_build_tables_init(&tables);
2688
2689 acpi_build(&tables, MACHINE(qdev_get_machine()));
2690
2691 acpi_ram_update(build_state->table_mr, tables.table_data);
2692
2693 if (build_state->rsdp) {
2694 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2695 } else {
2696 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2697 }
2698
2699 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2700 acpi_build_tables_cleanup(&tables, true);
2701 }
2702
2703 static void acpi_build_reset(void *build_opaque)
2704 {
2705 AcpiBuildState *build_state = build_opaque;
2706 build_state->patched = 0;
2707 }
2708
2709 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2710 GArray *blob, const char *name,
2711 uint64_t max_size)
2712 {
2713 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2714 name, acpi_build_update, build_state);
2715 }
2716
2717 static const VMStateDescription vmstate_acpi_build = {
2718 .name = "acpi_build",
2719 .version_id = 1,
2720 .minimum_version_id = 1,
2721 .fields = (VMStateField[]) {
2722 VMSTATE_UINT8(patched, AcpiBuildState),
2723 VMSTATE_END_OF_LIST()
2724 },
2725 };
2726
2727 void acpi_setup(void)
2728 {
2729 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2730 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2731 AcpiBuildTables tables;
2732 AcpiBuildState *build_state;
2733
2734 if (!pcms->fw_cfg) {
2735 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2736 return;
2737 }
2738
2739 if (!pcmc->has_acpi_build) {
2740 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2741 return;
2742 }
2743
2744 if (!acpi_enabled) {
2745 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2746 return;
2747 }
2748
2749 build_state = g_malloc0(sizeof *build_state);
2750
2751 acpi_set_pci_info();
2752
2753 acpi_build_tables_init(&tables);
2754 acpi_build(&tables, MACHINE(pcms));
2755
2756 /* Now expose it all to Guest */
2757 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2758 ACPI_BUILD_TABLE_FILE,
2759 ACPI_BUILD_TABLE_MAX_SIZE);
2760 assert(build_state->table_mr != NULL);
2761
2762 build_state->linker_mr =
2763 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2764 "etc/table-loader", 0);
2765
2766 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2767 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2768
2769 if (!pcmc->rsdp_in_ram) {
2770 /*
2771 * Keep for compatibility with old machine types.
2772 * Though RSDP is small, its contents isn't immutable, so
2773 * we'll update it along with the rest of tables on guest access.
2774 */
2775 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2776
2777 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2778 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2779 acpi_build_update, build_state,
2780 build_state->rsdp, rsdp_size);
2781 build_state->rsdp_mr = NULL;
2782 } else {
2783 build_state->rsdp = NULL;
2784 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2785 ACPI_BUILD_RSDP_FILE, 0);
2786 }
2787
2788 qemu_register_reset(acpi_build_reset, build_state);
2789 acpi_build_reset(build_state);
2790 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2791
2792 /* Cleanup tables but don't free the memory: we track it
2793 * in build_state.
2794 */
2795 acpi_build_tables_cleanup(&tables, false);
2796 }
AR7 emulation for QEMU