hw/sparc64/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu-common.h"
  27 #include "cpu.h"
  28 #include "hw/hw.h"
  29 #include "hw/pci/pci.h"
  30 #include "hw/pci-host/apb.h"
  31 #include "hw/i386/pc.h"
  32 #include "hw/char/serial.h"
  33 #include "hw/timer/m48t59.h"
  34 #include "hw/block/fdc.h"
  35 #include "net/net.h"
  36 #include "qemu/timer.h"
  37 #include "sysemu/sysemu.h"
  38 #include "hw/boards.h"
  39 #include "hw/nvram/openbios_firmware_abi.h"
  40 #include "hw/nvram/fw_cfg.h"
  41 #include "hw/sysbus.h"
  42 #include "hw/ide.h"
  43 #include "hw/loader.h"
  44 #include "elf.h"
  45 #include "sysemu/block-backend.h"
  46 #include "exec/address-spaces.h"
  47 #include "qemu/cutils.h"
  48
  49 //#define DEBUG_IRQ
  50 //#define DEBUG_EBUS
  51 //#define DEBUG_TIMER
  52
  53 #ifdef DEBUG_IRQ
  54 #define CPUIRQ_DPRINTF(fmt, ...)                                \
  55     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  56 #else
  57 #define CPUIRQ_DPRINTF(fmt, ...)
  58 #endif
  59
  60 #ifdef DEBUG_EBUS
  61 #define EBUS_DPRINTF(fmt, ...)                                  \
  62     do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
  63 #else
  64 #define EBUS_DPRINTF(fmt, ...)
  65 #endif
  66
  67 #ifdef DEBUG_TIMER
  68 #define TIMER_DPRINTF(fmt, ...)                                  \
  69     do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
  70 #else
  71 #define TIMER_DPRINTF(fmt, ...)
  72 #endif
  73
  74 #define KERNEL_LOAD_ADDR     0x00404000
  75 #define CMDLINE_ADDR         0x003ff000
  76 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  77 #define PROM_VADDR           0x000ffd00000ULL
  78 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  79 #define APB_MEM_BASE         0x1ff00000000ULL
  80 #define APB_PCI_IO_BASE      (APB_SPECIAL_BASE + 0x02000000ULL)
  81 #define PROM_FILENAME        "openbios-sparc64"
  82 #define NVRAM_SIZE           0x2000
  83 #define MAX_IDE_BUS          2
  84 #define BIOS_CFG_IOPORT      0x510
  85 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  86 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  87 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  88
  89 #define IVEC_MAX             0x40
  90
  91 #define TICK_MAX             0x7fffffffffffffffULL
  92
  93 struct hwdef {
  94     const char * const default_cpu_model;
  95     uint16_t machine_id;
  96     uint64_t prom_addr;
  97     uint64_t console_serial_base;
  98 };
  99
 100 typedef struct EbusState {
 101     PCIDevice pci_dev;
 102     MemoryRegion bar0;
 103     MemoryRegion bar1;
 104 } EbusState;
 105
 106 void DMA_init(ISABus *bus, int high_page_enable)
 107 {
 108 }
 109
 110 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
 111                             Error **errp)
 112 {
 113     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 114 }
 115
 116 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
 117                                   const char *arch, ram_addr_t RAM_size,
 118                                   const char *boot_devices,
 119                                   uint32_t kernel_image, uint32_t kernel_size,
 120                                   const char *cmdline,
 121                                   uint32_t initrd_image, uint32_t initrd_size,
 122                                   uint32_t NVRAM_image,
 123                                   int width, int height, int depth,
 124                                   const uint8_t *macaddr)
 125 {
 126     unsigned int i;
 127     uint32_t start, end;
 128     uint8_t image[0x1ff0];
 129     struct OpenBIOS_nvpart_v1 *part_header;
 130     NvramClass *k = NVRAM_GET_CLASS(nvram);
 131
 132     memset(image, '\0', sizeof(image));
 133
 134     start = 0;
 135
 136     // OpenBIOS nvram variables
 137     // Variable partition
 138     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 139     part_header->signature = OPENBIOS_PART_SYSTEM;
 140     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 141
 142     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 143     for (i = 0; i < nb_prom_envs; i++)
 144         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 145
 146     // End marker
 147     image[end++] = '\0';
 148
 149     end = start + ((end - start + 15) & ~15);
 150     OpenBIOS_finish_partition(part_header, end - start);
 151
 152     // free partition
 153     start = end;
 154     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 155     part_header->signature = OPENBIOS_PART_FREE;
 156     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 157
 158     end = 0x1fd0;
 159     OpenBIOS_finish_partition(part_header, end - start);
 160
 161     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 162
 163     for (i = 0; i < sizeof(image); i++) {
 164         (k->write)(nvram, i, image[i]);
 165     }
 166
 167     return 0;
 168 }
 169
 170 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 171                                   const char *initrd_filename,
 172                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 173                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 174                                   uint64_t *kernel_entry)
 175 {
 176     int linux_boot;
 177     unsigned int i;
 178     long kernel_size;
 179     uint8_t *ptr;
 180     uint64_t kernel_top;
 181
 182     linux_boot = (kernel_filename != NULL);
 183
 184     kernel_size = 0;
 185     if (linux_boot) {
 186         int bswap_needed;
 187
 188 #ifdef BSWAP_NEEDED
 189         bswap_needed = 1;
 190 #else
 191         bswap_needed = 0;
 192 #endif
 193         kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
 194                                kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
 195         if (kernel_size < 0) {
 196             *kernel_addr = KERNEL_LOAD_ADDR;
 197             *kernel_entry = KERNEL_LOAD_ADDR;
 198             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 199                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 200                                     TARGET_PAGE_SIZE);
 201         }
 202         if (kernel_size < 0) {
 203             kernel_size = load_image_targphys(kernel_filename,
 204                                               KERNEL_LOAD_ADDR,
 205                                               RAM_size - KERNEL_LOAD_ADDR);
 206         }
 207         if (kernel_size < 0) {
 208             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 209                     kernel_filename);
 210             exit(1);
 211         }
 212         /* load initrd above kernel */
 213         *initrd_size = 0;
 214         if (initrd_filename) {
 215             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 216
 217             *initrd_size = load_image_targphys(initrd_filename,
 218                                                *initrd_addr,
 219                                                RAM_size - *initrd_addr);
 220             if ((int)*initrd_size < 0) {
 221                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 222                         initrd_filename);
 223                 exit(1);
 224             }
 225         }
 226         if (*initrd_size > 0) {
 227             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 228                 ptr = rom_ptr(*kernel_addr + i);
 229                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 230                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 231                     stl_p(ptr + 28, *initrd_size);
 232                     break;
 233                 }
 234             }
 235         }
 236     }
 237     return kernel_size;
 238 }
 239
 240 void cpu_check_irqs(CPUSPARCState *env)
 241 {
 242     CPUState *cs;
 243     uint32_t pil = env->pil_in |
 244                   (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
 245
 246     /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
 247     if (env->ivec_status & 0x20) {
 248         return;
 249     }
 250     cs = CPU(sparc_env_get_cpu(env));
 251     /* check if TM or SM in SOFTINT are set
 252        setting these also causes interrupt 14 */
 253     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
 254         pil |= 1 << 14;
 255     }
 256
 257     /* The bit corresponding to psrpil is (1<< psrpil), the next bit
 258        is (2 << psrpil). */
 259     if (pil < (2 << env->psrpil)){
 260         if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 261             CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
 262                            env->interrupt_index);
 263             env->interrupt_index = 0;
 264             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 265         }
 266         return;
 267     }
 268
 269     if (cpu_interrupts_enabled(env)) {
 270
 271         unsigned int i;
 272
 273         for (i = 15; i > env->psrpil; i--) {
 274             if (pil & (1 << i)) {
 275                 int old_interrupt = env->interrupt_index;
 276                 int new_interrupt = TT_EXTINT | i;
 277
 278                 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
 279                   && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
 280                     CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
 281                                    "current %x >= pending %x\n",
 282                                    env->tl, cpu_tsptr(env)->tt, new_interrupt);
 283                 } else if (old_interrupt != new_interrupt) {
 284                     env->interrupt_index = new_interrupt;
 285                     CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
 286                                    old_interrupt, new_interrupt);
 287                     cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 288                 }
 289                 break;
 290             }
 291         }
 292     } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 293         CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
 294                        "current interrupt %x\n",
 295                        pil, env->pil_in, env->softint, env->interrupt_index);
 296         env->interrupt_index = 0;
 297         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 298     }
 299 }
 300
 301 static void cpu_kick_irq(SPARCCPU *cpu)
 302 {
 303     CPUState *cs = CPU(cpu);
 304     CPUSPARCState *env = &cpu->env;
 305
 306     cs->halted = 0;
 307     cpu_check_irqs(env);
 308     qemu_cpu_kick(cs);
 309 }
 310
 311 static void cpu_set_ivec_irq(void *opaque, int irq, int level)
 312 {
 313     SPARCCPU *cpu = opaque;
 314     CPUSPARCState *env = &cpu->env;
 315     CPUState *cs;
 316
 317     if (level) {
 318         if (!(env->ivec_status & 0x20)) {
 319             CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
 320             cs = CPU(cpu);
 321             cs->halted = 0;
 322             env->interrupt_index = TT_IVEC;
 323             env->ivec_status |= 0x20;
 324             env->ivec_data[0] = (0x1f << 6) | irq;
 325             env->ivec_data[1] = 0;
 326             env->ivec_data[2] = 0;
 327             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 328         }
 329     } else {
 330         if (env->ivec_status & 0x20) {
 331             CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
 332             cs = CPU(cpu);
 333             env->ivec_status &= ~0x20;
 334             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 335         }
 336     }
 337 }
 338
 339 typedef struct ResetData {
 340     SPARCCPU *cpu;
 341     uint64_t prom_addr;
 342 } ResetData;
 343
 344 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
 345                                   QEMUBHFunc *cb, uint32_t frequency,
 346                                   uint64_t disabled_mask, uint64_t npt_mask)
 347 {
 348     CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
 349
 350     timer->name = name;
 351     timer->frequency = frequency;
 352     timer->disabled_mask = disabled_mask;
 353     timer->npt_mask = npt_mask;
 354
 355     timer->disabled = 1;
 356     timer->npt = 1;
 357     timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 358
 359     timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu);
 360
 361     return timer;
 362 }
 363
 364 static void cpu_timer_reset(CPUTimer *timer)
 365 {
 366     timer->disabled = 1;
 367     timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 368
 369     timer_del(timer->qtimer);
 370 }
 371
 372 static void main_cpu_reset(void *opaque)
 373 {
 374     ResetData *s = (ResetData *)opaque;
 375     CPUSPARCState *env = &s->cpu->env;
 376     static unsigned int nr_resets;
 377
 378     cpu_reset(CPU(s->cpu));
 379
 380     cpu_timer_reset(env->tick);
 381     cpu_timer_reset(env->stick);
 382     cpu_timer_reset(env->hstick);
 383
 384     env->gregs[1] = 0; // Memory start
 385     env->gregs[2] = ram_size; // Memory size
 386     env->gregs[3] = 0; // Machine description XXX
 387     if (nr_resets++ == 0) {
 388         /* Power on reset */
 389         env->pc = s->prom_addr + 0x20ULL;
 390     } else {
 391         env->pc = s->prom_addr + 0x40ULL;
 392     }
 393     env->npc = env->pc + 4;
 394 }
 395
 396 static void tick_irq(void *opaque)
 397 {
 398     SPARCCPU *cpu = opaque;
 399     CPUSPARCState *env = &cpu->env;
 400
 401     CPUTimer* timer = env->tick;
 402
 403     if (timer->disabled) {
 404         CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
 405         return;
 406     } else {
 407         CPUIRQ_DPRINTF("tick: fire\n");
 408     }
 409
 410     env->softint |= SOFTINT_TIMER;
 411     cpu_kick_irq(cpu);
 412 }
 413
 414 static void stick_irq(void *opaque)
 415 {
 416     SPARCCPU *cpu = opaque;
 417     CPUSPARCState *env = &cpu->env;
 418
 419     CPUTimer* timer = env->stick;
 420
 421     if (timer->disabled) {
 422         CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
 423         return;
 424     } else {
 425         CPUIRQ_DPRINTF("stick: fire\n");
 426     }
 427
 428     env->softint |= SOFTINT_STIMER;
 429     cpu_kick_irq(cpu);
 430 }
 431
 432 static void hstick_irq(void *opaque)
 433 {
 434     SPARCCPU *cpu = opaque;
 435     CPUSPARCState *env = &cpu->env;
 436
 437     CPUTimer* timer = env->hstick;
 438
 439     if (timer->disabled) {
 440         CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
 441         return;
 442     } else {
 443         CPUIRQ_DPRINTF("hstick: fire\n");
 444     }
 445
 446     env->softint |= SOFTINT_STIMER;
 447     cpu_kick_irq(cpu);
 448 }
 449
 450 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
 451 {
 452     return muldiv64(cpu_ticks, NANOSECONDS_PER_SECOND, frequency);
 453 }
 454
 455 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
 456 {
 457     return muldiv64(timer_ticks, frequency, NANOSECONDS_PER_SECOND);
 458 }
 459
 460 void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
 461 {
 462     uint64_t real_count = count & ~timer->npt_mask;
 463     uint64_t npt_bit = count & timer->npt_mask;
 464
 465     int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 466                     cpu_to_timer_ticks(real_count, timer->frequency);
 467
 468     TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
 469                   timer->name, real_count,
 470                   timer->npt ? "disabled" : "enabled", timer);
 471
 472     timer->npt = npt_bit ? 1 : 0;
 473     timer->clock_offset = vm_clock_offset;
 474 }
 475
 476 uint64_t cpu_tick_get_count(CPUTimer *timer)
 477 {
 478     uint64_t real_count = timer_to_cpu_ticks(
 479                     qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset,
 480                     timer->frequency);
 481
 482     TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n",
 483            timer->name, real_count,
 484            timer->npt ? "disabled" : "enabled", timer);
 485
 486     if (timer->npt) {
 487         real_count |= timer->npt_mask;
 488     }
 489
 490     return real_count;
 491 }
 492
 493 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
 494 {
 495     int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 496
 497     uint64_t real_limit = limit & ~timer->disabled_mask;
 498     timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
 499
 500     int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
 501                     timer->clock_offset;
 502
 503     if (expires < now) {
 504         expires = now + 1;
 505     }
 506
 507     TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
 508                   "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
 509                   timer->name, real_limit,
 510                   timer->disabled?"disabled":"enabled",
 511                   timer, limit,
 512                   timer_to_cpu_ticks(now - timer->clock_offset,
 513                                      timer->frequency),
 514                   timer_to_cpu_ticks(expires - now, timer->frequency));
 515
 516     if (!real_limit) {
 517         TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
 518                 timer->name);
 519         timer_del(timer->qtimer);
 520     } else if (timer->disabled) {
 521         timer_del(timer->qtimer);
 522     } else {
 523         timer_mod(timer->qtimer, expires);
 524     }
 525 }
 526
 527 static void isa_irq_handler(void *opaque, int n, int level)
 528 {
 529     static const int isa_irq_to_ivec[16] = {
 530         [1] = 0x29, /* keyboard */
 531         [4] = 0x2b, /* serial */
 532         [6] = 0x27, /* floppy */
 533         [7] = 0x22, /* parallel */
 534         [12] = 0x2a, /* mouse */
 535     };
 536     qemu_irq *irqs = opaque;
 537     int ivec;
 538
 539     assert(n < 16);
 540     ivec = isa_irq_to_ivec[n];
 541     EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
 542     if (ivec) {
 543         qemu_set_irq(irqs[ivec], level);
 544     }
 545 }
 546
 547 /* EBUS (Eight bit bus) bridge */
 548 static ISABus *
 549 pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
 550 {
 551     qemu_irq *isa_irq;
 552     PCIDevice *pci_dev;
 553     ISABus *isa_bus;
 554
 555     pci_dev = pci_create_simple(bus, devfn, "ebus");
 556     isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0"));
 557     isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
 558     isa_bus_irqs(isa_bus, isa_irq);
 559     return isa_bus;
 560 }
 561
 562 static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp)
 563 {
 564     EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
 565
 566     if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(),
 567                      pci_address_space_io(pci_dev), errp)) {
 568         return;
 569     }
 570
 571     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 572     pci_dev->config[0x05] = 0x00;
 573     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 574     pci_dev->config[0x07] = 0x03; // status = medium devsel
 575     pci_dev->config[0x09] = 0x00; // programming i/f
 576     pci_dev->config[0x0D] = 0x0a; // latency_timer
 577
 578     memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
 579                              0, 0x1000000);
 580     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 581     memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
 582                              0, 0x4000);
 583     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
 584 }
 585
 586 static void ebus_class_init(ObjectClass *klass, void *data)
 587 {
 588     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 589
 590     k->realize = pci_ebus_realize;
 591     k->vendor_id = PCI_VENDOR_ID_SUN;
 592     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 593     k->revision = 0x01;
 594     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 595 }
 596
 597 static const TypeInfo ebus_info = {
 598     .name          = "ebus",
 599     .parent        = TYPE_PCI_DEVICE,
 600     .instance_size = sizeof(EbusState),
 601     .class_init    = ebus_class_init,
 602 };
 603
 604 #define TYPE_OPENPROM "openprom"
 605 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
 606
 607 typedef struct PROMState {
 608     SysBusDevice parent_obj;
 609
 610     MemoryRegion prom;
 611 } PROMState;
 612
 613 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 614 {
 615     hwaddr *base_addr = (hwaddr *)opaque;
 616     return addr + *base_addr - PROM_VADDR;
 617 }
 618
 619 /* Boot PROM (OpenBIOS) */
 620 static void prom_init(hwaddr addr, const char *bios_name)
 621 {
 622     DeviceState *dev;
 623     SysBusDevice *s;
 624     char *filename;
 625     int ret;
 626
 627     dev = qdev_create(NULL, TYPE_OPENPROM);
 628     qdev_init_nofail(dev);
 629     s = SYS_BUS_DEVICE(dev);
 630
 631     sysbus_mmio_map(s, 0, addr);
 632
 633     /* load boot prom */
 634     if (bios_name == NULL) {
 635         bios_name = PROM_FILENAME;
 636     }
 637     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 638     if (filename) {
 639         ret = load_elf(filename, translate_prom_address, &addr,
 640                        NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
 641         if (ret < 0 || ret > PROM_SIZE_MAX) {
 642             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 643         }
 644         g_free(filename);
 645     } else {
 646         ret = -1;
 647     }
 648     if (ret < 0 || ret > PROM_SIZE_MAX) {
 649         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 650         exit(1);
 651     }
 652 }
 653
 654 static int prom_init1(SysBusDevice *dev)
 655 {
 656     PROMState *s = OPENPROM(dev);
 657
 658     memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX,
 659                            &error_fatal);
 660     vmstate_register_ram_global(&s->prom);
 661     memory_region_set_readonly(&s->prom, true);
 662     sysbus_init_mmio(dev, &s->prom);
 663     return 0;
 664 }
 665
 666 static Property prom_properties[] = {
 667     {/* end of property list */},
 668 };
 669
 670 static void prom_class_init(ObjectClass *klass, void *data)
 671 {
 672     DeviceClass *dc = DEVICE_CLASS(klass);
 673     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 674
 675     k->init = prom_init1;
 676     dc->props = prom_properties;
 677 }
 678
 679 static const TypeInfo prom_info = {
 680     .name          = TYPE_OPENPROM,
 681     .parent        = TYPE_SYS_BUS_DEVICE,
 682     .instance_size = sizeof(PROMState),
 683     .class_init    = prom_class_init,
 684 };
 685
 686
 687 #define TYPE_SUN4U_MEMORY "memory"
 688 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
 689
 690 typedef struct RamDevice {
 691     SysBusDevice parent_obj;
 692
 693     MemoryRegion ram;
 694     uint64_t size;
 695 } RamDevice;
 696
 697 /* System RAM */
 698 static int ram_init1(SysBusDevice *dev)
 699 {
 700     RamDevice *d = SUN4U_RAM(dev);
 701
 702     memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size,
 703                            &error_fatal);
 704     vmstate_register_ram_global(&d->ram);
 705     sysbus_init_mmio(dev, &d->ram);
 706     return 0;
 707 }
 708
 709 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
 710 {
 711     DeviceState *dev;
 712     SysBusDevice *s;
 713     RamDevice *d;
 714
 715     /* allocate RAM */
 716     dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
 717     s = SYS_BUS_DEVICE(dev);
 718
 719     d = SUN4U_RAM(dev);
 720     d->size = RAM_size;
 721     qdev_init_nofail(dev);
 722
 723     sysbus_mmio_map(s, 0, addr);
 724 }
 725
 726 static Property ram_properties[] = {
 727     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 728     DEFINE_PROP_END_OF_LIST(),
 729 };
 730
 731 static void ram_class_init(ObjectClass *klass, void *data)
 732 {
 733     DeviceClass *dc = DEVICE_CLASS(klass);
 734     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 735
 736     k->init = ram_init1;
 737     dc->props = ram_properties;
 738 }
 739
 740 static const TypeInfo ram_info = {
 741     .name          = TYPE_SUN4U_MEMORY,
 742     .parent        = TYPE_SYS_BUS_DEVICE,
 743     .instance_size = sizeof(RamDevice),
 744     .class_init    = ram_class_init,
 745 };
 746
 747 static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 748 {
 749     SPARCCPU *cpu;
 750     CPUSPARCState *env;
 751     ResetData *reset_info;
 752
 753     uint32_t   tick_frequency = 100*1000000;
 754     uint32_t  stick_frequency = 100*1000000;
 755     uint32_t hstick_frequency = 100*1000000;
 756
 757     if (cpu_model == NULL) {
 758         cpu_model = hwdef->default_cpu_model;
 759     }
 760     cpu = cpu_sparc_init(cpu_model);
 761     if (cpu == NULL) {
 762         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 763         exit(1);
 764     }
 765     env = &cpu->env;
 766
 767     env->tick = cpu_timer_create("tick", cpu, tick_irq,
 768                                   tick_frequency, TICK_INT_DIS,
 769                                   TICK_NPT_MASK);
 770
 771     env->stick = cpu_timer_create("stick", cpu, stick_irq,
 772                                    stick_frequency, TICK_INT_DIS,
 773                                    TICK_NPT_MASK);
 774
 775     env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
 776                                     hstick_frequency, TICK_INT_DIS,
 777                                     TICK_NPT_MASK);
 778
 779     reset_info = g_malloc0(sizeof(ResetData));
 780     reset_info->cpu = cpu;
 781     reset_info->prom_addr = hwdef->prom_addr;
 782     qemu_register_reset(main_cpu_reset, reset_info);
 783
 784     return cpu;
 785 }
 786
 787 static void sun4uv_init(MemoryRegion *address_space_mem,
 788                         MachineState *machine,
 789                         const struct hwdef *hwdef)
 790 {
 791     SPARCCPU *cpu;
 792     Nvram *nvram;
 793     unsigned int i;
 794     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 795     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 796     ISABus *isa_bus;
 797     SysBusDevice *s;
 798     qemu_irq *ivec_irqs, *pbm_irqs;
 799     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 800     DriveInfo *fd[MAX_FD];
 801     DeviceState *dev;
 802     FWCfgState *fw_cfg;
 803
 804     /* init CPUs */
 805     cpu = cpu_devinit(machine->cpu_model, hwdef);
 806
 807     /* set up devices */
 808     ram_init(0, machine->ram_size);
 809
 810     prom_init(hwdef->prom_addr, bios_name);
 811
 812     ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX);
 813     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
 814                            &pci_bus3, &pbm_irqs);
 815     pci_vga_init(pci_bus);
 816
 817     // XXX Should be pci_bus3
 818     isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
 819
 820     i = 0;
 821     if (hwdef->console_serial_base) {
 822         serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
 823                        NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
 824         i++;
 825     }
 826
 827     serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS);
 828     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
 829
 830     for(i = 0; i < nb_nics; i++)
 831         pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
 832
 833     ide_drive_get(hd, ARRAY_SIZE(hd));
 834
 835     pci_cmd646_ide_init(pci_bus, hd, 1);
 836
 837     isa_create_simple(isa_bus, "i8042");
 838
 839     /* Floppy */
 840     for(i = 0; i < MAX_FD; i++) {
 841         fd[i] = drive_get(IF_FLOPPY, 0, i);
 842     }
 843     dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC));
 844     if (fd[0]) {
 845         qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
 846                             &error_abort);
 847     }
 848     if (fd[1]) {
 849         qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
 850                             &error_abort);
 851     }
 852     qdev_prop_set_uint32(dev, "dma", -1);
 853     qdev_init_nofail(dev);
 854
 855     /* Map NVRAM into I/O (ebus) space */
 856     nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
 857     s = SYS_BUS_DEVICE(nvram);
 858     memory_region_add_subregion(get_system_io(), 0x2000,
 859                                 sysbus_mmio_get_region(s, 0));
 860
 861     initrd_size = 0;
 862     initrd_addr = 0;
 863     kernel_size = sun4u_load_kernel(machine->kernel_filename,
 864                                     machine->initrd_filename,
 865                                     ram_size, &initrd_size, &initrd_addr,
 866                                     &kernel_addr, &kernel_entry);
 867
 868     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
 869                            machine->boot_order,
 870                            kernel_addr, kernel_size,
 871                            machine->kernel_cmdline,
 872                            initrd_addr, initrd_size,
 873                            /* XXX: need an option to load a NVRAM image */
 874                            0,
 875                            graphic_width, graphic_height, graphic_depth,
 876                            (uint8_t *)&nd_table[0].macaddr);
 877
 878     fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
 879     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 880     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 881     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 882     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 883     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 884     if (machine->kernel_cmdline) {
 885         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 886                        strlen(machine->kernel_cmdline) + 1);
 887         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
 888     } else {
 889         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 890     }
 891     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 892     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 893     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
 894
 895     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 896     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 897     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 898
 899     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 900 }
 901
 902 enum {
 903     sun4u_id = 0,
 904     sun4v_id = 64,
 905     niagara_id,
 906 };
 907
 908 static const struct hwdef hwdefs[] = {
 909     /* Sun4u generic PC-like machine */
 910     {
 911         .default_cpu_model = "TI UltraSparc IIi",
 912         .machine_id = sun4u_id,
 913         .prom_addr = 0x1fff0000000ULL,
 914         .console_serial_base = 0,
 915     },
 916     /* Sun4v generic PC-like machine */
 917     {
 918         .default_cpu_model = "Sun UltraSparc T1",
 919         .machine_id = sun4v_id,
 920         .prom_addr = 0x1fff0000000ULL,
 921         .console_serial_base = 0,
 922     },
 923     /* Sun4v generic Niagara machine */
 924     {
 925         .default_cpu_model = "Sun UltraSparc T1",
 926         .machine_id = niagara_id,
 927         .prom_addr = 0xfff0000000ULL,
 928         .console_serial_base = 0xfff0c2c000ULL,
 929     },
 930 };
 931
 932 /* Sun4u hardware initialisation */
 933 static void sun4u_init(MachineState *machine)
 934 {
 935     sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
 936 }
 937
 938 /* Sun4v hardware initialisation */
 939 static void sun4v_init(MachineState *machine)
 940 {
 941     sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
 942 }
 943
 944 /* Niagara hardware initialisation */
 945 static void niagara_init(MachineState *machine)
 946 {
 947     sun4uv_init(get_system_memory(), machine, &hwdefs[2]);
 948 }
 949
 950 static void sun4u_class_init(ObjectClass *oc, void *data)
 951 {
 952     MachineClass *mc = MACHINE_CLASS(oc);
 953
 954     mc->desc = "Sun4u platform";
 955     mc->init = sun4u_init;
 956     mc->max_cpus = 1; /* XXX for now */
 957     mc->is_default = 1;
 958     mc->default_boot_order = "c";
 959 }
 960
 961 static const TypeInfo sun4u_type = {
 962     .name = MACHINE_TYPE_NAME("sun4u"),
 963     .parent = TYPE_MACHINE,
 964     .class_init = sun4u_class_init,
 965 };
 966
 967 static void sun4v_class_init(ObjectClass *oc, void *data)
 968 {
 969     MachineClass *mc = MACHINE_CLASS(oc);
 970
 971     mc->desc = "Sun4v platform";
 972     mc->init = sun4v_init;
 973     mc->max_cpus = 1; /* XXX for now */
 974     mc->default_boot_order = "c";
 975 }
 976
 977 static const TypeInfo sun4v_type = {
 978     .name = MACHINE_TYPE_NAME("sun4v"),
 979     .parent = TYPE_MACHINE,
 980     .class_init = sun4v_class_init,
 981 };
 982
 983 static void niagara_class_init(ObjectClass *oc, void *data)
 984 {
 985     MachineClass *mc = MACHINE_CLASS(oc);
 986
 987     mc->desc = "Sun4v platform, Niagara";
 988     mc->init = niagara_init;
 989     mc->max_cpus = 1; /* XXX for now */
 990     mc->default_boot_order = "c";
 991 }
 992
 993 static const TypeInfo niagara_type = {
 994     .name = MACHINE_TYPE_NAME("Niagara"),
 995     .parent = TYPE_MACHINE,
 996     .class_init = niagara_class_init,
 997 };
 998
 999 static void sun4u_register_types(void)
1000 {
1001     type_register_static(&ebus_info);
1002     type_register_static(&prom_info);
1003     type_register_static(&ram_info);
1004
1005     type_register_static(&sun4u_type);
1006     type_register_static(&sun4v_type);
1007     type_register_static(&niagara_type);
1008 }
1009
1010 type_init(sun4u_register_types)