hw/misc/mos6522.c

   1 /*
   2  * QEMU MOS6522 VIA emulation
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  * Copyright (c) 2018 Mark Cave-Ayland
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #include "qemu/osdep.h"
  27 #include "hw/hw.h"
  28 #include "hw/input/adb.h"
  29 #include "hw/misc/mos6522.h"
  30 #include "qemu/timer.h"
  31 #include "sysemu/sysemu.h"
  32 #include "qemu/cutils.h"
  33 #include "qemu/log.h"
  34 #include "trace.h"
  35
  36 /* XXX: implement all timer modes */
  37
  38 static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti,
  39                                  int64_t current_time);
  40
  41 static void mos6522_update_irq(MOS6522State *s)
  42 {
  43     if (s->ifr & s->ier) {
  44         qemu_irq_raise(s->irq);
  45     } else {
  46         qemu_irq_lower(s->irq);
  47     }
  48 }
  49
  50 static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti)
  51 {
  52     MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
  53
  54     if (ti->index == 0) {
  55         return mdc->get_timer1_counter_value(s, ti);
  56     } else {
  57         return mdc->get_timer2_counter_value(s, ti);
  58     }
  59 }
  60
  61 static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti)
  62 {
  63     MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
  64
  65     if (ti->index == 0) {
  66         return mdc->get_timer1_load_time(s, ti);
  67     } else {
  68         return mdc->get_timer2_load_time(s, ti);
  69     }
  70 }
  71
  72 static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti)
  73 {
  74     int64_t d;
  75     unsigned int counter;
  76
  77     d = get_counter_value(s, ti);
  78
  79     if (ti->index == 0) {
  80         /* the timer goes down from latch to -1 (period of latch + 2) */
  81         if (d <= (ti->counter_value + 1)) {
  82             counter = (ti->counter_value - d) & 0xffff;
  83         } else {
  84             counter = (d - (ti->counter_value + 1)) % (ti->latch + 2);
  85             counter = (ti->latch - counter) & 0xffff;
  86         }
  87     } else {
  88         counter = (ti->counter_value - d) & 0xffff;
  89     }
  90     return counter;
  91 }
  92
  93 static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val)
  94 {
  95     trace_mos6522_set_counter(1 + ti->index, val);
  96     ti->load_time = get_load_time(s, ti);
  97     ti->counter_value = val;
  98     mos6522_timer_update(s, ti, ti->load_time);
  99 }
 100
 101 static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti,
 102                                  int64_t current_time)
 103 {
 104     int64_t d, next_time;
 105     unsigned int counter;
 106
 107     /* current counter value */
 108     d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time,
 109                  ti->frequency, NANOSECONDS_PER_SECOND);
 110
 111     /* the timer goes down from latch to -1 (period of latch + 2) */
 112     if (d <= (ti->counter_value + 1)) {
 113         counter = (ti->counter_value - d) & 0xffff;
 114     } else {
 115         counter = (d - (ti->counter_value + 1)) % (ti->latch + 2);
 116         counter = (ti->latch - counter) & 0xffff;
 117     }
 118
 119     /* Note: we consider the irq is raised on 0 */
 120     if (counter == 0xffff) {
 121         next_time = d + ti->latch + 1;
 122     } else if (counter == 0) {
 123         next_time = d + ti->latch + 2;
 124     } else {
 125         next_time = d + counter;
 126     }
 127     trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d);
 128     next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) +
 129                          ti->load_time;
 130     if (next_time <= current_time) {
 131         next_time = current_time + 1;
 132     }
 133     return next_time;
 134 }
 135
 136 static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti,
 137                                  int64_t current_time)
 138 {
 139     if (!ti->timer) {
 140         return;
 141     }
 142     if (ti->index == 0 && (s->acr & T1MODE) != T1MODE_CONT) {
 143         timer_del(ti->timer);
 144     } else {
 145         ti->next_irq_time = get_next_irq_time(s, ti, current_time);
 146         timer_mod(ti->timer, ti->next_irq_time);
 147     }
 148 }
 149
 150 static void mos6522_timer1(void *opaque)
 151 {
 152     MOS6522State *s = opaque;
 153     MOS6522Timer *ti = &s->timers[0];
 154
 155     mos6522_timer_update(s, ti, ti->next_irq_time);
 156     s->ifr |= T1_INT;
 157     mos6522_update_irq(s);
 158 }
 159
 160 static void mos6522_timer2(void *opaque)
 161 {
 162     MOS6522State *s = opaque;
 163     MOS6522Timer *ti = &s->timers[1];
 164
 165     mos6522_timer_update(s, ti, ti->next_irq_time);
 166     s->ifr |= T2_INT;
 167     mos6522_update_irq(s);
 168 }
 169
 170 static void mos6522_set_sr_int(MOS6522State *s)
 171 {
 172     trace_mos6522_set_sr_int();
 173     s->ifr |= SR_INT;
 174     mos6522_update_irq(s);
 175 }
 176
 177 static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti)
 178 {
 179     return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time,
 180                     ti->frequency, NANOSECONDS_PER_SECOND);
 181 }
 182
 183 static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti)
 184 {
 185     uint64_t load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 186
 187     return load_time;
 188 }
 189
 190 static void mos6522_portA_write(MOS6522State *s)
 191 {
 192     qemu_log_mask(LOG_UNIMP, "portA_write unimplemented\n");
 193 }
 194
 195 static void mos6522_portB_write(MOS6522State *s)
 196 {
 197     qemu_log_mask(LOG_UNIMP, "portB_write unimplemented\n");
 198 }
 199
 200 uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
 201 {
 202     MOS6522State *s = opaque;
 203     uint32_t val;
 204
 205     switch (addr) {
 206     case VIA_REG_B:
 207         val = s->b;
 208         break;
 209     case VIA_REG_A:
 210         val = s->a;
 211         break;
 212     case VIA_REG_DIRB:
 213         val = s->dirb;
 214         break;
 215     case VIA_REG_DIRA:
 216         val = s->dira;
 217         break;
 218     case VIA_REG_T1CL:
 219         val = get_counter(s, &s->timers[0]) & 0xff;
 220         s->ifr &= ~T1_INT;
 221         mos6522_update_irq(s);
 222         break;
 223     case VIA_REG_T1CH:
 224         val = get_counter(s, &s->timers[0]) >> 8;
 225         mos6522_update_irq(s);
 226         break;
 227     case VIA_REG_T1LL:
 228         val = s->timers[0].latch & 0xff;
 229         break;
 230     case VIA_REG_T1LH:
 231         /* XXX: check this */
 232         val = (s->timers[0].latch >> 8) & 0xff;
 233         break;
 234     case VIA_REG_T2CL:
 235         val = get_counter(s, &s->timers[1]) & 0xff;
 236         s->ifr &= ~T2_INT;
 237         mos6522_update_irq(s);
 238         break;
 239     case VIA_REG_T2CH:
 240         val = get_counter(s, &s->timers[1]) >> 8;
 241         break;
 242     case VIA_REG_SR:
 243         val = s->sr;
 244         s->ifr &= ~SR_INT;
 245         mos6522_update_irq(s);
 246         break;
 247     case VIA_REG_ACR:
 248         val = s->acr;
 249         break;
 250     case VIA_REG_PCR:
 251         val = s->pcr;
 252         break;
 253     case VIA_REG_IFR:
 254         val = s->ifr;
 255         if (s->ifr & s->ier) {
 256             val |= 0x80;
 257         }
 258         break;
 259     case VIA_REG_IER:
 260         val = s->ier | 0x80;
 261         break;
 262     default:
 263     case VIA_REG_ANH:
 264         val = s->anh;
 265         break;
 266     }
 267
 268     if (addr != VIA_REG_IFR || val != 0) {
 269         trace_mos6522_read(addr, val);
 270     }
 271
 272     return val;
 273 }
 274
 275 void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
 276 {
 277     MOS6522State *s = opaque;
 278     MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
 279
 280     trace_mos6522_write(addr, val);
 281
 282     switch (addr) {
 283     case VIA_REG_B:
 284         s->b = (s->b & ~s->dirb) | (val & s->dirb);
 285         mdc->portB_write(s);
 286         break;
 287     case VIA_REG_A:
 288         s->a = (s->a & ~s->dira) | (val & s->dira);
 289         mdc->portA_write(s);
 290         break;
 291     case VIA_REG_DIRB:
 292         s->dirb = val;
 293         break;
 294     case VIA_REG_DIRA:
 295         s->dira = val;
 296         break;
 297     case VIA_REG_T1CL:
 298         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 299         mos6522_timer_update(s, &s->timers[0],
 300                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 301         break;
 302     case VIA_REG_T1CH:
 303         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 304         s->ifr &= ~T1_INT;
 305         set_counter(s, &s->timers[0], s->timers[0].latch);
 306         break;
 307     case VIA_REG_T1LL:
 308         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 309         mos6522_timer_update(s, &s->timers[0],
 310                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 311         break;
 312     case VIA_REG_T1LH:
 313         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 314         s->ifr &= ~T1_INT;
 315         mos6522_timer_update(s, &s->timers[0],
 316                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 317         break;
 318     case VIA_REG_T2CL:
 319         s->timers[1].latch = (s->timers[1].latch & 0xff00) | val;
 320         break;
 321     case VIA_REG_T2CH:
 322         /* To ensure T2 generates an interrupt on zero crossing with the
 323            common timer code, write the value directly from the latch to
 324            the counter */
 325         s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8);
 326         s->ifr &= ~T2_INT;
 327         set_counter(s, &s->timers[1], s->timers[1].latch);
 328         break;
 329     case VIA_REG_SR:
 330         s->sr = val;
 331         break;
 332     case VIA_REG_ACR:
 333         s->acr = val;
 334         mos6522_timer_update(s, &s->timers[0],
 335                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 336         break;
 337     case VIA_REG_PCR:
 338         s->pcr = val;
 339         break;
 340     case VIA_REG_IFR:
 341         /* reset bits */
 342         s->ifr &= ~val;
 343         mos6522_update_irq(s);
 344         break;
 345     case VIA_REG_IER:
 346         if (val & IER_SET) {
 347             /* set bits */
 348             s->ier |= val & 0x7f;
 349         } else {
 350             /* reset bits */
 351             s->ier &= ~val;
 352         }
 353         mos6522_update_irq(s);
 354         break;
 355     default:
 356     case VIA_REG_ANH:
 357         s->anh = val;
 358         break;
 359     }
 360 }
 361
 362 static const MemoryRegionOps mos6522_ops = {
 363     .read = mos6522_read,
 364     .write = mos6522_write,
 365     .endianness = DEVICE_NATIVE_ENDIAN,
 366     .valid = {
 367         .min_access_size = 1,
 368         .max_access_size = 1,
 369     },
 370 };
 371
 372 static const VMStateDescription vmstate_mos6522_timer = {
 373     .name = "mos6522_timer",
 374     .version_id = 0,
 375     .minimum_version_id = 0,
 376     .fields = (VMStateField[]) {
 377         VMSTATE_UINT16(latch, MOS6522Timer),
 378         VMSTATE_UINT16(counter_value, MOS6522Timer),
 379         VMSTATE_INT64(load_time, MOS6522Timer),
 380         VMSTATE_INT64(next_irq_time, MOS6522Timer),
 381         VMSTATE_TIMER_PTR(timer, MOS6522Timer),
 382         VMSTATE_END_OF_LIST()
 383     }
 384 };
 385
 386 const VMStateDescription vmstate_mos6522 = {
 387     .name = "mos6522",
 388     .version_id = 0,
 389     .minimum_version_id = 0,
 390     .fields = (VMStateField[]) {
 391         VMSTATE_UINT8(a, MOS6522State),
 392         VMSTATE_UINT8(b, MOS6522State),
 393         VMSTATE_UINT8(dira, MOS6522State),
 394         VMSTATE_UINT8(dirb, MOS6522State),
 395         VMSTATE_UINT8(sr, MOS6522State),
 396         VMSTATE_UINT8(acr, MOS6522State),
 397         VMSTATE_UINT8(pcr, MOS6522State),
 398         VMSTATE_UINT8(ifr, MOS6522State),
 399         VMSTATE_UINT8(ier, MOS6522State),
 400         VMSTATE_UINT8(anh, MOS6522State),
 401         VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0,
 402                              vmstate_mos6522_timer, MOS6522Timer),
 403         VMSTATE_END_OF_LIST()
 404     }
 405 };
 406
 407 static void mos6522_reset(DeviceState *dev)
 408 {
 409     MOS6522State *s = MOS6522(dev);
 410
 411     s->b = 0;
 412     s->a = 0;
 413     s->dirb = 0xff;
 414     s->dira = 0;
 415     s->sr = 0;
 416     s->acr = 0;
 417     s->pcr = 0;
 418     s->ifr = 0;
 419     s->ier = 0;
 420     /* s->ier = T1_INT | SR_INT; */
 421     s->anh = 0;
 422
 423     s->timers[0].frequency = s->frequency;
 424     s->timers[0].latch = 0xffff;
 425     set_counter(s, &s->timers[0], 0xffff);
 426
 427     s->timers[1].frequency = s->frequency;
 428     s->timers[1].latch = 0xffff;
 429 }
 430
 431 static void mos6522_init(Object *obj)
 432 {
 433     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 434     MOS6522State *s = MOS6522(obj);
 435     int i;
 436
 437     memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 0x10);
 438     sysbus_init_mmio(sbd, &s->mem);
 439     sysbus_init_irq(sbd, &s->irq);
 440
 441     for (i = 0; i < ARRAY_SIZE(s->timers); i++) {
 442         s->timers[i].index = i;
 443     }
 444
 445     s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s);
 446     s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s);
 447 }
 448
 449 static Property mos6522_properties[] = {
 450     DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0),
 451     DEFINE_PROP_END_OF_LIST()
 452 };
 453
 454 static void mos6522_class_init(ObjectClass *oc, void *data)
 455 {
 456     DeviceClass *dc = DEVICE_CLASS(oc);
 457     MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc);
 458
 459     dc->reset = mos6522_reset;
 460     dc->vmsd = &vmstate_mos6522;
 461     dc->props = mos6522_properties;
 462     mdc->parent_reset = dc->reset;
 463     mdc->set_sr_int = mos6522_set_sr_int;
 464     mdc->portB_write = mos6522_portB_write;
 465     mdc->portA_write = mos6522_portA_write;
 466     mdc->update_irq = mos6522_update_irq;
 467     mdc->get_timer1_counter_value = mos6522_get_counter_value;
 468     mdc->get_timer2_counter_value = mos6522_get_counter_value;
 469     mdc->get_timer1_load_time = mos6522_get_load_time;
 470     mdc->get_timer2_load_time = mos6522_get_load_time;
 471 }
 472
 473 static const TypeInfo mos6522_type_info = {
 474     .name = TYPE_MOS6522,
 475     .parent = TYPE_SYS_BUS_DEVICE,
 476     .instance_size = sizeof(MOS6522State),
 477     .instance_init = mos6522_init,
 478     .abstract = true,
 479     .class_size = sizeof(MOS6522DeviceClass),
 480     .class_init = mos6522_class_init,
 481 };
 482
 483 static void mos6522_register_types(void)
 484 {
 485     type_register_static(&mos6522_type_info);
 486 }
 487
 488 type_init(mos6522_register_types)